JP2011159734A - Wiring board - Google Patents

Wiring board Download PDF

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JP2011159734A
JP2011159734A JP2010019109A JP2010019109A JP2011159734A JP 2011159734 A JP2011159734 A JP 2011159734A JP 2010019109 A JP2010019109 A JP 2010019109A JP 2010019109 A JP2010019109 A JP 2010019109A JP 2011159734 A JP2011159734 A JP 2011159734A
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wiring
diameter
hole
holes
wiring board
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JP5461212B2 (en
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Seiichi Abe
誠一 阿部
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Kyocera SLC Technologies Corp
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Kyocera SLC Technologies Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board which can make signal wiring satisfactorily transmit a high-speed signal exceeding, for example, 2.5 GHz with low loss, and can satisfactorily supply power supply. <P>SOLUTION: The wiring board is constituted by laminating build-up wiring layers 3 including signal wiring, ground wiring and power source wiring on the upper and lower surfaces of a core substrate 1 having many through holes 5 at an outer peripheral part and a center part, with build-up insulating layers 2 interposed. In the wiring board, small-diameter through-holes 5S are arrayed at the outer peripheral part at first adjacent intervals and large-diameter through-holes 5L are arranged at the center part at second adjacent intervals smaller than the first adjacent intervals, and the signal wiring is connected to the small-diameter through-holes 5S and the ground wiring and power source wiring are connected to the large-diameter through-holes 5L. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体集積回路素子を搭載するための配線基板に関するものである。   The present invention relates to a wiring board for mounting a semiconductor integrated circuit element.

従来、半導体集積回路素子を搭載するための配線基板として、ビルドアップ法により形成された配線基板が知られている。図４はビルドアップ法により形成された従来の配線基板の一例を示す概略断面図であり、図５は図４の切断線Ａ−Ａにおける横断面図である。   Conventionally, a wiring board formed by a build-up method is known as a wiring board for mounting a semiconductor integrated circuit element. FIG. 4 is a schematic cross-sectional view showing an example of a conventional wiring board formed by a build-up method, and FIG. 5 is a cross-sectional view taken along a cutting line AA in FIG.

図４に示すように、従来の配線基板２０は、コア基板１１の上下面にビルドアップ絶縁層１２およびビルドアップ配線層１３が交互に積層されている。   As shown in FIG. 4, in the conventional wiring board 20, the buildup insulating layers 12 and the buildup wiring layers 13 are alternately stacked on the upper and lower surfaces of the core substrate 11.

コア基板１１の上下面には銅箔や銅めっき層から成るコア導体層１４が被着されている。また、コア基板１１の上面から下面にかけてコア導体層１４の一部として機能する銅めっき層が被着された多数のスルーホール１５が形成されている。   A core conductor layer 14 made of copper foil or a copper plating layer is deposited on the upper and lower surfaces of the core substrate 11. In addition, a large number of through holes 15 to which a copper plating layer functioning as a part of the core conductor layer 14 is deposited are formed from the upper surface to the lower surface of the core substrate 11.

ビルドアップ絶縁層１２には、それぞれに複数のビアホール１６が形成されており、ビアホール１６を含む各ビルドアップ絶縁層１２の表面には銅めっき層から成るビルドアップ配線層１３が被着形成されている。そしてビルドアップ配線層１３は、ビアホール１６を介して上下のものが互い接続されているとともにスルーホール１５に電気的に接続している。さらに、このビルドアップ配線層１３のうち、上面側における最外層のビルドアップ絶縁層１２上に被着された一部は、半導体集積回路素子Ｓの電極端子に導電バンプＢ１を介して電気的に接続される円形の半導体素子接続パッド１３ａを形成しており、これらの半導体素子接続パッド１３ａは格子状の並びに多数並んで形成されている。また、下面側における最外層のビルドアップ絶縁層１２上に被着された一部は、外部電気回路基板の配線導体に電気的に接続される円形の外部接続パッド１３ｂであり、この外部接続パッド１３ｂは格子状の並びに複数並んで形成されている。   A plurality of via holes 16 are formed in each of the build-up insulating layers 12, and a build-up wiring layer 13 made of a copper plating layer is deposited on the surface of each build-up insulating layer 12 including the via holes 16. Yes. The build-up wiring layer 13 is electrically connected to the through hole 15 while the upper and lower layers are connected to each other through the via hole 16. Further, a part of the buildup wiring layer 13 deposited on the outermost buildup insulating layer 12 on the upper surface side is electrically connected to the electrode terminal of the semiconductor integrated circuit element S via the conductive bump B1. Circular semiconductor element connection pads 13a to be connected are formed, and a large number of these semiconductor element connection pads 13a are arranged in a grid. Further, a part of the lower surface side deposited on the outermost buildup insulating layer 12 is a circular external connection pad 13b that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of 13b are formed in a grid.

さらに、最外層のビルドアップ絶縁層１２およびその上のビルドアップ配線層１３上には、半導体素子接続パッド１３ａおよび外部接続パッド１３ｂを露出させるソルダーレジスト層１７が被着されている。そして、半導体素子接続パッド１３ａの露出部に半導体集積回路素子Ｓの電極端子が半田や金等から成る導電バンプＢ１を介して電気的に接続されるとともに外部接続パッド１３ｂの露出部に図示しない外部電気回路基板の配線導体が半田ボールＢ２を介して電気的に接続される。   Further, a solder resist layer 17 for exposing the semiconductor element connection pads 13a and the external connection pads 13b is deposited on the outermost buildup insulating layer 12 and the buildup wiring layer 13 thereon. The electrode terminal of the semiconductor integrated circuit element S is electrically connected to the exposed portion of the semiconductor element connection pad 13a via the conductive bump B1 made of solder, gold, etc., and the exposed portion of the external connection pad 13b is not shown in the drawing. The wiring conductor of the electric circuit board is electrically connected via the solder ball B2.

ところで、半導体集積回路素子Ｓは、配線基板２０からの十分な電源供給を確保するためにその下面の中央部に接地用と電源用との電極端子を多数設けるとともに下面の外周部に信号用の電極端子を多数設けた端子配置を採用する場合が増えている。このような半導体素子Ｓを搭載する場合、配線基板２０におけるビルドアップ配線層１３の接地配線および電源配線を介してコア基板１１の中央部に設けたスルーホール１５に接続し、信号配線をコア基板１１の外周部に設けたスルーホール１５に接続する方法が採用されている。さらに、近時の配線基板においては、図５に示すように、コア基板１１の中央部に例えば直径が１００μｍの小径のスルーホール１５Ｓを３００μｍのピッチで設けるとともにコア基板１１の外周部に例えば直径が３００μｍの大径のスルーホール１５Ｌを６００μｍのピッチで設け、中央部の小径のスルーホール１５Ｓには接地配線および電源配線を接続し、外周部の大径のスルーホール１５Ｌには信号配線を接続することにより、多数の電源線および接地線を設けて電源供給を行なう配線基板が提案されている。   By the way, the semiconductor integrated circuit element S is provided with a large number of electrode terminals for grounding and power supply at the center of the lower surface thereof in order to ensure sufficient power supply from the wiring board 20 and at the outer peripheral portion of the lower surface for signals. Increasing use of a terminal arrangement with a large number of electrode terminals is increasing. When such a semiconductor element S is mounted, the signal wiring is connected to the core board 11 through the ground hole and the power supply wiring of the build-up wiring layer 13 in the wiring board 20 and connected to the through hole 15 provided in the central portion of the core board 11. A method of connecting to a through hole 15 provided on the outer peripheral portion of 11 is adopted. Furthermore, in recent wiring boards, as shown in FIG. 5, small through holes 15S having a diameter of 100 μm, for example, are provided at the center of the core board 11 at a pitch of 300 μm, and the diameter of the outer periphery of the core board 11 is, for example, Is provided with a large-diameter through hole 15L of 300 μm at a pitch of 600 μm, and ground wiring and power supply wiring are connected to the small-diameter through hole 15S in the central portion, and signal wiring is connected to the large-diameter through hole 15L in the outer peripheral portion. Thus, a wiring board has been proposed in which a large number of power lines and ground lines are provided to supply power.

しかしながら、信号配線を直径が３００μｍの大径のスルーホールに接続した場合、その大径のスルーホールと接地配線や電源配線との間に形成される静電容量が大きくなるため大径のスルーホールにおけるインピーダンスが小さくなって、大径のスルーホールに接続した信号配線に例えば２．５ＧＨｚを超える高速信号を伝送させると、信号の反射損が大きくなり、信号を良好に伝送することができなくなってしまう。また、スルーホールの直径が３００μｍと大径である場合、スルーホール内にめっき液が良好に供給されるので例えば１５〜２０μｍ程度の厚みの銅めっき層を容易に被着させることが可能であるが、スルーホールの直径を１００μｍ程度の小径なものとした場合、そのような小径のスルーホール内にはめっき液を十分に供給することが困難であることから、厚みが１５〜２０μｍ程度の厚い銅めっき層を被着させることができず、必然的にスルーホール内に被着させた銅めっき層の厚みが薄いものとなる。スルーホール内に被着させた銅めっき層の厚みが薄い場合、スルーホールにおける電気抵抗がその分高くなるので、例えば直径が１００μｍ程度のスルーホールを３００μｍの狭いピッチで多数設けて、それらに接地配線や電源配線を接続したとしても十分な電源供給を行なうことはできなくなってしまう。   However, if the signal wiring is connected to a large-diameter through-hole having a diameter of 300 μm, the capacitance formed between the large-diameter through-hole and the ground wiring or power supply wiring increases, so that the large-diameter through-hole When the signal impedance connected to the large-diameter through hole is reduced, and a high-speed signal exceeding 2.5 GHz, for example, is transmitted to the signal wiring connected to the large-diameter through hole, the signal reflection loss increases and the signal cannot be transmitted satisfactorily. End up. Further, when the through hole has a large diameter of 300 μm, the plating solution is satisfactorily supplied into the through hole, so that it is possible to easily deposit a copper plating layer having a thickness of, for example, about 15 to 20 μm. However, when the through hole has a small diameter of about 100 μm, it is difficult to sufficiently supply the plating solution into the through hole of such a small diameter, so the thickness is about 15 to 20 μm. The copper plating layer cannot be deposited, and the thickness of the copper plating layer deposited in the through hole is inevitably thin. When the thickness of the copper plating layer deposited in the through hole is thin, the electrical resistance in the through hole is increased accordingly. For example, a large number of through holes having a diameter of about 100 μm are provided at a narrow pitch of 300 μm and grounded to them. Even if wiring or power supply wiring is connected, sufficient power supply cannot be performed.

特許第４２８２１９０号公報Japanese Patent No. 4282190

本発が解決しようとする課題は、信号配線に例えば２．５ＧＨｚを超える高速信号を低損失で良好に伝送させることが可能であるとともに、良好な電源供給が可能な配線基板を提供することにある。   The problem to be solved by the present invention is to provide a wiring board that can transmit a high-speed signal exceeding 2.5 GHz, for example, to a signal wiring satisfactorily with low loss and can supply a good power. is there.

本発明の配線基板は、外周部および中央部に多数のスルーホールを有するコア基板の上下面にビルドアップ絶縁層を介して信号配線および接地配線および電源配線を含むビルドアップ配線層を積層してなる配線基板であって、前記外周部に小径スルーホールを第１の隣接間隔で配列するとともに前記中央部に大径スルーホールを前記第１の隣接間隔以下の第２の隣接間隔で配置し、前記小径スルーホールに前記信号線を接続するとともに前記大径スルーホールに前記接地配線および電源配線を接続したことを特徴とするものである。   In the wiring board of the present invention, a build-up wiring layer including signal wiring, ground wiring, and power supply wiring is laminated on the upper and lower surfaces of a core substrate having a large number of through holes in the outer peripheral portion and the central portion through a build-up insulating layer. A small-diameter through hole is arranged in the outer peripheral portion at a first adjacent interval, and a large-diameter through hole is arranged in the central portion at a second adjacent interval equal to or less than the first adjacent interval, The signal line is connected to the small diameter through hole, and the ground wiring and the power supply wiring are connected to the large diameter through hole.

本発明の配線基板によると、信号配線を小径スルーホールに接続したことから、信号配線に接続された小径スルーホールにおける接地配線または電源配線との間に形成される静電容量を小さいものとしてインピーダンスの低下を防止することができ、それにより、信号の反射を低減して例えば２．５ＧＨｚを超える高速の信号を低損失で良好に伝送させることができる。また、接地配線および電源配線が接続される大径スルーホールを小径スルーホールの隣接間隔以下の隣接間隔で配列することにより、大径スルーホールに被着された銅めっき層の総横断面積を大きなものとすることができ、それにより、良好な電源供給が行なえる。   According to the wiring board of the present invention, since the signal wiring is connected to the small-diameter through hole, the capacitance formed between the ground wiring or the power supply wiring in the small-diameter through hole connected to the signal wiring is reduced, and the impedance is reduced. Thus, the reflection of the signal can be reduced, and a high-speed signal exceeding, for example, 2.5 GHz can be successfully transmitted with low loss. In addition, by arranging the large-diameter through holes to which the ground wiring and power supply wiring are connected at an adjacent interval that is equal to or less than the adjacent interval between the small-diameter through holes, the total cross-sectional area of the copper plating layer deposited on the large-diameter through hole is increased. Therefore, a good power supply can be performed.

図１は、本発明の配線基板の実施形態の一例を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. 図２は、図１の切断線Ａ−Ａにおける横断面図である。FIG. 2 is a cross-sectional view taken along line AA in FIG. 図３は、多数のスルーホールを所定の面積の領域に所定の隣接間隔で配列した場合におけるスルーホール内の銅めっき層の総横断面積を示すグラフである。FIG. 3 is a graph showing the total cross-sectional area of the copper plating layer in the through hole when a large number of through holes are arranged in a region of a predetermined area at a predetermined adjacent interval. 図４は、従来の配線基板を示す概略断面図である。FIG. 4 is a schematic cross-sectional view showing a conventional wiring board. 図５は、図４の切断線Ａ−Ａにおける横断面図である。FIG. 5 is a cross-sectional view taken along section line AA in FIG.

以下、本発明にかかる配線基板について図面を参照して詳細に説明する。
図１は、本発明における配線基板の実施形態の一例を示す概略断面図であり、半導体集積回路素子をフリップチップ接続により搭載した場合を示している。 Hereinafter, a wiring board according to the present invention will be described in detail with reference to the drawings.
FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention, and shows a case where a semiconductor integrated circuit element is mounted by flip-chip connection.

図１に示すように、本例の配線基板１０は、コア基板１の上下面に複数のビルドアップ絶縁層２およびビルドアップ配線層３が交互に積層されている。   As shown in FIG. 1, in the wiring board 10 of this example, a plurality of buildup insulating layers 2 and buildup wiring layers 3 are alternately stacked on the upper and lower surfaces of the core substrate 1.

コア基板１は、厚みが５０〜８００μｍ程度であり、例えばガラス繊維束を縦横に織ったガラスクロスにビスマレイミドトリアジン樹脂やエポキシ樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成る絶縁基板の上下面に銅箔や銅めっき層から成るコア導体層４が被着されているとともに絶縁基板の上面から下面にかけてコア導体層４の一部として機能する銅めっき層が被着された多数のスルーホール５が形成されている。なお、スルーホール５の直径は１００〜３００μｍ程度であり、その内部は樹脂により充填されている。   The core substrate 1 has a thickness of about 50 to 800 μm, and is made of an electrically insulating material in which a glass cloth in which glass fiber bundles are woven vertically and horizontally is impregnated with a thermosetting resin such as bismaleimide triazine resin or epoxy resin. A large number of core conductor layers 4 made of copper foil or copper plating layers are deposited on the upper and lower surfaces, and copper plating layers that function as a part of the core conductor layers 4 are deposited from the upper surface to the lower surface of the insulating substrate. A through hole 5 is formed. The diameter of the through hole 5 is about 100 to 300 μm, and the inside is filled with resin.

ビルドアップ絶縁層２は、厚みが２０〜５０μｍ程度であり、それぞれに直径が３５〜１００μｍ程度の複数のビアホール６が形成されており、各ビルドアップ絶縁層２の表面およびビアホール６の内面には、ビルドアップ配線層３が被着形成されている。そしてビルドアップ配線層３は、スルーホール５に電気的に接続している。さらに、このビルドアップ配線層３のうち、配線基板１０の上面側における最外層のビルドアップ絶縁層２上に被着された一部は、半導体集積回路素子Ｓの電極端子に導電バンプＢ１を介してフリップチップ接続により電気的に接続される円形の半導体素子接続パッド３ａを形成しており、これらの半導体素子接続パッド３ａは格子状の並びに複数並んで形成されている。そして、これらの半導体素子接続パッド３ａはその外周部がソルダーレジスト層７により覆われているとともに上面の中央部がソルダーレジスト層７から露出しており、半導体素子接続パッド３ａの露出部に半導体素子Ｓの電極端子が半田や金等から成る導電バンプＢ１を介して電気的に接続される。   The build-up insulating layer 2 has a thickness of about 20 to 50 μm, and a plurality of via holes 6 each having a diameter of about 35 to 100 μm are formed on each of the build-up insulating layers 2 and the inner surfaces of the via holes 6. The build-up wiring layer 3 is deposited. The buildup wiring layer 3 is electrically connected to the through hole 5. Further, a part of the buildup wiring layer 3 deposited on the outermost buildup insulating layer 2 on the upper surface side of the wiring board 10 is connected to the electrode terminal of the semiconductor integrated circuit element S via the conductive bump B1. Thus, a circular semiconductor element connection pad 3a that is electrically connected by flip-chip connection is formed, and a plurality of these semiconductor element connection pads 3a are formed in a lattice pattern. These semiconductor element connection pads 3a are covered with the solder resist layer 7 at the outer periphery thereof, and the center part of the upper surface is exposed from the solder resist layer 7. The semiconductor element connection pad 3a is exposed to the semiconductor element at the exposed portion of the semiconductor element connection pad 3a. The electrode terminals of S are electrically connected through conductive bumps B1 made of solder, gold or the like.

他方、配線基板１０の下面側における最外層のビルドアップ絶縁層２上に被着された一部は、外部電気回路基板の配線導体に電気的に接続される円形の外部接続パッド３ｂであり、この外部接続パッド３ｂは格子状の並びに複数並んで形成されている。この外部接続パッド３ｂはその外周部がソルダーレジスト層７により覆われているとともに、その下面中央部がソルダーレジスト層７から露出しており、外部接続パッド７の露出部に、図示しない外部電気回路基板の配線導体が半田ボールＢ２を介して電気的に接続される。なお、ソルダーレジスト層７は、最外層のビルドアップ配線層３を保護するとともに、半導体素子接続パッド３ａや外部接続パッド３ｂの露出部を画定する。なお、ビルドアップ配線層３は、信号配線および接地配線および電源配線を含んでいる。   On the other hand, a part of the lower surface side of the wiring board 10 deposited on the outermost buildup insulating layer 2 is a circular external connection pad 3b that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of external connection pads 3b are arranged in a lattice. The external connection pad 3b is covered with a solder resist layer 7 at the outer peripheral portion thereof, and the central portion of the lower surface is exposed from the solder resist layer 7. An external electric circuit (not shown) is exposed on the exposed portion of the external connection pad 7. The wiring conductor of the board is electrically connected via the solder ball B2. The solder resist layer 7 protects the outermost buildup wiring layer 3 and defines exposed portions of the semiconductor element connection pads 3a and the external connection pads 3b. The build-up wiring layer 3 includes signal wiring, ground wiring, and power supply wiring.

そして、配線基板１０においては、コア基板１の外周部に形成されたスルーホール５が例えば直径が１００〜２００μｍ程度の小径スルーホール５Ｓであり、コア基板１の中央部に形成されたスルーホール５が例えば直径が２５０〜３５０μｍ程度の大径スルーホール５Ｌである。   In the wiring substrate 10, the through hole 5 formed in the outer peripheral portion of the core substrate 1 is a small diameter through hole 5 </ b> S having a diameter of about 100 to 200 μm, for example, and the through hole 5 formed in the central portion of the core substrate 1. Is a large-diameter through hole 5L having a diameter of about 250 to 350 μm, for example.

小径スルーホール５Ｓは、互いの隣接間隔が例えば２５０μｍ以上となる第１の隣接間隔で配列されており、信号配線が接続されている。小径スルーホール５Ｓは、その直径が例えば１００〜２００μｍと小さく、スルーホール５Ｓと接地配線や電源配線との間に形成される静電容量を小さいものとすることができる。したがって、小径スルーホール５Ｓに接続される信号配線に例えば２．５ＧＨｚを超える高速の信号を伝送させたとしても、その信号を低損失で良好に伝送させることができる。なお、小径スルーホール５Ｓは、その直径が１００μｍ未満となると、その形成が煩雑になるとともに内面への銅めっき層の良好な被着が困難となる傾向にあり、２００μｍを超えると、小径スルーホール５Ｓと接地配線や電源配線との間に形成される静電容量が大きくなりすぎて例えば２．５ＧＨｚを超える高速の信号を低損失で伝送することが困難となる。したがって、小径スルーホール５Ｓは、その直径が１００〜２００μｍであることが好ましい。   The small-diameter through holes 5S are arranged at a first adjacent interval in which the adjacent interval is, for example, 250 μm or more, and the signal wiring is connected thereto. The small-diameter through hole 5S has a small diameter of, for example, 100 to 200 μm, and can have a small capacitance formed between the through-hole 5S and the ground wiring or power supply wiring. Therefore, even if a high-speed signal exceeding 2.5 GHz, for example, is transmitted to the signal wiring connected to the small-diameter through hole 5S, the signal can be transmitted favorably with low loss. If the diameter of the small diameter through hole 5S is less than 100 μm, the formation of the small diameter through hole becomes complicated and it is difficult to satisfactorily deposit the copper plating layer on the inner surface. The capacitance formed between 5S and the ground wiring or power supply wiring becomes too large, and it becomes difficult to transmit a high-speed signal exceeding 2.5 GHz, for example, with low loss. Accordingly, the small diameter through hole 5S preferably has a diameter of 100 to 200 μm.

大径スルーホール５Ｌは、前記第１の隣接間隔以下の第２の隣接間隔で配列されており、接地配線および電源配線が接続されている。大径スルーホール５Ｌは、その直径が２５０〜３００μｍと大きいものの、小径のスルーホール５Ｓの隣接間隔以下の隣接間隔で配列することにより、２５０〜３５０μｍと大径であったとしても大径スルーホール５に被着された銅めっき層の総横断面積を大きなものとすることができる。図３は、直径を５０〜４００μｍの間でそれぞれ５０μｍきざみに変化させたスルーホールを１０ｍｍ角の領域に隣接間隔２５０μｍとして配列するとともにスルーホール内に１５μｍの銅めっき層を被着させた場合における各スルーホール径毎の銅めっき層の総横断面積を示すグラフである。図３に示すように、直径が２５０μｍのスルーホールの場合、直径が１００μｍの小径スルーホールの場合と比較して銅めっき層の総横断面積は約１．４倍となる。したがって大径スルーホール５Ｌを介して良好に電源供給を行なうことができる。なお、大径スルーホール５Ｌの直径が２５０μｍ未満であると、小径スルーホール５Ｓを含むスルーホール５の数が増加してスルーホール５の加工に長時間を要する傾向にあり、３５０μｍを超えると、大径スルーホール５Ｌに被着させた銅めっき層の総横断面積が減少して電源供給能力が低下してしまう傾向にある。さらに、大径スルーホール５Ｌの直径を２５０〜３５０μｍとすることにより、大径スルーホール５Ｌ内に銅めっき層を被着させる際、大径スルーホール５Ｌ内にめっき液が良好に供給されるので大径スルーホール５Ｌに例えば１５〜２０μｍ程度の厚みの銅めっき層を容易に被着させることが可能である。したがって、大径スルーホール５Ｌの直径は２５０〜３５０μｍの範囲が好ましい。   The large-diameter through holes 5L are arranged at a second adjacent interval that is equal to or less than the first adjacent interval, and a ground wiring and a power supply wiring are connected to the large-diameter through hole 5L. The large-diameter through hole 5L has a large diameter of 250 to 300 μm. However, by arranging the large-diameter through hole at an adjacent interval equal to or smaller than the adjacent interval of the small-diameter through hole 5S, The total cross-sectional area of the copper plating layer deposited on 5 can be increased. FIG. 3 shows a case where through holes whose diameters are changed in 50 μm increments between 50 and 400 μm are arranged in a 10 mm square region with an adjacent interval of 250 μm and a 15 μm copper plating layer is deposited in the through holes. It is a graph which shows the total cross-sectional area of the copper plating layer for every through-hole diameter. As shown in FIG. 3, in the case of a through hole having a diameter of 250 μm, the total cross-sectional area of the copper plating layer is about 1.4 times that in the case of a small diameter through hole having a diameter of 100 μm. Therefore, power can be supplied satisfactorily through the large diameter through hole 5L. If the diameter of the large-diameter through hole 5L is less than 250 μm, the number of through-holes 5 including the small-diameter through-hole 5S tends to increase and it takes a long time to process the through-hole 5, and if it exceeds 350 μm, There is a tendency that the total cross-sectional area of the copper plating layer deposited on the large-diameter through hole 5L is reduced and the power supply capability is lowered. Furthermore, by setting the diameter of the large diameter through hole 5L to 250 to 350 μm, when a copper plating layer is deposited in the large diameter through hole 5L, the plating solution is satisfactorily supplied into the large diameter through hole 5L. For example, a copper plating layer having a thickness of about 15 to 20 μm can be easily applied to the large-diameter through hole 5L. Therefore, the diameter of the large diameter through hole 5L is preferably in the range of 250 to 350 μm.

かくして、本発明の配線基板によれば、信号配線に例えば２．５ＧＨｚを超える高速信号を低損失で良好に伝送させることが可能であるとともに、良好な電源供給が可能な配線基板を提供することができる。   Thus, according to the wiring board of the present invention, it is possible to provide a wiring board capable of transmitting a high-speed signal exceeding 2.5 GHz to the signal wiring satisfactorily with low loss and capable of supplying a good power supply. Can do.

１ コア基板
２ ビルドアップ絶縁層
３ ビルドアップ配線層
５ スルーホール
５Ｓ 小径スルーホール
５Ｌ 大径スルーホール 1 Core substrate 2 Build-up insulating layer 3 Build-up wiring layer 5 Through hole 5S Small diameter through hole 5L Large diameter through hole

Claims (2)

外周部および中央部に多数のスルーホールを有するコア基板の上下面にビルドアップ絶縁層を介して信号配線および接地配線および電源配線を含むビルドアップ配線層を積層してなる配線基板であって、前記外周部に小径スルーホールを第１の隣接間隔で配列するとともに前記中央部に大径スルーホールを前記第１の隣接間隔以下の第２の隣接間隔で配置し、前記小径スルーホールに前記信号線を接続するとともに前記大径スルーホールに前記接地配線および電源配線を接続したことを特徴とする配線基板。   A wiring board formed by laminating a build-up wiring layer including a signal wiring, a ground wiring, and a power supply wiring on the upper and lower surfaces of a core substrate having a large number of through holes in the outer peripheral part and the central part, Small-diameter through-holes are arranged in the outer peripheral portion with a first adjacent interval, and large-diameter through-holes are arranged in the central portion with a second adjacent interval that is equal to or less than the first adjacent interval, and the signal is placed in the small-diameter through hole. A wiring board characterized by connecting a wire and connecting the ground wiring and power wiring to the large-diameter through hole. 前記小径スルーホールの直径が１００〜２００μｍであり、前記大径スルーホールの直径が２５０〜３５０μｍであることを特徴とする請求項１記載の配線基板。   2. The wiring board according to claim 1, wherein the diameter of the small diameter through hole is 100 to 200 [mu] m, and the diameter of the large diameter through hole is 250 to 350 [mu] m.
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
JP2014192432A (en) * 2013-03-28 2014-10-06 Kyocer Slc Technologies Corp Wiring board

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JP2001168531A (en) * 1999-12-14 2001-06-22 Ibiden Co Ltd Multilayer printed wiring board and manufacturing method therefor
JP2003209359A (en) * 2002-01-11 2003-07-25 Dainippon Printing Co Ltd Core board and its manufacturing method
JP2005347391A (en) * 2004-06-01 2005-12-15 Ibiden Co Ltd Printed wiring board

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JPH07240581A (en) * 1994-02-28 1995-09-12 Nec Ibaraki Ltd Method for forming via hole of high-density circuit substrate
JP2001168531A (en) * 1999-12-14 2001-06-22 Ibiden Co Ltd Multilayer printed wiring board and manufacturing method therefor
JP4282190B2 (en) * 1999-12-14 2009-06-17 イビデン株式会社 Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
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JP2005347391A (en) * 2004-06-01 2005-12-15 Ibiden Co Ltd Printed wiring board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014192432A (en) * 2013-03-28 2014-10-06 Kyocer Slc Technologies Corp Wiring board
US9277657B2 (en) 2013-03-28 2016-03-01 Kyocera Slc Technologies Corporation Wiring board

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