JP2011155779A - Digital protective relay device for power system provided with testing facility - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital protective relay wherein relay calculation, the verification of sequence logic, and comprehensive performance test can be carried out by simulating a system failure without any special tester. <P>SOLUTION: The digital protective relay includes: an input converter 3; an analog input unit 4 connected to the input converter 3; and a relay sequence computation unit 5 connected to the analog input unit 4 through a system bus 2. The analog input unit 4 includes: an analog filter 41; an A/D conversion unit 42 connected to the analog filter 41; a digital filter processing unit 43 connected to the A/D conversion unit 42; a memory 45 in which data of voltage waveform and current waveform observed in the case of the system failure and input conditions, such as system-side equipment conditions, are written in advance; and a change-over switch 44 installed in the stage subsequent to or preceding the digital filter processing unit 43. The digital protective relay is provided with testing facilities that change over the change-over switch 44 according to an external command and perform relay calculation, sequence processing and logic processing in accordance with data in the memory 45. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a digital power protection relay device having a test function.

  To eliminate faults such as short-circuits and ground faults that occur in the power system, protective relay devices installed for each element such as power transmission lines, transformers, buses, and generators that form the power system are generated within the defensive range. This is done by disconnecting the section including the failure point from the remaining healthy power system by the circuit breaker.

  At present, digital protection relay devices that have digitized the current and voltage information of the system and realized an algorithm for discriminating system failure by software processing are the mainstream of protection relay devices.

  The outline of the digital protection relay device is as follows. In the digital protection relay device for extra highs, the current and voltage information of the power system is sampled and digitized at a cycle of 30 degrees electrical angle and 3.75 degrees for high speed devices. For this data, an algorithm operation for realizing digital filter processing and failure detection, that is, a so-called protection relay operation is performed to detect a system failure. Furthermore, a sequence logic constituted by a combination of input conditions such as the state of the device and the state of other devices and some relay calculation results is executed, and a final trip command, so-called trip command, is output.

  The test method of the protection relay device is described. The characteristic test of the relay itself, which is a failure detection function of the protection relay, includes verification of static characteristics and verification by a comprehensive operation test.

  For verification of the static characteristics, the error management of the characteristics and the measurement of the operating time are performed by inputting the AC amount in the vicinity of the set value by a distortion-free tester.

  On the other hand, the comprehensive operation test is carried out by a simulated power transmission line or a digital simulator. For example, [Patent Document 1] describes that a system constant is input and a system phenomenon is simulated by a system analysis program.

  Such a test is a test for simulating an actual failure of the equipment to be protected and confirming the overall function of the apparatus. For that purpose, the scale of the verification facility for the comprehensive operation test is large, and in order to realize the intended test case, it is necessary to adjust the simulated transmission line facility, and the number of man-hours required for the test also increases.

  In general operation tests, verification by simulation of system failure is generally performed at the time of relay device development or shipping test, but the relay operation algorithm was changed, the sequence logic was changed or modified. In some cases, it is conducted as part of a comprehensive operational test. There are also cases where the analysis and re-verification of relay device operation is performed for complex system failures that actually occur. In this case, the system is simulated by a digital simulator or recorded in the event of a system failure. If waveform data such as voltage and current on the system side of the system can be used, a method of creating a reproduced waveform based on the recorded waveform data can be considered.

  [Patent Document 1] includes a signal storage unit for providing an external computer, receiving an analog input signal such as a system input, converting it into a digital signal and storing it, and a second signal for storing a test digital input signal. It is described that an accumulation unit is provided and these signals are input to a digital arithmetic processing unit to perform a test.

  When simulating, it is necessary to create a model in which there is no difference between the system model and the actual system, and considerable effort is required to create the system model in order to realize the desired conditions. Even if the data recorded at the time of system failure can be used, it is necessary to process the actual recorded waveform with a personal computer etc. and use a test facility that can output the waveform data to an amplifier etc. Labor is required for processing of test equipment and waveform data.

  Therefore, in order to perform verification by the comprehensive operation test when the relay algorithm or sequence logic is changed or modified, it is necessary to pay considerable effort not only to prepare the test equipment but also to prepare the verification conditions.

JP-A-8-317544

  As described above, in order to simulate the transient waveform conditions at the time of a system failure, a large-scale test facility such as a digital simulator or a simulated transmission line facility is required, and labor to adjust the test conditions suitable for the system is required. Therefore, considerable cost is required to verify the arithmetic algorithm and sequence logic. This is the same not only when relays are developed, but also when arithmetic algorithms and sequence logic are modified.

  Furthermore, after the device was installed in the actual system, the implementation of the comprehensive operation test on site was limited due to the problems of equipment and time constraints as described above.

  An object of the present invention is to provide a digital power protection relay device having a test function capable of performing relay operation, sequence logic verification, and comprehensive operation test by simulating a system failure without a special tester. It is in.

  Another object of the present invention is to provide a comprehensive operation test function by simulating a system failure as a function of the relay device without special equipment, so that confirmation by the relay operation and the comprehensive operation of the sequence logic can be easily performed. An object of the present invention is to provide a power digital protection relay device having a test function.

  Still another object of the present invention is to provide a power digital protection relay device having a test function that can be easily verified in a short time when the relay algorithm is changed or the sequence logic is changed.

  Still another object of the present invention is to provide a recording function reproduction function (playback function) at the time of an actual system failure so that it can be easily verified for a complex system failure. It is to provide a digital protection relay device.

  In order to achieve the above object, a digital power protection relay device having a test function of the present invention is a memory in which input conditions such as voltage waveform and current waveform data at the time of a system failure and equipment conditions on the system side are written in advance. Is installed inside the digital relay, and a changeover switch that can be switched from the outside is provided so that either the analog input amount taken in from the system side or the waveform data written in the memory can be read, and the relay device can be verified. In the case of implementation, the changeover switch is switched to the waveform data memory side, the waveform data written in the memory is sequentially read out at the sampling period of the protection relay, and the operation of the relay is performed according to the read data. This is the same as when a current or voltage waveform simulating a system failure is applied from the outside using a simulated transmission line, etc. It is obtained as results are obtained.

  The change-over switch may be configured to be switched by software control in a test setting or the like of the human interface unit of the protective relay, or may be switched by a hardware switch provided in the relay device.

  The waveform data writing memory may be a removable portable memory or a memory fixed on the substrate.

  Even if the changeover switch is provided between an A / D converter that converts an analog quantity into a digital quantity and a relay computation section such as a microprocessor, the software switch is performed in the middle of the computation section, for example, after digital filter processing is performed. The current and voltage data may be implemented by software in a processing part for transferring the current and voltage data to the arithmetic unit of the relay algorithm.

  In addition, when expanding the verification range to hardware such as analog filters and A / D converters that make up a digital relay, a changeover switch is provided in front of the analog filter, and the results read from the memory are converted from digital to analog. The circuit configuration is such that it is converted into an analog signal of a predetermined level through a converter (D / A converter), and is again taken in from the pre-filter stage through a switch. With this configuration, it is possible to verify the relay operation for the waveform data at the time of system failure written in the waveform data memory in advance, including hardware such as an analog filter and an A / D converter.

  In addition, by providing an interface between the waveform data writing memory and the outside, it is easy to write waveform data recorded by other devices or waveform data acquired by simulation or the like to the memory from the outside when an actual system failure occurs. It is possible to verify relay response. In the case where a portable memory is applied, data can be easily moved by attaching and detaching the memory.

  Easily evaluate relay algorithm algorithm or sequence logic by writing typical cases of internal and external failures in the memory in advance and switching them to evaluate the calculation results. It can be implemented.

It is a block diagram of the digital protection relay apparatus which is one Example of this invention. It is a processing flowchart of the analog input data in an analog input part. It is a block diagram which shows the detail of the structural example 1 of the analog input circuit which implement | achieves the protection relay which mounted the failure simulation function of a present Example. It is a block diagram which shows the detail of the structural example 2 of an analog input circuit. It is a circuit block diagram of the analog input part which switches the analog data after A / D conversion. It is a circuit block diagram of the analog input part which employ | adopted portable memory. It is a circuit block diagram of the analog input part which implement | achieved switching of A / D conversion output and waveform data with hardware. It is a circuit block diagram of the analog input part which applies failure simulation data from the front | former stage of an analog filter. It is a figure which shows the example of a data save memory. It is a figure which shows the example of the human interface for a test setting. It is a figure which shows the example of a simulation waveform. It is a figure which shows the example of a test data management table. It is a figure which shows the example of arrangement | positioning of a waveform data memory. It is a flowchart which shows the example of an analog part process flow. It is a figure which shows the example of memory arrangement | positioning of the simulation data of input conditions. It is a figure which shows the example of the simulation data of an input condition. It is a figure which shows the example of the human interface of a reproduction test function.

  An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a configuration diagram of the digital protection relay device of this embodiment.

  The digital protection relay device 1 of this embodiment includes an analog input unit 4 connected to the input converter 3 and the input converter 3, a relay sequence calculation unit 5 connected to the analog input unit 4 via the system bus 2, and An I / O unit 6 is included.

  The input converter 3 is a converter that converts the current and voltage of the system taken in via the PT and CT installed in power equipment such as a transformer and a circuit breaker into a low voltage signal that can be handled by the analog input unit 4. is there.

  The analog input unit 4 is connected to the analog filter 41, the A / D conversion unit 42 connected to the analog filter 41, the digital filter processing unit 43 connected to the A / D conversion unit 42, and the switching connected to the digital filter processing unit 43. The switch 44 includes a memory 45 connected to the changeover switch 44 and a bus interface 46. In the memory 45, input conditions such as voltage waveform and current waveform data at the time of system failure and device conditions on the system side are written in advance.

  The analog signal on the system side converted into a low voltage by the input converter 3 is taken into the analog filter 41. The analog filter 41 has a characteristic of removing unnecessary frequency components. The output of the analog filter 41 is input to the A / D converter 42 and digitized. The digital filter processing unit 43 is realized by software processing by hardware or a microprocessor, and the digital filter processing unit 43 cuts a frequency unnecessary for the digital relay calculation at the next stage or extracts a necessary frequency. . The result is transferred to the relay / sequence operation unit 5 through the bus interface 46 and the system bus 2.

  The relay sequence calculation unit 5 includes a system bus interface 51, a calculation unit 52 connected to the system bus interface 51 via an internal bus 54, and a memory 53. The digital filter processing unit 43 may include the relay sequence calculation unit 5.

  The relay sequence calculation unit 5 reads digital data via the system bus 2. The calculation unit 52 reads the output result of the analog input unit 4 via the system bus interface 51, and performs a relay calculation and a sequence calculation based on the relay calculation result. The external state necessary for the sequence calculation is taken in via the I / O unit 6. The final trip command and display output are also executed via the I / O unit 6.

  The I / O unit 6 is connected to the system bus interface 61 and the system bus interface 61 via an internal bus 64, and includes a DO unit 62 including an auxiliary relay driver and an auxiliary relay, and a DI including a buffer, a photocoupler, and the like. A portion 63 is included. The DO unit 62 and the DI unit 63 may be separated and provided separately.

  The flow of data processing inside the digital relay will be described. Analog information such as voltage and current on the system side is relayed and sequenced via the input converter 3, analog filter 41, A / D converter 42, digital filter processor 43, bus interface 46 and system bus 2. The I / O unit 6 is controlled according to the calculation result.

  FIG. 2 shows a processing flow of analog input data in the analog input unit 4 of the digital relay. An unnecessary frequency component is removed by the analog filter 41, and the result is digitally converted by the A / D converter 42. Further, digital filter processing is performed on the digitally converted data by the digital filter processing unit 43, and the result is passed to the next relay operation unit via the interface unit of the bus interface 46.

  In this embodiment, a memory 45 in which analog waveform data for testing is written is provided in the analog input unit 4, a changeover switch 44 is provided in front of taking in analog input data used for relay calculation, and from the system side during relay operation, Is selected by the changeover switch 44 and relay calculation is performed. When the relay test is set, the changeover switch 44 is switched and the data on the memory 45 side is selectively acquired and the relay calculation is performed. With this circuit configuration, waveform data is read instead of system side data depending on the test conditions, relay operation is performed in the same way as during operation, and the data on the memory 45 is imported as if it was acquired from the system side, and the relay The operation of the relay can be verified by performing the calculation and the sequence calculation.

  FIG. 3 is a block diagram showing details of the configuration example 1 of the analog input circuit that realizes the protection relay in which the failure simulation function of this embodiment is implemented. An analog filter 41, an A / D conversion unit 42, and a digital filter processing unit 43 are provided in series. In the configuration example 1, a changeover switch 44 is provided between the digital filter processing unit 43 and the bus interface 46, a memory 45 for writing test waveform data is provided, and the data to be transferred to the bus interface 46 by the changeover switch 44 is digitally filtered. Either the output of the processing unit 43 or the contents of the test waveform data memory 45 can be selectively switched. The bus interface 46 further passes data to the relay operation unit at the next stage. Test waveform data is written in advance in the test waveform data memory 45.

  During normal relay operation, the changeover switch 44 selects the result of the digital filter processing unit 43 and transfers the analog data fetched from the system side to the relay calculation unit at the next stage. The analog input data processing flow of the analog input unit is performed.

  On the other hand, when the changeover switch 44 is switched to the test waveform data memory 45 side, the relay enters the test mode, and instead of taking in the analog data on the system side, the pre-written waveform data is read and the contents are read. Based on the above, the relay calculation of the next stage is performed.

  In FIG. 3, the changeover switch 44 is provided between the bus interface 46 which is an interface part between the digital filter processing unit 43 and the relay operation unit, but the same applies even if the changeover switch 44 is provided in the preceding stage of the digital filter processing unit 43. Function can be realized.

  FIG. 4 is a block diagram showing details of the configuration example 2 of the analog input circuit. An analog filter 41 and an A / D converter 42 are provided in series, and a changeover switch 44 is provided between the output of the A / D converter 42 and the digital filter processor 43. As in the configuration example 1, the changeover switch 44 selectively switches between the output of the A / D converter 42 and the output of the memory 45 for writing test waveform data, and the digital filter processing unit 43 in the next stage. The circuit configuration is to be transferred to

  FIG. 5 shows a hardware circuit configuration example capable of realizing the analog input unit 4 of this embodiment. The circuit configuration example shown in FIG. 5 is an example realized by a memory fixedly mounted on a substrate. An analog filter 41 for inputting system side information from the input converter in series and an A / D converter 42 for A / D converting the signal are provided, and an A / D converter 42 is provided on this bus via the internal bus 48 of the analog input unit 4. An / D conversion unit 42, a calculation unit 100, a memory 45, a bus interface 46, and an interface 49 for reading and writing memory contents are provided.

  FIG. 6 shows a configuration example of another hardware circuit capable of realizing the analog input unit 4 of the present embodiment. The circuit configuration example shown in FIG. 6 is a configuration example using a portable memory, so-called flash memory card, USB memory, or the like. An analog filter 41 for inputting system side information from the input converter in series and an A / D converter 42 for A / D converting the signal are provided, and an A / D converter 42 is provided on this bus via the internal bus 48 of the analog input unit 4. A / D conversion unit 42, a calculation unit 100, and a bus interface 46 are provided. Further, a portable memory interface 101 and a socket 102 adapted to the physical use of the memory 45 are provided on the internal bus 48, and the waveform data writing memory 45 is connected via the socket 102.

  In the examples of FIGS. 5 and 6, it is assumed that the changeover switch is realized by software, but an example in which the changeover switch is configured by hardware is illustrated in FIG. 7.

  In FIG. 7, a selector 103 that realizes a changeover switch is provided between the output of the A / D converter 42 and the internal bus 48 of the arithmetic unit 100. In this embodiment, the selector 103 selects either the waveform data write memory 45 or the output of the A / D converter 42 and outputs the selected data to the internal bus 48 of the arithmetic unit 100. The read / write interface 49 of the memory 45 has an independent configuration in this example, but may be configured to read the memory 45 via the internal bus 48.

  In the example shown in FIGS. 5, 6 and 7, the configuration for verifying the algorithm of the relay operation and the sequence logic based on the waveform data previously written in the memory is shown. However, an analog filter or an A / D converter is not used. FIG. 8 shows a configuration diagram in the case where the soundness of the included relay system is confirmed.

  In this example, a changeover switch 106 is provided before the analog filter 41. The changeover switch 106 is a circuit that selects either the input signal 107 or the input signal 108 by setting. In this example, the input signal 107 is connected to the output signal of the input converter that takes in the analog input information of the system. Connected to the internal bus 48 of the arithmetic unit 100 are an output of the A / D converter 42, a memory 45 for writing waveform data, a bus interface 46, and an interface 49 for reading and writing memory. A D / A conversion output unit 105 that generates an analog waveform from waveform data is provided on the internal bus 48, and the D / A conversion output unit 105 is connected to an input signal 108 of the changeover switch 106.

  During normal operation, the changeover switch 106 selects the input signal 107 on the system side, and performs a relay operation according to the input information on the system side. On the other hand, in the test waveform application mode, the changeover switch 108 is switched to the input signal 108 side, and the arithmetic unit 100 reads out the waveform data from the waveform data memory 45 in which the test waveform is written in advance. Output from the A conversion output unit 105. The arithmetic unit 100 repeats the process of reading data and giving an output command to the D / A conversion output unit 105 in accordance with the sampling period of the data written in the waveform data memory 45.

  By this processing, waveform data is output from the D / A converter 105 and is again taken into the analog filter 41, the A / D conversion unit 42, and the relay calculation unit 100 via the changeover switch 106, and the relay calculation processing is performed. Is done. By this processing, it is possible to confirm the soundness of the relay system including the analog filter and the A / D converter based on pre-written waveform data.

  FIG. 9 is a diagram illustrating a configuration example of data recorded in the memory 45. As shown in FIG. 9, the sampled input electric quantity is arranged in time series in the recording data, and the state of the relay, the state of the circuit breaker, and the like are recorded.

  FIG. 10 shows an example of a test setting screen in the protection relay device. A human interface as shown in FIG. 10 is provided, and the changeover switch 44 is switched from the system side to the memory 45 side on the condition that the comprehensive operation simulation item 71 is selected on the setting 72 side.

  Further, by providing a simulation selection function like the simulation case selection 80, it is possible to simulate a plurality of predetermined failure cases such as an internal failure and an external failure.

  FIG. 10 shows a state where Case 1 (74) is selected. Since the system failure waveform data prepared in the memory 45 has a finite simulated failure time, a simulation start trigger signal is required. This trigger signal may be a switch on the human interface or a hardware switch, and may also use the selected condition of the setting 72 or case 1 (74).

  FIG. 12 shows a data table for managing test data. Test data 1 (91) means data of case 1, and for test data 1 to test data N, the data start address 92 on the memory 45, the number of data samples 93, and other management information 94 are stored. Yes.

  FIG. 13 shows an example in which actual waveform data is stored in the memory. Waveform data 1 (121) is the waveform data area of case 1. The waveform data may be arranged in a regular time series, but in this example, the waveform data is stored in order from the memory address 131.

  FIG. 11 shows an example of a simulated waveform. The instantaneous values of the waveforms are stored in the memory as shown in FIG. 13 with the sampling points 142, 143 and 144 and the time of one sampling period Δt in order from the sampling point 141.

  In this example, the data at the sampling point 141 is stored in the memory address 131, and the sampling point 142 is stored in the memory address 132, and so on. Further, the memory address 131 as the first data is stored in the data start address 92 in the data table shown in FIG.

  With this configuration, by reading the data start address corresponding to the selected test data case, the top memory address of the waveform data can be acquired. Furthermore, by storing the number of samples of data forming the simulated waveform in the management information 94 in the management table shown in FIG. 12, it is possible to specify the number of times of reading when performing the failure simulation.

  With this configuration, it is possible to equip a plurality of test cases whose simulated fault data length is not constant. In consideration of the case where the sampling period of the digital relay and the sampling period of the waveform data are not the same, the management table shown in FIG. If the sampling period does not match, various data can be used by thinning out the waveform data. As the management information, use for gain and offset correction is also conceivable.

  FIG. 14 shows an example of a processing flowchart for realizing the simulated failure function of this embodiment. FIG. 14 representatively shows a processing flowchart in the case of implementing the analog input circuit configuration shown in FIG. 1, and shows a series of processing that is performed by a digital relay at a constant cycle, usually at a sampling cycle.

  In step 151, analog data read processing is started. Conventionally, the data read processing of the A / D converter from step 153 is performed, but in this embodiment, it is determined in step 152 whether or not the mode is the comprehensive operation simulation test mode.

  By this determination, it is determined whether or not the changeover switch is switched. In the case of normal operation, the process proceeds to step 153 to read the data of the A / D converter, perform the relay operation in step 163, and perform the sequence logic operation in step 164. And the main processing of the relay function unit, which is performed every sampling cycle, is completed.

  If the comprehensive operation simulation test mode is selected, the process does not proceed to the A / D converter read processing in step 153, and in step 154, it is determined whether the simulation test is in progress or before the start.

  If the simulation test has not started, it is determined in step 155 whether a test start trigger has been accepted. As described above, this is configured by human interface settings, external switch conditions, and the like.

  If the trigger has not been received, the process proceeds to relay calculation processing in step 163. In this case, since the waveform data used for the relay calculation is not read out, the relay is in a no-input state.

  When the trigger is accepted, the management information shown in FIG. 12 is acquired in step 156 according to the test case selected in FIG. In step 157, the read address counter is set in accordance with this information. In step 158, data is read out. In step 159, data is transferred to the relay operation unit.

  Step 160 is a part for determining the number of readings, and is a determination part for sequentially reading up to the number of data samples specified in the test data management information. When the waveform data of the selected test case has not reached the end, that is, when the number of samples has not been read, in step 161, the read address is added so as to designate the address of the next sample data.

  In the case shown in FIG. 13, data is sequentially read from the memory address 131 to the memory address 132, the memory address 133, and so on every cycle. In the addition of the read address in step 161, if the sampling period of the waveform data does not match the calculation period of the relay according to the management information 94, it is possible to cope by adjusting the addition value so as to skip reading. It is. On the contrary, when the calculation cycle of the relay is larger than the sampling cycle of the waveform data, or when the sampling frequency is not an integral multiple, it can be dealt with by performing mathematical interpolation processing.

  In step 160, when the number of waveform data samples has been read, the process proceeds to step 162 to finish the simulation test process and wait for the next trigger reception.

  The reproduction test using the data recorded according to the example shown in FIG. 7 is performed by setting the playback mode 211 for performing the selection of the recording data and the reproduction test on the test setting screen shown in FIG. There is no significant difference from the configuration of the comprehensive operation simulation test described above, and the process of reading out from the waveform data memory for failure simulation prepared in advance can be realized by changing to reading out from the recording data memory shown in FIG.

  In the description so far, the configuration in which the analog information on the system side is simulated by the waveform data on the memory has been described, but a method for simulating the ON / OFF information fetched from the system side device and other devices will be described.

  FIG. 16 shows a time chart of the input information to be simulated. Originally, such information is taken from an external device through an input circuit. In the configuration shown in FIG. 1, the data is taken from the DI unit 63. These pieces of input information are used by the calculation unit 52 that performs the sequence logic calculation. In the case of simulating these with the data on the memory 45, like the waveform data, these pieces of information are arranged in the memory 45, and the information acquired from the actual input circuit is switched to the information read from the memory 45, so that the external condition The mock test including can be done.

  FIG. 15 shows an example in which data for realizing the simulated input information shown in FIG. In the example shown in FIG. 16, eight input conditions including the input conditions 191 to 194 are shown. For each sampling period, the information on these eight points is converted into data, prepared on the memory, and assigned to the sampling points 201 to 205, respectively. Similar to the waveform data, this data is read at a sampling period and used for sequence logic calculation instead of an external input condition, thereby realizing a simulation test including the external condition.

  Here, the case where data previously written in the memory for testing is used has been described. However, the data at the time of failure recorded in the memory by the recording function of the protection relay may be used. That is, some digital relays have a data recording function for analyzing the relay operation. By connecting the changeover switch to a data recording memory, recording can be performed when a system failure occurs. It is possible to easily read out the data and reproduce the relay operation at the time of system failure. Further, the memory for writing the system failure data may be configured to be shared with the memory for the data recording function, or may be configured to be arranged individually.

With the above configuration, a digital protection relay having a system failure simulation function and a playback function at the time of system failure can be realized.
According to the present embodiment, typical cases of internal and external failures of the system are written in the memory in advance, and the operation results are evaluated by switching them. Evaluation at the time of change can be easily performed.

  In addition, it is possible to easily verify the overall operation by simulating the system failure in the test at the time of trial operation, and it is possible to easily confirm the external display, connection with other devices, etc. It can greatly contribute to the reduction of man-hours.

  In addition, it is possible to easily reproduce and verify the relay response by simply writing the data saved by another protection relay or oscillo-recording device in the event of a complicated system failure into the memory for waveform reproduction mounted on the protection relay. It can be realized, and the labor of the test equipment can be greatly simplified and the man-hours required for the reproduction test and verification can be greatly reduced.

  Further, by using a portable memory, it becomes easy to transfer data from the protection relay of the data recording source to the protection relay used for the test, which contributes to the improvement of the test efficiency.

  Moreover, the function of reproducing the relay operation can be realized by providing the function of reading the contents of the waveform recording memory at the time of system failure provided in the protection relay as data for relay calculation and operating the relay calculation and sequence logic. This function realizes a relay operation reproduction function when a complicated system event occurs, and is effective not only for relay response analysis but also for response verification of other devices.

41 Analog Filter 42 A / D Converter 43 Digital Filter Processor 44 Changeover Switch 45 Memory 46 Bus Interface

Claims (6)

  An input converter, an analog input unit connected to the input converter, and a relay sequence calculation unit connected to the analog input unit via a system bus, the analog input unit including an analog filter; An A / D converter connected to the analog filter, a digital filter processor connected to the A / D converter, and input of voltage waveform and current waveform data at the time of system failure and equipment conditions on the system side A memory in which conditions are written in advance, and a change-over switch installed at the front stage or the rear stage of the digital filter processing unit, and the relay switch and sequence processing according to the data on the memory by switching the change-over switch by an external command. A digital power protection relay device with a test function for logic processing.   2. The power digital protection provided with the test function according to claim 1, wherein the waveform data existing as data on the memory is read out instead of the analog data fetched from the system side according to the test setting, and the protection relay calculation is performed. Relay device.   2. The power having the test function according to claim 1, wherein the sequence processing is performed by reading the ON / OFF data existing as data on the memory instead of the ON / OFF data fetched from the outside according to the test setting. Digital protection relay device.   2. The test function for performing a protective relay operation according to claim 1, wherein the memory is a removable portable memory including a USB memory and a flash memory, and an interface capable of mounting the portable memory is provided. Power digital protection relay device.   The data at the time of a system failure is recorded in the memory, the recorded data is read out instead of the data on the system side by a test setting, and a playback function for reproducing the relay response at that time is provided. Power digital protection relay device with testing function.   2. Even if the sampling cycle of the waveform data is different from the sampling cycle on the relay side, the operation of the relay is verified by matching the operation cycle of the relay by performing data thinning processing and interpolation. A digital protective relay device for electric power having the test function described in 1.

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