JPH01286721A - Input circuit for digital protection relay, method of inspecting same circuit and digital protective relay with same circuit - Google Patents

Abstract

PURPOSE:To provide a small-sized apparatus to be easily inspected and monitored by filter-calculating a signal fed in a time division manner from means for inputting a predetermined reference signal together with a voltage or current input signal of a power system by calculating means. CONSTITUTION:Signals inA-inN obtained by PT, CT from the voltage, current of a power system are input to a multiplexer MPX3 through folding error preventing filters 1A+1N, and a reference voltage Vref is also input from a reference voltage source 2 to the MPX3. The MPX3 periodically sequentially switches a plurality of inputs to sample-hold it by a sample-holding circuit 4, A/D-converts it by an A/D converter 5, and inputs it to an inner bus 9 through a buffer RAM 6. A digital signal processor DSP 7 calculates data from the bus 9 according to a program of a ROM 8. A calculated result is output to a standardizing bus 12 through a dual-port memory 10 and an interface 11. Thus, the inspection of a relay can be accurately performed faithfully at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital protective relay device, and particularly to a digital signal processing processor (hereinafter abbreviated as DSP) that performs the same digital filter operation on an input signal. and inspection signals.

The present invention relates to a method for inspecting a digital protective relay device that inspects an analog input circuit and a DSP.

[Conventional technology]

Conventionally, digital protection relays have been described in the Journal of the Institute of Electrical Engineers of Japan, Vol. 105, No. 12, p.
8. Hitachi Review VoQ, 61 Na11 (1979-11
) and Japanese Patent Publication No. 62-49809, the input filter consists of an RC active filter, and after filtering, a sample hold (hereinafter abbreviated as S/H) L,, A/D conversion, and a protection relay are used. Performing calculations. For this reason, analog circuits have been inspected and monitored by constantly applying harmonic signals from the front stage of the filter. In addition, high-precision detection voltage is S/H.
Apply from.

I was checking the accuracy of A/D conversion. Furthermore, zero-phase monitoring, reverse-phase monitoring, etc. were performed for inspection and monitoring.

Conventionally, many inspection circuits were added for these inspections and monitoring.

[Problem to be solved by the invention]

In the above conventional technology, the input filter is an RC active filter. In an RC active filter, variations in characteristics of a plurality of filters occur due to initial value deviations of elements constituting the filter.

In addition, characteristics deteriorate due to temperature characteristics and aging of the element. Furthermore, analog circuits are less reliable than digital circuits, so harmonic monitoring, such as the one described above,
It was necessary to add many inspection and monitoring functions such as A/D accuracy monitoring, zero-phase monitoring, and reverse-phase monitoring.

Therefore, since an additional circuit for inspection and monitoring is required, the circuit scale becomes large, and there is a problem that miniaturization is not possible. Furthermore, since adjustments and inspections were required, maintenance-free operation could not be achieved and reliability could not be increased.

It is an object of the present invention to overcome the drawbacks of the above-mentioned prior art, to facilitate inspection and monitoring of the input circuit of a protective relay device, to eliminate maintenance and inspection, and to improve the reliability of a digital protective relay device. The objective is to provide an inspection method that can significantly improve

Another object of the present invention is to provide a miniaturized input circuit for a protective relay device that allows easy inspection and monitoring of the input circuit of the digital protective relay device.

Another object of the present invention is to provide a highly reliable digital protective relay device.

[Means to solve the problem]

The above objectives are as follows: (1) An A/D converter and a digital signal processor (DS) that input analog signals and convert them into digital quantities;
P) is mounted on the same printed circuit board.

After A/D conversion, the DSP performs digital filter calculations for multiple channels in a time-division manner.

(2) Apply a signal serving as a reference voltage to one of the plurality of inputs.

(3) Filter calculations for external input signals and filter calculations for reference voltage signals are processed by the same program.

(4) Only the filter coefficients used in the filter calculation for the reference voltage signal in (3) above are changed, compared with known data, and abnormality detection of the analog input circuit is performed every period of the digital filter.

(5) Furthermore, in the CPU of another printed circuit board, the above (4)
The results calculated using the method shown in 2 are compared with known data to detect anomalies.

As described above, the above objective can be achieved.

In addition, in order to achieve the other objectives mentioned above, a reference signal generation source that generates a reference signal that is input to the input circuit of the digital protective relay device for inspection of the input circuit together with the voltage and current information signals of the power system. It has been established. In addition, a value corresponding to the reference signal is held in the digital signal processor in the input circuit, and the result of filtering this value is D/A converted and output to the multiplexer together with the voltage and current information signals of the power system. /A' converter is installed.

Furthermore, to achieve the other objects mentioned above, an input circuit.

In the input circuit section of the digital protective relay device, which consists of an arithmetic processing section that performs protection calculations and a digital input/output section,
In order to inspect the input circuit, a reference signal generation source is provided that generates a reference signal to be input to the multiplexer together with the voltage and current information signals of the power system.

[Effect]

The DSP uses A/D converted data and filter coefficients to time-divisionally perform digital filter calculations on many channels. At this time, the filter coefficients are made different for external input data and reference voltage data, and the program is be exactly the same.

As a result, since the filter calculation is performed under exactly the same conditions as the channels of external input data and the channels of reference voltage data, inspection can be performed faithfully and with high precision.

Further, since the above inspection is performed every sampling period of the digital filter, the inspection can be completed in a short time, and there is no need to lock the relay, so that processing efficiency can be improved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a digital protection relay device to which the present invention is applied;
In particular, the block configuration of the analog input section is shown.

In FIG. 1, LA, IB, and IN are aliasing error prevention filters for removing signal components of 1/2 or more of the sampling frequency, 2 is a reference voltage source that supplies a reference voltage Vre, 3 is a multiplexer, and 4 is a multiplexer. Sample and hold circuit, 5 is analog/digital converter, 6 is buffer R
AM, 7 is a digital signal processing processor (DSP),
8 is a program ROM (Read Only Memory) for instructions that stores a program for controlling the arithmetic processing unit of the DSP and data input/output;
9 is an internal bus, 1o is a dual port memory 1c that can be accessed from both directions, 11 is an interface circuit, 12
is a standardized bus (VME bus, Multi bus, etc.). In addition, in FIG. 1, inA, inB and in
N is the voltage and current information signal from the power grid. V
rel is a reference signal, which is a DC signal or an AC signal.

Next, the outline of the DSP shown at 7 in FIG. 1 will be explained. Figure 2 shows the block configuration of the DSP. In Figure 2, 21 is an address register that specifies the address of the external memory, 22 is a data register, and 23 is a data register.
AM, 24 is an n-bit x n-bit high-speed parallel multiplier. The high-speed parallel multiplier has input data i to the multiplier.
It multiplies nX and inY during one instruction cycle and outputs the result outZ.

25 is an instruction ROM that stores a program for controlling DSP arithmetic processing and data input/output;
6 is a control circuit that controls interrupts such as external control signals a, b, and C, and 27 is an ALU (Arit
hmetic Logic Unit), which is an arithmetic unit that performs addition and subtraction, etc., 28 is an accumulator, and 29 is a DSP.
internal buses (data bus, address bus).

Incidentally, the instruction ROMs 8 and 25 may be configured to include only one of them.

As mentioned earlier, DSP features include the ability to perform multiply-accumulate operations within one instruction cycle, and pipeline processing, making it possible to process fixed and floating point data. It is possible to realize high-speed numerical operations.

As described above, by using a DSP, it is possible to realize a digital filter that repeats product-sum operations on fixed and floating point data at high speed.

In Fig. 3, which shows the block configuration of a digital filter, (a) is an IIR type (infinite-type).
Extent Impulse Re5ponse) filter, (b) is an FIR type (Finite-exten
t Impulse Re5ponse) filter.

In (a), Xn is the input signal, 31 is the gain coefficient H
132, 33, 34 and 35 are filter coefficients Bl, B2
．． This is a multiplication unit that multiplies Al and A2, respectively. 36
is a delay unit that delays the signal WIl by one time of the sampling period T; 37 is a delay unit that delays the signal wn-i by one time of the sampling period T; 38, 39, 310, and 311 are adders; is the output signal of the filter.

In (b), X 11 is the input signal, 312 is X's
313 is a delay unit that delays X'n-1 by one time; 314, 315, and 316 are multipliers that multiply filter coefficients A'O, A'1, and A'2; 317 and 318 is an adder, and YI is a filter output.

Next, the calculation of the digital filter will be described. Third
The IIR type digital filter shown in (a) of the figure performs the following calculations.

Wn=H−Xn+B l ・Wn−t+B 2 ・Wn
-z =・(1) Y, =W, + A 1 ・W, −Work+
A2.Wn-z-(2)H gain coefficient Al, A2. Bl, B2: Filter coefficients Perform the calculations shown below.

y'n=A O-X'o+A 1 "X'n-1+A
2'X't-z...(3) A' O, A' 1. A' 2: Filter coefficient X'
. -1:X'. -time delay data X' n -z
: Two-time delay data of X'n X'B: Input data Y'n: Output data IIR type and FIR type digital filters can be easily realized by programming with software in DSP. Therefore, it goes without saying that filters of different types and filters of different orders can be arbitrarily configured by software.

Also, taking the IIR type as an example, it has the same configuration as a low-pass filter and a band-pass filter.

Bypass filters, notch filters, low-pass notch filters, bypass notch filters, and all-pass filters can be realized. Below are some examples of equations representing the transfer function of the filter.

In addition, here, the general formula for the transfer function of the second-order filter% formula% Kokote, AO=O, A1=2. Let A2=-1.

(Bypass filter) Here, AO=1. Let A1=-2 and A2=1.

(Notchi filter) Kokote, AO=1. Al=-y, A2=1 In Figure 4,
An overview of the frequency characteristics of various filters is shown.

(a) Low-pass filter (b) Band-pass filter (c) Bypass filter (d) Notch filter (e) Low-pass notch filter (f) Bypass notch filter (g) All-pass filter From the above, digital filters have coefficients Al, A2
．． By changing Bl and B2.

The arithmetic processing is the same, and different types of filters can be easily changed.

Next, the operation of the embodiment of the present invention will be explained.

FIG. 5 is a flow chart for explaining the operation of the embodiment. The following description will be made using the block diagram of FIG. 1 and the flowchart of FIG. 5.

First, data input will be explained.

IA, IB, and IN in Figure 1 are signals inA that transmit the voltage and current of the power system via PT-CT (transformer/current transformer).
, inB and inN.

IA, IB, and IN prevent aliasing errors due to sampling and also act as input buffers and input to the multiplexer shown at 3. Similarly to these operations, the reference voltage Vrez is supplied from the reference voltage source shown in 2.
is input to the multiplexer. The reference voltage may be either a DC signal or an AC signal.

The MPX shown at 3 sequentially switches a plurality of inputs periodically and inputs them to the S/H circuit shown at 4. The S/H circuit is A
In order to increase the accuracy of A/D conversion, analog input data is held during A/D conversion. The A/D converter shown at 5 converts the sampled and held analog signal into a digital signal and inputs it to the buffer RAM shown at 6.

The DSP shown in 7 inputs the input data stored in the buffer RAM 6 and performs calculations based on the program stored in the instruction ROM shown in 8 for controlling the calculation processing of the DSP and the input/output of data.

Next, the processing of the DSP will be explained using FIG.

In FIG. 5, a block 51 performs initial processing, clears the DSP internal RAM 23, and stores the digital filter coefficients as initial data in the DSP internal RAM 23.
Enter 3. In this case, inA, in shown in FIG.
The filter coefficients for filtering B and inN and Vr@t are different, and these coefficients are input into the RAM 23 inside the DSP at the time of initialization.

FIG. 6 shows a memory map of the DSP internal RAM 23.

As shown in FIG. 6, the filter coefficients for A c h "N c h are stored from address B and the filter coefficients for Vretch are stored from address C. Block 52 in FIG. 5 inputs the filter calculation. This block is synchronized with data.

As mentioned earlier, the block 53 in FIG. 5 is a data input section that transfers input data from the memory outside the DSP to the DSP internal RAM 23. The number of input data is stored starting from address A in FIG.

In block 54 of FIG. 5, (1), (2
) and (3). In this block, a filter operation is performed on the signal from the power system of Aeh=Nch, that is, the input inA"inH, using the filter coefficients stored from address B in FIG. 6.

Block 55 in FIG. 5 is a block that performs the same digital filter calculation as block 54 in FIG. 5 on the reference signal V r @t. However, this block 5
5, the filter coefficients stored from address C in FIG. 6 are used for calculation. In other words, the arithmetic processing algorithm and arithmetic processing program are completely the same, only the coefficients are changed, and the data shown from addresses E and F in FIG.
This is data (Wn-1 and Wn-i shown earlier) during the digital filter calculation of etch.

Block 56 in FIG. 5 is a block that determines whether the result of the digital filter calculation of Vrezch is greater than or equal to the allowable value E. That is, if it is smaller than ε, it outputs the data as shown in 58 and waits for input, and if it is larger than ε, then
It is determined that there is an abnormality in the input circuit, and it is checked again in block 57 whether or not it has been repeated n times. Here, as a result of checking,
If this is repeated n times in a row, it is determined that there is a possibility that the input circuit has failed, and the relay output is locked in block 59 to prevent malfunction. Furthermore, the input circuit can be inspected for each sampling of the digital filter, with zero or more input circuit "failure" indications at block 510.

The above is an overview of the processing of the present invention, and it will be further explained in detail using an example of the processing timing of the present invention and an example of input/output waveforms of a digital filter.

FIG. 7 is an example of a processing timing waveform. In FIG. 7, first, by the S/H command shown in (a), S/HL,
Thereafter, A/D conversion is performed according to the A/D conversion command shown in (b), and this data is stored in the buffer RAM 6 shown in (c). Once all the input data and the vrei signal have been A/D converted and stored in the buffer RAM 6, the interrupt signal shown in (d) for activating the DSP is input to the DSP. Upon receiving this interrupt signal, the DSP inputs the input data stored in the buffer RAM to the RAM 23 inside the DSP, as shown in (6). After the input, the DSP performs the same digital filter operation on each input signal and the reference signal V r e i.The coefficients of the digital filters of Ach and Nch are the same, but only the coefficients of Perform digital filter calculation by changing .

After the digital filter calculation, the DSP uses the Vreieh calculation result to detect an abnormality, and outputs the digital calculation result if normal, and failure information if abnormal. These series of operations are repeated every period T, which is the sampling period of the digital filter.

Here, as shown in FIG. 8, a concrete explanation will be given using an example of the input/output waveforms of the digital filter when the reference signal Vrex is a DC voltage.

In FIG. 8, (a) is the reference signal v11, (b
) is an interrupt signal. (C) is an output example when a low-pass filter (LPF) is used as the digital filter operated for inspection. After the LPF is reset, the digital filter operation becomes a step response to the input Vret, but after that, when the gain is 1, the output becomes equal to the input Vre*. The DC component is passed through as is.

That is, if the input circuit operates normally and the filter calculation is performed normally, the output of the LPF will have the same magnitude as Vrez. In this way, by comparing the magnitude of the output of the LPF with the reference voltage value Vret every sampling period and determining whether the result is greater than or equal to the allowable value E,
Input circuits (including digital filters) can be easily checked for abnormalities. Furthermore, since this inspection cycle is the same as the sampling cycle T of the digital filter, abnormality inspection can be performed at a higher speed than ever before.

Note that To in the figure indicates an invalid time during which the present invention cannot be applied due to a delay in the transient response of the digital filter.

FIG. 8(d) is an example of output when a band pass filter (BPF) is used as the digital filter operated for inspection. After resetting like BPFtLPF,
This is a step response to the input V r e i.

After that, the DC component is blocked due to the characteristics of the BPF, so the output becomes 0 during normal operation. Therefore, by comparing the BPF output with the allowable value ε, it is possible to check for abnormalities in the input circuit and digital filter. It is clear that filters for one inspection can be applied not only to LPF and BPF, but also to the above-mentioned notch, bypass, low-pass notch, bypass notch, etc., as long as they can be realized by changing only the filter coefficients. Also, LPF + BP
Combinations like F can also be applied.

Next, as shown in FIG. 9, the case where the reference signal is a sine wave signal will be explained. In FIG. 9, (a) is the reference signal Vrex, and (b) is the digital filter (
This is an example of the output of LPF. A reference signal with a frequency raised to fall within the attenuation range of the LPF is applied. As a result, when the LPF is operating normally, the output amplitude becomes smaller than the allowable value ε, as shown in the figure. Therefore, by monitoring this output amplitude, abnormality can be detected.

FIG. 10 is an example of input and output waveforms when the frequency of the reference signal is set as the passband of the digital filter.

In FIG. 10, (a) is the reference signal Vrez, (b
) is an example of the filter output waveform, (c) is an example of the waveform obtained by full-wave rectification of the filter output, and (d) is an example of the absolute value waveform of the full-wave rectified waveform obtained in (c). That is, if the input circuit and digital filter operations are performed normally, the absolute value will be the known data v1, and the amplitude will also be within the tolerance value ε, as shown in the figure. Therefore, it is possible to detect an abnormality using the following equation.

IVo-V-1≧i...(9)≧
The embodiment described above is the MPX shown in FIG. 1.

This is about abnormality detection in S/H, A/D, buffer memory, and digital filter calculation. Next, in addition to the above,
DSP and ROM shown in FIG.

An example of abnormality detection for RAM and INF will be described.

FIG. 11 is a block diagram showing the second embodiment.

In FIG. 11, the block indicated by a is the same as the block shown in FIG. The block indicated by b is
The entire block of a is inspected. In b, 13 is a general-purpose CPU, and 14 is an instruction ROM for the CPU.
, 15 is an internal bus, 16 is a data RAM, and 17 is an interface circuit.

In this way, since a standardized bus is used, blocks (printed circuit boards) as shown in b can be easily connected and expanded.

Next, the operation of the second embodiment will be explained.

FIG. 12 is an example of processing timing for explaining the operation of FIG. 11. In FIG.

(a) is S/) (command signal, (b) is A/D command signal,
(c) shows the buffer RAM, (d) shows the interrupt signal that activates the DSP, (e) shows the processing content of the DSP, and (f) shows the processing content of the CPU shown at 13 in Fig. 11. Figure 12 is the same as Figure 7 explained in the first embodiment and (a).
, (b), (c) and (d) are similar.

The DSP first inputs A-N and VRet.

Next, a digital filter operation is performed on the input data of AN and V r e i. In this case, A-N and vr
The filter coefficients are different from ei. After the digital filter calculation is completed, the calculation result is output.

The CPU takes in the digital filter calculation result by the DSP via the standardization bus. After inputting data, perform abnormality detection calculation. The abnormality detection calculation is the same as the method described in the first embodiment.

FIG. 13 is a processing flowchart of the second embodiment. In FIG. 13, block 71 is initial processing;
Block 72 is a synchronization process, block 73 is a data input process, block 74 is a digital filter operation of A to Nch, and block 75 is Vrl! Digital filter calculation of ff1eh, block 76 performs data output processing.Up to this point, processing is performed in the DSP, and subsequent processing is performed in the CPU. Block 77 is a data input process, block 78 is an abnormality determination process, block 79 is a confirmation process, and block 71 is a data input process.
0 performs relay output lock processing, and block 711 performs failure information output processing. The processing of each block in FIG. 13 is the same as the processing shown in FIG. 5, so detailed explanation will be omitted.

In the second embodiment shown in FIG. 13, the input circuit (MPX, S/H, A/D, buffer RAM) and the input circuit (MPX, S/H, A/D, buffer RAM) and Not only digital filter calculation but also DS
P, ROM, RAM.

It has the advantage of being able to detect abnormalities including the INF circuit and the INF circuit.

In this way, the digital filter can time-divisionally process data of a plurality of channels using a single program using a DSP, and by changing the coefficients, different types of filters can be easily realized. Therefore, by detecting abnormalities by changing only the coefficients of the filter using a program that performs filter calculations on input signals, the reliability of inspection can be significantly improved, and inspection can be performed easily and quickly.

FIG. 14 is a block diagram showing an applied embodiment of the present invention. In FIG. 14, IA to IC.

The blocks indicated by 3 to 12 are the same as the blocks shown in FIG. 2' is a digital to analog converter. The operation will be explained below.

In FIG. 1, a reference voltage source is provided, but the reference voltage source needs to be highly accurate. Therefore, instead of the reference voltage source, a value corresponding to the reference voltage is set in advance in the DSP, and this value is calculated by the DSP.

This calculation output is D/A converted and input to MPX. With this configuration, an abnormality can be detected by generating all kinds of signals with the DSP and calculating the responses of the digital filter to these signals. Furthermore, since inspection can be performed by, for example, creating a harmonic signal using a DSP, the reliability of inspection can be increased. FIG. 15 shows a memory inside the DSP to show an example of this applied embodiment.
Data to be input to /A is stored in advance, and this data is input to D/A. Other than this, it is the same as 61 and 62 in FIG. 6 shown earlier.

FIG. 16 shows a block configuration of a sine wave generator configured using a DSP. In Figure 16, 91.92 and 9
3 is a multiplication section, 94 and 95 are delay sections, and 96 and 97 are addition sections. In this block, a sine wave can be generated by performing the calculation shown in the following equation.

Yn=B1・Yn-t+ B 24n-z + A O
'Xn...(10) In the above equation, let F be the frequency of the sine wave generator, B be the bandwidth, and T be the sampling period.

B 1 = 2exp(-πB-T) cos(2πF-
T)...(11) B2=-axp(-2πB-T)-
(12) Therefore, it goes without saying that the frequency can be arbitrarily changed by arbitrarily changing the above-mentioned coefficients.

In this way, the sine wave signal is D/A converted and inputted to the MPX, and the frequency of the sine wave is changed and inputted to check the output of the digital filter.

This makes inspection of the digital filter even more reliable. In addition, a highly accurate reference voltage source is not required, making it possible to reduce costs, which is very effective.

A protection relay device including an input circuit to which the present invention is applied will be described.

In FIG. 17, 101 is an input circuit of the present invention, 102
103 is a DI/Do unit that performs digital input/output; 104 is a panel that sets and changes the setting value and displays the setting value and the status of the protection relay device; 105 is a setting interface; 106 is a display interface, 12 is a standardized bus, and is a data and address bus of the protection relay device.

Next, the operation will be explained.

First, voltage and current information signals from the power system are taken into the input circuit shown at 101, converted into digital quantities, subjected to digital filter processing, and the data is transferred to the arithmetic processing section shown at 102. The arithmetic processing section takes in the input data as well as the setting value via the panel shown at 104 and the setting interface shown at 105 for each sampling, and performs a protection calculation as shown in the following equation, for example.

Σ(1,-Z-Vn)1. −Z<K・(13)
n=1 However, 1: Current data V: Voltage data 2: Setting value K: Comparison value calculation processing section compares the comparison value shown in equation (13) above, and then performs sequence processing. and detect accidents.

At the time of the accident, it was shown as 103. It operates to output a trip command signal to the circuit breaker via the digital human output section. In the protective relay shown in FIG. 17, the input circuit 101 can be easily inspected.

〔Effect of the invention〕

According to the present invention, the analog input circuit (MPX, S/H, A/ D and buffer memory) and digital filter calculations can be easily checked, and the following effects are achieved.

(1) Analog input circuits can be inspected and monitored constantly at every sampling period of the digital filter, allowing for faithful and highly accurate inspections.

(2) The additional circuit for inspection that was previously provided is no longer required.
The input circuit of the digital protective relay device and the digital protective relay device can be made smaller, lower in cost, and significantly improved in reliability.

(3) Since inspection and monitoring can be performed automatically for each sampling, there is no need to maintain the analog input section of the protection relay.

(4) Since inspection can be carried out at high speed, inspection of the protective relay system can be completed in a short time, so processing efficiency can be improved and a highly reliable digital protective relay device can be provided.

(5) Since inspection can be performed quickly, there is no need to lock the relay during inspection.

From the above, the merits of practical application are very large.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment of the present invention;
FIG. 3 is a block diagram of the DSP, FIG. 3 is a block diagram of the digital filter, FIG. 4 is a diagram showing an example of the characteristics of the digital filter, FIG. 5 is a processing flow diagram of the first embodiment of the present invention, and FIG. 6 is a diagram showing a memory map of the DSP internal RAM of the first embodiment of the present invention, and FIG. 7 is a diagram showing the memory map of the DSP internal RAM of the first embodiment of the present invention.
FIG. 8 is a diagram showing a waveform example (1) of each part of the first embodiment of the present invention, and FIG. 9 is a diagram showing an example of the waveforms of each part of the first embodiment of the present invention. A diagram showing a waveform example (2), and FIG. 10 shows a waveform example (3) of each part of the first embodiment of the present invention.
), FIG. 11 is a block diagram of the second embodiment of the present invention, FIG. 12 is a diagram showing an example of processing timing of the second embodiment of the present invention, and FIG. 13 is a block diagram of the second embodiment of the present invention. 14 is a block configuration diagram of an applied example of the present invention, FIG. 15 is a diagram showing a memory map of the DSP internal RAM of an applied example of the present invention, and FIG. 16 is a processing flow diagram of the applied example of the present invention. FIG. 17 is a block diagram of a sine wave generator and a diagram of a protective relay device including an input circuit to which the present invention is applied. IA, IB~IN...aliasing error prevention filter, 2.
...Reference voltage source that supplies reference voltage Vre□, 3...
Multiplexer, 4... Sample hold circuit, 5...
... A/D converter, 6... Buffer RAM, 7...
Digital signal processing processor, 8...Instruction 1st color 2nd purpose ■ αbC Fig. 3 (Kyu) 317 31g series, 4 Fig. 5 8 For 8 Kyo Fig. 9 Fig. 10 Fig. 13 Fig. 1 Cow Mouth Figure 15 ICn

Claims (1)

[Scope of Claims] 1. Input means for inputting a voltage or current information signal of an electric power system, reference signal generation means for generating a predetermined reference signal to be input together with the voltage or current information signal, and the input voltage Or, the input of a digital protective relay device comprising time-division signal sending means for time-divisionally sending out a current information signal and a reference signal, and arithmetic means for inputting the signal from said time-division signal sending means and performing filter arithmetic processing. circuit. 2. It has a calculation means for time-divisionally taking in the voltage or current information signal of the power system and performing filter calculation processing, and the calculation means inputs a reference signal together with the voltage or current information signal of the power system, and An input circuit for a digital protective relay device characterized by changing a filter coefficient of a digital filter for a signal and performing a filter calculation. 3. Input means for inputting a voltage or current information signal of the electric power system; time-division signal transmission means for transmitting the input signal in a time-division manner; and inputting signals from the time-division signal transmission means to perform filter calculations. In an input circuit of a digital protective relay device, a D/A converter is provided, and a value corresponding to a preset reference signal stored in the calculation means is outputted from the calculation means. The output value is D/A in the D/A converter.
An input circuit for a digital protective relay device, characterized in that the input circuit converts the converted signal and outputs the converted signal to the input means. 4. In the input circuit of the digital protective relay device according to claim 3, the D/A output to the input means
A digital protective relay device characterized in that the converted value is a value obtained by subjecting the calculation means to a sine wave generation calculation, and converting the sine wave signal, which is the calculation result, into a D/A converter by the D/A converter. input circuit. 5. Input means for inputting a voltage or current information signal of a power system; reference signal generating means for generating a predetermined reference signal to be input together with the voltage or current information signal; and the input voltage or current information signal and a reference. It has a time-division signal sending means for sending out signals in a time-division manner, and an arithmetic means for inputting the signal from the time-division signal sending means and performing filter arithmetic processing, and the arithmetic means is connected via a standardized bus. providing a separate module having at least a CPU connected to it;
An input circuit for a digital protective relay device, wherein the separate module compares a filter calculation result by the calculation means with a predetermined value. 6. Input a predetermined reference signal together with the voltage or current information signal of the power system, change the filter coefficient for the reference signal, perform the same filter calculation with a digital filter, and convert the calculation result to a predetermined value. A method for inspecting an input circuit of a digital protective relay device, the method comprising inspecting an input circuit of a digital protective relay device. 7. A method for inspecting an input circuit of a digital protective relay device, wherein the predetermined reference signal according to claim 6 is an AC reference signal in a pass band or a stop band of the digital filter. 8. A method for inspecting an input circuit of a digital protective relay device according to claim 6, characterized in that the inspection is carried out every time the digital filter is synchronized with sampling. 9. An input means for inputting a voltage or current information signal of the power system, a time division signal transmission means for transmitting the input signal in a time division manner, and a digital filter for inputting the signal from the time division signal transmission means. In an input circuit of a digital protective relay device comprising a calculation means for performing calculation processing, a D/A converter is provided, and a value corresponding to a preset reference signal stored in the calculation means is output from the calculation means. Then, the output value is converted into D/A by the D/A converter.
is input into the time-division signal sending means together with the voltage or current signal information, changes the filter coefficient for the D/A converted value, performs the same calculation as the digital filter, and applies the calculation result to a predetermined value. A method for inspecting an input circuit of a digital protective relay device, which is characterized by comparing and inspecting a value. 10. Input means for inputting a voltage or current information signal of a power system; reference signal generating means for generating a predetermined reference signal to be input together with the voltage or current information signal; an input circuit having a calculation means for inputting and performing filter calculation processing; a calculation processing unit for inputting a set value and the calculation result from the input circuit and performing a protection calculation; and the calculation processing unit, when an accident is detected, A digital protective relay device consisting of a digital input/output section that outputs a trip command signal. 11. An input means for inputting a voltage or current information signal of the electric power system, a calculation means for filtering and processing the input signal, and outputting a predetermined reference signal stored in the calculation means, and an input circuit having a D/A converter that converts a value into a D/A converter and outputs the result to the input means; an arithmetic processing unit that inputs a set value and the operation result from the input circuit and performs a protection operation; and the operation A digital protective relay device consisting of a digital input/output section in which the processing section outputs a trip command signal to the breaker when an accident is detected. 12. Input means for inputting a voltage or current information signal of a power system; reference signal generating means for generating a predetermined reference signal to be input together with the voltage or current information signal; an input circuit having a calculation means for receiving input and performing filter calculation; and another module for comparing the calculation result with a predetermined value; and a digital input/output section in which the arithmetic processing section outputs a trip command signal to the breaker when an accident is detected.