JP2011154537A - Layout device and layout method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout device and a layout method, allowing simple skew adjustment in a clock tree design. <P>SOLUTION: The layout device 1 includes an assumption skew value storage part 141, a delay insertion part 133, and a delay adjustment part 134. The assumption skew value storage part 141 stores a predetermined assumption skew value according to the number of stages of a clock tree. When the assumption skew value is a request skew value or below, the delay insertion part 133 inserts a delay adjustment buffer 206 into a topmost side of the clock tree. The delay adjustment part 134 adjusts delay of the delay adjustment buffer 206 after wiring of the clock tree such that the skew value of the clock tree becomes the request skew value or below. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a layout apparatus and layout method, and more particularly to a layout apparatus and layout method in clock tree design of a semiconductor integrated circuit.

  With the recent increase in frequency of semiconductor integrated circuits, it is required to secure a timing margin between the synchronization circuits. Therefore, it is necessary to reduce the clock skew of the clock tree. However, much design time is spent adjusting the clock skew when designing a semiconductor integrated circuit.

  On the other hand, the structure of the clock tree has been enlarged due to the increase in the number of synchronization circuits accompanying the increase in the scale of the semiconductor integrated circuit. Therefore, more design time is spent adjusting the clock skew. Against this background, there has been an increasing demand (necessity) for adjusting the clock skew of a semiconductor integrated circuit in a short time.

  Patent Document 1 discloses a technique in which a flip-flop included in a clock tree is divided into a plurality of groups and a delay buffer is inserted in the preceding stage of the group so that the circuit scale converges below a threshold value. . After the division, the clock tree is configured so that the number of layers from the clock terminal to which the clock is input to the delay buffer becomes a predetermined number by repeatedly changing the combination of groups and the number of relay buffers.

  At this time, configuring the clock tree means that the relay buffer is used hierarchically so that the delay amount determined by the input capacity and the wiring capacity is equal from the clock input terminal that is the starting point to the block that is the target buffer. Is to configure.

  Patent Document 2 discloses a technique for repeatedly dividing a region where flip-flops are arranged on a semiconductor integrated circuit based on the number of data connection paths, and connecting the flip-flops of the divided regions in a tree shape. Has been.

JP 2006-107206 A JP 2007-123336 A

  However, the delay amount of the clock tree is determined by the number and arrangement positions of blocks including target flip-flops, buffers, trees, and the like. That is, these quantities and arrangement positions are not determined unless the actual layout is arranged and wired, and the difference between the temporary wiring delay time and the actual wiring delay time estimated from the wiring capacity and the input capacity becomes large. In addition, the delay amount after the routing of the path between the two points becomes larger than the difference in the delay time estimated from the placement and routing of the path between the two points even between various paths based on the clock tree structure.

  Therefore, in the technique disclosed in Patent Document 1, the difference between the MAX value and the MIN value of the clock delay difference (hereinafter referred to as skew value) of a plurality of clock paths from the clock terminal to the end of the clock tree is the difference between the semiconductor integrated circuit. If the skew value exceeds the allowable skew value in the timing design (hereinafter referred to as the required skew value), change the number of target blocks to which the relay buffer is connected or change the number of relay buffers, and perform placement and routing again. The clock tree must be built repeatedly until it falls within the required skew value.

  Therefore, the clock path from the clock terminal to the delay buffer is not determined in a single wiring process, and it is necessary to go back to the process of determining the number of stages of the clock tree until the number of stages is limited. As a result, there is a problem that the number of clock tree design steps increases.

  The layout device according to the present invention includes an assumed skew value storage means for storing an assumed skew value determined in advance according to the number of stages of the clock tree, and a maximum value of the clock tree when the assumed skew value is less than or equal to the required skew value. Delay insertion means for inserting delay means on the upper side; delay adjustment means for adjusting the delay of the delay means after wiring of the clock tree so that the skew value of the clock tree is equal to or less than the required skew value; Is provided. With such a configuration, it is not necessary to change the clock tree structure for delay adjustment after the clock tree is wired, so that the wiring process can be reduced.

  The layout method according to the present invention refers to a presumed skew value determined in advance according to the number of stages of the clock tree, and when the assumed skew value is equal to or less than the required skew value, delay means is provided on the uppermost side of the clock tree. The delay of the delay means is adjusted after wiring of the clock tree so that the skew value of the clock tree is equal to or less than the required skew value. Thus, the skew value of the clock tree can be adjusted only by adjusting the delay of the delay means without changing the structure of the clock tree.

  According to the present invention, it is possible to provide a layout apparatus and a layout method capable of performing simple skew adjustment in clock tree design.

1 is a diagram illustrating a configuration example of a layout device according to a first exemplary embodiment. 3 is a flowchart for explaining a layout method according to the first exemplary embodiment; 3 is a detailed flowchart for explaining a layout method according to the first exemplary embodiment; FIG. 3 is a diagram illustrating a table of assumed skew values according to the first exemplary embodiment. 3 is a diagram illustrating a configuration example of a parent clock tree according to the first embodiment; FIG. 3 is a diagram illustrating a configuration example of a clock tree according to the first embodiment; FIG. FIG. 3 is a diagram showing a clock tree wiring process according to the first exemplary embodiment; FIG. 3 is a diagram showing a clock tree wiring process according to the first exemplary embodiment; FIG. 3 is a diagram showing a clock tree wiring process according to the first exemplary embodiment; FIG. 3 is a diagram showing a clock tree wiring process according to the first exemplary embodiment; FIG. 3 is a diagram illustrating a delay distribution of a clock tree in the middle of wiring according to the first exemplary embodiment; FIG. 3 is a diagram illustrating a delay distribution of a clock tree in the middle of wiring according to the first exemplary embodiment; FIG. 3 is a diagram illustrating a delay distribution of a clock tree in the middle of wiring according to the first exemplary embodiment; FIG. 3 is a diagram illustrating a delay distribution of a clock tree in the middle of wiring according to the first exemplary embodiment; FIG. 3 is a diagram illustrating a configuration example of a clock tree after wiring according to the first exemplary embodiment; FIG. 3 is a diagram showing a delay distribution of a clock tree after wiring according to the first exemplary embodiment; FIG. 3 is a diagram showing a delay distribution of a clock tree after wiring according to the first exemplary embodiment; FIG. 3 is a diagram showing a delay distribution of a clock tree after wiring according to the first exemplary embodiment; FIG. 3 is a diagram showing a delay distribution of a clock tree after wiring according to the first exemplary embodiment; FIG. 6 is a diagram illustrating a configuration example of a clock tree after insertion of a delay adjustment buffer according to the first embodiment; FIG. 6 is a diagram showing a change in the delay distribution of the clock tree by the delay adjustment according to the first embodiment. FIG. 6 is a diagram showing a change in the delay distribution of the clock tree by the delay adjustment according to the first embodiment. FIG. 4 is a diagram illustrating a configuration example of a layout device according to a second exemplary embodiment. 5 is a detailed flowchart for explaining a layout method according to a second exemplary embodiment; FIG. 10 is a diagram for explaining an arrangement area according to the second embodiment. FIG. 10 is a diagram illustrating a table of assumed skew values according to the second exemplary embodiment. 10 is a flowchart for explaining a layout method according to the third exemplary embodiment; FIG. 10 is a diagram illustrating a clock tree wiring process according to the third exemplary embodiment; FIG. 10 is a diagram illustrating a clock tree wiring process according to the third exemplary embodiment; FIG. 10 is a diagram illustrating a clock tree wiring process according to the third exemplary embodiment; FIG. 10 is a diagram illustrating a clock tree wiring process according to the third exemplary embodiment; FIG. 10 is a diagram illustrating a delay distribution of a clock tree in the middle of wiring according to the third exemplary embodiment; FIG. 10 is a diagram illustrating a delay distribution of a clock tree in the middle of wiring according to the third exemplary embodiment; FIG. 10 is a diagram illustrating a delay distribution of a clock tree in the middle of wiring according to the third exemplary embodiment; FIG. 10 is a diagram illustrating a delay distribution of a clock tree in the middle of wiring according to the third exemplary embodiment; FIG. 10 is a diagram illustrating a configuration example of a clock tree after wiring according to the third exemplary embodiment; FIG. 10 is a diagram showing a delay distribution of a clock tree after wiring according to the third embodiment; FIG. 10 is a diagram showing a delay distribution of a clock tree after wiring according to the third embodiment; FIG. 10 is a diagram showing a delay distribution of a clock tree after wiring according to the third embodiment; FIG. 10 is a diagram showing a delay distribution of a clock tree after wiring according to the third embodiment; FIG. 10 is a diagram illustrating a configuration example of a clock tree after delay adjustment according to the third exemplary embodiment; FIG. 10 is a diagram illustrating a delay distribution of a clock tree after delay adjustment according to the third exemplary embodiment; FIG. 10 is a diagram illustrating a delay distribution of a clock tree after delay adjustment according to the third exemplary embodiment; FIG. 10 is a diagram illustrating a delay distribution of a clock tree after delay adjustment according to the third exemplary embodiment; FIG. 10 is a diagram illustrating a delay distribution of a clock tree after delay adjustment according to the third exemplary embodiment;

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. A configuration example of the layout apparatus 1 according to the present embodiment is shown in FIG. The layout device 1 includes a keyboard 11, a mouse 12, a processing device 13, a storage device 14, and a display device 15.

  The keyboard 11 includes character keys, numeric keys, function instruction keys, and the like, and performs various key inputs. The mouse 12 inputs position data indicated by the mouse cursor. The input device such as the keyboard 11 and the mouse 12 inputs an instruction for calculating the skew of the input clock signal of the logic circuit and an instruction for verifying the skew calculation result of the clock signal.

  The processing device 13 is a microcomputer including a CPU (Central Processing Unit) 131, a memory 132, and the like. The CPU 131 and the memory 132 include, for example, a ROM (Read Only Memory), a RAM (Random Access Memory), and the like. The processing device 13 controls the entire device, performs processing for calculating the skew of the clock signal, stores the clock signal skew calculation result in the storage device 14 in a file format, and is stored in the storage device 14. A process for reading the skew calculation result of the clock signal being read into the internal memory, a process for causing the display device 15 to display the skew calculation result of the clock signal, and the like are performed.

  The processing device 13 also performs a delay insertion unit 133 for inserting a delay buffer, a delay adjustment unit 134 for adjusting a delay time by the delay buffer, a tree division unit 135 for dividing the clock tree from the parent clock tree, and wiring of the clock tree A wiring unit 136 is also provided.

  The storage device 14 includes an assumed skew value storage unit 141. The assumed skew value storage unit 141 is, for example, an HDD (Hard Disk Drive) or a RAM, and stores a skew calculation result of a clock signal, a clock tree performance evaluation result, and the like. The display device 15 is a display device such as a CRT (Cathode Ray Tube) or an LCD (Liquid Crystal Display), and displays a skew calculation result of clock signals, various messages, and the like.

  Next, the layout method according to this embodiment will be described. FIG. 2 shows a flowchart for explaining the layout method. First, data necessary for laying out a clock tree is input using the keyboard 11 or the like of the layout device 1 (step S101). As the data input at this time, for example, information such as net information, product information, a clock tree performance evaluation result, and a required skew value (MIN, MAX) is input.

  Next, based on the input data, the processing device 13 determines the structure of the clock tree (step S102). FIG. 3 shows a detailed flowchart of step S102.

  First, the processing device 13 determines the number of driveable FFs (flip-flops) determined from the drive capability of the CTS buffer (hereinafter referred to as drive buffer) based on the net information and product information input in step S101. Obtained as F (step S1021).

  Next, the processing device 13 obtains the number n (the number of drive means) of the drive buffers necessary for the terminal side of the clock tree (before the flip-flop) by n = total number of connected FFs / F (step S1022). For example, if the total number of FFs connected to one target clock domain is 320 and the number of FFs that can be driven by the drive buffer is 20, the number of drive buffers n required on the end side of the clock tree is n. = 320/20 = 16.

  When the number of drive buffers is determined, the processing device 13 determines the number of stages (number of hierarchies) of the parent clock tree (step S1023). For example, if the clock tree is a two-branch clock tree with one start point and n end points, the number of stages of the drive buffer and the relay buffer constituting the clock tree, that is, the number of stages of the parent clock tree is m−. 1 = logn, that is, m = (logn) +1. At this time, the parent clock tree means a configuration of a temporary clock tree that is not arranged and routed and is not divided in the subsequent steps. Further, the relay buffer means a buffer provided in the preceding stage of each branch point of the clock tree.

  The bottom of the log corresponds to the number of branches of the clock tree. In the above example, the bottom of the log is 2 because of the two-branch structure. As shown in the above example, when the number of relay buffers required on the terminal side is 16, the number m of stages of the parent clock tree is determined as m = 5 stages according to the following equation.

  Next, the processing device 13 reads the clock tree performance evaluation result stored in the assumed skew value storage unit 141, and assumes a skew value corresponding to the number m of clock tree stages (hereinafter referred to as an assumed skew value) dt. Is obtained with reference to the clock tree performance evaluation result (assumed skew value table) in FIG. 4 (step S1024). As shown in the above example, when the number m of clock tree stages is 5, the assumed skew value dt is 400 ps from the table of FIG. The clock tree performance evaluation result is arbitrarily set based on the evaluation results in the clock tree design.

  When the assumed skew value corresponding to the number m of clock tree stages is determined, the processing device 13 compares the assumed skew value dt with the requested skew value (step S1025). Here, the required skew value means a delay time allowed for the designed clock tree. If the assumed skew value dt is larger than the required skew value, the processor 13 decrements the number m of clock tree stages by assuming that the assumed two-branch structure clock tree does not satisfy the required skew value (step S1). S1026) Based on the clock tree stage number m after subtraction and the clock tree performance evaluation result, the assumed skew value dt is obtained again (step S1024).

  As shown in the above example, when the required skew value is 250 ps when the number of clock tree stages m = 5 and the assumed skew value dt = 400 ps, the assumed skew value dt becomes larger. Therefore, the processing device 13 subtracts one stage of the clock tree and obtains an assumed skew value dt = 300 ps in the case of m = 4 in step S1024. Then, the assumed skew value dt and the requested skew value are compared again (step S1025). This time, the assumed skew value dt = 300 ps> the required skew value 250 ps, and the assumed skew value dt is larger. Therefore, the processing device 13 further subtracts the number of stages of the clock tree (step S1026), refers to the clock tree performance evaluation result with m = 3, and obtains an assumed skew value (step S1024). As a result, if the number of stages of the clock tree is m = 3, the assumed skew value dt = 200 ps, which is smaller than the required skew value 250 ps, and the process proceeds to the next step S1027.

  Next, based on the number n of relay buffers and the number m of relay buffers obtained in step S1023, the tree dividing unit 135 obtains the division number J for dividing the target clock domain by the following equation (step S1027). ). Then, the tree dividing unit 135 divides the parent clock tree into a plurality of clock trees based on the number of divisions.

  As shown in the above example, in the target clock domain, when the number of drive buffers n = 16 required for the end of the clock tree having a two-branch structure and the number m of clock tree stages m = 3, J = 16/2 (3-1) Power = 16/4 = 4 divisions. FIG. 5 shows a clock tree (parent clock tree 200) when not divided. Further, FIG. 6 shows clock trees 2001 to 2004 obtained by dividing the clock tree into four parts in order to reduce the skew of one clock tree. Since the skew target is reduced from 320 to 80, the assumed skew value is also reduced.

  At this time, the buffer arranged on the uppermost side of each of the clock trees 2001 to 2004 is referred to as a group buffer 204 (2041 to 2044). The most significant side means the preceding stage side (clock terminal 201 side) of the branch point closest to the clock terminal 201 to which the clock is input among the branch points of the clock tree. The clock tree 2001 is provided with a group buffer 2041. Similarly, a group buffer 2042 is provided in the clock tree 2002, a group buffer 2043 is provided in the clock tree 2003, and a group buffer 2044 is provided in the clock tree 2004. Note that what is connected to the terminal side is not limited to the flip-flop 205 but may be a logic circuit such as a latch or a macro.

  Through the above steps S1021 to S1027, the processing device 13 determines the configuration of the clock tree. Subsequently, returning to the flowchart of FIG. 2, steps after step S103 will be described.

  When the structure of the clock tree is determined, the processing device 13 arranges the buffer of the clock tree (step S103). Then, as illustrated in FIGS. 7 to 10, the wiring unit 136 performs wiring from the flip-flop 205 to each of the group buffers 2041 to 2044 (Step S <b> 104). The skew distributions of the skew values of the clock trees 2001 to 2004 at this time are shown in FIGS. 11 to 14, the horizontal axis indicates the skew value of each path included in the clock tree, and the vertical axis indicates the number of paths having the skew value indicated by the horizontal axis. In step S1025 described above, since the assumed skew value is set to be smaller than the required skew value, the delay distribution curves 301 to 304 of the clock trees 2001 to 2004 are as shown in FIGS. It is within the range of the requested skew value.

  The wiring unit 136 performs wiring from each group buffer 204 to the clock terminal 201 (step S105). FIG. 15 shows the clock tree in which the wiring has been completed in steps S103 to S105. At this time, the wiring from the clock terminal 201 to each of the group buffers 2041 to 2044 is preferably connected in a bundle rather than hierarchically as shown in FIG. That is, the clock terminal 201 and the group buffers 2041 to 2044 are connected via one branch point. Therefore, the number of stages from the clock terminal 201 to the clock trees 2001 to 2004 does not change. Further, the delay amounts applied from the clock terminal 201 to the group buffers 2041 to 2044 are all the same. As a result, it is determined whether or not the number of stages of the entire clock tree is within the limit, and if it is not within the limit, there is no need to reconstruct the tree.

  Next, the processing device 13 calculates the delay time of all paths from the clock terminal 201 to the flip-flop 205 (step S106). Based on the calculation result of the delay time, the processing device 13 detects a clock tree that does not satisfy the required skew value. Specifically, the clock buffer group buffers that exceed the required skew value due to the difference between the temporary wiring and the actual wiring or the added delay from the skew estimation by the wiring in step S105 are stored in the group buffers 2041 to 2044. (Step S107).

  FIGS. 16 to 19 show examples of delay distribution curves of skew values of clock trees 2001 to 2004 in which all the wirings are completed. In FIG. 16, the delay distribution curve 301 of the clock tree 2001 exceeds the required skew value MAX. Similarly, the delay distribution curve 304 of the clock tree 2004 in FIG. 19 is also below the required skew value MIN. On the other hand, the delay distribution curves 302 and 303 of the clock trees 2002 and 2003 satisfy the required skew value. In this case, the group buffer 2041 and the group buffer 2044 are extracted by the processing device 13.

  When the group buffer 2041 and the group buffer 2044 that do not satisfy the required skew value are extracted in step S107, the processing device 13 calculates the insertion amount of the delay adjustment buffer 206 that satisfies the required value for the group buffers 2041 and 2044. (Step S108). Note that the delay adjustment buffer 206 (corresponding to the delay means) means both the high-drive buffer 2061 that shifts in a direction in which the delay time is increased and the delay buffer 2062 that shifts in a direction in which the delay time is delayed. .

  In the above example, in the clock tree 2001, as shown in FIG. 16, the skew of the clock tree exceeds the MAX value of the requested skew value. Therefore, the processing device 13 shifts the delay time in the direction of increasing the delay time without changing the skew of the clock tree 2001, and calculates the insertion amount of the high drive buffer 2061 that satisfies the required skew value. Note that the high drive buffer 2061 is inserted between the input pin of the group buffer 2041 and the clock terminal 201 by the delay insertion unit 133. That is, the delay insertion unit 133 inserts the high drive type buffer 2061 on the uppermost side of the clock tree 2001.

  Similarly, in the clock tree 2004, the MIN value of the requested skew value is exceeded. Therefore, the processing device 13 calculates the insertion amount of the delay buffer 2062 that satisfies the requested skew value by shifting in the direction of delaying the delay time without changing the skew of the clock tree 2004. The delay buffer 2062 is inserted between the input pin of the group buffer 2044 and the clock terminal 201 by the delay insertion unit 133. That is, the delay insertion unit 133 inserts the delay buffer 2062 on the uppermost side of the clock tree 2004.

  Then, the delay adjustment unit 134 inserts the delay adjustment buffer 206 or changes the relay buffer 203 or the group buffer 204 (step S109). That is, the delay adjustment unit 134 adjusts the delay time of the clock tree 2001 or 2004 as a whole. For example, when it is desired to increase the delay time of the entire clock tree, the high drive type buffer 2061 is inserted, and when it is desired to delay the delay time, the delay buffer 2062 is inserted.

  FIG. 20 shows a circuit of the clock tree after the delay adjustment buffer 206 is inserted. As described above, the high drive buffer 2061 is inserted between the input pin of the group buffer 2041 and the clock terminal 201, and the delay buffer 2062 is inserted between the input pin of the group buffer 2044 and the clock terminal 201. The delay adjustment unit 134 adjusts the delay by inserting the delay adjustment buffer 206, but the skew value of each clock tree may be adjusted using a buffer with a variable delay amount.

  FIG. 21 shows the delay distribution of the clock tree 2001 after the delay adjustment, and FIG. 22 shows the delay distribution of the clock tree 2004 after the delay adjustment. In FIG. 21, the delay distribution curve of the clock tree 2001 after the connection of the clock terminal 201 and before the insertion of the delay adjustment buffer 206 is a curve 3011. On the other hand, a delay distribution curve of the clock tree 2001 after connection of the clock terminal 201 and insertion of the delay adjustment buffer 206 is a curve 3012. By inserting the high drive type buffer 2061, the delay time of the entire clock tree 2001 is accelerated. The delay distribution curve 3012 after the high drive buffer 2061 is inserted is within the required skew value range.

  On the other hand, delay adjustment in the clock tree 2004 will be described with reference to FIG. A delay distribution curve of the clock tree 2004 after connection of the clock terminal 201 and before insertion of the delay adjustment buffer 206 is a curve 3041. On the other hand, a delay distribution curve of the clock tree 2004 after connection of the clock terminal 201 and insertion of the delay adjustment buffer 206 is a curve 3042. Similar to the clock tree 2001 in FIG. 21, the delay distribution curve of the clock tree 2004 is moved from the curve 3041 to the curve 3042 by inserting the delay buffer 2062. As a result, the skew of the clock tree 2004 is also within the required skew value range. Therefore, all the delays of the clock tree 2001 to the clock tree 2004 are within the range of the requested skew value by the delay adjustment in step S109. With the above steps, the processing of the layout method according to the present embodiment is completed.

  As described above, in the layout apparatus and layout method according to the present embodiment, the clock tree wiring is performed using the assumed skew value with reference to the clock tree performance evaluation result. Then, when the skew value has an error due to the difference between the temporary wiring and the actual wiring and the required skew value is not satisfied, the error is eliminated by inserting the delay adjustment buffer 206 or the like. Therefore, when the wiring of the clock tree and the insertion of the delay adjustment buffer 206 are completed, the tree structure of the clock tree does not have to be changed for skew adjustment. That is, since the tree structure does not change after wiring, the skew values of the clock trees 2001 to 2004 do not change. As a result, the wiring process from the end of the clock tree to the clock terminal 201 is only required once. Therefore, simple skew adjustment can be performed in a short time only by adjusting the delay adjustment buffer 206 without repeating division and rewiring again after wiring.

  In addition, the configuration including the tree dividing unit 135 can reduce the number of paths in the entire clock tree. Therefore, the number of skew targets is reduced, and the time for calculating the delay time of all paths from the clock terminal 201 to the flip-flop 205 can be reduced.

Embodiment 2
A second embodiment according to the present invention will be described. The layout apparatus 2 according to the present embodiment illustrated in FIG. 23 includes a circuit area detection unit 137 in addition to the configuration of the layout apparatus illustrated in FIG. Since other configurations are the same as those of the layout apparatus 1, description thereof is omitted.

  Next, the layout method according to the present embodiment will be described with reference to the flowchart of FIG. The flowchart shown in FIG. 24 includes step S201 in addition to the flowchart shown in FIG. 3, and includes step S202 instead of step S1024. First, as described in the first embodiment, input data such as net information, product information, clock tree performance evaluation results, required skew values (MIN, MAX), and the like are input using the keyboard 11 or the like (step S101). . At this time, in this embodiment, cell arrangement information is further input. The cell arrangement information is information indicating how a logic circuit such as a flip-flop is arranged on a cell.

  Next, the circuit area detecting unit 137 calculates the flip-flop arrangement area S of the clock tree to be designed based on the cell arrangement information (step S201). A method for calculating the arrangement area S will be described with reference to FIG. When the X coordinate and the Y coordinate of the cell arrangement information of the flip-flop to be connected to the clock tree are (X, Y), the range represented by (Xmax−Xmin) × (Ymax−Ymin) is the arrangement area. S. In FIG. 25, an area of (Xmax−Xmin) × (Ymax−Ymin) on an IC (Integrated Circuit) chip 401, that is, S2 corresponds to the arrangement area S.

  The subsequent steps S1021 to S1023 are the same as those in the first embodiment. That is, the number F of flip-flops 205 that can be driven by the drive buffer 202 is obtained (step S1021), and the necessary number of drive buffers 202 is obtained based on the value of F (step S1022). Then, the number of clock tree stages is determined (step S1023).

  Next, the processing device 13 reads the clock tree performance evaluation result stored in the assumed skew value storage unit 141. Then, based on the layout area S detected by the circuit area detection unit 137 in step S201 and the number of stages m determined in step S103, the clock tree performance evaluation result is referred to and an assumed skew value dt is obtained (step S202). Specifically, the processing apparatus 13 estimates the assumed skew value dt with reference to a table as shown in FIG. The table shown in FIG. 26 is an example, and the present invention is not limited to this.

  For example, assuming that the number of stages m of the clock tree is 5 and the arrangement area S is S2 square millimeters, the skew value dt assumed under this condition is 400 ps.

  Then, the processing device 13 compares the assumed skew value dt with the requested skew value (step S1025). As a result, when the assumed skew value dt satisfies the required skew value, the tree dividing unit 135 divides the clock tree (step S1027). On the other hand, when the assumed skew value dt does not satisfy the required skew value, the processing device 13 reduces the number m of clock tree stages by one (step S1026), and refers to the clock tree performance evaluation result again to obtain the assumed skew value dt. (Step S202).

  Thus, the determination of the clock tree structure according to the present embodiment is completed (step S102). In addition, since the process after step S102 (step S103-step S109) is the same as that of Embodiment 1, description is abbreviate | omitted.

  As described above, when the layout apparatus 2 and the layout method according to the present embodiment are used, the arrangement area S is added as a parameter when the assumed skew value dt is obtained. As a result, a more accurate estimated skew value dt can be estimated.

Embodiment 3
A third embodiment according to the present invention will be described. Since the configuration of the layout apparatus according to the present embodiment is the same as that of the first embodiment, description of the configuration is omitted. FIG. 27 shows a flowchart of the layout method according to the present embodiment. The layout method according to the present embodiment includes a delay buffer arrangement (step S301) in addition to the layout method of the first embodiment. The layout method according to the present embodiment includes steps S302 to S304 instead of steps S107 to S109 of the layout method according to the first embodiment.

  A layout method according to the present embodiment will be described. Since the process from data input (step S101) to clock tree arrangement (step S103) is the same as that of the first embodiment, description thereof is omitted.

  When the clock tree arrangement is completed, the delay insertion unit 133 arranges the delay buffer 2062 between the clock terminal 201 and the group buffer 204 of each clock tree before wiring (steps S104 and 105) is performed (step S301). ). At this time, the delay insertion unit 133 arranges the number of delay buffers 2062 in which the skew values of the clock trees 2001 to 2004 exceed the requested skew value dt.

  Next, the wiring unit 136 performs wiring from the flip-flop 205 to the group buffer 204 (step S104). As in FIGS. 7 to 10, FIGS. 28 to 31 are diagrams showing the wiring of the clock trees 2001 to 2004. FIG. Also, the delay distribution of the clock trees 2001 to 2004 wired in step S104 and before the delay buffer 2062 is connected is shown in FIGS. At this time, since the delay buffer 2062 is not yet connected, the delay distributions of the clock trees 2001 to 2004 are all within the range of the requested skew value dt.

  Then, the clock terminal 201 and each group buffer 204 are connected via the delay buffer 2062 (step S105). A circuit diagram at that time is shown in FIG. When the wiring is performed in step S105, the delay buffer 2062 causes a delay in the skew values of the clock trees 2001 to 2004.

  The processing device 13 calculates the delay time of all paths from the clock terminal 201 to the flip-flop 205 (step S106). 37 to 40 show the calculated delay distribution curves of the clock trees 2001 to 2004. FIG. As shown in FIGS. 37 to 40, all delay distribution curves 301 to 304 of the clock trees 2001 to 2004 exceed the required skew value MAX due to the delay caused by the insertion of the delay buffer 2062.

  Based on the calculation result of the delay time, the processing device 13 detects a clock tree that exceeds the MAX of the requested skew value, and extracts the group buffer 204 of the clock tree (step S302). In the above example, since the delay distribution curves of all the clock trees exceed the required skew value MAX, all the group buffers 2041 to 2044 are extracted.

  Then, the processing device 13 calculates a delay amount that exceeds the MAX of the requested skew value, and calculates a deletion amount of the delay buffer 2062 based on the calculation result (step S303). Thereafter, the delay adjusting unit 134 deletes the delay buffer 2062 according to the calculated deletion amount of the delay buffer 2062 (step S304).

  FIG. 41 shows a circuit diagram of the clock tree after the delay buffer 2062 is deleted in the above example. Looking at the delay distribution curve after wiring in step S105, the delay distribution curve 301 of the clock tree 2001 greatly exceeds the MAX of the requested skew value (see FIG. 37). Therefore, the delay adjustment unit 134 deletes three delay buffers 2062. Similarly, the delay distribution curves 302 and 303 of the clock trees 2002 and 2003 do not exceed the required skew value MAX as much as the delay distribution curve 301 of the clock tree 2001 (see FIGS. 38 and 39). The two delay buffers 2062 are deleted from the clock trees 2002 and 2003. Furthermore, since the delay distribution curve 304 of the clock tree 2004 slightly exceeds the required skew value MAX (see FIG. 40), the delay adjustment unit 134 deletes one delay buffer 2062. In this way, the delay adjustment unit 134 deletes the delay buffer 2062 corresponding to the delay amount calculated from the delay buffer 2062 inserted in advance.

  Here, the delay distribution curves of the clock trees 2001 to 2004 after the delay adjusting unit 134 adjusts the delay by deleting the delay buffer 2062 are shown in FIGS. The delay distribution curves 301 to 304 of all the clock trees 2001 to 2004 are within the required skew value range. Thus, the process of the layout method according to the present embodiment is completed.

  As described above, in the layout method according to the present embodiment, the number of delay buffers 2062 exceeding the required delay time is inserted between the group buffer 204 and the clock terminal 201, and the delay buffer 2062 is deleted. Perform delay adjustment. Therefore, in the delay adjustment process of the delay adjustment unit 134, the delay value is not increased and only the delay value is shortened, so that the delay adjustment is determined in one direction. Further, the delay amount to be adjusted is only the delay amount due to the deleted delay buffer 2062 and the divided wiring. As a result, the expected delay reduction amount and the delay reduction amount of the clock tree after delay adjustment coincide with each other with high accuracy, and the number of delay adjustments can be reduced. Therefore, a short delay adjustment is possible.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

1, 2 Layout device 11 Keyboard 12 Mouse 13 Processing device 14 Storage device 15 Display device 131 CPU
132 Memory 133 Delay Insertion Unit 134 Delay Adjustment Unit 135 Tree Division Unit 136 Wiring Unit 137 Circuit Area Detection Unit 141 Assumed Skew Value Storage Unit 200 Parent Clock Tree 201 Clock Terminal 202 Drive Buffer 203 Relay Buffer 204 Group Buffer 205 Flip-Flop 206 Delay Adjustment Buffers 301 to 304, 3011, 3012, 3041, and 3042 Delay distribution curve 401 IC chip 2001 to 2004 Clock tree 2041 to 2044 Group buffer 2061 High drive buffer 2062 Delay buffer

Claims (10)

An assumed skew value storage means for storing an assumed skew value determined in advance according to the number of stages of the clock tree;
When the assumed skew value is less than or equal to the required skew value, a delay insertion unit that inserts a delay unit on the topmost side of the clock tree;
Delay adjusting means for adjusting the delay of the delay means after wiring of the clock tree so that the skew value of the clock tree is equal to or less than the required skew value;
A layout apparatus comprising:   The clock tree is divided from the parent clock tree based on the number of driving means for driving the logic circuit arranged on the terminal side of the parent clock tree and the number of stages of the clock tree corresponding to the number of the driving means. The layout apparatus according to claim 1, further comprising a tree dividing unit.   The layout apparatus according to claim 1, wherein the assumed skew value is a value determined in advance according to an area in which the logic circuit is arranged on a semiconductor substrate in addition to the number of stages of the clock tree. The layout device further includes wiring means for wiring a clock terminal from which a clock is output and the clock tree,
The layout device according to claim 1, wherein the wiring unit performs wiring so that the clock terminal and the delay unit are connected through one branch point.   The delay insertion means inserts the delay means before routing the clock tree so that the skew value of the clock tree is larger than the required skew value. Layout equipment. Refer to the assumed skew value determined in advance according to the number of stages of the clock tree,
When the assumed skew value is less than or equal to the required skew value, a delay means is inserted at the top of the clock tree,
A layout method for adjusting a delay of the delay means after wiring of the clock tree so that a skew value of the clock tree is equal to or less than the required skew value. Determine the number of driving means for driving the logic circuit arranged at the end of the parent clock tree,
According to the number of the driving means, determine the number of stages of the clock tree,
The layout method according to claim 6, wherein the clock tree is divided from the parent clock tree based on the number of the driving units and the number of stages of the clock tree.   8. The layout method according to claim 6, wherein the assumed skew value is a value determined in advance according to an area where the logic circuit is arranged on a semiconductor substrate in addition to the number of stages of the clock tree.   The wiring between the clock terminal from which a clock is output and the clock tree is performed so that the clock terminal and the delay means are connected via one branch point. The layout method according to the item.   10. The delay means is inserted in the uppermost side of the clock tree so that a skew value of the clock tree is larger than the required skew value before wiring of the clock tree. 11. The layout method described in 1.

Images