JP5883633B2 - Layout apparatus and layout method - Google Patents

Description

  The present invention relates to a standard cell layout technique, and further to a technique for reducing power consumption in a semiconductor device by reducing an excessive timing margin while complying with a design rule.

  In order to efficiently design a logic scale integration (Large Scale Integration), a standard cell (simply referred to as a “cell”) showing a pattern for realizing a predetermined function is designed for each function in advance, and the circuit to be designed A plurality of standard cells are laid out on the chip according to the functions included in. In addition, a clock tree for distributing clock signals is constructed in the logic LSI. The clock tree is one of logical structures for clock distribution.

  Patent Document 1 describes a technique of repeatedly dividing a region where flip-flops are arranged on a semiconductor integrated circuit based on the number of data connection paths, and connecting the flip-flops of the divided regions in a tree shape. Yes.

  Patent Document 2 describes a technique in which a flip-flop included in a clock tree is divided into a plurality of groups and a delay buffer is inserted at the front stage of the group so that the circuit scale converges below a threshold value. .

JP 2007-123336 A JP 2006-107206 A

  In the implementation of a logic LSI, a layout design considering timing is generally performed. In this case, it is necessary to comply with design rule constraints such as maximum transition (Max_transition) and maximum capacitance (Max_capacitance) in addition to setup and hold timing constraints.

  In a general EDA (Electronic Design Automation) tool for layout design, a technique is used in which a leak area and the like are reduced within a range satisfying timing constraints, and standby and operating power (power consumption) are minimized.

  On the other hand, in the design rule constraint, satisfying it is the highest priority, but in reality, the constraint is realized with a considerable margin. Therefore, in a case where the design rule constraint is satisfied with an excessive margin, it is considered that the power consumption can be further reduced by reducing the margin. Such a situation is not limited to the clock logic implemented by clock tree generation (CTS: Clock Tree Synthesys), but is also the same for data lines that are subject to normal timing optimization.

  The inventor of the present application has studied a margin reduction technique and an actual implementation procedure from the above viewpoint.

  As a good or bad index in clock tree generation (CTS), “low clock skew latency” can be cited. In recent years, “low power consumption” is also an important item, and the clock gating insertion technique is generally used, but clock gating is the propagation of the clock signal itself in the period when there is no change in the data signal. The effect of clock gating is greatly influenced by the logic of the LSI. For this reason, the EDA tool for semiconductor device layout design has a function of deleting a buffer inserted in CTS (and a combinational circuit inserted in advance in the clock logic), a function of deleting a clock area by resizing, and a function of reducing power. It has been. In this case, the selection of cells that can be deleted and resized has the objective function of not deteriorating the skew latency.

  Looking at the design rule constraints, the maximum transition value described in the library depends on the frequency at the time of library characterization. If the LSI frequency is lower than this, the constraint value itself can be relaxed. Is possible. Although the maximum capacitance value is the same, there are many cases in which the maximum capacitance value is actually restricted due to electromigration (EM) restrictions.

  For this reason, in the case of an LSI with a low operating frequency, the maximum transition value and the maximum capacitance value can be relaxed, so that it is possible to drive with a lower driving capability and to route the wiring itself for a longer time. The inventors of the present application have found that by constructing a clock tree based on this relaxation condition, it is possible to reduce the cell area (clock area) of the clock tree and further reduce power consumption.

  Also, in the data logic, as with the clock logic, it is considered that the number of cells can be reduced within the range that satisfies the setup rule hold timing and satisfies the design rule constraints.

  An object of the present invention is to provide a technique for reducing power consumption in a semiconductor device by reducing an excessive timing margin while complying with a design rule.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, a memory device capable of storing information related to cell layout in a semiconductor device, and a clock tree for generating a clock tree for distributing a clock signal to each unit in the semiconductor device are generated by referring to the information in the memory device. The layout device includes an arithmetic processing device capable of executing arithmetic processing for reducing an excessive timing margin in the clock tree. The arithmetic processing unit includes: a first process for determining whether or not a transition constraint and a capacitance constraint on the clock line have a margin; and a size of a clock buffer in the clock line according to a determination result in the first process. A second process for down or deletion is executed. The arithmetic processing unit is configured to determine whether or not power reduction is possible by reducing or deleting the size of the clock buffer in the second process, and depending on a determination result in the third process, A fourth process for adjusting the size of the clock buffer is executed.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, power consumption in the semiconductor device can be reduced by reducing an excessive timing margin while observing the design rule.

1 is a block diagram illustrating a configuration example of a layout device according to the present invention. It is a flowchart which shows the whole flow of the process performed with the arithmetic processing unit in the layout apparatus shown by FIG. It is a detailed flowchart of the clock tree generation process in FIG. 3 is a detailed flowchart of timing margin reduction processing in FIG. 2. It is a detailed flowchart of the data line optimization process in FIG. It is explanatory drawing of the load distribution by a timing gating cell. It is explanatory drawing of the maximum capacitance restriction | limiting of a buffer. It is explanatory drawing of the relationship between the drive capability of a buffer, the charge / discharge current of a buffer, and a through current. It is explanatory drawing of size adjustment of a clock buffer. It is explanatory drawing of size adjustment of a clock buffer. It is explanatory drawing of clock gating cell optimization. It is explanatory drawing of clock gating cell optimization. It is explanatory drawing of data line optimization.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A layout device (10) according to a typical embodiment of the present invention refers to a storage device (13) capable of storing information related to cell layout in a semiconductor device, and information in the storage device. And an arithmetic processing unit (12) capable of generating a clock tree for distributing a clock signal to each part in the semiconductor device and executing arithmetic processing for reducing an excessive timing margin in the generated clock tree. .

  The arithmetic processing unit performs a first process (S71) for determining whether the transition constraint and the capacitance constraint on the clock line have a margin, and a clock in the clock line according to a determination result in the first process. A second process (S72) for reducing or deleting the buffer size is executed. In addition, the arithmetic processing unit determines whether the power reduction is possible by reducing or deleting the size of the clock buffer in the second process (S73), and the determination result in the third process. Accordingly, a fourth process (S74) for adjusting the size of the clock buffer is executed.

  According to the above configuration, an excessive timing margin can be reduced, and power consumption in the semiconductor device can be reduced by reducing or deleting the size of the clock buffer. Further, the excessive timing margin is reduced by checking the maximum transition and the maximum capacitance and within a range that satisfies the constraint value, and the design rule is observed.

  [2] In the above [1], the arithmetic processing unit determines whether or not there is a margin in the timing of the clock signal transmitted through the clock gating cell after the size adjustment of the clock buffer in the fourth process. And a sixth process (S76) for reducing or reducing the size of the clock gating cell according to the determination result in the fifth process. it can. Thus, by optimizing the clock gating cell, the power consumption in the semiconductor device can be further reduced.

  [3] In the above [2], on the assumption that the setup / hold timing is satisfied, the arithmetic processing unit is configured so as to satisfy the transition constraint and capacitance constraint on the data line. It can be configured to execute the process (S4) for optimizing the data line by minimizing the size. Thus, by optimizing the data line, the power consumption in the semiconductor device can be further reduced.

  [4] In the above [3], the arithmetic processing unit determines whether or not power reduction is possible (S407), and optimizes the data line based on the determination result (S404, S405). Can be configured. By determining whether or not power reduction is possible, the data line can be optimized appropriately.

2. Details of Embodiments Embodiments will be further described in detail.

Embodiment 1
FIG. 1 shows a configuration example of a layout apparatus according to the present invention.

  The layout device 10 shown in FIG. 1 is configured using a computer system including a display device 11, an arithmetic processing device 12, a storage device 13, and an input device 14. The storage device 13 is a hard disk device using, for example, a magnetic disk as a recording medium. The storage device 13 stores various programs and various information used for the layout of the semiconductor device. Various information used for the layout of the semiconductor device includes a net list and a library. The arithmetic processing unit 12 includes a microcomputer capable of executing a program for automatic placement and routing (Plaace and Route) processing, and its peripheral circuits. The processing in the arithmetic processing circuit 12 includes construction of a clock tree for distributing the clock signal to each part in the semiconductor device and adjustment of clock skew between the clock trees. In the layout device 12, a netlist or library in the storage device 13 is referred to as necessary. The input device 14 includes a keyboard and a mouse, and is used for inputting various information related to the layout processing of the semiconductor device. The display device 11 is a liquid crystal display or the like, and can display various information related to the layout processing of the semiconductor device.

  In a semiconductor device such as a logic LSI, a clock tree for distributing clock signals is constructed. The clock tree is one of the logical structures for clock distribution, and multiple delay elements are used to minimize the variation in clock arrival time (clock skew) from the clock logic start point to the flip-flop circuit in the semiconductor device. Is built in a tree shape.

  FIG. 2 shows the overall flow of the automatic placement and routing process executed by the arithmetic processing unit 12. In this automatic placement and routing process, automatic placement and routing of cells is performed according to the net list of the semiconductor device.

  First, the arithmetic processing unit 12 reads a net list in the storage device 13 (S1), and a floor plan is formed based on the net list (S2). Then, cell placement is performed using the created floor plan (S3), and then data line optimization processing is performed (S4). Then, it is determined whether or not there is a timing error (S5). In this determination, if it is determined that there is an error, the floor plan is created again. If it is determined in step S5 that there is no error, clock tree generation processing is performed (S6). Then, in order to reduce power consumption in the semiconductor device, timing margin reduction processing for reducing an excessive timing margin in the clock tree is performed (S7). After the timing margin reduction processing is completed, clock wiring processing is performed (S8). Then, a check is performed to confirm that no rule violation has occurred in the actual load state after the clock wiring (S9). In this check, when it is confirmed that no rule violation has occurred in the actual load state after clock wiring, timing optimization between flip-flop circuits is performed (S10).

  FIG. 3 shows a detailed flow of the clock tree generation process in step S6.

  In the clock tree generation process, various information in the semiconductor device that is the target of the automatic placement and routing process is referred to. The various types of information include clock gating timing information 31, clock gating fan-out information 32, manual arrangement information 33, manual path fine adjustment information 34, and the like, which are stored in the storage device 13. Yes.

  In the clock tree generation process, first, a clock gating timing check is performed based on the clock gating timing information (S61). If there is no margin for clock gating timing, the fan-out information 32 of clock gating is referred to and the number of fan-outs is checked (S62). When the fan-out number is large, it causes timing violation, so load distribution by the timing gating cell is performed (S63). For example, as shown in FIG. 6A, as shown in FIG. 6B, the clock signal is supplied to the large number of flip-flop circuits 63 to 67 from the output terminal of the gating cell 61. Thus, by dividing the load by the gating cells 61 and 62, the fan-out number of the gating cell 61 can be reduced, and the load can be reduced.

  Next, the manual arrangement information 33 and the manual path adjustment information 34 are referred to, and an individual clock countermeasure is performed manually (S64). This individual clock countermeasure includes division of the clock path, fixation of the clock path, and fixed arrangement of the cells. As a specific example, the transmission path of an asynchronous clock input from the outside is divided into an external output path and a transmission path to a flip-flop circuit, or when the operation takes two cycles, such as a flash module. Clock latency is adjusted. If it is determined that there is “room” in the clock gating timing check in step S61, or if “fan out is small” in the fan out check in step S62, the above steps are performed. The individual clock countermeasure of step S64 is performed without performing load division of the clock gating cell of S63.

  After the individual clock countermeasure in step 64, the clock tree structure is constructed (S65), and the clock skew in each clock domain is adjusted (S66). Here, the “clock domain” refers to a circuit area driven by a clock input. In adjusting the clock skew, a buffer or an inverter is inserted in the clock transmission path. Then, a frequency check in each clock domain is performed (S67). When the clock domain is a high-speed system, the clock tree generation process (S6) is terminated after delay adjustment between the clock domains is performed. When the clock domain is a low speed system, the clock tree generation process (S6) is terminated without adjusting the delay between the clock domains in step S68 in order to reduce simultaneous switching noise.

  FIG. 4 shows a detailed process flow of the timing margin reduction process (S7) in FIG.

  In this timing margin reduction process, the clock tree generation result (CTS result) 41 in step S6, transition information 42 of each clock net, capacitance information 43 of each clock net, power information 45, and timing information 31 are referred to. It is assumed that these pieces of information are already stored in the storage device 13 when the timing margin reduction process (S7) is started. By referring to the transition information 42 of each clock net, the maximum transition constraint value of each clock net can be known. Further, the maximum capacitance constraint value of each clock net can be known by referring to the capacitance information 43 of each clock net. Here, the maximum transition constraint value and the maximum capacitance constraint value are obtained as follows.

  That is, the target frequency is determined, and the maximum transition constraint value corresponding to the target frequency is determined. For each cell, the maximum capacity satisfying the maximum transition constraint value is obtained. Then, the upper limit of the maximum capacitance due to the EM constraint (a uniform value for each frequency) is compared with the maximum capacity satisfying the maximum transition constraint value, and the stricter value is defined as the maximum capacitance constraint value.

  FIG. 7A shows an example of the maximum capacitance constraint value of the buffer. In this example, the target frequency is 300 MHz, the transition constraint value is 0.8 ns, and the EM constraint upper limit value is 0.8 pF. When the target frequency is determined, the maximum transition corresponding to the target frequency is determined, and the maximum capacity value that satisfies this maximum transition is determined for each cell. The maximum capacitance value is compared with the EM constraint upper limit value, and the stricter value is set as the maximum capacitance constraint value. In the example of FIG. 7A, the maximum capacity satisfying the maximum transition constraint value is set as the maximum capacitance constraint value up to the buffers BUF1X to BUF4X. However, in the case of the buffers BUF8X to BUF32X, the EM constraint is more severe. The EM constraint upper limit value is set as the maximum capacitance constraint value. As a result, as shown in FIG. 7B, the maximum capacitance constraint value is increased according to the drivability of the cell, but from a certain drivability, it is uniform regardless of the cell.

  Therefore, in the timing margin reduction process (S7), first, the CTS result 41, the transition information 42 of each clock net, and the capacitance information 43 of each clock net are referred to, and the maximum transition and the maximum capacitance are checked (S71). ). If it is determined in this check that there is a margin in the maximum transition and the maximum capacitance, the size of the clock buffer is reduced or the clock buffer is deleted within a range that satisfies the constraint value (S72). That is, the size of the clock buffer is minimized within a range that satisfies the constraint value, and the buffer is reduced as necessary.

  Here, the size of the clock buffer can be reduced by reducing the number of MOS transistors connected in parallel or by reducing the ratio between the gate width and the gate length of the MOS transistors.

  Although the cell power is reduced by reducing or deleting the size of the clock buffer in step S72, it is conceivable that the charge / discharge current increases due to an increase in net capacity. Therefore, the power check is performed with reference to the CTS result 41 and the power information 45 (S73). In this power check, the total value of the charge / discharge current and the through current of the buffer is obtained, and a combination that minimizes the power (total power) based on the total value is selected. For example, as shown in FIG. 8A, when the output clock of the buffer B1 is distributed to the buffers B2, B3, and B4, as shown in FIG. This is because the charge / discharge current of the buffer B1 and the through current of the buffers B2 to B4 differ depending on the drivability (driving ability). For example, when the drivability of the buffer B1 is large, the discharge current of the clock buffer B1 is large, but the through current of the buffers B2 to B4 is relatively small. However, if the drivability of the buffer B1 is reduced, the charge / discharge current of the buffer B1 is reduced, but the through current of the buffers B2 to B4 is increased. Therefore, in the power check in step S73, it is necessary to consider the total value of the charge / discharge current and the through current of the buffer.

Here, the total power value Ptotal (B1) of the buffer B1 is expressed by the following equation. Pcell (B1) is the power consumed in the buffer B1, “f” is the frequency, “C _N1 ” is the capacitance of the node N1, and “V” is the voltage.

  If it is determined in step S71 that “there is no margin for maximum transition and maximum capacitance”, the power check in step S73 is performed without reducing the size of the clock buffer.

  If it is determined in the power check in step S73 that “power reduction is possible”, the size of the clock buffer is adjusted according to the determination result (S74).

  9 and 10 show how the size of the clock buffer is adjusted.

  As shown in FIG. 9A, when the drivability of the buffer B1 is “× 16”, the drivability (× 16) of the buffer B1 satisfies the maximum transition and the maximum capacitance, as shown in FIG. As shown in B), the size is reduced to “× 12” (S72). If it is determined in the power check in step S73 that “the power can be reduced”, the drivability (× 12) of the buffer B1 is indicated by “C” in FIG. X8 "is adjusted (S74). Further, as shown in FIG. 10A, when the drivability of the buffer B1 is “× 16” and the drivability of the buffer 3 is “× 8”, the maximum transition and the maximum capacitance are satisfied. The drivability (× 16) of the buffer B1 and the drivability (× 8) of the buffer B3 are respectively reduced in size to “× 12” and “× 4” as shown in FIG. 10B (S72). ). Further, the buffer B5 in FIG. 10A is deleted in a state satisfying the maximum transition and the maximum capacitance. In the clock buffer size adjustment in step S74, the size of the clock buffer may be increased based on the result of the power check in step S73.

  After adjusting the size of the clock buffer in step S74, a timing check for clock gating cell optimization is performed (S75). In the power check in step S73, if it is determined that “power reduction is not possible”, the timing check in step S75 is performed without adjusting the size of the clock buffer. If it is determined in the timing check in step S75 that there is “timing margin”, the clock gating cell is optimized (S76). In this optimization process, the size of the clock gating cell is reduced. In addition, the clock gating cells are reduced by integrating the logically equivalent clock gating cells with sufficient timing.

  11 and 12 show the state of clock gating cell optimization.

  As shown in FIG. 11A, consider a case where the enable signal EN output from the flip-flop circuit FF is transmitted to the clock gating cells G1 and G2 via the inverter 110 and the logic circuit 111. If it is determined in step S75 that “timing margin is available”, the size of the clock gating cell is reduced. For example, as shown in FIG. 11B, the size of the clock gating cell G1 is reduced from “× 16” to “× 8”. Note that it is conceivable that the delay time from the flip-flop circuit FF to the clock gating cell G1 increases because the gating setup time increases due to the size reduction of the clock gating cell. For this reason, in the clock gating cell optimization in step S75, it is determined whether or not there is a setup violation when the size is reduced, and it is determined that there is no setup violation and it is determined that there is “timing margin”. Is done. Further, as shown in FIG. 12A, the clock gating cells G1 and G2 are logically equivalent clock gating cells, and therefore, in the determination of step 75, there is “timing margin”. If it is determined, as shown in FIG. 12B, the clock gating cells G1 and G2 are integrated into one. That is, the clock gating cell G2 is deleted, and the clock signal is distributed through one clock gating cell G1.

  In order to avoid the case where the charge / discharge current increases due to the downsizing of the clock gating cell or the integration of the clock gating cells, the power as in step S73 may be checked in step 75. good.

  FIG. 5 shows a detailed flow of the data line optimization process in step S4 in FIG.

  In the data line optimization process, countermeasures for multiple fan-out nets are taken (S401). With this multi-fan out net measure, physical errors such as the interval between wires and the width of the wires are found. Then, a process for improving the setup / hold timing of the flip-flop circuit in the data line is performed (S402). Then, it is determined whether there is a path having a timing margin (S403). In this determination, if it is determined that “there is a path with timing margin”, it is determined whether or not the buffer size can be reduced (S404). If it is determined in this determination that “the buffer size can be reduced”, the buffer size is reduced or the buffer is deleted (S405). For example, as shown in FIG. 13A, when the size of the buffer B1 is “× 16”, the size of the buffer B1 is reduced to “× 12” as shown in FIG. Further, as shown in FIG. 13C, the size of the buffer B1 is reduced to “× 8”. In step S405, after the buffer size is reduced or the buffer is deleted, the power is estimated (S406), and it is determined whether or not the total power is improved due to the buffer size reduction or the like. (S407). This determination can be performed in the same manner as the power check in step S73 in the timing margin reduction process (see FIG. 4) in the clock tree. If it is determined in step S407 that “total power is improved (YES)”, it is determined whether there is a margin in the DRC (Design Rule Check) constraint (S408). Here, the DRC constraint includes a maximum transition and a maximum capacitance. If it is determined in step S408 that “the DRC constraint has a margin (YES)”, the process returns to the determination in step S404, and the buffer size is reduced again. Further, when it is determined that the buffer cannot be downsized (NO) in the determination in step S404, and when it is determined that the total power is not improved (NO) in the determination in step S407, If it is determined in the determination in step S408 that “the DRC constraint has no margin (NO)”, it is determined whether or not the search for all instances (meaning “cell”) has been completed. (S409). In this determination, if it is determined that the search for all the cells has not been completed (NO), the next cell is selected (S411), and whether or not the buffer size can be reduced for that cell. (S404), buffer size reduction, and buffer deletion (S405). In this manner, when it is determined whether or not the buffer size can be reduced (S404) or the buffer size is reduced or the buffer is deleted (S405) for all the cells, It is determined that the search for all cells has been completed (YES) ", the next timing path is selected, and it is determined whether or not the timing path is a path with a timing margin (S403). If it is determined in step S403 that the path is not a path with timing margin (NO), it is determined whether or not the search for all the paths has been completed (S410). . In this determination, if it is determined that “search for all paths has not been completed (NO)”, the next timing path is selected, and is the timing path having a timing margin? It is determined whether or not (S403). If it is determined in step S410 that "search for all paths has been completed (YES)", the data line optimization process in step S4 is terminated, and step S2 in FIG. A determination is made.

  According to the first embodiment, the following operational effects are obtained.

  (1) In the timing margin reduction process (S7), the maximum transition and the maximum capacitance are checked (S71). If it is determined in this check that there is a margin in the maximum transition and the maximum capacitance, the size of the clock buffer is reduced or the clock buffer is deleted within a range that satisfies the constraint value (S72). Although the cell power is reduced by reducing or deleting the size of the clock buffer in step S72, it is considered that the charge / discharge current increases due to the increase in the net capacity. A power check is performed (S73). If it is determined in the power check in step S73 that “power reduction is possible”, the size of the clock buffer is adjusted according to the determination result (S74). By performing such processing, an excessive timing margin can be reduced, and power consumption in the semiconductor device can be reduced by reducing or deleting the size of the clock buffer. Further, the excessive timing margin is reduced by checking the maximum transition and the maximum capacitance and within a range satisfying the constraint value. In other words, the design rules are observed.

  (2) A power check is performed (S73). In the power check in step S73, if it is determined that “power reduction is possible”, the size of the clock buffer is adjusted in accordance with the determination result (S74), so the size of the clock buffer in step S72 is reduced. Cell power can be reduced by deleting or deleting, but it is possible to avoid a case where the charge / discharge current increases due to an increase in net capacity.

  (3) After adjusting the size of the clock buffer in step S74, a timing check for optimizing the clock gating cell is performed (S75), and if it is determined that there is “timing margin”, the clock gating cell Is optimized (S76). In this optimization process, the size of the clock gating cell is reduced. In addition, the clock gating cells are reduced by integrating the logically equivalent clock gating cells with sufficient timing. Thus, by optimizing the clock gating cell, the power consumption in the semiconductor device can be further reduced.

  (4) In the data line optimization process (S4), it is determined whether or not there is a path having a timing margin (S403). In this determination, if it is determined that “there is a path with timing margin”, it is determined whether or not the buffer size can be reduced (S404). If it is determined in this determination that “the buffer size can be reduced”, the buffer size is reduced or the buffer is deleted (S405). Thereby, the power consumption in the semiconductor device can be further reduced.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in FIG. 4, the clock gating cell timing check (S75) and the clock gating cell optimization process (S76) may be executed before the maximum transition and maximum capacitance check (S71). .

DESCRIPTION OF SYMBOLS 10 Layout apparatus 11 Display apparatus 12 Arithmetic processing apparatus 13 Storage apparatus 14 Input apparatus

Claims (8)

A storage device capable of storing information on the layout of cells in the semiconductor device;
Referring to the information in the storage device, a clock tree for distributing the clock signal to each part in the semiconductor device can be generated, and arithmetic processing for reducing an excessive timing margin in the generated clock tree can be executed. An arithmetic processing unit, and
The arithmetic processing device includes: a first process for determining whether or not there is a margin in the transition constraint and the capacitance constraint on the clock line;
A second process for reducing or deleting the size of the clock buffer in the clock line according to the determination result in the first process;
A third process for determining whether or not power reduction is possible in consideration of the total value of the charge / discharge current and the through current of the clock buffer after the second process;
A layout device that performs a fourth process for adjusting a size of the clock buffer according to a determination result in the third process; The arithmetic processing unit , after adjusting the size of the clock buffer in the fourth process, to determine whether there is a margin in the timing of the clock signal transmitted through the clock gating cell;
The layout apparatus according to claim 1, wherein a sixth process is performed to reduce or reduce the size of the clock gating cell in accordance with a determination result in the fifth process. The arithmetic processing unit assumes that the setup / hold timing is satisfied, and minimizes the cell size in the data line within a range that satisfies the transition constraint and capacitance constraint on the data line. The layout apparatus according to claim 2, wherein a process for optimizing the process is executed. 4. The layout apparatus according to claim 3, wherein the arithmetic processing unit determines whether or not power reduction is possible and optimizes the data line based on the determination result. A layout method capable of generating a clock tree for distributing a clock signal to each part in a semiconductor device using an arithmetic processing device capable of executing arithmetic processing,
A first process for determining whether or not there is a margin in transition constraints and capacitance constraints on the clock line;
A second process for reducing or deleting the size of the clock buffer in the clock line according to the determination result in the first process;
A third process for determining whether or not power reduction is possible in consideration of the total value of the charge / discharge current and the through current of the clock buffer after the second process;
A layout method for causing the arithmetic processing unit to execute a fourth process for adjusting a size of the clock buffer according to a determination result in the third process. A fifth process for determining whether or not there is a margin in the timing of the clock signal transmitted through the clock gating cell after the size adjustment of the clock buffer in the fourth process;
The layout method according to claim 5, wherein the arithmetic processing unit is configured to execute a sixth process for reducing or reducing the size of the clock gating cell according to a determination result in the fifth process. Assuming that the setup and hold timing is satisfied, the process to optimize the data line by minimizing the cell size in the data line within the range that satisfies the transition constraint and capacitance constraint on the data line. The layout method according to claim 6, which is executed by the arithmetic processing unit . The layout method according to claim 7, wherein it is determined whether or not power reduction is possible, and the arithmetic processing unit is caused to perform processing for optimizing data based on the determination result.

Images