JP2011129570A - Method of evaluating impurity in silicon epitaxial wafer - Google Patents

Method of evaluating impurity in silicon epitaxial wafer Download PDF

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JP2011129570A
JP2011129570A JP2009284020A JP2009284020A JP2011129570A JP 2011129570 A JP2011129570 A JP 2011129570A JP 2009284020 A JP2009284020 A JP 2009284020A JP 2009284020 A JP2009284020 A JP 2009284020A JP 2011129570 A JP2011129570 A JP 2011129570A
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impurity
epitaxial wafer
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JP5201126B2 (en
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Chisa Yoshida
知佐 吉田
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Shin Etsu Handotai Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of carrying out a qualitative and quantitative analysis of a heavy metal impurity included in a silicon epitaxial wafer in a highly sensitive manner. <P>SOLUTION: The method of evaluating an impurity in a silicon epitaxial wafer has: a film forming process of vapor-phase growing a silicon single-crystal thin film on a silicon single-phase crystal substrate under a hydrogen atmosphere by supplying a source gas during the process; a cooling process of calculating a temperature at which a specified value or process average value for the concentration of a to-be-evaluated impurity present in the silicon single-phase crystal thin film matches the solid solution limit concentration of the to-be-evaluated impurity and cooling a silicon epitaxial wafer having the silicon single-crystal thin film formed thereon by the film forming process under temperatures at least ranging from 50°C below to 50°C above the calculated temperature at a 20°C/sec or greater cooling rate after silicon epitaxial wafer film-formation; and an evaluation process of chemically analyzing the surface layer of the silicon single-crystal thin film to evaluate the concentration of the to-be-evaluated impurity. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、シリコンエピタキシャルウェーハの不純物評価方法に関し、具体的には、シリコンエピタキシャルウェーハ中の金属不純物濃度を高い感度で評価できる評価方法に関する。   The present invention relates to an impurity evaluation method for a silicon epitaxial wafer, and specifically relates to an evaluation method capable of evaluating a metal impurity concentration in a silicon epitaxial wafer with high sensitivity.

シリコンエピタキシャルウェーハは、例えば以下の通りにして製造される。
すなわち、シリコン単結晶基板を気相成長装置の反応容器内に載置し、水素ガスを流した状態で、1100℃〜1200℃まで反応容器内を昇温する(昇温工程)。
そして、反応容器内の温度が1100℃以上になると、基板表面に形成されている自然酸化膜(SiO:Silicon Dioxide)が除去される。
A silicon epitaxial wafer is manufactured as follows, for example.
That is, a silicon single crystal substrate is placed in a reaction vessel of a vapor phase growth apparatus, and the temperature in the reaction vessel is raised to 1100 ° C. to 1200 ° C. in a state where hydrogen gas is allowed to flow (temperature raising step).
When the temperature in the reaction vessel reaches 1100 ° C. or higher, the natural oxide film (SiO 2 : Silicon Dioxide) formed on the substrate surface is removed.

この状態で、トリクロロシラン(SiHCl:Trichlorosilane)等のシリコン原料ガス、ジボラン(B:Diborane)あるいはホスフィン(PH:Phosphine)等のドーパントガスを水素ガスとともに反応容器内に供給する。こうして基板の主表面にシリコン単結晶薄膜を気相成長させる(成膜工程)。 In this state, a silicon source gas such as trichlorosilane (SiHCl 3 : Trichlorosilane) or a dopant gas such as diborane (B 2 H 6 : Diborane) or phosphine (PH 3 : Phosphine) is supplied into the reaction vessel together with hydrogen gas. In this way, a silicon single crystal thin film is vapor-phase grown on the main surface of the substrate (deposition process).

このようにして薄膜を気相成長させた後に、原料ガスおよびドーパントガスの供給を停止し、水素雰囲気に保持したまま反応容器内の温度を降温させる(冷却工程)。   After vapor-depositing the thin film in this manner, the supply of the source gas and the dopant gas is stopped, and the temperature in the reaction vessel is lowered while maintaining the hydrogen atmosphere (cooling step).

ところで、上述の通りにシリコンエピタキシャルウェーハを製造する過程で、重金属不純物がエピタキシャル層(シリコン単結晶薄膜)内に混入すると、その基板を用いて作製したデバイスの特性が異常となってしまうことがある。
特に、デバイスが作りこまれるデバイス活性層となるエピタキシャル層の表層側に不純物汚染があると、デバイスへの悪影響が大きくなる。
By the way, in the process of manufacturing a silicon epitaxial wafer as described above, if heavy metal impurities are mixed in the epitaxial layer (silicon single crystal thin film), the characteristics of a device manufactured using the substrate may become abnormal. .
In particular, if there is impurity contamination on the surface layer side of the epitaxial layer that becomes the device active layer in which the device is built, the adverse effect on the device is increased.

従来のエピタキシャルシリコンウェーハ中の重金属不純物評価法としては、例えばAAS(Atomic Absorption Spectroscopy:原子吸光分析)、ICP−MS(Inductively Coupled Plasma−Mass Spectroscopy:誘導結合型プラズマ質量分析)、TRXF(Total Reflection X−ray Fluorescence:全反射蛍光X線分析)等により定性・定量分析する手法が挙げられる。   Examples of conventional methods for evaluating heavy metal impurities in an epitaxial silicon wafer include AAS (Atomic Absorption Spectroscopy), ICP-MS (Inductively Coupled Plasma-Mass Spectroscopy), TRXF (Inductively Coupled Plasma Mass Analysis), TRXF -Ray Fluorescence: Total reflection fluorescent X-ray analysis), etc.

また、上記したシリコンエピタキシャルウェーハ製造時の冷却工程において、400℃以下で雰囲気ガスを水素雰囲気から窒素雰囲気に切り替えることで、Cuをウェーハの表面に析出させ、Cu汚染を高感度に検出する評価方法が開示されている(特許文献1参照)。
またこの他には、アンモニアの濃度が過酸化水素水より高濃度である処理液を用いてシリコンウェーハを30分以上エッチングし、表面に形成されたLPDの個数を調べることによりシリコンウェーハのCu汚染等の評価を行う方法が開示されている(特許文献2参照)。
Also, in the cooling process at the time of manufacturing the silicon epitaxial wafer, an evaluation method for detecting Cu contamination with high sensitivity by precipitating Cu on the wafer surface by switching the atmosphere gas from a hydrogen atmosphere to a nitrogen atmosphere at 400 ° C. or lower. Is disclosed (see Patent Document 1).
In addition to this, the silicon wafer is etched for 30 minutes or more by using a treatment liquid having a higher ammonia concentration than hydrogen peroxide solution, and the number of LPDs formed on the surface is examined, whereby the silicon wafer is contaminated with Cu. Have been disclosed (see Patent Document 2).

特許第3664101号公報Japanese Patent No. 3664101 特許第3717691号公報Japanese Patent No. 3717691

しかし、従来の評価方法でシリコンエピタキシャルウェーハに含まれる重金属不純物量を測定しようとしても、そのウェーハ中に存在する不純物の量は微量であるために、分析・評価する感度が充分でない場合があった。
そのため、モニターウェーハにおける評価において、従来の分析手法で良好と評価された製造工程において製造されたシリコンエピタキシャルウェーハを用いて半導体デバイスを製造した場合であっても、デバイス特性が悪いものが製造されてしまう場合があるという問題点があった。
However, even when trying to measure the amount of heavy metal impurities contained in a silicon epitaxial wafer by the conventional evaluation method, the amount of impurities present in the wafer is very small, so the sensitivity to analyze and evaluate may not be sufficient. .
Therefore, in the evaluation on the monitor wafer, even when the semiconductor device is manufactured using the silicon epitaxial wafer manufactured in the manufacturing process evaluated as good by the conventional analysis method, the device having poor device characteristics is manufactured. There was a problem that it might end.

また、Cuについてはエピタキシャルウェーハ製造工程の冷却工程での雰囲気ガスを工夫することで高感度化をはかる方法が提案されているが、それ以外の重金属不純物については高感度化のための有効な前処理方法が知られていなかった。   For Cu, a method has been proposed for improving the sensitivity by devising the atmosphere gas in the cooling process of the epitaxial wafer manufacturing process, but for other heavy metal impurities, effective methods for increasing the sensitivity are proposed. The processing method was not known.

本発明は、前述のような問題に鑑みてなされたもので、シリコンエピタキシャルウェーハに含まれる重金属不純物の定性・定量分析を高感度に行うことができる不純物評価方法を提供することを目的とする。   The present invention has been made in view of the above-described problems, and an object thereof is to provide an impurity evaluation method capable of performing qualitative and quantitative analysis of heavy metal impurities contained in a silicon epitaxial wafer with high sensitivity.

上記課題を解決するため、本発明では、シリコンエピタキシャルウェーハの不純物評価方法であって、原料ガスを供給しながらシリコン単結晶基板上にシリコン単結晶薄膜を水素雰囲気中で気相成長させる成膜工程と、該成膜工程により前記シリコン単結晶薄膜が形成されたシリコンエピタキシャルウェーハを、前記シリコン単結晶薄膜中に存在する評価対象不純物の濃度の規格値又は工程平均値と前記評価対象不純物の固溶限界濃度が一致する温度を算出し、該算出温度の少なくとも上下50℃の温度範囲において、前記シリコンエピタキシャルウェーハの成膜後の冷却速度を20℃/sec以上として冷却する冷却工程と、前記シリコン単結晶薄膜の表層を化学分析して、前記評価対象不純物の濃度を測定する評価工程とを行うことを特徴とするシリコンエピタキシャルウェーハの不純物評価方法を提供する。   In order to solve the above-described problems, the present invention provides a method for evaluating impurities of a silicon epitaxial wafer, in which a silicon single crystal thin film is vapor-phase grown in a hydrogen atmosphere on a silicon single crystal substrate while supplying a source gas. And a silicon epitaxial wafer on which the silicon single crystal thin film is formed by the film forming step, a standard value or a process average value of the concentration of the impurity to be evaluated existing in the silicon single crystal thin film and a solid solution of the impurity to be evaluated A cooling step of calculating a temperature at which the critical concentrations coincide with each other, cooling in a temperature range of at least 50 ° C. above and below the calculated temperature at a cooling rate after film formation of the silicon epitaxial wafer of 20 ° C./sec or more; A chemical analysis of the surface layer of the crystal thin film, and an evaluation step of measuring the concentration of the impurity to be evaluated. To provide an impurity evaluation method of a silicon epitaxial wafer to be.

シリコンエピタキシャルウェーハ中のほとんどの不純物は、シリコン単結晶薄膜形成のためのエピタキシャル反応直後の高温域では固溶した状態で存在する。そして、それが冷却工程で固溶限界となる温度に達した時点で析出が始まる。そこで、評価対象不純物の濃度の規格値や工程平均値(過去のシリコンエピタキシャルウェーハの製造実績から算出できる)と、評価対象不純物の固溶限界濃度が一致する温度を算出する。そして、その算出温度の少なくとも上下50℃の温度範囲において冷却速度を20℃/sec以上に制御して冷却すると、シリコン単結晶薄膜の表層部に評価対象不純物が集まる。
そしてシリコン単結晶薄膜中の評価対象不純物、特に金属不純物が集まったシリコン単結晶薄膜の表層を化学分析して評価対象不純物の濃度を測定することによって、シリコンエピタキシャルウェーハ中の金属不純物の濃度を従来に比べて高感度かつ定量的に評価することができる。
Most impurities in the silicon epitaxial wafer exist in a solid solution state in a high temperature region immediately after the epitaxial reaction for forming a silicon single crystal thin film. Precipitation begins when it reaches a temperature at which the solid solution limit is reached in the cooling step. Therefore, the temperature at which the standard value of the concentration of the impurity to be evaluated and the process average value (which can be calculated from the past production results of the silicon epitaxial wafer) matches the solid solution limit concentration of the impurity to be evaluated is calculated. When the cooling rate is controlled to 20 ° C./sec or more in a temperature range of at least 50 ° C. above and below the calculated temperature, impurities to be evaluated collect in the surface layer portion of the silicon single crystal thin film.
The concentration of the metal impurity in the silicon epitaxial wafer is conventionally determined by chemical analysis of the surface layer of the silicon single crystal thin film in which the impurities to be evaluated in the silicon single crystal thin film, particularly the metal impurities are collected, to measure the concentration of the impurity to be evaluated. Can be evaluated more sensitively and quantitatively.

ここで、前記冷却速度を、30℃/sec以下とすることが好ましい。
これ以上冷却速度を上げても、評価対象不純物の検出能力を更に向上させることができないのに対して、冷却速度をさらに上げるための特別な冷却設備が必要になってコストアップにつながるが、このように、冷却速度を30℃/sec以下とすることによって、過剰な冷却設備を設ける必要もなく、また評価対象不純物の検出能力の向上の両立を図ることができる。
Here, the cooling rate is preferably 30 ° C./sec or less.
Even if the cooling rate is increased further, the ability to detect the impurities to be evaluated cannot be further improved. On the other hand, a special cooling facility for further increasing the cooling rate is required, leading to an increase in cost. As described above, by setting the cooling rate to 30 ° C./sec or less, it is not necessary to provide an excessive cooling facility, and it is possible to improve both the detection capability of the impurities to be evaluated.

また、前記評価対象不純物を、Niとすることが好ましい。
一般的なシリコンエピタキシャルウェーハのシリコン単結晶薄膜中のNiの含有量は1×10atoms/cm台から1×1011atoms/cm台と想定される。
そこで、図2を参照すると、この濃度範囲がNiの固溶限界となる温度帯は、300℃〜400℃となる。このため評価対象不純物をNiとした場合、冷却工程において、少なくとも400℃から300℃までの範囲内の冷却速度を20℃/sec以上に制御することで、シリコン単結晶薄膜表層へのNi析出を制御することが可能となり、従来は困難であった効率的なNi濃度の評価が可能となる。
Moreover, it is preferable that the evaluation object impurity is Ni.
The content of Ni in a silicon single crystal thin film of a general silicon epitaxial wafer is assumed to be 1 × 10 9 atoms / cm 3 to 1 × 10 11 atoms / cm 3 .
Therefore, referring to FIG. 2, the temperature range in which this concentration range becomes the solid solubility limit of Ni is 300 ° C. to 400 ° C. Therefore, when the impurity to be evaluated is Ni, by controlling the cooling rate in the range from at least 400 ° C. to 300 ° C. to 20 ° C./sec or more in the cooling process, Ni precipitation on the surface layer of the silicon single crystal thin film This makes it possible to control the Ni concentration, which has been difficult in the prior art.

以上説明したように、シリコン単結晶薄膜の成膜反応後の冷却工程において、評価対象不純物の規格値や工程平均値とその汚染元素の固溶限界濃度が一致する温度、すなわち汚染元素が過飽和になり始める温度帯の近傍(±50℃程度)において、シリコンエピタキシャルウェーハを20℃/sec以上で急冷する。
これによって、シリコン単結晶薄膜内の汚染元素が表層側に集まってくるため、その汚染元素が集中した領域をWSA(Wafer Surface Analysis)法やステップエッチ分析等の方法で分析することによって、シリコン単結晶薄膜の成膜工程でのシリコンエピタキシャルウェーハの汚染を従来より高感度に評価することができる。
As described above, in the cooling process after the film formation reaction of the silicon single crystal thin film, the temperature at which the standard value of the impurity to be evaluated and the process average value coincide with the solid solution limit concentration of the contaminating element, that is, the contaminating element becomes supersaturated. The silicon epitaxial wafer is rapidly cooled at 20 ° C./sec or more in the vicinity of the temperature range where it begins to become (about ± 50 ° C.).
As a result, the contaminating elements in the silicon single crystal thin film gather on the surface layer side. Therefore, by analyzing the region where the contaminating elements are concentrated by a method such as WSA (Wafer Surface Analysis) method or step etch analysis, It is possible to evaluate the contamination of the silicon epitaxial wafer in the process of forming the crystalline thin film with higher sensitivity than before.

本発明のシリコンエピタキシャルウェーハの評価方法の概略の一例を示したフローチャートである。It is the flowchart which showed an example of the outline of the evaluation method of the silicon epitaxial wafer of this invention. シリコン中のNiの固溶度の温度依存性を示した図である。It is the figure which showed the temperature dependence of the solid solubility of Ni in silicon. シリコン単結晶薄膜の成膜反応後の冷却工程における350℃付近の冷却速度とシリコン単結晶薄膜表層部に集まったNiの濃度の関係を示した図である。It is the figure which showed the relationship between the cooling rate of 350 degreeC vicinity in the cooling process after the film-forming reaction of a silicon single crystal thin film, and the density | concentration of Ni collected in the silicon single crystal thin film surface layer part.

以下、本発明についてより具体的に説明する。
従来の評価方法により、シリコンエピタキシャルウェーハに含まれる重金属不純物の量を検出するには感度が充分ではなく、精度良く評価できない場合があった。
そのため、従来の分析手法で良好と評価されたシリコンエピタキシャルウェーハを用いて半導体デバイスを製造した場合であっても、デバイス特性の低いものが製造されてしまう場合があるという問題点があった。
Hereinafter, the present invention will be described more specifically.
In some cases, the conventional evaluation method has insufficient sensitivity to detect the amount of heavy metal impurities contained in the silicon epitaxial wafer, and the evaluation cannot be performed with high accuracy.
Therefore, even when a semiconductor device is manufactured using a silicon epitaxial wafer evaluated as good by a conventional analysis method, there is a problem that a device having low device characteristics may be manufactured.

そこで、本発明者はこのような問題点を解決すべく鋭意検討、実験を重ねた。
その結果、シリコンエピタキシャルウェーハの表層の不純物濃度に影響を与える条件として、エピタキシャル層(シリコン単結晶薄膜)成長後の冷却条件に着目した。特に、含まれる重金属不純物が過飽和になる温度帯での冷却速度に着目し、この冷却速度を変えることを発想した。
Therefore, the present inventor conducted intensive studies and experiments in order to solve such problems.
As a result, attention was paid to cooling conditions after growth of the epitaxial layer (silicon single crystal thin film) as a condition affecting the impurity concentration of the surface layer of the silicon epitaxial wafer. In particular, we focused on the cooling rate in the temperature range where the heavy metal impurities contained are supersaturated, and have conceived of changing this cooling rate.

そして更なる鋭意検討・実験を重ねた結果、シリコン単結晶薄膜中に存在する評価対象不純物の濃度の規格値又は工程平均値と、固溶限界濃度が一致する温度を算出して、その算出温度の少なくとも上下50℃の温度範囲で、成膜後のシリコンエピタキシャルウェーハの冷却速度を20℃/sec以上とすることによって、評価対象不純物をシリコン単結晶薄膜の表層部に集めることができ、この部分を化学分析することによって、従来より高感度に不純物の濃度を評価できることを知見し、本発明を完成させた。   As a result of further intensive studies and experiments, the temperature at which the standard value or the process average value of the concentration of the impurity to be evaluated existing in the silicon single crystal thin film coincides with the solid solution limit concentration is calculated, and the calculated temperature The impurity to be evaluated can be collected in the surface layer portion of the silicon single crystal thin film by setting the cooling rate of the silicon epitaxial wafer after film formation to 20 ° C./sec or more at least in the temperature range of 50 ° C. or above. As a result of chemical analysis, it has been found that the concentration of impurities can be evaluated with higher sensitivity than in the past, and the present invention has been completed.

以下、本発明について図を参照して詳細に説明するが、本発明はこれらに限定されるものではない。
まず、本発明のシリコンエピタキシャルウェーハの評価方法について図1を参照して説明する。図1は本発明のシリコンエピタキシャルウェーハの評価方法の概略の一例を示したフローチャートである。
Hereinafter, the present invention will be described in detail with reference to the drawings, but the present invention is not limited thereto.
First, a method for evaluating a silicon epitaxial wafer according to the present invention will be described with reference to FIG. FIG. 1 is a flowchart showing an example of an outline of the silicon epitaxial wafer evaluation method of the present invention.

先ず、図1に示すように、気相成長装置の反応容器内に備えられたサセプタに、搬送装置を用いてシリコン単結晶基板を載置する(図1(a)、仕込み)。
次いで、反応容器内に水素ガスを流した状態で、反応容器内の温度をシリコン単結晶薄膜を気相成長するための成膜温度まで昇温する(図1(b)、昇温)。この成膜温度は、基板表面の自然酸化膜を水素で除去できる1000℃以上に設定する。
First, as shown in FIG. 1, a silicon single crystal substrate is placed on a susceptor provided in a reaction vessel of a vapor phase growth apparatus using a transfer device (FIG. 1 (a), preparation).
Next, with the hydrogen gas flowing in the reaction vessel, the temperature in the reaction vessel is raised to a film formation temperature for vapor phase growth of the silicon single crystal thin film (FIG. 1B, temperature rise). The film forming temperature is set to 1000 ° C. or higher at which the natural oxide film on the substrate surface can be removed with hydrogen.

次いで、反応容器内を成膜温度に保持したままで、水素ガスとともに原料ガスおよびドーパントガスをそれぞれ所定流量で供給して、水素雰囲気にてシリコン単結晶薄膜が所定膜厚となるまでシリコン単結晶基板上にシリコン単結晶薄膜を成長させる(図1(c)、成膜工程)。   Next, while keeping the inside of the reaction vessel at the film forming temperature, the source gas and the dopant gas are supplied at a predetermined flow rate together with the hydrogen gas, and the silicon single crystal is obtained until the silicon single crystal thin film reaches a predetermined film thickness in a hydrogen atmosphere. A silicon single crystal thin film is grown on the substrate (FIG. 1C, film forming step).

この後に原料ガスおよびドーパントガスの供給を停止し、キャリアガスである水素を流しながら反応容器内の温度を下降させてシリコンエピタキシャルウェーハを冷却する(図1(d)、冷却工程)。
この冷却工程では、シリコン単結晶薄膜中に存在する評価対象不純物の濃度の規格値や工程平均値と評価対象不純物の固溶限界濃度が一致する温度を算出し、算出温度の少なくとも上下50℃の温度範囲において、シリコンエピタキシャルウェーハの成膜後の冷却速度を20℃/sec以上として冷却する。
また、800℃から400℃程度の間で、水素雰囲気から窒素雰囲気へと切り換えることができる。
Thereafter, the supply of the source gas and the dopant gas is stopped, and the silicon epitaxial wafer is cooled by lowering the temperature in the reaction vessel while flowing hydrogen as the carrier gas (FIG. 1 (d), cooling step).
In this cooling step, a temperature at which the standard value of the concentration of the impurity to be evaluated existing in the silicon single crystal thin film or the process average value matches the solid solution limit concentration of the impurity to be evaluated is calculated, and at least 50 ° C. above and below the calculated temperature. In the temperature range, the cooling rate after film formation of the silicon epitaxial wafer is set to 20 ° C./sec or more for cooling.
Further, the hydrogen atmosphere can be switched to the nitrogen atmosphere between about 800 ° C. and 400 ° C.

シリコンウェーハ中のほとんどの不純物は、シリコン単結晶薄膜形成のためのエピタキシャル反応直後の高温域では固溶した状態で存在しており、冷却工程で固溶限界となる温度に達した時点から析出が始まる。
そこで、シリコン単結晶薄膜中に存在する評価対象不純物の濃度の規格値や工程平均値と、評価対象不純物の固溶限界濃度が一致する温度を算出して、この算出温度の少なくとも上下50℃の温度範囲において、シリコン単結晶薄膜の成膜工程後の冷却工程での冷却速度を20℃/sec以上に制御すると、シリコンエピタキシャルウェーハ中の評価対象の不純物がシリコン単結晶薄膜の表層領域に集まる。
そしてこれを利用して、後述する評価工程において評価対象不純物が集まったこの領域を化学分析することで、高い感度でシリコンエピタキシャルウェーハ中の不純物濃度を測定することができるようになる。
Most impurities in the silicon wafer exist in a solid solution state in the high temperature region immediately after the epitaxial reaction for forming the silicon single crystal thin film, and precipitation begins when the temperature reaches the solid solution limit in the cooling process. Begins.
Therefore, a temperature at which the standard value or process average value of the concentration of the impurity to be evaluated existing in the silicon single crystal thin film coincides with the solid solution limit concentration of the impurity to be evaluated is calculated. In the temperature range, when the cooling rate in the cooling step after the silicon single crystal thin film forming step is controlled to 20 ° C./sec or more, impurities to be evaluated in the silicon epitaxial wafer gather in the surface layer region of the silicon single crystal thin film.
Then, by utilizing this, by chemically analyzing this region where the evaluation target impurities are collected in the evaluation process described later, the impurity concentration in the silicon epitaxial wafer can be measured with high sensitivity.

ここで、評価対象不純物を、Niとすることができる。
一般的なシリコンエピタキシャルウェーハのシリコン単結晶薄膜中のNiの含有量は、1×10〜1×1011atoms/cmの水準と想定される。
そして、図2に示すように、Niの汚染量が上記範囲内である5×1010atoms/cm程度の場合、その汚染量と固溶度が一致する温度は、350℃前後になる。
従って、評価対象不純物がNiの場合は、冷却中のシリコンエピタキシャルウェーハの温度が少なくとも400℃から300℃までの温度帯を通過する時には、冷却速度を20℃/sec以上に制御することになる。
なお、図2は、シリコン中のNiの固溶度の温度依存性を示した図である。
Here, the evaluation target impurity may be Ni.
The content of Ni in a silicon single crystal thin film of a general silicon epitaxial wafer is assumed to be a level of 1 × 10 9 to 1 × 10 11 atoms / cm 3 .
As shown in FIG. 2, when the contamination amount of Ni is about 5 × 10 10 atoms / cm 3 within the above range, the temperature at which the contamination amount and the solid solubility coincide with each other is about 350 ° C.
Accordingly, when the impurity to be evaluated is Ni, the cooling rate is controlled to 20 ° C./sec or higher when the temperature of the silicon epitaxial wafer being cooled passes through a temperature range of at least 400 ° C. to 300 ° C.
FIG. 2 is a diagram showing the temperature dependence of the solid solubility of Ni in silicon.

デバイス特性に悪影響を及ぼすNiを評価対象不純物に選び、シリコンエピタキシャルウェーハの温度が少なくとも400℃から300℃までの温度域での冷却速度を20℃/sec以上に制御することで、Niをシリコン単結晶薄膜の表層部に集める。
そして、後述する評価工程においてNi濃度の評価を行うことができる。
Ni that adversely affects the device characteristics is selected as an impurity to be evaluated, and the temperature of the silicon epitaxial wafer is controlled to a temperature of at least 400 ° C. to 300 ° C. so that the cooling rate is 20 ° C./sec or more. Collect on the surface layer of the crystal thin film.
And Ni density | concentration can be evaluated in the evaluation process mentioned later.

また、冷却速度を、30℃/sec以下とすることができる。
シリコン単結晶薄膜中に存在する評価対象不純物の濃度の規格値と、固溶限界濃度が一致する温度の少なくとも上下50℃の範囲での成膜後のシリコンエピタキシャルウェーハの冷却速度を上げれば上げるほど、特別な冷却設備が必要になりコストがかかるが、評価対象不純物が集まる量は飽和気味になり、それ以上に冷却速度を上げてもさほど変化が見られないようになる。
しかし、冷却速度が30℃/sec以下であれば、過剰な冷却設備が必要ではなく、評価対象不純物の集まる量は十分に多い状態を維持することができ、好都合である。
Moreover, a cooling rate can be 30 degrees C / sec or less.
The higher the cooling rate of the silicon epitaxial wafer after film formation in the range of at least 50 ° C. above and below the temperature at which the standard concentration of the impurity to be evaluated existing in the silicon single crystal thin film and the solid solution limit concentration match, Although special cooling equipment is required and costs are high, the amount of impurities to be evaluated becomes saturated, and even if the cooling rate is increased further, no significant change is observed.
However, if the cooling rate is 30 ° C./sec or less, an excessive cooling facility is not necessary, and the amount of impurities to be evaluated can be kept sufficiently large, which is convenient.

そして、窒素雰囲気のままで取出温度に至ったら、気相成長装置からシリコンエピタキシャルウェーハを取り出す(図1(e)、取出し)。   When the extraction temperature is reached in the nitrogen atmosphere, the silicon epitaxial wafer is taken out from the vapor phase growth apparatus (FIG. 1 (e), taking out).

続いて、シリコンエピタキシャルウェーハのシリコン単結晶薄膜の表層領域に集まった評価対象の不純物の濃度を化学分析、例えばステップエッチ法、WSA法、AAS、ICP−MS、TRXF等によって測定する(図1(f)、表層不純物の評価工程)。   Subsequently, the concentration of the impurity to be evaluated collected in the surface layer region of the silicon single crystal thin film of the silicon epitaxial wafer is measured by chemical analysis, for example, step etch method, WSA method, AAS, ICP-MS, TRXF (FIG. 1 ( f) Surface layer impurity evaluation step).

ここで、図3は、シリコン単結晶薄膜の成膜反応後の冷却工程における350℃付近の冷却速度とシリコン単結晶薄膜表層部に集まったNiの濃度の関係を示した図である。
図3に示すように、冷却速度が高いほど、シリコン単結晶薄膜の表層付近にNiが集まっている。つまり、このシリコン単結晶薄膜中に存在する評価対象不純物の濃度の規格値と、固溶限界濃度が一致する温度帯を急冷した後、表層をステップエッチ法、WSA法、AAS、ICP−MS、TRXF等により分析すれば、高感度で不純物を検出することができる。
Here, FIG. 3 is a diagram showing the relationship between the cooling rate around 350 ° C. and the concentration of Ni collected in the surface layer portion of the silicon single crystal thin film in the cooling step after the film formation reaction of the silicon single crystal thin film.
As shown in FIG. 3, the higher the cooling rate, the more Ni is collected near the surface layer of the silicon single crystal thin film. That is, after quenching a temperature range in which the standard value of the concentration of the impurity to be evaluated existing in the silicon single crystal thin film and the solid solution limit concentration match, the surface layer is subjected to the step etch method, WSA method, AAS, ICP-MS, If analyzed by TRXF or the like, impurities can be detected with high sensitivity.

このように、評価対象不純物の濃度の規格値や工程平均値と、評価対象不純物の固溶限界濃度が一致する温度範囲の少なくとも上下50℃の温度範囲において冷却速度を20℃/sec以上に制御して冷却することによってシリコン単結晶薄膜の表層部に集まった評価対象不純物の濃度を化学分析することによって、シリコンエピタキシャルウェーハ中の評価対象不純物濃度を従来より高い精度で評価することができる。   As described above, the cooling rate is controlled to 20 ° C./sec or more in a temperature range at least 50 ° C. above and below the temperature range in which the standard value or process average value of the concentration of the impurity to be evaluated matches the solid solution limit concentration of the impurity to be evaluated Then, the concentration of the impurity to be evaluated collected in the surface layer portion of the silicon single crystal thin film by cooling is chemically analyzed, whereby the concentration of the impurity to be evaluated in the silicon epitaxial wafer can be evaluated with higher accuracy than before.

そして、モニターとなるシリコンエピタキシャルウェーハの評価対象不純物濃度が規格値より低濃度かどうかを判定(良品と判断)することにより、そのシリコンエピタキシャルウェーハの製造工程を管理することができる。   Then, by determining whether the evaluation target impurity concentration of the silicon epitaxial wafer to be monitored is lower than the standard value (determining that it is a non-defective product), the manufacturing process of the silicon epitaxial wafer can be managed.

このように、先の評価工程での評価結果を元に、シリコンエピタキシャルウェーハの工程管理を行うことで、評価対象不純物濃度が規格値以下のデバイス特性が良好な高品質シリコンエピタキシャルウェーハを製造することができる。   In this way, manufacturing process of silicon epitaxial wafer based on the evaluation result in the previous evaluation process, manufacturing high-quality silicon epitaxial wafers with good device characteristics whose evaluation target impurity concentration is below standard value Can do.

以下、実施例及び比較例を示して本発明をより具体的に説明するが、本発明はこれらに限定されるものではない。
(実施例1−3、比較例1)
あらかじめ同一バッチのシリコン単結晶基板が全溶解化学分析法を用いて1×1010atoms/cm以下(検出下限)のNi濃度であることを確かめた面方位(100)、P型(0.015Ωcm)のシリコン単結晶基板を4枚準備し、その主表面上に、成膜温度1130℃でP型(10Ωcm)のシリコン単結晶薄膜5μmを気相成長させた。
EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.
(Example 1-3, Comparative Example 1)
The plane orientation (100), P + type (0) in which it was confirmed in advance that the same batch of silicon single crystal substrates had a Ni concentration of 1 × 10 10 atoms / cm 3 or less (lower detection limit) using total dissolution chemical analysis. .015 Ωcm) of silicon single crystal substrates were prepared, and a P - type (10 Ωcm) silicon single crystal thin film of 5 μm was vapor-phase grown on the main surface at a film forming temperature of 1130 ° C.

そして、成膜後のシリコンエピタキシャルウェーハを冷却する際に、400℃から300℃までの間の冷却速度を、15℃/sec(比較例1)、20℃/sec(実施例1)、30℃/sec(実施例2)、35℃/sec(実施例3)と変えて、シリコンエピタキシャルウェーハを製造した。   When the silicon epitaxial wafer after film formation is cooled, the cooling rate between 400 ° C. and 300 ° C. is 15 ° C./sec (Comparative Example 1), 20 ° C./sec (Example 1), 30 ° C. A silicon epitaxial wafer was manufactured by changing to / sec (Example 2) and 35 ° C./sec (Example 3).

これらのシリコンエピタキシャルウェーハ計4枚を、ステップエッチング法(特開2005−265718号公報、特許3755586号公報等参照)によって、シリコン単結晶薄膜の表層1.5μmを抽出し、ICP−MS装置によってNiを含む重金属の濃度を測定した。その結果を表1に示す。   A total of 4 silicon epitaxial wafers were extracted by a step etching method (see Japanese Patent Application Laid-Open No. 2005-265718, Japanese Patent No. 3755586, etc.) and a surface layer of a silicon single crystal thin film of 1.5 μm was extracted. The concentration of heavy metals containing was measured. The results are shown in Table 1.

Figure 2011129570
Figure 2011129570

この結果、表1に示すように、比較例1の冷却条件ではシリコン単結晶薄膜の表層中のNi濃度はICP−MS装置の検出下限(1×1010atoms/cm)以下であり、Niが存在するかしないかすら確認できず、高感度な不純物濃度評価を行うことができなかった。
これに対し、実施例1−3の冷却条件の場合、Ni濃度がそれぞれ8.0×1010atoms/cm(実施例1)、4.0×1011atoms/cm(実施例2)、4.2×1011atoms/cm(実施例3)と検出され、比較例1の場合に比べて高い感度でシリコン単結晶薄膜の表層部のNiの濃度を評価することが可能であった。
また、実施例1と実施例2を比較すると、実施例2の方がよりNiは高濃度になっており、冷却速度が速いほど評価能力が高いことが判った。しかし、実施例2よりさらに冷却レートをあげた実施例3の条件の場合、実施例2より若干検出されたNi濃度は高くなっているが、大きな差は無かった。すなわち、冷却速度を実施例2より上げても、Niの検出能力の更なる向上はあまり期待できない。それよりも、冷却速度をさらに上げるための特別な冷却設備が必要になり、コストアップにつながってしまうため、冷却速度の上限は30℃/sec程度がよいことも判った。
As a result, as shown in Table 1, under the cooling conditions of Comparative Example 1, the Ni concentration in the surface layer of the silicon single crystal thin film is below the detection lower limit (1 × 10 10 atoms / cm 3 ) of the ICP-MS device, It was not possible to confirm even the presence or absence of impurities, and it was not possible to perform highly sensitive impurity concentration evaluation.
On the other hand, in the cooling conditions of Example 1-3, the Ni concentration was 8.0 × 10 10 atoms / cm 3 (Example 1), 4.0 × 10 11 atoms / cm 3 (Example 2), respectively. It was detected as 4.2 × 10 11 atoms / cm 3 (Example 3), and it was possible to evaluate the Ni concentration in the surface layer portion of the silicon single crystal thin film with higher sensitivity than in the case of Comparative Example 1. It was.
Further, when Example 1 and Example 2 were compared, it was found that in Example 2, the Ni concentration was higher and the evaluation ability was higher as the cooling rate was faster. However, in the case of the condition of Example 3 where the cooling rate was further increased than that of Example 2, the detected Ni concentration was slightly higher than that of Example 2, but there was no significant difference. That is, even if the cooling rate is increased from that in Example 2, further improvement in Ni detection capability cannot be expected. In addition, a special cooling facility for further increasing the cooling rate is required, which leads to an increase in cost. Therefore, it has been found that the upper limit of the cooling rate is preferably about 30 ° C./sec.

なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は、例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。
例えば、本発明で薄膜を気相成長させる気相成長装置は限定されず、縦型(パンケーキ型)、バレル型(シリンダ型)、枚葉式等の各種気相成長装置に適用可能である。
The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
For example, the vapor phase growth apparatus for vapor phase growth of a thin film in the present invention is not limited, and can be applied to various vapor phase growth apparatuses such as a vertical type (pancake type), a barrel type (cylinder type), and a single wafer type. .

Claims (3)

シリコンエピタキシャルウェーハの不純物評価方法であって、
原料ガスを供給しながらシリコン単結晶基板上にシリコン単結晶薄膜を水素雰囲気中で気相成長させる成膜工程と、
該成膜工程により前記シリコン単結晶薄膜が形成されたシリコンエピタキシャルウェーハを、前記シリコン単結晶薄膜中に存在する評価対象不純物の濃度の規格値又は工程平均値と前記評価対象不純物の固溶限界濃度が一致する温度を算出し、該算出温度の少なくとも上下50℃の温度範囲において、前記シリコンエピタキシャルウェーハの成膜後の冷却速度を20℃/sec以上として冷却する冷却工程と、
前記シリコン単結晶薄膜の表層を化学分析して、前記評価対象不純物の濃度を測定する評価工程とを行うことを特徴とするシリコンエピタキシャルウェーハの不純物評価方法。
An impurity evaluation method for a silicon epitaxial wafer,
A film forming step of vapor-phase-growing a silicon single crystal thin film in a hydrogen atmosphere on a silicon single crystal substrate while supplying a source gas;
A silicon epitaxial wafer in which the silicon single crystal thin film is formed by the film forming step, a standard value or a process average value of the concentration of the impurity to be evaluated existing in the silicon single crystal thin film, and a solid solution limit concentration of the impurity to be evaluated And a cooling step of cooling the silicon epitaxial wafer at a cooling rate of 20 ° C./sec or more in a temperature range at least 50 ° C. above and below the calculated temperature,
A method for evaluating an impurity of a silicon epitaxial wafer, comprising: chemically analyzing a surface layer of the silicon single crystal thin film to measure a concentration of the impurity to be evaluated.
前記冷却速度を、30℃/sec以下とすることを特徴とする請求項1に記載のシリコンエピタキシャルウェーハの不純物評価方法。   The impurity evaluation method for a silicon epitaxial wafer according to claim 1, wherein the cooling rate is set to 30 ° C / sec or less. 前記評価対象不純物を、Niとすることを特徴とする請求項1または請求項2に記載のシリコンエピタキシャルウェーハの不純物評価方法。   The impurity evaluation method for a silicon epitaxial wafer according to claim 1 or 2, wherein the impurity to be evaluated is Ni.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016032035A (en) * 2014-07-29 2016-03-07 株式会社Sumco Method for manufacturing epitaxial silicon wafer

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199416A (en) * 1996-01-17 1997-07-31 Sumitomo Sitix Corp Semiconductor substrate and manufacture thereof
JPH10178020A (en) * 1996-12-18 1998-06-30 Nec Yamagata Ltd Manufacture of semiconductor device
JPH1116844A (en) * 1997-06-23 1999-01-22 Sumitomo Metal Ind Ltd Production of epitaxial silicon wafer and material wafer
JPH11150119A (en) * 1997-11-14 1999-06-02 Sumitomo Sitix Corp Method and device for heat-treating silicon semiconductor substance
JP2003502836A (en) * 1999-06-14 2003-01-21 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド Manufacturing method of epitaxial silicon wafer having intrinsic gettering
JP2007281119A (en) * 2006-04-05 2007-10-25 Sumco Corp Wafer for evaluating heat treatment, method of evaluating heat treatment, and method of manufacturing semiconductor wafer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199416A (en) * 1996-01-17 1997-07-31 Sumitomo Sitix Corp Semiconductor substrate and manufacture thereof
JPH10178020A (en) * 1996-12-18 1998-06-30 Nec Yamagata Ltd Manufacture of semiconductor device
JPH1116844A (en) * 1997-06-23 1999-01-22 Sumitomo Metal Ind Ltd Production of epitaxial silicon wafer and material wafer
JPH11150119A (en) * 1997-11-14 1999-06-02 Sumitomo Sitix Corp Method and device for heat-treating silicon semiconductor substance
JP2003502836A (en) * 1999-06-14 2003-01-21 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド Manufacturing method of epitaxial silicon wafer having intrinsic gettering
JP2007281119A (en) * 2006-04-05 2007-10-25 Sumco Corp Wafer for evaluating heat treatment, method of evaluating heat treatment, and method of manufacturing semiconductor wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016032035A (en) * 2014-07-29 2016-03-07 株式会社Sumco Method for manufacturing epitaxial silicon wafer

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