JP2011123796A - Data transfer device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the issuance of a wasteful request that may occur in DMAC interlock. <P>SOLUTION: A writing DMAC 111 and reading DMAC 112 interlock and access a memory. A write request receiving counter 1153 calculates the data amount of write requests (number of write requests) by the write DMAC 111 and notifies the data amount to the reading DMAC 112. Preferably, the receipt notification (Ack notification) of the write request is also notified. A size comparison part 116 compares the data amount of the write request and the data amount of the write request of which request is satisfied on the basis of the received Ack notification. If they match, a request issuance control part 118 controls to access the memory of the read DMAC 112. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a data transfer apparatus and method, and more particularly, to a technique for suppressing issuance of useless requests that may occur in conjunction with DMAC.

  In the technical field of data transfer of digital data such as image data, a DMA (Direct Memory Access) method is widely known. The DMA transmits and receives digital data between a peripheral device and a memory via a DMA controller (hereinafter referred to as “DMAC”) such as a dedicated chip or a control circuit. By transferring data without going through a CPU (Central Processing Unit), the entire system is reduced in processing load and processing speed.

  As an applied technique of the DMA system, a technique called DMAC linkage is known (for example, Patent Document 1). For example, in DMAC linkage, a plurality of DMACs are used on an ASIC (Application Specific IC) to read certain data from the memory using the first DMAC, perform predetermined processing, and then process the processed data as the second data. This is a technique of operating a plurality of DMACs in conjunction with each other, such as writing back to the memory using the DMAC. The purpose of DMAC linkage is to reduce the use capacity of the main memory and simplify the control by the software program.

  Patent Document 1 describes a technique relating to an arbitration method in the case of interlocking DMACs that require matching of memory access amounts in a DMAC interlocking system. However, no consideration is given to interlocking such as reading after confirming whether write data transfer has been completed reliably when DMAC is interlocked, and there is a possibility of performance degradation if retransmission occurs.

  A case in which retransmission or the like occurs is caused by the subsequent DMAC issuing an automatic request in conjunction with the DMAC even though the preceding DMAC request has failed for some reason on the transmission path used by the DMAC. The request issued by the subsequent DMAC becomes a useless protocol and requires retransmission.

  When the DMAC is linked with the software program, since reading is performed after confirming that data has been written to the area set by the descriptor, such a useless protocol as described above does not occur. However, in the case of interlocking with the data size, the request is issued only by determining whether or not the subsequent DMAC has a request issue condition, and thus the above-described problem occurs.

  When a useless request is issued, the time required for retransmission increases. As a result, productivity is reduced. Further, when a retry buffer is used for retransmission as in the PCI-Express standard, the retry buffer is occupied by useless requests. The capacity of the retry buffer to cope with this increases.

  The present invention has been made in view of such circumstances. An object of the present invention is to provide a data transfer apparatus and method capable of suppressing the issuance of useless requests in a data transfer apparatus in which a plurality of direct memory access controllers access memory in conjunction.

  To achieve the above object, the present invention provides, as a first aspect, a first direct memory access controller, and a second direct memory access controller that performs memory access in conjunction with the first direct memory access controller, The first direct memory access controller calculates a first data amount that is an amount of data that is about to perform a memory access, and receives a request for notifying the second direct memory access controller of the first data amount A counter, and the second direct memory access controller uses the first data amount and the data amount of successful data as a result of the first direct memory access controller attempting to perform memory access. Size to compare with a certain second amount of data A request issuing control means for performing control to execute memory access of the second direct memory access controller when the first data amount and the second data amount coincide with each other as a result of the comparison; A data transfer apparatus is provided.

  In order to achieve the above object, the present invention provides, as a second aspect, a first direct memory access controller and a second direct memory access that performs memory access in conjunction with the first direct memory access controller. A data transfer method using a controller, wherein the first direct memory access controller calculates a first data amount which is a data amount to be subjected to memory access, and the second direct memory access A step of notifying the controller of the first amount of data, the first amount of data, and a second amount of data that has succeeded as a result of the first direct memory access controller attempting to perform a memory access; Comparing the data amount of the first data and the first data as a result of the comparison And when said second data amount matches, characterized in that it comprises a step, the performing control to execute the memory access of the second direct memory access controller provides a data transfer method.

  According to the present invention, it is possible to provide a data transfer apparatus and method capable of suppressing the issuance of useless requests in a data transfer apparatus in which a plurality of direct memory access controllers perform memory access in conjunction.

It is a block diagram which shows the hardware structural example of embodiment by this invention. It is explanatory drawing explaining the outline of DMAC interlocking | linkage in this embodiment. It is explanatory drawing for demonstrating the subject solved by this embodiment. It is a block diagram of the principal part of this embodiment. It is a flowchart which shows the flow of a processing operation of the size comparison part 116 of this embodiment.

  FIG. 1 is a configuration diagram illustrating a hardware configuration example of an embodiment according to the present invention. In the present embodiment, the present invention is applied to an image forming apparatus known as a so-called MFP or multifunction peripheral. The image forming apparatus 100 includes a first ASIC 101, a second ASIC 102, a third ASIC 103, a CPU 104, a memory 105, a scanner 106, a plotter 107, and an HDD 108.

  The scanner 106 is an image reading device such as a flatbed scanner or an auto document feeder, and is driven by the control of the first ASIC 101. The first ASIC 101 is a scanner image processing ASIC. The second ASIC 102 compresses an image read using the scanner 106 to create compressed data, or compresses an image output using the plotter 107 to generate compressed data. The HDD 108 is a hard disk drive, and is a secondary storage device that stores compressed data of an image read using the scanner 106 and compressed data of an image output using the plotter 107.

  The CPU 104 is a central processing unit that functions as a controller that controls the entire image forming apparatus 100. The memory 105 is a primary storage device that functions as a work memory for various data processing. The third ASIC 103 decompresses compressed data of an image to be output using the plotter 107, converts the resolution, and performs gradation processing. The plotter 107 is an image forming apparatus such as an electrophotographic system or an inkjet system, and is driven by the control of the third ASIC 103.

  The interface between the first ASIC 101 and the second ASIC 102, between the second ASIC 102 and the CPU 104, and between the CPU 104 and the third ASIC 103 is PCI-Express. The data transfer in PCI-Express is a protocol in which a receipt notification from the receiving side returns to the transmitting side in one request (packet) according to the specification.

  The receipt notification has two values, “Ack” and “Nak”. When Ack returns, it indicates that the data transfer has been performed normally. On the other hand, in the case of Nak, it indicates that there is an abnormality in data transfer, and is a protocol that prompts the transmission side to retransmit. Further, Ack and Nak are not issued every time for one request, but are issued based on an issuance interval recommended in the PCI-Express standard.

  Data transfer between the first ASIC 101 and the second ASIC 102, between the second ASIC 102 and the CPU 104, and between the CPU 104 and the third ASIC 103 is performed by a direct memory access (hereinafter referred to as “DMA”) method. Further, these data transfers involve DMA controller linkage (hereinafter referred to as “DMAC linkage”) as shown in FIG.

  FIG. 2 is an explanatory diagram for explaining an outline of DMAC interlocking in the present embodiment. FIG. 2 shows, as an example, data transfer by DMA between the second ASIC 102 and the CPU 104 and DMAC linkage. That is, the device on the DMAC side may not be the second ASIC 102, and the device on the storage device side may not be the CPU 104. As illustrated, the second ASIC 102 includes a write DMAC 111, a read DMAC 112, an arbitration unit 113, and a PCI-Express interface 114. The CPU 104 includes a PCI-Express interface 115. The arbitration unit 113 is a bus arbiter that arbitrates the use of a bus (in this embodiment, PCI-Express) that is a transmission path of transfer data. The DMAC linkage will be described with reference to FIG.

  In the DMAC linkage, a plurality of DMACs are linked in which data (image data in the present embodiment) is written from the write DMAC 111 to the memory 105, and when the write data exceeds a certain amount, the read DMAC 112 reads the data from the memory 105. A series of control is performed. In the example of FIG. 2, for example, the write DMAC 111 writes the data input from the scanner 106 to the memory 105, the read data is read by the DMAC 112, the image processing unit (not shown) performs image processing, and then the write DMAC 111 again. Is written to the memory 105.

  In the configuration as shown in FIG. 2, the write DMAC 111 notifies the read DMAC 112 of the data size (size notification) when the data transfer to the arbitration unit 113 is completed when the DMAC is linked. When the read DMAC 112 reads write data from the memory 105, the read DMAC 112 issues a read request when the write DMAC 111 has written data of a desired data size to the memory 105 and the size exceeds a certain amount. To do.

  However, when data transfer is performed via PCI-Express at the end of the arbitration unit 113, a communication error may occur on PCI-Express. In this case, the request transfer of the read request from the read DMAC 112 is not performed. It becomes a useless protocol. This will be described with reference to FIG. FIG. 3 is an explanatory diagram for explaining a problem to be solved by the present embodiment.

  In FIG. 3, the write DMAC 111 has written image data, and the written data size is read and passed to the DMAC 112. The read DMAC 112 has a condition for issuing a read request, and the size comparison unit 116 compares the data size passed from the write DMAC 111 with the condition. If the data size matches the read request issuance condition as a result of the comparison, the read DMAC 112 issues a read request.

  Requests issued by each DMAC are sequentially stored in the request buffer on the request receiving side, that is, the storage device side. Here, a write request issued by the write DMAC 111 is set to Wn in the order of issue, and a read request issued by the read DMAC 112 is set to Rn in the order of issue (where n is a natural number and indicates the order of issue). In the example illustrated in FIG. 3, it is a condition that the issue condition of the read request used for the comparison by the size comparison unit 116 is the size of the data transferred by the write request from W1 to W3. The read DMAC 112 issues read requests sequentially when the write data is accumulated for W1 to W3.

  By the way, as described in the last part of the description of FIG. 1, in the PCI-Express data transfer adopted by the present embodiment, a receipt notification (Ack or Nak) from the request receiving side is issued for each request. Not issued, but issued based on the issuance interval recommended by the standard. However, in the DMAC linkage in which a plurality of DMACs are linked, the write DMAC 111 issues a write request and sequentially transfers the size of the data to be transferred to the read DMAC 112, so that a read request is automatically issued in conjunction. . Therefore, even if there is some abnormality in the data transfer and the data cannot be received on the request receiving side, the processing of the next DMAC may start automatically, causing a problem that the issued packet is wasted. .

  In FIG. 3, as an example in which this problem occurs, a case where a receipt failure notification (Nak) is issued for a W2 request (packet) is shown. As shown in the figure, W2 data transfer is not established on the receiving side and Nak (W2) is returned, but R1 and R2 requests are also issued before that. In this case, requests after W2 are discarded on the receiving side, and all of them need to be retransmitted. Therefore, the protocols R1 and R2 are useless.

  When linked with a software program, reading is performed after confirming that data has been written to the area set by the descriptor, so that the above-mentioned useless protocol does not occur. However, when the data size is linked, the read request is issued only under the read request issuance condition of the read DMAC 112, and thus the above-described problem occurs.

  As a configuration for solving the above problems, the present embodiment includes a configuration as shown in FIG. FIG. 4 is a configuration diagram of a main part of the present embodiment. FIG. 4 shows DMA data transfer and DMAC linkage between the second ASIC 102 and the CPU 104 as in FIG. The PCI-Express interface 115 on the request receiving side illustrated in FIG. 2 includes an endpoint controller unit 1151 illustrated in FIG. Further, the write DMAC 111 includes a write size holding unit 117. The read DMAC 112 includes a size comparison unit 116 and a request issue control unit 117.

  The write size holding unit 117 holds the size written by the write DMAC 111 (that is, the data size of transferred write data), and notifies the read DMAC 112 of the size.

  The size comparison unit 116 compares the notified write size with the set interlocking condition (read request issuance condition), and if the interlocked condition is met, calculates the number of issued write requests from the notified write size. To do. In addition, based on the Ack notification transmitted from the endpoint controller unit 1151, the number of write requests that have received the Ack notification is calculated, and the number of issued write requests and the number of write requests that have received the Ack notification are compared. Next, a read request issuance permission is issued based on the comparison result.

  Here, the calculation of the number of issued write requests is “data size / PayLoad size = number of issued write requests”. The PayLoad size is uniquely determined in the system and is not changed in the system.

  The endpoint controller unit 1151 includes a DMAC information reception unit 1152, a write request reception counter 1153, and a logical layer block 1154. The request received from the arbitration unit 113 is transferred to the PCI-Express logical layer block 1154 for processing such as transfer. In general, tag information is added to a request transmitted from the DMAC. The tag information is also notified to the DMAC information receiving unit 1152.

  The DMAC information reception unit 1152 notifies the write request reception counter 1153 when there is a request from a desired DMAC (in this example, “write DMAC 111”). To determine whether the DMAC is a desired one, tag information issued from the DMAC is used. In FIG. 4, for the convenience of explanation, the DMAC that first transmits a request to the request reception side is simplified so that only the write DMAC 111 is used. However, since there is actually access from other DMACs, the desired DMAC It is necessary to count the number of accesses from.

  The write request reception counter 1153 counts the number of requests when a request reception notification is received from a desired DMAC from the DMAC information reception unit 1152. When an Ack notification is received from the logical layer block 1154, the counter information (in this example, “the number of write requests”) at that time is notified to the read DMAC 112 together with the received Ack notification.

  A flow of processing operations executed by the size comparison unit 116 based on the Ack notification thus notified and the counter information counted by the write request reception counter 1153 will be described with reference to FIG. FIG. 5 is a flowchart showing the flow of processing operations of the size comparison unit 116 of the present embodiment. The operation subject of each step in FIG. 5 is the size comparison unit 116.

  Since the write size is sequentially notified from the write size holding unit 117, the size comparison unit 116 can determine whether or not the write size has been updated. When the write size is updated by the write DMAC 111 (step S101 / Yes), it is determined whether or not the read request issuance condition is met (step S102). If they do not match (step S102 / No), it waits for the update of the write size again. If they match (Yes in step S102), it is determined whether the written size matches the number of requests that received the Ack notification (step S103).

  As described above, the write request reception counter 1153 counts the number of issued write requests, and notifies the size comparison unit 116 every time an Ack notification is received. The number of requests that have received the Ack notification is obtained by counting the number of times the size comparison unit 116 has received the notification.

  If they match as a result of the determination in step S103, the size comparison unit 116 issues a read request using the request issuance control unit 118 (step S104). If they do not match, the process waits until the number of requests having received the Ack notification matches.

  According to the above-described embodiment, in the data transfer device including the first direct memory access controller and the second direct memory access controller that accesses the memory in conjunction with the first direct memory access controller, the data by the first direct memory access controller After confirming that the transfer has been completed, a memory access request is issued by the second direct memory access controller, so it can be said that it is possible to prevent the generation of useless requests and the generation of protocols. As a result, the time required for retransmission can be suppressed, and a reduction in productivity can be prevented. In addition, it is possible to reduce the capacity of the retry buffer for dealing with useless retransmission requests.

100 Image forming apparatus 111 Write DMAC
112 Read DMAC
113 Arbitration unit 114, 115 PCI-Express interface 116 Size comparison unit 117 Write size holding unit 118 Request issue control unit 1151 Endpoint controller unit 1152 DMAC information reception unit 1153 Write request reception counter 1154 Logical layer block

JP 2001-215561 A

Claims (6)

A first direct memory access controller;
A second direct memory access controller for accessing memory in conjunction with the first direct memory access controller;
A request reception counter that calculates a first data amount that is the amount of data that the first direct memory access controller has attempted to execute a memory access and notifies the second direct memory access controller of the first data amount. When,
Have
The second direct memory access controller includes a first data amount, a second data amount that is a data amount of data that has succeeded as a result of the first direct memory access controller attempting to perform a memory access, and Size comparison means to compare,
As a result of the comparison, when the first data amount and the second data amount coincide with each other, a request issuance control unit that performs control to execute memory access of the second direct memory access controller;
A data transfer device comprising: The request reception counter receives a notification signal regarding the success or failure of the result of the first direct memory access controller attempting to perform memory access, and the notification signal is sent together with the first data amount each time the reception is received. 2 direct memory access controller,
2. The data transfer apparatus according to claim 1, wherein the size comparison unit measures the second data amount based on the notification signal.   The size comparison means receives a notification of the data amount of the memory access that the first direct memory access controller tried to execute from the first direct memory access controller, and automatically, based on the notification, the first direct memory access controller 3. The data transfer apparatus according to claim 1, wherein the data amount is compared with the second data amount.   4. The data transfer apparatus according to claim 1, further comprising DMAC information receiving means for selecting a memory access from a desired direct memory access controller and notifying the request reception counter.   5. The data transfer apparatus according to claim 1, wherein PCI-Express is used as a data transmission path. A first direct memory access controller;
A data transfer method using a second direct memory access controller that accesses a memory in conjunction with the first direct memory access controller,
Calculating a first amount of data that is the amount of data that the first direct memory access controller is attempting to perform a memory access;
Notifying the second direct memory access controller of the first data amount;
Comparing the first amount of data with a second amount of data that is the amount of data that was successful as a result of the first direct memory access controller attempting to perform a memory access;
A step of performing control to execute memory access of the second direct memory access controller when the first data amount and the second data amount coincide with each other as a result of the comparison;
A data transfer method comprising:

Images