JP2005165619A - Method for controlling data transferring device, data transferring device, storage device controller, method for controlling storage device controller, and channel adaptor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for controlling a data transferring device, a data transferring device, a storage device controller, a method for controlling the storage device controller, and a channel adaptor for efficiently utilizing a CPU. <P>SOLUTION: This data transfer device is provided with a memory equipped with a queue which stores data transfer information including information to specify a first storage region and information to specify a second storage region, a first processor which registers the data transfer information in the queue, and a DMA controller (DMAC) equipped with a register which executes data transfer processing to transfer data stored in the first storage region to the second storage region. The first processor writes a stop command being a command showing the stop of the data transfer processing to be performed by the DMAC in the register of the DMAC, and the DMAC reads the data transfer information registered in the queue, and after executing data transfer processing based on the read data transfer information, the DMAC stops the following data transfer processing registered in the queue when the data stop command is set in the register. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a data transfer device control method, a data transfer device, a storage device control device, a storage device control device control method, and a channel adapter.

As a method for directly transferring data between a memory and a device without using a CPU, a DMA transfer technique using a DMA (Direct Memory Access) controller has been widely used. At the time of DMA transfer, the CPU sets information necessary for data transfer such as a data transfer source and a transfer destination in the DMA controller and instructs data transfer processing. When an instruction for data transfer processing is given, the DMA controller performs data transfer processing without going through the CPU.
JP 2003-91497 A

  However, in the conventional DMA transfer processing, since the CPU directly sets information such as the data transfer source and transfer destination in the register of the DMA controller, in a situation where data transfer processing frequently occurs, the CPU The time required for the setting process to the DMA controller cannot be ignored. When the DMA controller finishes the data transfer process, it notifies the CPU by an interrupt or the like. However, as the data transfer process increases, the notification from the DMA controller to the CPU also increases. Processing will be interrupted.

  The present invention has been made in view of such a background, and a data transfer apparatus control method, a data transfer apparatus, a storage device control apparatus, and a storage device control apparatus control capable of efficiently using a CPU. It is an object to provide a method and a channel adapter.

  A memory including a queue for storing data transfer information including information for specifying a first storage area and information for specifying a second storage area; a first processor for registering the data transfer information in the queue; A second processor that performs a data transfer process for transferring data stored in the first storage area to the second storage area and includes a register, wherein the first processor A stop command, which is a command indicating that the data transfer processing performed by the second processor is stopped, is written to the register of the second processor, and the second processor stores the data transfer information registered in the queue The data transfer processing is performed based on the read data transfer information, and whether the stop command is set in the register. Or the determining, if the stop command to the register is set, and to cancel the data transfer process for subsequent said data transfer information registered in the queue.

  A data transfer apparatus, a data transfer apparatus control method, a storage device control apparatus, a storage device control apparatus control method, and a channel adapter that can efficiently use a CPU can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

=== First Embodiment ===
FIG. 1 is a block diagram showing a computer according to an embodiment of the present invention.
The computer 1 includes a CPU 10, a RAM 20, a storage device 30, an input device 40, an output device 50, a DMA controller 60, and an I / O interface 70.

  The CPU 10 is a processor that controls the entire computer 1. The CPU 10 implements various functions by reading out the program recorded in the storage device 30 to the RAM 20 as appropriate and executing the program stored in the RAM 20. For the storage device 30, various devices such as a hard disk, a flexible disk, and a semiconductor storage device can be used. The storage device 30 may be connected to the outside of the computer 1 as shown in the figure, or may be integrated into the computer 1. The input device 40 is a device used for the user to input data into the computer 1 and is, for example, a keyboard or a mouse. The output device 50 is a device for outputting information to the outside and is, for example, a display or a printer.

  The I / O interface 70 is an interface for the computer 1 to communicate with an external device. The I / O interface 70 is, for example, a communication interface connected to a LAN (Local Area Network) or a serially connected RS232C interface. The I / O interface 70 includes a buffer memory 71. Under the control of the CPU 10, the received data can be written into the buffer memory 71, or the data stored in the buffer memory 71 can be transmitted to an external device. it can.

  The DMA controller 60 transfers data between the device and the memory or between the memory and the memory. When the DMA controller 60 starts the data transfer process in response to an instruction from the CPU 10, the DMA controller 60 can continue the data transfer process without using the CPU 10. For example, the DMA controller 60 can perform data transfer processing for transferring data between the buffer memory 71 provided in the I / O interface 70 and the storage device 30. The DMA controller 60 includes a plurality of registers, one of which is a start register 61. The start register 61 is a register for starting the operation of the DMA controller 60. The DMA controller 60 starts data transfer processing when the start register 61 is written. One of the other registers included in the DMA controller 60 is an abort register 62. The abort register 62 is a register for ending the operation of the DMA controller 60. The DMA controller 60 stops the data transfer process when a predetermined value is written in the abort register 62. The process in which the DMA controller 60 stops the data transfer process will be described later.

  The RAM 20 is provided with two queues. The queue is a storage area that is controlled so that data is read out using a FIFO (First In First Out) method. The transfer information queue 21 is a queue for the CPU 10 to register data transfer information for setting data necessary for data transfer, such as an address of a data transfer source and a data length of data to be transferred. The end status queue 22 is a queue for registering an end status indicating the result of the data transfer process when the DMA controller 60 ends the data transfer process. The end status is data in which an error code or the like is set, for example. The CPU 10 registers data transfer information in the transfer information queue 21. The DMA controller 60 reads the data transfer information from the transfer information queue 21 and performs data transfer processing based on the read data transfer information. The DMA controller 60 registers the end status of the data transfer process in the end status queue 22.

=== Data transfer information ===
FIG. 2 is a diagram illustrating an example of data transfer information. As shown in FIG. 2, the data transfer information includes a transfer ID column 201, a transfer direction column 202, a disk address column 203, and a transfer length column 204.

In the transfer ID column 201, an ID for specifying data transfer information is set. When generating the data transfer information, the CPU 10 assigns an ID for specifying each data transfer information and sets it in the transfer ID column 201.
A value indicating the direction in which data is transferred between the storage device 30 and the buffer memory 71 is set in the transfer direction column 202. For example, when “0” is set in the transfer direction column 202, the data stored in the buffer memory 71 is transferred to the storage device 30. When “1” is set in the transfer direction column 202, the data stored in the storage device 30 is transferred to the buffer memory 71.
In the disk address column 203, the address of the storage device 30 is set. The DMA controller 60 transfers data stored in the disk address column 203 of the storage device 30 to the buffer memory 71, or stores data stored in the buffer memory 71 from the disk address column 203 of the storage device 30. Or forward to.
In the transfer length column 204, the data length of data transferred between the buffer memory 71 and the storage device 30 is set.

  The DMA controller 60 can specify a storage area for the data length set in the transfer length column 204 from the address set in the disk address column 203 on the storage device 30 based on the data transfer information. it can. For example, when “0” is set in the transfer direction column 202 of the data transfer information, the DMA controller 60 is set in the transfer length column 204 from the address set in the disk address column 203 on the storage device 30. The data read from the buffer memory 71 is transferred to the storage area for the data length.

  In the present embodiment, it is assumed that the DMA controller 60 always reads / writes from / to the same address in the buffer memory 71 and does not set the address of the buffer memory 71 in the data transfer information. Of course, the address of the buffer memory 71 may be set in the data transfer information, and the DMA controller 60 may read / write data from / to the address.

=== Data transfer processing ===
FIG. 3 is a flowchart showing a flow of data transfer processing between the buffer memory 71 and the storage device 30 in the present embodiment.

The CPU 10 registers data transfer information in the transfer information queue 21 of the RAM 20 (S3001). The CPU 10 writes to the start register of the DMA controller 60 and instructs the start of data transfer processing (S3002).
When the DMA controller 60 detects that the start register has been written, it reads the data transfer information from the transfer information queue 21 (S3003). The DMA controller 60 performs data transfer processing based on the read data transfer information (S3004). When completing the data transfer process, the DMA controller 60 registers the end status in the end status queue 22 (S3005).

On the other hand, while performing other processes, the CPU 10 checks whether a new end status is registered in the end status queue 22 between the processes (S3006). When detecting that the end status has been written to the end status queue 22 (S3006: YES), the CPU 10 performs processing according to the end status (S3007). The process according to the end status is, for example, outputting a message indicating that the data transfer process has failed to the output device 50 when the data transfer process by the DMA controller 60 has ended abnormally.
If the subsequent data transfer information is registered in the transfer information queue 21, the DMA controller 60 continues the processing from (S3003) without waiting for the write to the start register.

  In the data transfer process described above, the DMA controller 60 starts the data transfer process by the CPU 10 writing to the start register of the DMA controller 60. However, the DMA controller 60 monitors the transfer information queue 21, The data transfer process may be started when it is detected that the data transfer information has been written.

  As described above, the CPU 10 can instruct the DMA controller 60 to perform a plurality of data transfer processes by registering the data transfer information in the transfer information queue 21. The DMA controller 60 reads data transfer information from the transfer information queue 21 and performs data transfer processing based on the read data transfer information. Therefore, the CPU 10 sets data necessary for data transfer processing as data transfer information and sets the transfer information. Data transfer processing can be performed asynchronously independent of processing registered in the queue 21.

  According to the present invention, the first processor (CPU 10) registers the data transfer information in a queue (transfer information queue 21) provided in the memory (RAM 20), whereby the second processor (DMA controller 60). The data transfer process can be instructed to the second processor without directly exchanging data with). Therefore, the first processor can perform other processing without being notified of the end notification every time the data transfer processing ends from the second processor, so that the first processor can be used efficiently. It becomes possible to plan.

  Further, the first processor can grasp the result of the data transfer process performed by the second processor by referring to the memory (end status queue 22). Therefore, the first processor can indirectly obtain the end result of the data transfer process of the second processor via the memory without receiving the end notification directly from the second processor. Therefore, efficient operation of the first processor can be achieved.

  In general, since the clock for operating the CPU 10 is faster than the clock used for the DMA controller 60, the time for accessing the RAM 20 is longer than the time for accessing the registers of the DMA controller 60 from the CPU 10. Often short. Therefore, according to the present invention, the time required for the CPU 10 to set information necessary for data transfer processing to the DMA controller 60 is shortened, and the CPU 10 can operate more efficiently.

  The DMA controller 60 may perform burst transfer on the bus connecting the DMA controller 60 and the RAM 20 when reading the data transfer information from the RAM 20. As a result, the DMA controller 60 can read data with efficient use of the bus. Therefore, efficient transfer processing can be realized for the computer 1 as a whole.

  In general, when the CPU 10 causes the DMA controller 60 to execute data transfer processing continuously, the CPU 10 is necessary for subsequent data transfer after the DMA controller 60 detects that the data transfer processing has ended. Information must be set in the DMA controller 60. On the other hand, according to the present invention, the CPU 10 can write information necessary for data transfer processing into the RAM 20 regardless of the operation status of the DMA controller 60. Therefore, the CPU 10 can instruct the DMA controller 60 to perform a plurality of data transfer processes.

=== Data transfer cancellation processing ===
Here, for the data transfer information that the first processor (CPU 10) has already registered in the queue (transfer information queue 21), for example, the first processor wants to change its contents or delete it from the queue. Can be considered. At this time, for example, when the second processor (DMA controller 60) reads out data transfer information being changed by the first processor and performs data transfer processing based on the data transfer information, There is a possibility that the data transfer process between the storage areas different from the storage area to be instructed by the first processor by the data transfer information may be performed. Also, if the second processor performs a data transfer process based on data transfer information that is about to be deleted from the queue by the first processor, for example, the second processor performs a useless data transfer process. As a result, not only the processing efficiency of the second processor but also the data transfer efficiency of the entire data transfer device may be reduced.
Therefore, the first processor temporarily stops the data transfer process of the second processor so that the second processor does not read the data transfer information that the first processor is changing or deleting. There is a need. However, if the second processor cancels the data transfer process being executed while the data transfer process is being executed, the data transfer process needs to be performed again, resulting in a longer processing time for the data transfer as a whole. There is a risk that. Therefore, in the present invention, after the second processor completes the data transfer process, if a stop command that is a command to stop the data transfer process is set in the register (abort register 62), the subsequent processor The data transfer process is canceled.

Hereinafter, a process in which the first processor stops the data transfer process of the second processor will be described.
The CPU 10 instructs the DMA controller 60 to stop the data transfer process by setting a predetermined value in the abort register 62 of the DMA controller 60. As a value set in the abort register 62, a stop command for instructing to stop the data transfer processing based on a certain data transfer information and an instruction to immediately stop the data transfer processing being executed There are two types of forced termination commands. The stop command is a value such as “0x0001”, for example. The forced termination command is a value such as “0x0002”, for example.

FIG. 4 is a flowchart showing a flow of processing in which the DMA controller 60 stops the data transfer processing. The CPU 10 registers the data transfer information in the transfer information queue 21 and writes it in the start register 61 of the DMA controller 60, whereby the data transfer process of the DMA controller 60 is started.
When the DMA controller 60 detects that data has been written to the start register 61, it reads data transfer information from the transfer information queue 21 (S4001). The DMA controller 60 starts data transfer processing for transferring data between the buffer memory 71 and the storage device 30 based on the read data transfer information (S4002).
When the DMA controller 60 detects that writing has been made to the abort register 62 (S4003), the DMA controller 60 refers to the abort register 62 and checks whether a forced termination command is set (S4004). If the forced termination command is set in the abort register 62 (S4004: YES), the DMA controller 60 stops the data transfer process being executed (S4005). The DMA controller 60 creates an end status indicating that the data transfer process has been forcibly terminated, registers the created end status in the end status queue 22 (S4006), and ends the operation.

  On the other hand, if the abort command is not set in the abort register 62 (S4004: NO), the DMA controller 60 continues the data transfer process even if the abort command is written in the abort register 62 (S4007). . The DMA controller 60 performs data transfer processing between the buffer memory 71 and the storage device 30, and then refers to the abort register 62 to determine whether or not the abort command is set in the abort register 62 (S4008). . If the abort command is set in the abort register 62 (S4008: YES), the DMA controller 60 stops the subsequent data transfer processing. The DMA controller 60 creates an end status indicating that the subsequent processing is stopped and registers it in the end status queue 22 (S4009). When the abort command is not set in the abort register 62 (S4008: NO), an end status indicating that the process has ended normally is created and registered in the end status queue 22 (S4010). Thereafter, the process proceeds to (S4002), and data transfer processing is performed for subsequent data transfer information registered in the transfer information queue 21.

  As described above, in the present invention, after the second processor (DMA controller 60) completes the data transfer process, if a cancel command is set in the register (abort register 62), the subsequent data transfer process is canceled. To do. Therefore, the second processor does not stop the data transfer process during the data transfer process being executed. Also, the first processor (CPU 10) stops the data transfer process without monitoring whether the second processor has completed the data transfer process or receiving a completion notification from the second processor. The second processor can be instructed to stop the operation. Therefore, the first processor can easily set the stop command in the register of the second processor so that the subsequent data transfer process is stopped when the second processor completes the data transfer process. Two processors can be controlled. Therefore, it is possible to minimize the decrease in the data transfer capability of the entire data transfer apparatus (computer 1) due to the suspension of the data transfer process of the second processor while efficiently using the first processor. .

  If the first processor cannot confirm that the second processor has stopped the data transfer process within a predetermined time after setting the stop command in the register of the second processor, the second processor A forced termination command may be written in the register so that the processor forcibly terminates the data transfer process. As a result, for example, when the second processor is waiting without being able to complete the data transfer process, the first processor forces the second processor to end the data transfer process. Can be controlled. Therefore, when the first processor stops the data transfer process of the second processor, the time taken for the second processor to stop the data transfer process can be prevented from exceeding a predetermined time. As a result, the first and second processors can perform efficient processing. Further, it is possible to suppress a decrease in data transfer capability of the entire data transfer apparatus.

  In this manner, the CPU 10 can prevent the subsequent data transfer processing from being performed when the DMA controller 60 finishes the data transfer processing. When the data transfer process of the DMA controller 60 is stopped, the CPU 10 updates the content of the data transfer information registered in the transfer information queue 21 or deletes it from the transfer information queue 21, for example.

  Thereafter, the CPU 10 writes “0” in the abort register 62 of the DMA controller 60 and clears the stop command and the forced end command set in the abort register 62. When the DMA controller 60 detects that writing to the abort register 62 has been made, the DMA controller 60 refers to the value set in the abort register 62. If the value set in the abort register 62 is not a stop command or a forced end command, the DMA controller 60 reads the data transfer information from the transfer information queue 21 and restarts the data transfer process.

  For example, the DMA controller 60 includes a restart register that is a register for instructing to restart the data transfer process, and the CPU 10 writes a value in this restart register instead of writing “0” in the abort register 62. May be set so that the DMA controller 60 resumes the data transfer process.

  Further, the registers such as the start register 61, the abort register 62, and the above-described restart register may be the same register (control register), for example. In this case, the DMA controller 60 starts, stops, forcibly terminates or restarts the data transfer process depending on whether or not “1” is set in a predetermined bit position of the value set in the control register. May be.

=== Deleting registered data transfer information ===
Here, when deleting the data transfer information registered in the transfer information queue 21, the CPU 10 sets a value indicating that the data transfer processing is not performed in the transfer length column 204 of the data transfer information to be deleted. You can also do it. The value indicating that data transfer processing is not performed is, for example, “0”. As a value indicating that data transfer processing is not performed, a value that is not used as a normal data length, such as “−1”, may be used. If the DMA controller 60 sets a value indicating that such data transfer processing is not performed in the transfer length column 204 of the data transfer information read from the transfer information queue 21, the DMA controller 60 does not perform the data transfer processing. can do.

  The CPU 10 can also cancel the data transfer process for the data transfer information registered in the transfer information queue 21 by deleting the data transfer information from the transfer information queue 21. However, the CPU 10 simply sets a value indicating that data transfer processing is not performed in the transfer length column 204 of the data transfer information registered in the transfer information queue 21, and the data transfer information registered in the transfer information queue 21. It is also possible to cancel the data transfer process. That is, the CPU 10 can achieve the same effect as deleting the data transfer information from the transfer information queue 21 only by updating the transfer length column 204 of the data transfer information registered in the transfer information queue 21. . Therefore, compared to the case where the CPU 10 deletes the data transfer information from the transfer information queue 21, the CPU 10 accesses the RAM 20 less when the value is set to the data length of the data transfer information registered in the transfer information queue 21. Become. Therefore, the processing load due to the CPU 10 accessing the RAM 20 is reduced, and the CPU 10 can operate efficiently. Further, the CPU 10 stops the data transfer process of the DMA controller 60 when deleting the data transfer information from the transfer information queue 21. For this reason, the access to the RAM 20 of the CPU 10 is reduced, and the processing time for canceling the data transfer process is shortened. Therefore, the time during which the DMA controller 60 stops the data transfer process is also shortened. Therefore, it is possible to suppress a decrease in the data transfer capability of the computer 1 due to the cancellation of the data transfer process.

  As described above, by reducing the processing load of the CPU 10 and shortening the processing stop time of the DMA controller 60, the data transfer processing efficiency of the computer 1 as a whole can be improved.

=== Second Embodiment ===
Next, an embodiment in which the present invention is applied to a storage device control apparatus will be described.
FIG. 5 is a block diagram showing an overall configuration of an information processing system described as the second embodiment according to the present invention.

  The information processing apparatus 100 and the storage device control apparatus 200 are connected to a network 400 and can communicate with each other via the network 400. The network 400 is, for example, a SAN (Storage Area Network). The network 400 may be connected by a LAN (Local Area Network) other than the SAN. Various protocols such as Fiber Channel, ESCON (registered trademark), FICON (registered trademark), and SCSI (Small Computer System Interface) can be used as the protocol of the network 400.

  The information processing apparatus 100 is a computer that provides an information processing service by using storage resources provided by the storage device control apparatus 200. The information processing service performed by the information processing apparatus 100 is, for example, a bank automatic deposit and payment system or an aircraft seat reservation system. The information processing apparatus 100 is a computer including a CPU (Central Processing Unit) and a memory, and various functions are realized by executing various programs by the CPU. The information processing apparatus 100 can be, for example, a mainframe computer, a workstation, a personal computer, or the like.

  The storage device 300 includes a large number of disk drives and provides a storage area to the information processing apparatus 100. As the disk drive, various devices such as a hard disk device, a flexible disk device, and a semiconductor storage device can be used. The storage device 300 may be configured as a disk array by a plurality of disk drives, for example. In this case, the storage area provided to the information processing apparatus 100 can be provided by a plurality of disk drives managed by RAID.

  The storage device control apparatus 200 is an apparatus that receives a data input / output request for the storage device 300 from the information processing apparatus 100 and performs processing related to data input / output with respect to the storage device 300. The storage device control apparatus 200 includes a channel control unit 210, a shared memory 220, a cache memory 230, and a disk control unit 240. The channel control unit 210 includes a communication interface for performing communication with the information processing apparatus 100 and has a function of receiving a data input / output request for the storage device 300 from the information processing apparatus 100. In response to the received data input / output request, the channel control unit 210 transmits to the disk control unit 240 a command that instructs the disk control unit 240 to input / output data to / from the storage device 300. The disk control unit 240 receives this command and performs processing related to data input / output with respect to the storage device 300. The shared memory 220 is a memory shared by the channel control unit 210 and the disk control unit 240, and stores, for example, commands for instructing control of data input / output as described above. The cache memory 230 stores data exchanged between the channel control unit 210 and the disk control unit 240.

  When the information processing apparatus 100 transmits a data input / output request (hereinafter referred to as a data write request) for requesting data writing to the storage device control apparatus 200, the channel control unit 210 receives the data input / output request. In response to the received data input / output request, the channel control unit 210 generates a command for instructing data writing (hereinafter referred to as a data write command), writes the command to the shared memory 220, and write data received from the information processing apparatus 100 Is written into the cache memory 230. The disk control unit 240 reads a data write command from the shared memory 120 and performs processing for writing the data written in the cache memory 230 to the storage device 300 based on the read command. Note that a data write command that the channel control unit 210 writes to the shared memory 220 and data that the channel control unit 210 writes to the cache memory 230 can be directly transmitted to the disk control unit 240.

=== Channel Control Unit ===
FIG. 6 is a block diagram illustrating a hardware configuration of the channel control unit 210. As shown in this figure, the channel control unit 210 includes a microprocessor 211, a local memory 212, a communication interface 213, a buffer memory 214, and a data transfer LSI 500, which are formed in the same unit. The channel control unit 210 may be integrated with the storage device control apparatus 200, or may be an independent channel control apparatus that can be detached from the storage device control apparatus 200.

  In this figure, the channel control unit 210 includes four microprocessors 211, four local memories 212, and four communication interfaces 213, two buffer memories 214, and one data transfer LSI 500. For example, one microprocessor 211 and two data transfer LSIs 500 may be provided. When the channel control unit 210 includes a plurality of data transfer LSIs 500, the microprocessor 211 needs to notify each of the plurality of data transfer LSIs 500 of the data transfer information. Therefore, the microprocessor 211 can indirectly notify the data transfer information to each of the data transfer LSIs 500 via the memory. Therefore, the processing efficiency of the data transfer process can be improved.

  The microprocessor 211 is a processor that controls the entire channel control unit 210, and implements various functions by executing programs stored in the local memory 212. Each of the four microprocessors 211 shown in FIG. 6 interprets the data input / output request received from the communication interface 213 independently, and instructs the data transfer LSI 500 to transfer data according to the received data input / output request. The disk controller 240 is instructed to read data from the storage device 300.

  Various programs and data are stored in the local memory 212. In the channel control unit 210 in this embodiment, each microprocessor 211 manages one local memory 212. The local memory 212 is connected to the microprocessor 211 via a bus. The local memory 212 is also indirectly connected to the data transfer LSI 500 via a bus in the microprocessor 211. The local memory 212 stores a program executed by the microprocessor 211 and stores data used by the program.

  The communication interface 213 is an interface for performing communication with the information processing apparatus 100, and includes a communication connector for performing communication with the information processing apparatus 100. In the case of the channel control unit 210, for example, data input from the information processing apparatus 100 according to a protocol of Fiber Channel, SCSI, FICON (registered trademark), ESCON (registered trademark), ACONARC (registered trademark), or FIBARC (registered trademark) is input. Receive output requests. The communication interface 213 stores the received data in the buffer memory 214. Further, the communication interface 213 can transmit the data stored in the buffer memory 214 to the information processing apparatus 100.

  Similar to the DMA controller 60 included in the computer 1 according to the first embodiment described above, the data transfer LSI 500 transfers data between a device and a memory or between a memory and a memory. In the present embodiment, the data transfer LSI 500 mainly transfers data between the buffer memory 214 and the cache memory 230. This data transfer process is performed as part of the data input / output process when the storage device control apparatus 200 receives a data input / output request from the information processing apparatus 100. When the communication interface 213 receives the data input / output request, the microprocessor 211 generates data transfer information in response to the received data input / output request, and writes the generated data transfer information in the local memory 212. The data transfer LSI 500 reads the data transfer information written in the local memory 212 and transfers data based on the read data transfer information. For example, when the channel control unit 210 receives a data write request from the information processing apparatus 100, the data transfer LSI 500 transfers the data received by the communication interface 213 and stored in the buffer memory 214 to the cache memory 230.

=== Data Transfer LSI ===
FIG. 7 is a block diagram showing a configuration of the data transfer LSI 500.
The data transfer LSI 500 includes a DMA 501, a PCI interface 502, a PCI interface 503, a buffer control unit 504, a cache interface 505, and a data transfer information fetch unit 506.

The PCI interface 502 is connected to the PCI bus, and exchanges data with the PCI bus. The data transfer LSI 500 is connected to the communication interface 213 via the PCI interface 502.
Similarly to the PCI interface 502, the PCI interface 503 is also connected to the PCI bus. The data transfer LSI 500 is connected to the microprocessor 211 and the local memory 212 via the PCI interface 503.
The communication interface 213, the microprocessor 211, the local memory 212, and the like may be connected using the same PCI bus. In that case, the data transfer LSI 500 only needs to have at least one PCI interface. The PCI interface 502 and the PCI interface 503 may be connected to an external device using a bus other than the PCI bus.

The buffer memory 214 is a buffer for temporarily storing data when the channel control unit 210 exchanges data with the information processing apparatus 100.
The buffer control unit 504 performs control for exchanging data with the buffer memory 214.
The cache interface 505 is an interface that exchanges data with the cache memory 230. The cache interface 505 may be provided with a buffer memory or the like for transferring data more efficiently.

The DMA 501 is, for example, a DMA (Direct Memory Access) processor.
The DMA 501 sets the storage area from which data is transferred and the information specifying the storage area from which data is transferred to the data stored in the data transfer source storage area. It can be transferred to a storage area. In addition to the DMA processor, the DMA 501 may be a program executed on a processor such as a microprocessor, or may be realized by incorporating logic on an application specific IC.
The data transfer information fetch unit 506 reads information necessary for data transfer from the local memory 212 and performs processing such as setting the register of the DMA 501. The data transfer information fetch unit 506 can be, for example, an application specific IC or a microprocessor.
The data transfer LSI 500 may not include the data transfer information fetch unit 506, and the DMA 501 may access the local memory 212.

=== Data transfer information ===
FIG. 8 is a table showing details of data transfer information, which is information necessary for the data transfer LSI 500 to transfer data. The data transfer information 600 includes a mask field 601, a transfer byte number field 602, a cache address field 603, a CRC field 604, a transfer direction field 605, a flag field 606, an identification information field 607, a chain flag field 608, an RCRC field 609, a buffer address. A column 610 and an LRC column 611 are provided.

The microprocessor 211 continuously writes a plurality of data transfer information 600 from a predetermined address in the local memory 212. Therefore, the data transfer LSI 500 can continuously read each of the plurality of data transfer information from the memory.
Further, the microprocessor 211 uses the data transfer information 600 necessary for a series of data transfer processes in units of a group of data transfer information 600 (hereinafter referred to as a transfer information list) formed from a predetermined number of data transfer information 600. Manage. A series of data transfer processes refers to, for example, a storage area on the cache memory 230 that is a data transfer source or a transfer destination is discontinuous with respect to data transfer performed in response to one data input / output request received by the channel control unit 210. In such a case, the data transfer LSI 500 performs a plurality of data transfer processes.

Hereinafter, each column of the data transfer information 600 will be described.
In the mask column 601, among the data transfer information 600 belonging to the transfer information list to which the data transfer information 600 belongs, the value set in each column of the data transfer information 600 processed immediately before by the data transfer LSI 500 is taken over. As an object, information indicating which column value is to be copied when copying and using each column of the data transfer information 600 is set.
In the transfer byte count column 602, the length of data to be transferred is set.
In the cache address column 603, an address on the cache memory 230 used as a transfer source or a transfer destination for the data transfer LSI 500 to transfer data is set.

  In the CRC column 604, an error detection code for data to be transferred is set. For example, the microprocessor 211 calculates a CRC code for data to be transferred using a CRC (Cyclic Redundancy Check) technique, and sets the CRC code in the CRC column 604. When the data transfer LSI 500 performs data transfer, it can use the value set in this field to confirm that there is no error in the data to be transferred. For example, if it is determined that there is an error in the data to be transferred, the data transfer LSI 500 can be configured not to perform data transfer processing.

  The transfer direction column 605 indicates whether the data transfer LSI 500 transfers the data stored in the cache memory 230 to the buffer memory 214 or transfers the data stored in the buffer memory 214 to the cache memory 230. The indicated value is set. In the transfer direction column 605, for example, “0” is set when the data transfer LSI 500 transfers data from the cache memory 230 to the buffer memory 214, and “1” when the data is transferred from the buffer memory 214 to the cache memory 230. Is set.

  Information indicating various setting items is set in the flag column 606. For example, the microprocessor 211 determines whether to perform error detection of data using the value in the CRC field, or whether to write data to the disk control unit 240 synchronously or asynchronously. The indicated value can be set in the flag column 606.

  In the identification information column 607, identification information (processing identification information) given by the microprocessor 211 for each transfer information list is set. As a result, the data transfer LSI 500 can continuously read out a series of data transfer information belonging to the same transfer information list from the local memory 212.

  In the chain flag column 608, a flag value indicating whether or not to process the data transfer information 600 that immediately follows in the series of data transfer information 600 belonging to the transfer information list is set. The data transfer LSI 500 uses the value set in the identification information column 607 or the chain flag column 608 to determine whether or not the data transfer information read from the memory belongs to the data transfer information group to be processed in association with it. Can do. In addition, the data transfer LSI 500 can read out other data transfer information 600 belonging to the data transfer group to which the data transfer information 600 belongs, and perform data transfer processing.

  In the RCRC column 609, an error detection code for data to be transferred is set. The error detection code set in the RCRC column 609 is calculated by, for example, a CRC method. In the RCRC column 609, for example, the storage device control apparatus 200 does not transfer data between the information processing apparatus 100 and the storage device 300, but transfers data related to data replication (remote copy) to another storage apparatus. This is an error detection code for data to be transferred when implemented. In the RCRC column 609, an error detection code for data to be transferred is set in the same manner as the CRC column 604 described above, but the error detection code set in the RCRC column 609 is copied to end status information described later. Are written in the local memory 212. Therefore, the microprocessor 211 can acquire an error detection code for the data to be transferred after the data transfer process is completed. For example, the microprocessor 211 detects an error in the data to be transferred in the past data transfer process acquired from the end status information as an initial value for calculating an error detection code for the data to be transferred in the data transfer process. A sign can be used. The microprocessor 211 can calculate an error detection code for the entire data to be transferred across a plurality of data transfer information 600.

In the buffer address column 610, an address on the buffer memory 214 used as a transfer source or a transfer destination for the data transfer LSI 500 to transfer data is set.
In the LRC column 611, an error detection code for the data transfer information 600 is set. This error detection code is, for example, an LRC code calculated by the LRC method. The microprocessor 211 sets a mask address 601, a transfer byte number field 602, a cache address field 603, a CRC field 604, a transfer direction field 605, a flag, with an address serving as a reference for writing the data transfer information 600 on the local memory 212 as an initial value. The LRC code is calculated using the values in the fields 606, identification information field 607, chain flag field 608, RCRC field 609, and buffer address field 610.

The data transfer LSI 500 can confirm whether or not the read data transfer information is correct information by using an error detection code attached to the data transfer information. Therefore, more reliable data transfer can be realized.
The microprocessor 211 also generates an error detection code including not only the data transfer information but also the reference position for determining the position where the data transfer LSI 500 reads the data transfer information from the local memory 212. Therefore, the data transfer LSI 500 has an error even when there is an error in the contents of the data transfer information, or even when the storage position on the memory from which the data transfer LSI 500 has read the data transfer information is incorrect. Can be detected.

  In the present embodiment, the error detection codes set in the CRC column 604, RCRC column 609, and LRC column 611 of the data transfer information 600 are not limited to CRC codes or LRC codes, but checksums and hammings. Various things, such as a code | symbol, can be used. Further, the data transfer LSI 500 may calculate the error detection codes set in the CRC column 604, the RCRC column 609, and the LRC column 611 of the data transfer information 600.

  In this embodiment, the identification information set in the identification information column 607 is set in units of transfer information lists, but the identification information may be given in units of data transfer information 600. The data transfer LSI 500 performs data transfer processing based on the data transfer information 600, and writes the end status information, which will be described later, into the local memory 212 in correspondence with the identification information assigned to each transfer information list. Therefore, the microprocessor 211 can obtain the result of the data transfer process in units of providing identification information.

=== End status information ===
FIG. 9 is a table showing an example of end status information that the data transfer LSI 500 writes to the local memory 212 when the data transfer by the data transfer LSI 500 ends.

The end status information 700 includes an identification information column 701, an end status code column 702, a transfer processing number column 703, and an RCRC column 704.
In the identification information column 701, the identification information set in the identification information column 607 of the data transfer information 600 read by the data transfer LSI 500 is set as it is. As a result, the data transfer LSI 500 associates the end status information 700 with the transfer information list. In the end status code column 702, a value indicating how the data transfer LSI 500 has finished transferring data is set. In the present embodiment, when the first bit of the end status code column 702 is “1”, it indicates that the data transfer LSI 500 has normally ended the data transfer process for the transfer information list. When the second bit is “1”, it indicates that the data transfer LSI 500 has forcibly terminated the data transfer process by the forced termination command of the microprocessor 211. When the third bit is “1”, it indicates that the data transfer LSI 500 has stopped the data transfer process by the stop command from the microprocessor 211. When the fourth bit is “1”, it indicates that the data transfer LSI 500 has stopped the data transfer process due to a hardware error.

  According to the present invention, the data transfer information 600 and the end status information 700 are associated with each other by the identification information provided to the data transfer information 600 by the microprocessor 211. Therefore, for example, even when a plurality of end status information 700 coexists in the local memory 212, the microprocessor 211 can specify which data transfer information 600 each end status is an end status of. Further, the microprocessor 211 can determine whether the data transfer LSI 500 has correctly processed the data transfer information 600 and returned the end status information 700 to the local memory 212. For example, when the address on the local memory 212 to which the end status information 700 is written by the data transfer LSI 500 is known, the microprocessor 211 indicates that the end status information 700 written to the local memory 212 by the data transfer LSI 500 is It can be confirmed that it corresponds to the instructed data transfer information 600. Accordingly, the microprocessor 211 indicates that the data transfer LSI 500 has read the data transfer information 600 expected by the microprocessor 211 and that the data transfer LSI 500 has written the end status information 700 to a known address on the local memory 212. Can be inspected.

In the transfer processing number column 703, the number of data transfer information 600 processed by the data transfer LSI 500 among the data transfer information 600 belonging to the transfer information list is set. The microprocessor 211 uses the chain flag column 608 of the data transfer information 600 to instruct the data transfer LSI 500 of the number of data transfer information 600 to be processed in the transfer information list, and the data transfer LSI 500 actually performs the data transfer. The number of processings is set in the transfer processing number field 703 of the end status information 700. The microprocessor 211 can compare the instructed number of data transfer processes with the number of processes performed by the data transfer LSI 500 to determine whether the data transfer LSI 500 has operated correctly.
In the RCRC column 704, the value set in the RCRC column 509 of the data transfer information 600 is set as it is. The data transfer LSI 500 calculates an error detection code for the data to be transferred based on the value set in the RCRC column 509 of the data transfer information 600 and sets the result in the RCRC column 704. You can also.

  In the present invention, the data transfer information is indirectly notified from the microprocessor 211 to the data transfer LSI 500 via the memory. When the data transfer LSI 500 writes the end status information 700 in the memory in this way, for example, The microprocessor 211 can check whether the data transfer processing has been performed by the data transfer LSI 500 by checking the end status afterwards.

The data transfer LSI 500 sets the identification information of the data transfer information 600 read from the local memory 212 in the identification information column 701 of the end status information 700 of the data transfer process. Therefore, even when a plurality of end status information 700 coexists on the local memory 212, the microprocessor 211 specifies which data transfer information 600 each of the end status information 700 is the end status information 700 for. Can do.
When the data transfer LSI 500 completes the data transfer process, the result is written as end status information 700 in order from a predetermined address in the local memory 212. In this embodiment, it is assumed that the predetermined address of the local memory 212 is set in advance in the register of the data transfer LSI 500 by the microprocessor 211 by initial setting or the like. Hereinafter, setting of each register of the data transfer LSI 500 will be described.

=== Register configuration ===
FIG. 10 is a diagram illustrating a register included in the data transfer LSI 500. The data transfer LSI 500 includes an LPBA register 801, an LSBA register 802, an LSIBA register 803, an LNUM register 804, an SNUM register 805, an LIP register 806, an STP register 807, an LOP register 808, a POP register 809, and an ABORT register 810.

In the LPBA register 801, an address (hereinafter referred to as a list base address) serving as a reference for the address at which the microprocessor 211 writes the data transfer information 600 in the local memory 212 is set. The microprocessor 211 writes the data transfer information 600 in order from the list base address set in the LPBA register 801.
In the LSBA register 802, an address serving as a reference for the address at which the data transfer LSI 500 writes the end status information 700 in the local memory 212 (hereinafter referred to as a status base address) is set. The data transfer LSI 500 writes the end status information 700 in order from the status base address.
In the LSIBA register 803, an address (hereinafter referred to as a status pointer address) on the local memory 212 to which a pointer (hereinafter referred to as a status pointer) indicating how many times the status transfer address is written by the data transfer LSI 500 is written. ) Is set.
In the LNUM register 804, the number of data transfer information 600 that can be set in one transfer information list is set.
In the SNUM register 805, the number that the data transfer LSI 500 can write the end status 700 on the local memory 212 is set.

The LIP register 806 is set by the microprocessor 211 with information (hereinafter referred to as a list write pointer) indicating the number of the transfer information list written in the local memory 212 by the microprocessor 211 from the list base address. The The microprocessor 211 updates the LIP register 806 every time the data transfer information 600 belonging to the transfer information list is written to the local memory 212.
A status pointer is set in the STP register 807. The data transfer LSI 500 updates the STP register 807 every time the end status information 700 is written to the local memory 212. In addition, the data transfer LSI 500 writes the value set in the STP register 807 to the status pointer address on the local memory 212.
In the LOP register 808, a pointer (hereinafter referred to as a list read pointer) indicating the number of the transfer information list to which the data transfer information 600 read by the data transfer LSI 500 belongs is from the list base address (hereinafter referred to as a list read pointer). Set by

  In the POP register 809, regarding the transfer information list to which the data transfer information 600 read out from the local memory 212 by the data transfer LSI 500 belongs, the number of data transfer LSI 500 that has actually performed the data transfer information 600 in the transfer information list. Is set. The microprocessor 212 compares the number of data transfer processes instructed by using the chain flag column 608 of the data transfer information 600 described above with the number of data transfer processes actually performed by the data transfer LSI 500, and corrects the data. It can be confirmed that the transfer process has been performed.

  The ABORT register 810 is a register for instructing to stop the data transfer processing performed by the data transfer LSI 500. The ABORT register 810 can be set with a value (hereinafter referred to as SUSABORT) that instructs the data transfer LSI 500 to perform data transfer processing in units of transfer information lists and to stop when each data transfer processing is completed. SUSABORT is a value such as “0x0004”, for example. In addition, a value (hereinafter referred to as MPABORT) for instructing to immediately end the data transfer processing being executed by the data transfer LSI 500 can be set in the ABORT register 810. MPABORT is a value such as “0x0001”, for example. The details of the process in which the data transfer LSI 500 cancels the data transfer process will be described later.

The data transfer LSI 500 has received a new data transfer processing instruction from the microprocessor 211 by comparing the list write pointer set in the LIP register 806 with the list read pointer set in the LOP register 808. Can be detected.
The data transfer LSI 500 can check whether there is a transfer information list to be processed subsequently by comparing the contents of the LIP register 806 and the LOP register 808.

  Thus, the microprocessor 211 can write the transfer information list in order from the list base address, and the data transfer LSI 500 can read the transfer information list in order from the list base address. That is, a queue for registering the transfer information list on the local memory 212 can be realized.

  Each register described above may be included in the data transfer information fetch circuit 506, or may be included in the DMA 501. Further, the information stored in these registers may be stored in the local memory 212 or the shared memory 220 instead of the register, and the data transfer LSI 500 may refer to the local memory 212 or the shared memory 220.

=== Flow of Data Transfer Processing Using Transfer Information List ===
Next, data transfer processing using a transfer information list according to the present embodiment will be described. FIG. 11 is a flowchart showing a flow of processing in which data transfer processing using a transfer information list is performed.

  The microprocessor 211 writes a predetermined number of data transfer information 600 set in the LNUM register 804 of the data transfer LSI 500 to the local memory 212 as a transfer information list (S11001), and sets a list pointer in the LIP register 806 of the data transfer LSI 500. (S11002).

On the other hand, the data transfer LSI 500 waits for a new list pointer to be set in the LIP register 806 while comparing the LIP register 806 and the LOP register 808 (S11003). When the data transfer LSI 500 detects that the list pointer is set in the LIP register 806 by the microprocessor 212 (S11003: NO), the data transfer LSI 500 reads the data transfer information 600 on the local memory 212 (S11004). In the data transfer LSI 500, the data transfer information fetch circuit 506 reads the data transfer information 600 from the local memory 212, and sets a value necessary for data transfer processing in the register of the DMA 501 (S11005). The data transfer LSI 500 performs processing related to data transfer between the cache memory 230 and the buffer memory 214 based on the read data transfer information 600 (S11006).
When the data transfer LSI 500 completes the data transfer process, it checks whether the value set in the chain flag column 608 of the data transfer information 600 is “1” (S11007). If the value set in the chain flag column 608 of the data transfer information 600 is “1” (S11007: YES), the process proceeds to (S11004). However, the data transfer information 600 to be read in the next (S11004) is the data transfer information stored in the address advanced by the data length of the data transfer information 600 from the address from which the data transfer LSI 500 previously read the data transfer information 600. 600 is read. In this way, the data transfer LSI 500 sequentially reads the data transfer information 600 based on the chain flag 608 of the read data transfer information 600. Note that the data transfer LSI 500 may read all the data transfer information 600 belonging to the same transfer information list at a time. In this case, the data transfer LSI 500 determines that the data transfer information 600 in which the same value is set in the identification information column 607 of the data transfer information 600 belongs to the same transfer information list.

  If the chain flag column 608 of the data transfer information 600 is not “1” (S11007: NO), the data transfer LSI 500 writes the result of the data transfer process as the end status information 700 in the local memory 212 (S11008). The status pointer set in the STP register 807 is incremented by one (S11009). The data transfer LSI 500 writes the status pointer set in the STP register 807 to the status pointer address on the local memory 212, increments the list pointer set in the LOP register 808 by 1, and updates the LOP register 808 (S11010).

  On the other hand, when the status pointer is updated by the data transfer LSI 500, the microprocessor 211 detects the update (S11011: YES), reads the end status information 700 from the local memory 212, and sends error information to the information processing apparatus 100, for example. An end process corresponding to the end status information 700, such as transmission or display of an error on the display device, is performed (S11012).

  As described above, the microprocessor 211 writes the plurality of data transfer information 600 as one transfer information list in the local memory 212, so that the data transfer LSI 500 continuously reads each of the plurality of data transfer information from the memory. Can do. Further, the data transfer LSI 500 can determine whether or not the data transfer information 600 read from the memory belongs to the data transfer information group to be processed in association using the identification information of the data transfer information 600. Further, the data transfer LSI 500 uses the identification information column 607 or the chain flag column 608 of the data transfer information 600 read from the local memory 212, and uses the other data transfer information belonging to the data transfer group to which the data transfer information belongs. 600 can be read and data transfer processing can be performed.

  For example, in a disk array device, write data accompanying a data write request from an external host device is transferred to a cache memory. In this case, a continuous address may not be secured for all the write data on the cache memory. As described above, when a plurality of data transfer processes are to be performed continuously, such as when the data transfer source and transfer destination storage areas are discontinuous areas, in the present invention, the first processor The same processing identification information is set in a plurality of data transfer information designating continuous storage areas, and the group of data transfer information is registered in the queue. The second processor can continuously perform the data transfer process corresponding to the group of data transfer transfer information by performing the data transfer process on the group of data transfer information attached with the same process identification information. .

  Note that the data transfer LSI 500 may periodically write the status pointer set in the STP register 807 to the local memory 212. Further, the data transfer LSI 500 may store the status pointer directly in the local memory 212 without using the STP register.

=== Cancellation of data transfer processing in units of transfer information list ===
Next, a process in which the data transfer LSI 500 stops the data transfer process as described above will be described.

  As described above, the data transfer LSI 500 continuously performs data transfer processing for a plurality of data transfer information 600 set in the transfer information list while “1” is set in the chain flag column 608. Here, when the microprocessor 211 writes SUSABORT to the ABORT register 810 of the data transfer LSI 500, the data transfer LSI 500 ends a series of data transfer processes for a plurality of data transfer information set in the transfer information list. After that, the data transfer process for the subsequent transfer information list written in the local memory 212 is stopped. On the other hand, when the microprocessor 211 writes MPABORT to the ABORT register 810 of the data transfer LSI 500, the data transfer LSI 500 stops the process even while the data transfer process is being performed. That is, the microprocessor 211 can forcibly terminate the process being executed by the data transfer LSI 500 by writing MPABORT to the ABORT register 810. Therefore, for example, when the data transfer LSI 500 does not write the end status information 700 in the local memory 212 for a certain period, the microprocessor 211 writes MPABORT in the ABORT register 810 and forcibly ends the data transfer processing of the data transfer LSI 500. In addition, the data transfer LSI 500 can be controlled.

  The flow in which the data transfer LSI 500 stops the data transfer processing is the same as the flow of stopping the data transfer processing of the DMA controller 60 according to the first embodiment described above with reference to FIG. The register in which the data transfer LSI 500 performs data transfer processing instead of the DMA controller 60 and the abort command or forced termination command is set is the ABORT register 810 instead of the abort register 62.

  Further, the data transfer process continued in (S4006) is a data transfer process for a plurality of data transfer information 600 set in the transfer information list here. The transfer information queue 21 is realized as a storage area continuous from the list base address on the local memory 212, and the end status queue 22 is realized as a storage area continuous from the status base address on the local memory 212.

  Further, the data transfer LSI 500 creates the end status information 700 as the end status as a result of the end of the data transfer process, and writes it in the local memory 212. At this time, the data transfer LSI 500 sets the identification information set in the identification information column 607 of the data transfer information 600 read from the local memory 212 in the identification information column 701. The data transfer LSI 500 sets “1” in the corresponding bit of the end status code field 702 when SUSABORT or MPABORT is set in the ABORT register 810.

  As described above, in the present invention, the second processor (data transfer LSI 500) performs a group of data transfer information (data transfer information group linked by the chain flag column 608) to which the same processing identification information is attached. After performing the data transfer process and performing the data transfer process for all of the group of data transfer information, if a cancel command is set in the register, the subsequent data transfer process is stopped. Therefore, the second processor can stop the data transfer process when a series of data transfer processes based on the group of data transfer information is completed. Therefore, the second processor does not stop the data transfer process in the middle of a plurality of data transfer processes to be processed continuously. Thereby, it is possible to minimize a decrease in the data transfer capability of the entire data transfer device due to the cancellation of the data transfer process of the second processor.

  Further, the data transfer LSI 500 sets a stop flag indicating whether or not the data transfer process is stopped in the end status code column 702 of the end status information 700 when the stop command is set in the ABORT register 810. Accordingly, the microprocessor 211 indicates that the data transfer LSI 500 has stopped the data transfer process in response to the stop command set in the ABORT register 810 of the data transfer LSI 500, and the end status code of the end status information 700 stored in the local memory 212. It can be obtained by referring to the column 702. Accordingly, the microprocessor 211 confirms that the data transfer LSI 500 has stopped the data transfer process without monitoring the operation of the data transfer LSI 500 or receiving a notification from the data transfer LSI 500 that the data transfer process has been stopped directly. It can be obtained indirectly via the local memory 212. Therefore, efficient operation of the microprocessor 211 can be achieved.

=== Other Embodiments ===
In this embodiment, the unit that the microprocessor 211 writes to the local memory 212 is the transfer information list unit, but it may be a data transfer information unit. For example, the LIP register 804 of the data transfer LSI 500 is information indicating the number of the plurality of data transfer information 600 stored on the local memory 212. When the microprocessor 211 writes a plurality of continuous data transfer information 600, the LIP register 804 is set to indicate what number the data transfer information 600 written last on the local memory 212 becomes. To do. The data transfer LSI 500 adds the data length of the data transfer information 600 to the list base address by the number set in the LOP register 808, obtains an address for reading the data transfer information 600 from the local memory 212, and obtains the data transfer information 600. Can be read. Further, the data transfer LSI 500 can continue to read the data transfer information 600 while adding the data length of the data transfer information 600 to the read address while the chain flag column 608 of the read data transfer information 600 is “1”. . Thus, the data transfer information transmitted from the microprocessor 211 to the data transfer LSI 500 is not the transfer information list unit but the data transfer information 600 unit, and the variable length data transfer information 600 can be transferred.

  In the embodiment of the present invention, the data transfer information 600 is written in the local memory 212 managed by the microprocessor 211. However, instead of the local memory 212, the shared memory 220, the cache memory 230, other memories, etc. Similarly, the microprocessor and the data transfer LSI may store the data in an accessible storage device.

  The present invention can also be applied to the disk control unit 240. For example, if the disk control unit 240 includes a microprocessor, a local memory, an interface for accessing the storage device 300, and a data transfer LSI, data relating to data transferred between the cache memory 230 and the storage device 300 In the transfer process, the same data transfer process as the data transfer process in the channel control unit 210 described above can be realized.

  In the present invention, the communication interface 213 (communication interface unit) included in the channel control unit 210, the microprocessor 211, the local memory 212, the data transfer LSI 500, and the interface (storage device interface) to the storage device 300 are integrated. The present invention can also be applied to storage device control devices that are arranged in an automatic manner. In this case, the data transfer LSI 500 can perform data transfer processing between the storage device 300 and the buffer memory 214 instead of the cache memory 230.

  Although the present embodiment has been described above, the above embodiment is intended to facilitate understanding of the present invention and is not intended to limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof.

1 is a block diagram illustrating a computer according to an embodiment of the present invention. It is a figure which shows an example of the data transfer information by one embodiment of this invention. It is a flowchart which shows the flow of the data transfer process by one embodiment of this invention. 6 is a flowchart showing a flow of processing in which a DMA controller 60 stops data transfer processing according to an embodiment of the present invention. It is a block diagram which shows the whole structure of the information processing system as 2nd Embodiment by one Embodiment of this invention. It is a block diagram which shows the hardware constitutions of the channel control part 210 by one embodiment of this invention. 3 is a block diagram showing a configuration of a data transfer LSI 500 according to an embodiment of the present invention. FIG. 4 is a table showing details of data transfer information, which is information necessary for data transfer by the data transfer LSI 500 according to an embodiment of the present invention. 6 is a table showing an example of end status information that the data transfer LSI 500 writes to the local memory 212 when data transfer by the data transfer LSI 500 ends according to an embodiment of the present invention. It is a table | surface which shows the register | resistor with which data transfer LSI500 by one embodiment of this invention is provided. It is a flowchart which shows the flow of the process in which the data transfer process using the transfer information list by one embodiment of this invention is performed.

Explanation of symbols

1 Computer 10 CPU 20 RAM
21 Transfer information queue 22 End status queue 30 Storage device 40 Input device 50 Output device 60 DMA controller 61 Start register 62 Abort register 70 I / O interface 71 Buffer memory 100 Information processing device 200 Storage device control device 210 Channel control unit 211 Microprocessor 212 Local Memory 213 Communication Interface 214 Buffer Memory 220 Shared Memory 230 Cache Memory 240 Disk Control Unit 300 Storage Device 400 Network 500 Data Transfer LSI 500
600 Data transfer information 700 End status information

Claims (15)

A memory comprising a queue for storing data transfer information including information for specifying a first storage area and information for specifying a second storage area;
A first processor for registering the data transfer information in the queue;
A second processor that performs data transfer processing for transferring data stored in the first storage area to the second storage area, and includes a register;
With
The first processor writes a stop command, which is a command indicating that the data transfer processing performed by the second processor is stopped, to the register of the second processor,
The second processor reads the data transfer information registered in the queue, performs the data transfer process based on the read data transfer information, and determines whether the stop command is set in the register And, if the cancel command is set in the register, canceling the data transfer process for the subsequent data transfer information registered in the queue,
A data transfer device. The data transfer device according to claim 1,
The first processor writes a resume command, which is a command indicating that the data transfer is resumed, to the register of the second processor;
The second processor determines whether the resume command is set in the register, and if the resume command is set in the register, the subsequent data transfer information registered in the queue Resuming the data transfer process for
A data transfer device. The data transfer device according to claim 1,
In the data transfer information, a data length of data transferred by the second processor is set,
The second processor determines whether or not a value indicating that data transfer processing is not performed is set in the data length of the data transfer information read from the queue, and the data length of the data transfer information When the value is set in, the data transfer processing based on the data transfer information is not performed,
A data transfer device. The data transfer device according to claim 1,
The second processor performs the data transfer process based on the data transfer information read from the queue, and writes end status information indicating a result of the data transfer process to the memory;
A data transfer device. The data transfer device according to claim 1,
The first processor sets identification information in the data transfer information and registers it in the queue,
The second processor performs the data transfer process based on the data transfer information read from the queue, determines whether the stop command is set in the register, and sets the stop command in the register. The data transfer process for the subsequent data transfer information registered in the queue is stopped,
The second processor includes a stop flag indicating whether the stop command is set in the register, information indicating a result of the data transfer process, and the identification information set in the data transfer information. Write end status information including to the memory,
The first processor reads the end status information from the memory and refers to the stop flag of the read end status information to determine whether the second processor has stopped the data transfer process. about,
A data transfer device. The data transfer device according to claim 5, wherein
The first processor writes a forced termination command, which is a command indicating termination of the data transfer processing performed by the second processor, to the register of the second processor,
The second processor determines whether or not the forced termination command is set in the register. If the forced termination command is set in the register, the second processor stops the data transfer process and enters the queue. Canceling the data transfer process for the registered subsequent data transfer information;
A data transfer device. The data transfer device according to claim 6, wherein
The first processor sets the stop command in the register of the second processor, determines whether the end status information has been written to the memory, and the end status information has been written to the memory In the case, with reference to the stop flag of the end status information written in the memory, it is determined whether the second processor has stopped the data transfer process,
The first processor writes the forced abort command to the register of the second processor when the second processor cannot determine that the data transfer process has been aborted in a predetermined period;
A data transfer device. The data transfer device according to claim 1,
For the group of data transfer information, the first processor sets process identification information indicating that each of the group of data transfer information corresponds to the related data transfer process of the group of data transfer information. Each of them is attached to each queue and registered in the queue.
The second processor performs the data transfer process for each of the group of data transfer information registered in the queue with the same process identification information attached, and the stop command is set in the register. And if the cancel command is set in the register, canceling the data transfer processing for the subsequent data transfer information registered in the queue;
A data transfer device. A memory comprising a queue for storing data transfer information including information for specifying a first storage area and information for specifying a second storage area;
A first processor for registering the data transfer information in the queue;
A second processor that performs data transfer processing for transferring data stored in the first storage area to the second storage area, and includes a register;
A data transfer device control method comprising:
The first processor writes a stop command, which is a command indicating that the data transfer processing performed by the second processor is stopped, to the register of the second processor,
The second processor reads the data transfer information registered in the queue, performs the data transfer process based on the read data transfer information, and determines whether the stop command is set in the register And, if the cancel command is set in the register, canceling the data transfer process for the subsequent data transfer information registered in the queue,
A method for controlling a data transfer apparatus. A communication interface unit including a buffer memory for receiving a data input / output request transmitted from the information processing apparatus to the storage device, and storing the received data input / output request;
A storage device interface unit that exchanges data with the storage device;
A memory comprising a queue for storing data transfer information including information for specifying a storage area of the buffer memory and information for specifying a storage area of the storage device;
A first processor for registering the data transfer information in the queue;
A second processor that performs data transfer processing for transferring data between the buffer memory and the storage device, and includes a register;
With
The first processor writes a stop command, which is a command indicating that the data transfer processing performed by the second processor is stopped, to the register of the second processor,
The second processor reads the data transfer information registered in the queue, performs the data transfer process based on the read data transfer information, and determines whether the stop command is set in the register And when the cancel command is set in the register, canceling the data transfer processing for the subsequent data transfer information registered in the queue,
A storage device control apparatus. A channel control unit for receiving a data input / output request transmitted from the information processing apparatus to the storage device;
A disk control unit for controlling data input / output with respect to the storage device;
A cache memory for storing data exchanged between the channel control unit and the disk control unit;
A storage device control device comprising:
The channel controller
A communication interface unit comprising a buffer memory for receiving the data input / output request from the information processing apparatus and storing the received data input / output request;
A memory comprising a queue for storing data transfer information including information for specifying a storage area of the buffer memory and information for specifying a storage area of the cache memory;
A first processor for registering the data transfer information in the queue;
A second processor for performing data transfer processing for transferring data between the buffer memory and the cache memory, and comprising a register;
With
The first processor writes a stop command, which is a command indicating that the data transfer process performed by the second processor is stopped, to the register of the second processor;
The second processor reads the data transfer information registered in the queue, performs the data transfer process based on the read data transfer information, and determines whether the stop command is set in the register And, if the cancel command is set in the register, canceling the data transfer process for the subsequent data transfer information registered in the queue,
A storage device control apparatus. A channel control unit for receiving a data input / output request transmitted from the information processing apparatus to the storage device;
A disk control unit for controlling data input / output with respect to the storage device;
A cache memory for storing data exchanged between the channel control unit and the disk control unit;
A storage device control device comprising:
The disk controller is
A cache interface unit comprising a buffer memory for transferring data to and from the cache memory and storing data read from the cache memory or data to be written to the cache memory;
A memory comprising a queue for storing data transfer information including information for specifying a storage area of the buffer memory and information for specifying a storage area of the storage device;
A first processor for registering the data transfer information in the queue;
A second processor for performing data transfer processing for transferring data between the buffer memory and the storage device, and comprising a register;
With
The first processor writes a stop command, which is a command indicating that the data transfer processing performed by the second processor is stopped, to the register of the second processor,
The second processor reads the data transfer information registered in the queue, performs the data transfer process based on the read data transfer information, and determines whether the stop command is set in the register And, if the cancel command is set in the register, canceling the data transfer process for the subsequent data transfer information registered in the queue,
A storage device control apparatus. A communication interface unit including a buffer memory for receiving a data input / output request transmitted from the information processing apparatus to the storage device, and storing the received data input / output request;
A storage device interface unit that exchanges data with the storage device;
A memory comprising a queue for storing data transfer information including information for specifying a storage area of the buffer memory and information for specifying a storage area of the storage device;
A first processor for registering the data transfer information in the queue;
A second processor that performs data transfer processing for transferring data between the buffer memory and the storage device, and includes a register;
A control method of a storage device control apparatus comprising:
The first processor writes a stop command, which is a command indicating that the data transfer processing performed by the second processor is stopped, to the register of the second processor,
The second processor reads the data transfer information registered in the queue, performs the data transfer process based on the read data transfer information, and determines whether the stop command is set in the register And, if the cancel command is set in the register, canceling the data transfer process for the subsequent data transfer information registered in the queue,
A control method for a storage device control apparatus. A channel control unit for receiving a data input / output request transmitted from the information processing apparatus to the storage device;
A disk control unit for controlling data input / output with respect to the storage device;
A cache memory for storing data exchanged between the channel control unit and the disk control unit;
A control method of a storage device control apparatus comprising:
The channel controller
A communication interface unit comprising a buffer memory for receiving the data input / output request from the information processing apparatus and storing the received data input / output request;
A memory comprising a queue for storing data transfer information including information for specifying a storage area of the buffer memory and information for specifying a storage area of the cache memory;
A first processor for registering the data transfer information in the queue;
A second processor for performing data transfer processing for transferring data between the buffer memory and the cache memory, and comprising a register;
With
The first processor writes a stop command, which is a command indicating that the data transfer processing performed by the second processor is stopped, to the register of the second processor,
The second processor reads the data transfer information registered in the queue, performs the data transfer process based on the read data transfer information, and determines whether the stop command is set in the register And, if the cancel command is set in the register, canceling the data transfer process for the subsequent data transfer information registered in the queue,
A control method for a storage device control apparatus. A channel adapter that receives a data input / output request transmitted from an information processing apparatus to a storage device,
A communication interface comprising a buffer memory for receiving the data input / output request and storing the received data input / output request;
A memory comprising a queue for storing data transfer information including information for specifying a storage area of the buffer memory and information for specifying a storage area of the cache memory;
A second processor for performing data transfer processing for transferring data between the buffer memory and the cache memory, and comprising a register;
With
A cache memory for storing data exchanged between the information processing apparatus and the storage device is connected,
In response to the data input / output request received by the communication interface, the first processor receives data transfer information including information indicating a storage area in the buffer memory and information indicating a storage area in the cache memory. Subscribe to the queue,
The first processor writes a stop command, which is a command indicating that the data transfer processing performed by the second processor is stopped, to the register of the second processor,
The second processor reads the data transfer information registered in the queue, performs the data transfer process based on the read data transfer information, and determines whether the stop command is set in the register And when the cancel command is set in the register, canceling the data transfer processing for the subsequent data transfer information registered in the queue,
Features a channel adapter.

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