JP2011118283A - Display device and electronic equipment using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device of an active matrix system in which organic electroluminescence (EL) elements are stacked for stably displaying an image without spoiling reliability of transistors, and which is suitable for a small display device by making a frame area well balanced, and by enabling efficient layout. <P>SOLUTION: The display device includes first display elements, second display elements, pixels, display areas, first pixel circuits, second pixel circuits, and control circuits. A high level signal voltage of a control signal supplied for the first pixel circuit is different from that of the control signal supplied for the second pixel circuit, and a low level signal voltage of the control signal supplied for the first pixel circuit is different from that of the control signal supplied for the second pixel circuit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display device and an electronic apparatus using the display device, and more particularly to an organic EL display device in which organic electroluminescence elements having different emission colors (hereinafter referred to as organic EL elements) are stacked and an electronic apparatus using the same.

  Organic EL display devices have attracted much attention as self-luminous devices that are expected to be thin and have low power consumption.

  In an active matrix display device such as an organic EL display device, display elements are arranged in a matrix in a display region, and display is performed by controlling the display elements by pixel circuits arranged corresponding to the display elements. A driving circuit for controlling each pixel circuit is provided in the periphery of the display area, and wiring such as power supply wiring and signal wiring is formed around the pixel area. Each pixel circuit and a driving circuit provided in the peripheral portion of the display area are formed of thin film transistors (TFTs) and are important elements for determining display quality.

  In general, an organic EL display device employs a configuration in which organic EL elements that are display elements are arranged in parallel. In this configuration, three subpixels of R (red), G (green), and B (blue) are arranged in parallel to form one pixel. In this case, an area of one pixel is divided into three subpixels R, G, and B.

  In contrast to this configuration, in Patent Document 1, a plurality of organic EL elements BU, GU, and RU are stacked in a sub-pixel region, and all active elements (TFTs) connected to the stacked organic EL elements are defined as an insulating substrate SUB. It is formed between the organic EL element BU layer closest to the insulating substrate.

JP 2007-012359 A

  However, in Patent Document 1, in a pixel circuit that independently drives a plurality of stacked organic EL elements BU, GU, and RU, a control signal that is input to the gate of each TFT when the TFT that configures the pixel circuit is controlled. Is common, the amplitude voltage of the control signal increases. Therefore, if this voltage exceeds the breakdown voltage of the TFT, there is a high possibility that the TFT will be destroyed, and the reliability of the circuit will be significantly reduced. Therefore, a drive circuit that performs stable display without reducing reliability is required.

  Accordingly, an object of the present invention is to provide an active matrix display device in which organic EL elements that stably display without degrading the reliability of TFTs are stacked, and an electronic apparatus using the active matrix display device. It is another object of the present invention to provide a display device suitable for downsizing and an electronic device using the same, which enables a balanced and efficient layout of the frame area.

  In order to solve the above problems, the present invention provides a first display element, a second display element, a pixel in which the first display element and the second display element are stacked, and the pixel A plurality of display areas arranged in a matrix, a first pixel circuit for driving the first display element, a second pixel circuit for driving the second display element, and the first And a control circuit for supplying a control signal to the second pixel circuit, wherein a high-level signal voltage of the control signal supplied to the first pixel circuit and the second pixel circuit are provided. The high-level signal voltage of the control signal supplied to the pixel circuit is a different voltage and is supplied to the low-level signal voltage of the control signal supplied to the first pixel circuit and the second pixel circuit. Control signal low level signal voltage is different voltage There is provided a display device, characterized in that there.

  According to the present invention, it is possible to provide an active matrix display device in which organic EL elements that stably display without degrading the reliability of TFTs and an electronic apparatus using the active matrix display device. In addition, by arranging a level shifter on the opposite side of the shift register arrangement side across the display area, the frame area can be balanced and efficiently laid out, and a display device suitable for miniaturization and an electronic device using the same Equipment can be provided.

1 is a schematic diagram illustrating an organic EL display device according to a first embodiment of the present invention. The waveform of the scanning signal in the scanning signal lines (SA1 to SAn) is shown. The waveform of the scanning signal in the scanning signal lines (SB1 to SBn) is shown. An example of the level shifter of this invention is shown. It is a level shifter and timing chart of a 1st embodiment of the present invention. It is explanatory drawing of the organic EL display element and pixel circuit of the organic EL display apparatus of this invention. It is the schematic which shows the organic electroluminescence display of the 2nd Embodiment of this invention. It is the schematic which shows the organic electroluminescence display of the 3rd Embodiment of this invention. It is a digital still camera system using the display device of the present invention. It is a figure which shows the organic electroluminescent display apparatus of a comparative example.

  The display device of the present invention includes a first display element, a second display element, a first pixel circuit for driving the first display element, and a second for driving the second display element. And a control circuit for supplying a control signal to the first pixel circuit and the second pixel circuit.

  FIG. 1 shows an embodiment of a display device of the present invention.

  In FIG. 1, three pixel circuits of a pixel circuit RC, a pixel circuit GC, and a pixel circuit BC are arranged. Although not shown, a display element is connected to each pixel circuit. A circuit composed of the shift register 2, the output buffers 3A and 3B, and the level shifter 4 is a control circuit that supplies a control signal to each pixel circuit. The control circuit used in the display device of the present invention has these configurations. It is not limited. The control signal supplied from the control circuit to the pixel circuit GC and the pixel circuit BC and the control signal supplied from the control circuit to the pixel circuit RC are controlled separately. The display device of the present invention only needs to have two pixel circuits that are separately controlled by the control circuit. In the display device of FIG. 1, one of the pixel circuit GC and the pixel circuit BC, and the pixel circuit RC. The two pixel circuits are sufficient. However, it is preferable to use three pixel circuits as shown in FIG.

  In the display device of the present invention, the first display element and the second display element are stacked to form a pixel, and a plurality of the pixels are arranged in a matrix to form a display region.

  Next, signal voltages of control signals supplied to the first pixel circuit and the second pixel circuit will be described.

  The high level (H level) signal voltage of the control signal supplied to each pixel circuit is supplied by the control circuit to the high level signal voltage of the control signal supplied to the first pixel circuit and the second pixel circuit. The high level signal voltage of the control signal to be set is set to a different voltage.

  On the other hand, the low level (L level) signal voltage of the control signal supplied to each pixel circuit is controlled by the control circuit using the low level signal voltage of the control signal supplied to the first pixel circuit and the second pixel circuit. The low level signal voltage of the control signal supplied to is set to a different voltage.

  Since the control signals supplied to the first pixel circuit and the second pixel circuit are separately controlled by the control circuit, the signal voltage of the control signal supplied to each pixel circuit can be set as described above.

  Here, of the first pixel circuit and the second pixel circuit, the high-level signal voltage of the control signal supplied to one pixel circuit is V1, and the high-level signal voltage of the control signal supplied to the other pixel circuit is Assume that the signal voltage is set to V2 (<V1). In this case, it is preferable that the V2 control signal is supplied as the low level signal voltage to the pixel circuit to which the V1 control signal is supplied as the high level signal voltage.

  Embodiments of the present invention will be described below with reference to FIGS. 1 to 9. In the drawings, parts not related to the present invention are omitted for clarity of explanation of the present invention, and similar parts are denoted by the same reference numerals throughout the description. These drawings schematically show a part of the configuration of an example of the configuration of the organic EL display device according to the present invention.

(First embodiment)
FIG. 1 is a schematic view showing an organic EL display device according to this embodiment.

  In FIG. 1, 1 is a display area, RC is a pixel circuit for driving an R (red) organic EL display element, GC is a pixel circuit for driving a G (green) organic EL display element, and BC is B (blue). 2 shows a pixel circuit for driving the organic EL display element. A plurality of pixel circuits RC, GC, BC are arranged in a matrix in the display area 1. A shift register 2 generates a scanning signal. Reference numerals 3A and 3B denote output buffers, and 4 denotes a level shifter. The output from each stage of the shift register 2 is input to the output buffer 3A and the level shifter 4. The output of the output buffer 3A is connected to scanning signal lines (SA1, SA2, SA3,..., SAn). The output from the level shifter 4 is input to the output buffer 3B, and the output of the output buffer 3B is connected to the scanning signal lines (SB1, SB2, SB3,..., SBn).

  That is, the control circuit of the present embodiment includes the shift register 2, the level shifter 4, and two output buffers (first output buffer and second output buffer). In the present embodiment, one of the first output buffer and the second output buffer is the output buffer 3A, and the other is the output buffer 3B. One output of the shift register 2 is input to the output buffer 3A and the level shifter 4, and the output of the level shifter 4 is input to the output buffer 3B. When the pixel circuit GC or the pixel circuit BC is the first pixel circuit, the control signal input to the first pixel circuit is the control signal output from the output buffer 3A, and the second pixel circuit (pixel circuit). RC) is a control signal output from the output buffer 3B.

  The scanning signal lines (SA1 to SAn) are input to the pixel circuits GC and BC, and the scanning signal lines (SB1 to SBn) are input to the pixel circuit RC. The arrows associated with the scanning signal lines (SA1 to SAn) and the scanning signal lines (SB1 to SBn) in FIG. 1 schematically indicate that they are input to the pixel circuit ahead of the arrows.

  Here, the high (H) level of the scanning signal in the scanning signal lines (SA1 to SAn) is V1, and the low (L) level is V2. The high (H) level of the scanning signal in the scanning signal lines (SB1 to SBn) is V2, and the low (L) level is V3. However, the potential relationship is V1> V2> V3.

  FIG. 2 shows the waveform of the scanning signal in the scanning signal lines (SA1 to SAn). Scan signals are output so as to sequentially become H level (V1) from SA1 to SAn.

  FIG. 3 shows the waveform of the scanning signal in the scanning signal lines (SB1 to SBn). The scanning signal is output so as to sequentially become H level (V2) from SB1 to SBn.

  The level shifter in the present embodiment converts the signal level [H level: V1, L level: V2] into different signal levels [H level: V2, L level: V3]. FIG. 4 is a circuit diagram showing an example of the level shifter of the present invention. Since the basic operation is described in Japanese Patent Application Laid-Open No. 2004-120735, description thereof is omitted.

  FIG. 5 is a circuit diagram (a) and a timing chart (b) of the level shifter of this embodiment.

  The level shifter shown in FIG. 5A includes a capacitor C, inverter circuits INV2 and INV3, and a transistor (M16) that functions as a switch. The input signal IN is input to one terminal of the capacitor C, and the other terminal of the capacitor C is connected to the input portion of the inverter circuit INV2. The output part of the inverter circuit INV2 is connected to the input part of the inverter circuit INV3, and the output signal OUT of the level shifter is output from the output part of the inverter circuit INV3. A transistor (M16) is connected between the input portion of the inverter circuit INV2 and the power supply V3, and a control signal RST is input to the gate of the transistor (M16). The inverter circuits INV2 and INV3 are supplied with power supplies V2 and V3.

  Next, the operation of the level shifter will be described more specifically with reference to the timing chart of FIG. However, description will be made assuming that the transistor (M16) is N channel and the control signal RST is H level: V2 and L level: V3.

[Time t1 to t2]
The control signal RST is at the H level, the transistor (M16) is ON, and the voltage V3 (L) level is input to the inverter circuit INV2. Therefore, the output signal OUT is output at the L (V3) level. The input signal IN is at L (V2) level.

[Time t2 to t3]
Although the control signal RST is at the L level and the transistor (M16) is OFF, the voltage V3 (L) level is maintained at the input portion of the inverter circuit INV2, and the output signal OUT is at the L (V3) level. It is output. Further, the input signal IN remains at the L (V2) level.

[Time t3 to t4]
The input signal IN changes from the L (V2) level to the H (V1) level at time t3. At this time, the potential at the input portion of the inverter circuit INV2 rises from the voltage V3 (L) level due to capacitive coupling by the capacitor C. The amount of voltage increase depends on the input capacitance of INV2, the parasitic capacitance such as the sidewall capacitance of the transistor (M16), in addition to the capacitance value of capacitor C, but the capacitance value of capacitor C exceeds the threshold voltage of INV2. Should be designed. When the potential of the input part of the inverter circuit INV2 exceeds the threshold voltage, the output of INV2 is inverted, and the output signal OUT changes from the L (V3) level to the H (V2) level. The output signal OUT maintains the H (V2) level until time t4. Although not shown here, when the input signal IN changes from the H (V1) level to the L (V2) level, the potential at the input portion of the inverter circuit INV2 drops due to capacitive coupling by the capacitor C. When the potential becomes lower than the threshold voltage of INV2, the output signal OUT changes from the H (V2) level to the L (V3) level.

[Time t4 to t5]
The control signal RST becomes H level, the transistor (M16) is turned ON, and the voltage V3 (L) level is input to the inverter circuit INV2. Therefore, the output signal OUT changes from the H (V2) level to the L (V3) level.

[Time t5 to t6]
Although the control signal RST is at the L level and the transistor (M16) is OFF, the voltage V3 (L) level is maintained at the input portion of the inverter circuit INV2, and the output signal OUT is at the L (V3) level. It is output.

[Time t6 to t7]
The input signal IN changes from the H (V1) level to the L (V2) level at time t6. At this time, the potential at the input portion of the inverter circuit INV2 drops due to capacitive coupling by the capacitor C. However, the potential is only lower than the threshold voltage of INV2, and the output signal OUT remains at the L (V3) level.

  The configuration example of the level shifter 4 has been described above, but the configuration is not particularly limited as long as a certain signal level can be converted into a desired signal level. The shift register 2 may be configured using a flip-prop or a clocked inverter, and the configuration is not particularly limited as long as the function can be realized. As for the output buffers 3A and 3B, a configuration in which two or more inverter circuits whose transistor sizes to be used are designed according to the impedance of the output destination is generally connected. However, the configuration is not particularly limited as long as the function can be realized.

  FIG. 6 is an explanatory diagram of an organic EL display element and a pixel circuit of the organic EL display device according to this embodiment.

  R represents a red organic EL display element, G represents a green organic EL display element, and B represents a blue organic EL display element. RC represents a pixel circuit for driving the organic EL display element R, GC represents a pixel circuit for driving the organic EL display element G, and BC represents a pixel circuit for driving the organic EL display element B. V1, V2, and V3 indicate power sources. The potential relationship is V1> V2> V3.

  The organic EL display elements R, G, and B having a laminated structure will be described. As a relation of lamination, the organic EL display element G and the organic EL display element B are arranged in parallel, and the organic EL display element R is disposed thereon. Are stacked and arranged. As for the organic EL display element G, the anode is connected to the pixel circuit GC, and the cathode is connected to the power source V2. As for the organic EL display element B, the anode is connected to the pixel circuit BC, and the cathode is connected to the power source V2. As for the organic EL display element R, the cathode is connected to the pixel circuit RC, and the anode is connected to the power source V2. That is, the cathode of the organic EL display element G, the cathode of the organic EL display element B, and the anode of the organic EL display element R are commonly connected to the power source V2. In addition, the anode of the organic EL display element G, the anode of the organic EL display element B, and the cathode of the organic EL display element R are connected to the pixel circuits RC, GC, and BC so as to be controlled independently.

  The configuration of the pixel circuits RC, GC, and BC will be described.

  In the pixel circuit GC, Q1 is a P-type driving transistor. Q2 is an N-type switch transistor, and C1 is a storage capacitor. The source electrode of Q1 is connected to the power source V1, and the drain electrode is connected to the anode of the green organic EL display element G. One terminal of the storage capacitor C1 is connected to the gate electrode of Q1, and the other terminal is connected to the power source V1. The source electrode of Q2 is connected to the data signal line DATA1, and the drain electrode is connected to the gate electrode of Q1. The gate electrode of Q2 is connected to the scanning signal line SA, and is connected to one of the scanning signal lines (SA1 to SAn) in FIG.

  In the pixel circuit BC, Q3 is a P-type driving transistor. Q4 is an N-type switch transistor, and C2 is a storage capacitor. The source electrode of Q3 is connected to the power source V1, and the drain electrode is connected to the anode of the blue organic EL display element B. One terminal of the storage capacitor C2 is connected to the gate electrode of Q3, and the other terminal is connected to the power source V1. The source electrode of Q4 is connected to the data signal line DATA2, and the drain electrode is connected to the gate electrode of Q3. The gate electrode of Q4 is connected to the scanning signal line SA, and is connected to one of the scanning signal lines (SA1 to SAn) in FIG.

  In the pixel circuit RC, Q5 is an N-type drive transistor. Q6 is an N-type switch transistor, and C3 is a storage capacitor. The source electrode of Q5 is connected to the power source V3, and the drain electrode is connected to the cathode of the red organic EL display element R. One terminal of the storage capacitor C3 is connected to the gate electrode of Q5, and the other terminal is connected to the power source V3. The source electrode of Q6 is connected to the data signal line DATA3, and the drain electrode is connected to the gate electrode of Q5. The gate electrode of Q6 is connected to the scanning signal line SB and is connected to one of the scanning signal lines (SB1 to SBn) in FIG.

  Next, the operation will be described.

  In the pixel circuit GC, when an H level scanning signal is input to the scanning signal line SA, Q2 is turned on, a data signal corresponding to the display image is applied from the data signal line DATA1 to the gate electrode of Q1, and the data The holding capacitor C1 is charged according to the signal. Thereafter, even if an L level scanning signal is inputted to the scanning signal line SA and Q2 is turned off, the voltage corresponding to the data signal is held in the holding capacitor C1, so that it is determined by the gate-source voltage of Q1. Drive current flows through the organic EL display element G to emit light. The drive current is supplied from the power supply V1 and flows to the power supply V2. The pixel circuit BC also operates in the same manner as the pixel circuit GC.

  In the pixel circuit RC, when an H level scanning signal is input to the scanning signal line SB, Q6 is turned on and a data signal corresponding to the display image is applied from the data signal line DATA3 to the gate electrode of Q5, and The storage capacitor C3 is charged according to the data signal. After this, even if an L level scanning signal is input to the scanning signal line SB and Q6 is turned off, the voltage corresponding to the data signal is held in the holding capacitor C3, so it is determined by the gate-source voltage of Q5. Drive current flows through the organic EL display element R and emits light. The operation is basically the same as that of the pixel circuits GC and BC, but the drive current is supplied from the power supply V2 and flows to the power supply V3.

  In this embodiment, regarding the signal level of the scanning signal lines (SA1 to SAn), the high (H) level may be V4 (V4 ≧ V1), and the signal level of the scanning signal lines (SB1 to SBn) is low (L ) The level may be V5 (V5 ≦ V3). In that case, the power supply of the level shifter 4 may be changed according to the signal level of the scanning signal line.

  In addition, although the pixel circuit is configured with the two transistors and one storage capacitor shown in FIG. 6, the present invention is not limited to this. Any pixel circuit that drives an organic EL display element, such as a voltage programming method or a current programming method having a function of compensating for variations in threshold voltage of transistors, can be applied.

  Further, the organic EL display elements R, G, and B having a laminated structure do not have to have the laminated structure shown in FIG. A configuration in which the organic EL display element R and the organic EL display element B are arranged in parallel and the organic EL display element G is laminated thereon, or the organic EL display element R and the organic EL display element G are arranged in parallel The organic EL display element B may be stacked and disposed thereon. Moreover, as shown in FIG. 7, the organic EL element laminated | stacked on the top does not need to cover all the organic EL elements arranged in parallel below, and is laminated | stacked by the structure which covers one of two organic EL elements. It may be configured.

  As described above, according to the present embodiment, it is possible to separately input scanning signals having different potentials to the pixel circuits GC and BC and the pixel circuit RC by using the level shifter. , It is not necessary to input a larger voltage than necessary to Q6. Therefore, it is possible to provide an active matrix organic EL display device in which organic EL elements are stably stacked without deteriorating the reliability of the TFT, with a circuit configuration that can be driven within the breakdown voltage of the TFT. Further, it is possible to provide a display device that is arranged in a well-balanced manner in the frame region and is suitable for downsizing.

(Second Embodiment)
FIG. 8 is a schematic diagram illustrating an example of an organic EL display device according to the present embodiment. Parts similar to those in FIG. 1 are given the same reference numerals.

  In FIG. 8, 1 is a display region, RC is a pixel circuit for driving an R (red) organic EL display element, GC is a pixel circuit for driving a G (green) organic EL display element, and BC is B (blue). 2 shows a pixel circuit for driving the organic EL display element. A plurality of pixel circuits RC, GC, BC are arranged in a matrix in the display area 1. A shift register 2 generates a scanning signal. Reference numerals 3A 'and 3B' denote output buffers, and 4 'denotes a level shifter. The output buffer 3B 'and the level shifter 4' are arranged on the opposite side of the shift register 2 and the output buffer 3A 'across the display area 1. The output from each stage of the shift register 2 is input to the output buffer 3A '. The output of the output buffer 3A ′ is connected to the scanning signal lines (SA1 ′, SA2 ′, SA3 ′,..., SAn ′), passes through the display area 1 and then input to the level shifter 4 ′. The output from the level shifter 4 'is input to the output buffer 3B', and the output of the output buffer 3B 'is connected to the scanning signal lines (SB1', SB2 ', SB3', ..., SBn ').

  That is, the control circuit of the present embodiment includes the shift register 2, the level shifter 4 ', and two output buffers (first output buffer and second output buffer). In the present embodiment, one of the first output buffer and the second output buffer is the output buffer 3A ', and the other is the output buffer 3B'. One output of the shift register 2 is input to the output buffer 3A ', the output of the output buffer 3A' is input to the level shifter 4 ', and the output of the level shifter 4' is input to the output buffer 3B '. When the pixel circuit GC or the pixel circuit BC is the first pixel circuit, the control signal input to the first pixel circuit is the control signal output from the output buffer 3A ′, and the second pixel circuit (pixel The control signal input to the circuit RC) is the control signal output from the output buffer 3B ′.

  The scanning signal lines (SA1 'to SAn') are input to the pixel circuits GC and BC, and the scanning signal lines (SB1 'to SBn') are input to the pixel circuit RC. The arrows associated with the scanning signal lines (SA1 'to SAn') and the scanning signal lines (SB1 'to SBn') in FIG. 8 schematically indicate that they are input to the pixel circuit ahead of the arrows.

  Here, the high (H) level of the scanning signal in the scanning signal lines (SA1 'to SAn') is V1, and the low (L) level is V2. The high (H) level of the scanning signal in the scanning signal lines (SB1 'to SBn') is V2, and the low (L) level is V3. However, the potential relationship is V1> V2> V3. Therefore, the waveform of the scanning signal in the scanning signal lines (SA1 'to SAn') can be the waveform of FIG. 2, and the waveform of the scanning signal in the scanning signal line (SB1 'to SBn') can be the waveform of FIG.

  Other configurations are the same as those in the first embodiment, and thus description thereof is omitted.

  In the present embodiment, regarding the signal level of the scanning signal lines (SA1 ′ to SAn ′), the high (H) level may be set to V4 (V4 ≧ V1), and the signal level of the scanning signal lines (SB1 ′ to SBn ′). The low (L) level may be V5 (V5 ≦ V3). In that case, the power supply of the level shifter 4 'may be changed in accordance with the signal level of the scanning signal line.

  As described above, by arranging the level shifter on the opposite side of the shift register arrangement side across the display area, the frame area can be balanced and efficient layout can be provided, so that a display device suitable for downsizing is provided. can do. As in the first embodiment, the active matrix organic EL display device has a circuit configuration that can be driven within the breakdown voltage of the TFT, and the organic EL elements are stably stacked without impairing the reliability of the TFT. Can be provided.

(Third embodiment)
The display device of each embodiment described above can be applied to various electronic devices.

  FIG. 9 is a block diagram of a digital still camera system as an electronic apparatus in which the display device of the present invention is used. In the figure, 10 is a digital still camera system, 11 is a photographing unit, 12 is a video signal processing circuit, 13 is a display panel, 14 is a memory, 15 is a CPU, and 16 is an operation unit.

  In FIG. 9, an image captured by the image capturing unit 11 or an image recorded in the memory 14 can be signal-processed by the image signal processing circuit 12 and viewed on the display panel 13. The CPU 15 controls the photographing unit 11, the memory 14, the video signal processing circuit 12, and the like by input from the operation unit 16 to perform photographing, recording, reproduction, and display suitable for the situation. In addition, the display panel 13 can be used as a display unit of various electronic devices.

(Comparative example)
FIG. 10 is an explanatory diagram of an organic EL display element and a pixel circuit of an organic EL display device of a comparative example. Parts similar to those in FIG. 1 are given the same reference numerals.

  R represents a red organic EL display element, G represents a green organic EL display element, and B represents a blue organic EL display element. Also in FIG. 10, RC represents a pixel circuit for driving the organic EL display element R, GC represents a pixel circuit for driving the organic EL display element G, and BC represents a pixel circuit for driving the organic EL display element B. V1, V2, and V3 indicate power sources. As described above, the potential relationship is V1> V2> V3.

  The organic EL display elements R, G, and B having a laminated structure are the same as those in FIG.

  The configuration of the pixel circuits RC, GC, and BC will be described. Portions similar to those in FIG. 1 are given the same reference numerals, and redundant descriptions are omitted. 1 is a scanning signal line to which the N-type switch transistors Q2, Q4, and Q6 are connected, and is connected to the scanning signal line S in common.

  Next, the operation will be described.

  In the pixel circuit GC, when an H level scanning signal is input to the scanning signal line S, Q2 is turned on and a data signal corresponding to the display image is applied from the data signal line DATA1 to the gate electrode of Q1, and the data The holding capacitor C1 is charged according to the signal. After this, even if an L level scanning signal is input to the scanning signal line S and Q2 is turned off, the voltage corresponding to the data signal is held in the holding capacitor C1, so that it is determined by the gate-source voltage of Q1. Drive current flows through the organic EL display element G to emit light. The drive current is supplied from the power supply V1 and flows to the power supply V2. The pixel circuit BC also operates in the same manner as the pixel circuit GC. The pixel circuit RC also basically operates in the same manner as the pixel circuit GC, but the drive current is supplied from the power supply V2 and flows to the power supply V3.

  According to the configuration of FIG. 10, the scanning signal line S is commonly connected to the gate electrodes of Q2, Q4, and Q6. Therefore, in order to reliably turn on / off Q2, Q4 and Q6 between the power supplies V1 to V3, the scanning signal is V4 (V4 ≧ V1) at the high (H) level and V5 (V5 ≦ V3) at the low (L) level. ) Is necessary.

  However, when the amplitude of the scanning signal is (V4-V5), if this voltage exceeds the breakdown voltage of the transistor, there is a high possibility that the transistor will be destroyed, and the reliability of the circuit will be significantly reduced.

  Since the organic EL display device according to the present invention is excellent in long-term reliability with respect to temperature changes in the use environment, it is assumed that the organic EL display device is used in a wide range of temperatures and humidity indoors, outdoors, and throughout the year. It can be used for information display devices of mobile devices such as mobile phones, portable computers, digital cameras, and digital video camera monitors that require high environmental resistance. Or it can utilize for the apparatus which implement | achieves multiple of each of those functions. The information display device includes an information input unit. For example, in the case of a mobile phone, the information input unit includes an antenna. In the case of a PDA or a portable PC, the information input unit includes an interface unit for a network. In the case of a still camera or a movie camera, the information input unit includes an optical sensor unit such as a CCD or CMOS.

  1: display area, 2: shift register, 3A, 3B, 3A ', 3B': output buffer, 4, 4 ': level shifter, RC, GC, BC: pixel circuit, R, G, B: organic EL display element

Claims (6)

A first display element;
A second display element;
A pixel in which the first display element and the second display element are stacked;
A display region in which a plurality of the pixels are arranged in a matrix;
A first pixel circuit for driving the first display element;
A second pixel circuit for driving the second display element;
A control circuit for supplying a control signal to the first pixel circuit and the second pixel circuit;
A display device comprising:
The high level signal voltage of the control signal supplied to the first pixel circuit and the high level signal voltage of the control signal supplied to the second pixel circuit are different voltages,
A display device, wherein a low-level signal voltage of a control signal supplied to the first pixel circuit is different from a low-level signal voltage of a control signal supplied to the second pixel circuit. Of the first pixel circuit and the second pixel circuit,
The high-level signal voltage of the control signal supplied to one pixel circuit is V1,
When the high-level signal voltage of the control signal supplied to the other pixel circuit is V2 (<V1),
2. The display device according to claim 1, wherein a V2 control signal is input as a low level signal voltage to a pixel circuit to which a V1 control signal is supplied as a high level signal voltage. The control circuit includes a shift register, a level shifter, a first output buffer, and a second output buffer,
One output of the shift register is input to the first output buffer and the level shifter, respectively.
The output of the level shifter is input to the second output buffer,
The control signal supplied to the first pixel circuit is a control signal output from the first output buffer,
3. The display device according to claim 1, wherein the control signal supplied to the second pixel circuit is a control signal output from the second output buffer. The control circuit includes a shift register, a level shifter, a first output buffer, and a second output buffer,
One output of the shift register is input to the first output buffer;
The output of the first output buffer is input to the level shifter;
The output of the level shifter is input to the second output buffer,
The control signal supplied to the first pixel circuit is a control signal output from the first output buffer,
3. The display device according to claim 1, wherein the control signal supplied to the second pixel circuit is a control signal output from the second output buffer.   The area where the shift register and the first output buffer are arranged is arranged on the opposite side of the display area with respect to the area where the level shifter and the second output buffer are arranged. The display device according to claim 4.   An electronic apparatus using the display device according to claim 1.

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