JP4339132B2 - Circuit, display device and electronic device - Google Patents

Description

  The present invention relates to a technology of a current output circuit and a DA converter circuit. Furthermore, the present invention relates to a current output circuit, a display device equipped with a DA converter circuit, and an electronic device.

  In recent years, the importance of thin display devices that display images has increased. As a thin display device, a liquid crystal display device that displays an image using a liquid crystal element is a display device (display) for various uses such as a mobile phone and a personal computer, taking advantage of thinness, high image quality, and light weight. Widely used as a device).

  On the other hand, development of a thin display device and a light emitting device using a light emitting element is also in progress. In this light emitting element, there are various elements using various materials such as organic materials, inorganic materials, thin film materials, bulk materials, and dispersion materials.

  A typical light-emitting element that is particularly promising for a thin display device is an organic light-emitting diode (OLED) element. An OLED display device using an OLED element has features such as a high response speed, a high viewing angle, and a low voltage drive suitable for moving image display, in addition to features that are thinner and lighter than existing liquid crystal display devices. Therefore, a wide range of applications such as mobile phones, personal digital assistants (PDAs), televisions, monitors and the like are expected, and it is attracting attention as a next-generation display.

  In particular, active matrix (AM) type OLED display devices are capable of high-definition and large-screen display, which is difficult with passive matrix (PM) type, and have high reliability with low power consumption operation exceeding that of PM type. However, expectations for practical use are very strong. Another advantage of the AM type is that if the drive circuit can be integrated on the panel, the frame of the panel can be narrowed, resulting in a high added value product.

  An OLED element is generally a current-driven light-emitting element having a structure including an anode, a cathode, and a layer containing an organic compound between the anode and the cathode. The current drive type is because the amount of current flowing through the OLED element and the light emission luminance are approximately proportional.

  In the AM type OLED display device, there are a voltage input method and a current input method as drive methods for displaying an image. In the former voltage input method, a video signal of voltage value format data is input as a video signal input to a pixel. On the other hand, in the latter current input method, a video signal of current value format data is input as a video signal input to the pixel. In the AM type OLED display device, as a general theory, the current input method tends to be more preferable.

  The reason why the current input method is preferable is a problem in display quality. In the pixel of the AM type OLED display device, a pixel driving transistor for controlling the light emission luminance of the OLED element of the pixel is connected in series to the OLED element regardless of whether the voltage input method or the current input method is used. In the voltage input method, usually, the voltage of the video signal is directly applied to the gate electrode of the pixel driving transistor. Therefore, when the OLED element emits light at a constant current, if the electric characteristics of the pixel driving transistor are not uniform among the pixels, the OLED element driving current of each pixel varies. The variation in the OLED element driving current results in a variation in the light emission luminance of the OLED element, and the quality of the display image is deteriorated as a sandstorm or carpet pattern unevenness when viewed on the entire screen.

  In particular, a polycrystalline (poly) silicon TFT is usually used as a pixel driving transistor. This is because when an amorphous silicon thin film transistor (TFT) is used as the pixel driving transistor, a current sufficient for light emission with high luminance cannot be obtained. However, polysilicon TFTs tend to have variations in electrical characteristics due to defects at crystal grain boundaries.

  Although the current input method is generally preferable to the voltage input method in the AM type OLED display device, there is a problem. One of them is that the drive circuit is slightly more complicated in the current input method than in the voltage input method, and is difficult to integrate on the panel.

  A panel configuration of a typical current input type AM display device will be described with reference to FIGS.

  FIG. 9 is a configuration diagram of the entire panel. In addition to the pixel portion 931 in which pixels are arranged in a matrix, there are many cases where a gate driving circuit 921 and a data driving circuit 911 are integrally formed on a panel. A one-dot chain line portion 913 in the data driving circuit 911 is a selector circuit. The dotted line portions 912a and 912b in FIG. 9 are current data output circuits, and have a configuration like the dotted line portion 842 in FIG. Reference numeral 841 denotes an output unit.

  The current data output circuit of FIG. 8 is roughly divided into four parts: a shift register unit, a digital data latch unit, a current source (current output circuit), and a DA switch. The current source (current output circuit) and the DA switch together constitute a current output DA converter circuit.

  Reference numerals 801 to 803 correspond to the shift register unit, 803 denotes a positive and reverse clock signal line, and checkers 801 to 802 are circuits indicated by reference numeral 403 in FIG. In the circuit 403, 411 and 413 are known clocked inverters, and 412 is a known inverter. The shift register section sequentially outputs and generates timing signals, and the digital data latch section reads image data (digital data) from the data signal line in accordance with the timing signals.

  Reference numerals 811 to 818 correspond to the digital data latch unit, 817 is a data signal line for each bit, 818 is a latch signal line, and checkers 815 to 816 are circuits indicated by 403 in FIG. In the circuit 403, 411 and 413 are known clocked inverters, and 412 is a known inverter. In FIG. 8, since the image data (digital data) is assumed to be 3 bits, there are three data signal lines. Further, checkers 815 to 816 of 812 and 813 are omitted in the drawing. Image data (digital data) read in accordance with the timing signal from the digital data latch unit is transmitted to the DA switches 821 to 823 in synchronization with the latch signal.

  A dot portion 824 corresponds to a current source (current output circuit), and a specific circuit configuration is shown in a dot portion 791 in FIG. A current source corresponding to each bit is provided independently. Therefore, for example, the current source circuit composed of 701, 711, 721, 731 and 741 is completely independent of the current source circuit composed of 702, 712, 722, 732 and 742. Reference numerals 741 to 741 denote voltage source switches, 771 to 773 denote reference current sources, 782 denotes an output unit, and 792 denotes a current output DA converter.

821 to 823 corresponding to the DA switch are denoted as 761 to 763 in FIG. Since each DA switch is installed in parallel, the total current of all the bit current sources in which the DA switch is on is output from the current data output circuit as a result.

  Since it is most convenient to process image data outside the panel as digital voltage data, the current output DA converter circuit in the current data output circuit of FIG. 8 is important. However, in the DA converter, it is necessary to set current values for all bits separately, and the operation becomes complicated. On the other hand, when the number of bits is large, the number of input lines for current setting increases, the layout becomes complicated, and the area increases.

  Since it is most convenient to process image data outside the panel as digital voltage data, the current output DA converter circuit in the current data output circuit of FIG. 8 is important. However, the DA converter has a disadvantage that a long setting time is required, for example, when the analog current to be output is zero or extremely small.

  It is an object of the present invention to provide a method for shortening the set time in a DA converter circuit that reads digital voltage value format data and outputs analog current value format data. The present invention can be used as a data driving circuit used in a current input type AM-type OLED display device.

  First, the present invention includes a current output DA converter circuit.

  The current output DA converter circuit includes a current output circuit including a plurality of drive transistors, and each drain of the plurality of drive transistors includes a switch that is controlled to be turned on / off according to bit data. It is desirable that However, the present invention is not limited to this. The current output DA converter circuit includes a plurality of drive transistors, the plurality of drive transistors electrically connecting gate electrodes to each other, and a switch is provided between the gate electrode and each drain of the plurality of drive transistors. It may include a current output circuit characterized by being provided.

  The current output DA converter circuit of the present invention has a function of exceptionally supplying a constant voltage when input data is predetermined.

  Furthermore, the present invention includes a display device and an electronic device that use the current output DA converter circuit.

The present invention reduces the time required for data output in a DA converter circuit that reads data in digital voltage value format and outputs data in analog current value format when the data to be output is a very small current.
The present invention can be used for a data driving circuit used in an AM type OLED display device of a current input system.

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1)
An embodiment of the present invention will be described with reference to FIGS. 9, 3, 4, and 1. FIG. In this example, the DA converter circuit of the present invention is used for a data drive circuit of an AM type OLED display device. In this example, data of a 3-bit digital voltage value format is read as image data, but it goes without saying that the DA converter circuit of the present invention has no limit on the number of bits. In the following description of this example, the portion corresponding to the circuit of FIG. 1 can be replaced with the circuit of FIG. 2 or FIG.

  FIG. 9 is a configuration diagram of the entire panel. A pixel portion 931 in which pixels are arranged in a matrix, a gate drive circuit 921, and a data drive circuit 911 are integrally formed on the panel. A one-dot chain line portion 913 in the data driving circuit 911 is a selector circuit. Dotted lines 912a and 912b in FIG. 9 are current data output circuits, and have a configuration similar to the dotted line 342 in FIG.

  Hereinafter, first, the 342 (FIG. 3) corresponding to the current data output circuits 912a and 912b will be described, and then the selector circuit 913 will be described.

  The current data output circuit 342 shown in FIG. 3 is roughly divided into five parts: a shift register unit, a digital data latch unit, a current source (current output circuit), a DA switch, and a voltage source switch. The current source (current output circuit) and the DA switch together constitute a current output DA converter circuit. Reference numeral 341 denotes an output unit.

  Numerals 301 to 303 correspond to the shift register unit, 303 is a positive and reverse clock signal line, and the checker units 301 to 302 are constituted by a circuit indicated by 403 in FIG. 4, for example. In the circuit 403, 411 and 413 are known clocked inverters, and 412 is a known inverter. However, the configuration of the checker units 301 to 302 is not limited to the circuit indicated by 403. Any circuit that realizes an equivalent function may be used.

  The shift register units 301 to 303 sequentially generate and generate timing signals, and the digital data latch unit reads image data (digital data) from the data signal lines in accordance with the timing signals.

  Numerals 311 to 318 correspond to digital data latch units, 317 is a data signal line for each bit, 318 is a latch signal line, and checkers 315 to 316 can use the circuit indicated by 403 in FIG. In the circuit 403, 411 and 413 are known clocked inverters, and 412 is a known inverter. In FIG. 3, since image data (digital data) is assumed to be 3 bits, there are three data signal lines. Further, checkers 315 to 316 of 312 and 313 are omitted in the drawing. Image data (digital data) read in accordance with the timing signal from the digital data latch unit is transmitted to the DA switches 321 to 323 in synchronization with the latch signal.

  A dot portion 324 corresponds to a current source (current output circuit), and a specific circuit configuration is shown in a dot portion 191 in FIG. Transistors 101 to 103 are drive transistors. The transistors 161 to 163 (FIG. 1) correspond to the DA switch. This DA switch transistor corresponds to 321-323 in FIG.

  In FIG. 1, the driving transistors corresponding to the respective bits are provided independently. For example, the first bit (MSB) is 101, the second bit is 102, the third bit (LSB) is 103, and the L / W size of each transistor is approximately 1: 2: 4. However, since the gate electrodes of the drive transistors 101 to 103 are electrically connected, it is possible to set the reference current at the same time. In this respect, the circuit of FIG. 1 differs from the circuit of FIG. Further, since the circuit of FIG. 1 has fewer transistors and wirings than the circuit of FIG. 7, the area can be reduced.

  The operation when setting the reference current in the current source (current output circuit) of FIG. 1 will be described.

  When setting the reference current, first, a signal that turns off the transistors 161 to 163 is input from the digital signal input lines 151 to 153. When the transistors 161 to 163 are n-channel type, they are low (low voltage) signals. However, the transistors 161 to 163 do not need to be turned off when there is no fear of leakage of current from the output unit 182 such as when the tip of 182 is in an electrically open (high impedance) state.

  Next, a signal for turning on the transistors 121 to 123 and 140 is input from the current setting signal input line 110. When these transistors are n-channel type, they are high (high voltage) signals. Then, a reference current flows from the reference current source 170 to the constant voltage source 181. At this time, the gates and drains of the drive transistors 101 to 103 are short-circuited. Therefore, when a signal that turns off the transistors 121 to 123 and 140 is input from the current setting signal input line 110 after the current has reached a steady value, the reference current is stored as the gate voltage of the drive transistors 101 to 103. .

  This completes the setting of the reference current. However, since the leakage current from the gate node of the driving transistors 101 to 103 is very small, the setting of the reference current needs to be repeated periodically (or irregularly).

  After setting the reference current, a digital voltage signal corresponding to the image signal is input from the digital signal input lines 151 to 153. Digital signal input lines 151-153 correspond to the data input section of current output DA converter circuit 192. Since the DA switch transistors 161 to 163 are installed in parallel, the total current of all the bit current sources in which the DA switch is on is output from the output unit 182 as a result. Thus, the digital voltage data is converted into an analog current.

  In the current output DA converter circuit 192 of FIG. 1, if there are variations in electrical characteristics such as threshold voltage values and field-effect mobility of the drive transistors 101 to 103, the display of intermediate gradation may be inaccurate. is there. However, accurate display at the maximum gradation is guaranteed by the above-described reference current setting.

  Further, in the current output DA converter circuit 192 of FIG. 1, since all the bits are set simultaneously, the complexity is eliminated as compared with the case of FIG.

  The example of FIG. 1 is a DA converter circuit that reads data in a 3-bit digital voltage value format and outputs data in an analog current value format. However, the digital voltage value in N bits (N is an arbitrary integer of 2 or more) The same configuration can be used for reading format data.

  In the example of FIG. 1, the drive transistors 101 to 103 are n-channel type and 181 is a low voltage source. However, the same configuration is possible even if the drive transistors 101 to 103 are p channel type and 181 is a high voltage source. Can be used. Even in another configuration, it has a plurality of drive transistors, the plurality of drive transistors electrically connecting gate electrodes to each other, and a switch between the gate electrode and each drain of the plurality of drive transistors. As long as it includes a current output circuit including

  Since it is most convenient to process image data outside the panel as digital voltage data, the current output DA converter circuit 192 (FIG. 1) or 335 (FIG. 3) in the current data output circuit of FIG. 3 is important. .

  However, for example, when the analog current to be output is zero or very small, a long setting time is required, which is inconvenient only with the current output DA converter circuit of FIG.

  In such a case, the voltage output function of the present invention is useful. Hereinafter, an operation of outputting a voltage using the voltage source switch transistors 331 to 333 will be described.

  In FIG. 3, reference numeral 334 denotes a constant voltage source (constant voltage line). Since the current output DA converter circuit of FIG. 1 is a low voltage current output circuit, the analog current to be output is zero when the voltage is high. Therefore, it is convenient to use 334 as a high voltage constant voltage. In this case, the voltage source switch transistors 331 to 333 may be connected in series as a p-channel type so that the voltage is output only when the digital voltage data is a low signal with all bits.

  In FIG. 3, the voltage source switch transistors 331 to 333 are p-channel type, but the present invention is not limited to this. Of course, an n-channel type can also be used in some cases.

  The voltage source switch transistors 331 to 333 may adopt other configurations.

  In summary, 342 corresponding to the current data output circuits 912a and 912b has been described. Next, the selector circuit 913 will be described. As a specific example of the selector circuit 913, a circuit configuration is shown in FIG. 10 (955), but the invention is not limited to this.

  The selector circuit 913 in FIG. 9 switches the output of the current data output circuit 912a or 912b to the data line 914a or 914b. In FIG. 9, the ratio between the number of current data output circuits and the number of data lines per selector circuit is 2: 2, but generally other ratios are possible. What is essential here is that a plurality of current data output circuits are provided for each selector circuit.

  By providing a plurality of current data output circuits for each selector circuit, the current source (dot portion 191 in FIG. 1) of the other current data output circuit even while one current data output circuit outputs data. It is possible to set the reference current. Therefore, the time can be effectively utilized.

  For example, it is possible to output data at 912b while setting the reference current to the current data output circuit 912a in the odd frame, and to output data at 912a while setting the reference current to the current data output circuit 912b at the even frame. . Then, it is not necessary to provide a period for setting the reference current separately from the period for data output, and the time can be effectively used.

  The selector circuit 913 of FIG. 9 is useful because it provides the above advantages, but is not an essential element of the present invention. Therefore, another configuration may be adopted instead of FIG.

(Embodiment 2)
Another example of the implementation of the present invention will be described with reference to FIGS. 5, 3, 4, and 2. In this example, the DA converter circuit of the present invention is used for a data drive circuit of an AM type OLED display device. In this example, data of a 3-bit digital voltage value format is read as image data, but it goes without saying that the DA converter circuit of the present invention has no limit on the number of bits. In the following description of this example, the portion corresponding to the circuit of FIG. 2 can be replaced with the circuit of FIG. 1 or FIG.

  FIG. 5 is a configuration diagram of the entire panel. A pixel portion 531 in which pixels are arranged in a matrix, a gate driving circuit 521, and a data driving circuit 511 are integrally formed on the panel. A dotted line portion 512 in FIG. 5 is a current data output circuit, and has a configuration like the dotted line portion 342 in FIG. In this example as well, a data driving circuit having a selector circuit as shown in FIG. 9 may be used instead of FIG. 5, but the configuration of the entire panel is as shown in FIG. 5 for simplicity of explanation.

  Hereinafter, 342 corresponding to the current data output circuit 512 will be described.

  The current data output circuit 342 shown in FIG. 3 is roughly divided into five parts: a shift register unit, a digital data latch unit, a current source (current output circuit), a DA switch, and a voltage source switch. The current source (current output circuit) and the DA switch together constitute a current output DA converter circuit.

  Numerals 301 to 303 correspond to the shift register unit, 303 is a positive and reverse clock signal line, and the checker units 301 to 302 are constituted by a circuit indicated by 403 in FIG. 4, for example. In the circuit 403, 411 and 413 are known clocked inverters, and 412 is a known inverter. However, the configuration of the checker units 301 to 302 is not limited to the circuit indicated by 403. Any circuit that realizes an equivalent function may be used.

  The shift register units 301 to 303 sequentially generate and generate timing signals, and the digital data latch unit reads image data (digital data) from the data signal lines in accordance with the timing signals.

  Numerals 311 to 318 correspond to digital data latch units, 317 is a data signal line for each bit, 318 is a latch signal line, and checkers 315 to 316 can use the circuit indicated by 403 in FIG. In the circuit 403, 411 and 413 are known clocked inverters, and 412 is a known inverter. In FIG. 3, since image data (digital data) is assumed to be 3 bits, there are three data signal lines. Further, checkers 315 to 316 of 312 and 313 are omitted in the drawing. Image data (digital data) read in accordance with the timing signal from the digital data latch unit is transmitted to the DA switches 321 to 323 in synchronization with the latch signal.

  A dot portion 324 corresponds to a current source (current output circuit), and a specific circuit configuration is shown in a dot portion 291 in FIG.

  Transistors 201 to 203 are driving transistors, and transistors 261 to 263 are DA switch transistors, which correspond to 321-323 in FIG.

In FIG. 2, drive transistors corresponding to the respective bits are provided independently. For example, the first bit (MSB) is 201, the second bit is 202, the third bit (LSB) is 203, and the L / W size of each transistor is preferably about 1: 2: 4. More generally speaking, the L / W size of each transistor is binary weighted, such as approximately 2 ⁰ : 2 ¹ :...: 2 ^N-1 (N is an arbitrary integer greater than or equal to 2). Is desirable.

  Since the drive transistors 202 to 203 have the gate electrodes electrically connected, it is possible to set the reference current at the same time. In this respect, the circuit of FIG. 2 differs from the circuit of FIG. Since the circuit of FIG. 2 has fewer transistors and wirings than the circuit of FIG. 7, the area can be reduced.

  Further, the gate electrode of the driving transistor 201 is not electrically connected to the gate electrodes 202 to 203. In this respect, the circuit of FIG. 2 is different from the circuit of FIG. Since the circuit of FIG. 2 sets the reference current for the driving transistor 201 of the first bit (MSB) independently of the other bits, the accuracy of the current value of the MSB data can be expected.

  The operation when setting the reference current in the current source (current output circuit) of FIG. 2 will be described.

  When setting the reference current, first, a signal that turns off the transistors 261 to 263 is input from the digital signal input lines 251 to 253. When the transistors 261 to 263 are n-channel type, they are low (low voltage) signals. However, the transistors 261 to 263 do not need to be turned off when there is no fear of leakage of current from the output unit 282, such as when the tip of 282 is in an electrically open (high impedance) state.

  Next, a signal for turning on the transistors 222 to 223 and 240 is input from the current setting signal input line 210. When these transistors are n-channel type, they are high (high voltage) signals. Then, a reference current flows from the reference current source 270 to the constant voltage source 281. At this time, the gates and drains of the drive transistors 202 to 203 are short-circuited. Therefore, when a signal that turns off the transistors 222 to 223 and 240 is input from the current setting signal input line 210 after the current reaches a steady value, the second and third bits are used as the gate voltages of the driving transistors 202 to 203. The reference current is stored.

  At the same time or at another timing, a signal for turning on the transistors 221 and 241 is input from the current setting signal input line 211. When these transistors are n-channel type, they are high (high voltage) signals. Then, a reference current flows from the reference current source 271 to the constant voltage source 281. At this time, the gate and drain of the driving transistor 201 are short-circuited. Therefore, when a signal that turns off the transistors 221 and 241 is input from the current setting signal input line 211 after the current has reached a steady value, the reference current of the first bit (MSB) is used as the gate voltage of the driving transistor 201. Remembered.

  This completes the setting of the reference current. However, since the leakage current from the gate node of the drive transistors 201 to 203 is very small, the setting of the reference current needs to be repeated periodically (or irregularly).

  After setting the reference current, a digital voltage signal corresponding to the image signal is input from the digital signal input lines 251 to 253. Digital signal input lines 251 to 253 correspond to the data input section of current output DA converter circuit 192. Since the DA switch transistors 261 to 263 are installed in parallel, the total current of the current sources of all the bits in which the DA switch is on is output from the output unit 282 as a result. Thus, the digital voltage data is converted into an analog current.

  In the current output DA converter circuit 292 of FIG. 2, if there are variations in the electrical characteristics such as the threshold voltage values and field effect mobility of the drive transistors 202 to 203, the display of the intermediate gradation may be inaccurate. is there. However, the above-described reference current setting ensures accurate display at the maximum gradation and the intermediate gradation of the MSB.

  Further, in the current output DA converter circuit 292 of FIG. 2, since the reference current setting is simultaneously performed for the second bit and the third bit, the complexity is eliminated as compared with the case of FIG. The

  The example of FIG. 2 is a DA converter circuit that reads data in a 3-bit digital voltage value format and outputs data in an analog current value format. However, the digital voltage value in N bits (N is an arbitrary integer greater than or equal to 2). The same configuration can be used for reading format data.

  In the example of FIG. 2, the drive transistors 201 to 203 are n-channel type and 281 is a low voltage source, but the same configuration is possible even if the drive transistors 201 to 203 are p-channel type and 281 is a high voltage source. Can be used. Even in another configuration, it has a plurality of drive transistors, the plurality of drive transistors electrically connecting gate electrodes to each other, and a switch between the gate electrode and each drain of the plurality of drive transistors. As long as it includes a current output circuit including

  Further, the position of the transistor 240 and the connection node of the capacitor 230 are not limited to the example of FIG. For example, it can be the same as the example of FIG. It is only necessary to be able to store the source-gate voltages of the drive transistors 202 to 203 when the reference current is set.

  In addition, the example of FIG. 2 has the same configuration as the example of FIG. 1 for 2 bits, and a configuration in which a reference current is set independently for the other 1 bit, but the example of FIG. 1 for the p bits. For the q bits, the reference current may be set independently (p and q are arbitrary integers of 2 or more). Furthermore, the x bit may have the same configuration as the example of FIG. 1, and the y bit may have the same configuration as the example of FIG.

  Since it is most convenient to process image data outside the panel as digital voltage data, the current output DA converter circuit 292 (FIG. 2) or 335 (FIG. 3) in the current data output circuit of FIG. 3 is important. .

  However, for example, when the analog current to be output is zero or very small, a long setting time is required, which is inconvenient only with the current output DA converter circuit of FIG.

  In such a case, the voltage output function of the present invention is useful. Hereinafter, an operation of outputting a voltage using the voltage source switch transistors 331 to 333 will be described.

  In FIG. 3, reference numeral 334 denotes a constant voltage source (constant voltage line). Since the current output DA converter circuit of FIG. 1 is a low voltage current output circuit, the analog current to be output is zero when the voltage is high. Therefore, it is convenient to use 334 as a high voltage constant voltage. In this case, the voltage source switch transistors 331 to 333 may be connected in series as a p-channel type so that the voltage is output only when the digital voltage data is a low signal with all bits.

  In FIG. 3, the voltage source switch transistors 331 to 333 are p-channel type, but the present invention is not limited to this. Of course, an n-channel type can also be used in some cases.

  The voltage source switch transistors 331 to 333 may adopt other configurations.

  The description has been made with respect to 342 corresponding to the current data output circuit 512.

(Embodiment 3)
Another example of the implementation of the present invention will be described with reference to FIGS. 5, 11, 4, and 2. FIG. In this example, the DA converter circuit of the present invention is used for a data drive circuit of an AM type OLED display device. In this example, data of a 3-bit digital voltage value format is read as image data, but it goes without saying that the DA converter circuit of the present invention has no limit on the number of bits. In the following description of this example, the portion corresponding to the circuit of FIG. 2 can be replaced with the circuit of FIG. 1 or FIG.

  FIG. 5 is a configuration diagram of the entire panel. A pixel portion 531 in which pixels are arranged in a matrix, a gate driving circuit 521, and a data driving circuit 511 are integrally formed on the panel. A dotted line portion 512 in FIG. 5 is a current data output circuit, and has a configuration like the dotted line portion 1342 in FIG. In this example as well, a data driving circuit having a selector circuit as shown in FIG. 9 may be used instead of FIG. 5, but the configuration of the entire panel is as shown in FIG. 5 for simplicity of explanation.

  Hereinafter, 1342 corresponding to the current data output circuit 512 will be described.

  The current data output circuit 342 shown in FIG. 3 is roughly divided into five parts: a shift register unit, a digital data latch unit, a current source (current output circuit), a DA switch, and a voltage source switch. The current source (current output circuit) and the DA switch together constitute a current output DA converter circuit.

  Reference numerals 1301 to 1303 correspond to the shift register units. Reference numeral 1303 denotes a positive and negative clock signal line, and the checker units 1301 to 1302 are constituted by a circuit indicated by 403 in FIG. In the circuit 403, 411 and 413 are known clocked inverters, and 412 is a known inverter. However, the configuration of the checker units 1301 to 1302 is not limited to the circuit indicated by 403. Any circuit that realizes an equivalent function may be used.

  The shift register units 1301 to 1303 sequentially output and generate timing signals, and the digital data latch unit reads image data (digital data) from the data signal lines in accordance with the timing signals.

  Reference numerals 1311 to 1318 correspond to digital data latch units, 1317 is a data signal line for each bit, 1318 is a latch signal line, and checkers 1315 to 1316 are circuits shown in FIG. In the circuit 403, 411 and 413 are known clocked inverters, and 412 is a known inverter. In FIG. 3, since image data (digital data) is assumed to be 3 bits, there are three data signal lines. In addition, checkers 1315 to 1316 of 1312 and 1313 are omitted in the drawing. Image data (digital data) read in accordance with the timing signal from the digital data latch unit is transmitted to the DA switches 1321 to 1323 in synchronization with the latch signal.

  A dot portion 1324 corresponds to a current source (current output circuit), and a specific circuit configuration is shown in a dot portion 291 in FIG.

  Transistors 201 to 203 are drive transistors, and transistors 261 to 263 are DA switch transistors, which correspond to 1321 to 1323 in FIG.

In FIG. 2, drive transistors corresponding to the respective bits are provided independently. For example, the first bit (MSB) is 201, the second bit is 202, the third bit (LSB) is 203, and the L / W size of each transistor is preferably about 1: 2: 4. More generally speaking, the L / W size of each transistor is binary weighted such that approximately 2 ⁰ : 2 ¹ :...: 2 ^N-1 (N is an arbitrary integer greater than or equal to 2). Is desirable.

  Since the drive transistors 202 to 203 have the gate electrodes electrically connected, it is possible to set the reference current at the same time. In this respect, the circuit of FIG. 2 differs from the circuit of FIG. Since the circuit of FIG. 2 has fewer transistors and wirings than the circuit of FIG. 7, the area can be reduced.

  Further, the gate electrode of the driving transistor 201 is not electrically connected to the gate electrodes 202 to 203. In this respect, the circuit of FIG. 2 is different from the circuit of FIG. Since the circuit of FIG. 2 sets the reference current for the driving transistor 201 of the first bit (MSB) independently of the other bits, the accuracy of the current value of the MSB data can be expected.

  The operation when setting the reference current in the current source (current output circuit) of FIG. 2 will be described.

  When setting the reference current, first, a signal that turns off the transistors 261 to 263 is input from the digital signal input lines 251 to 253. When the transistors 261 to 263 are n-channel type, they are low (low voltage) signals. However, the transistors 261 to 263 do not need to be turned off when there is no fear of leakage of current from the output unit 282, such as when the tip of 282 is in an electrically open (high impedance) state.

  Next, a signal for turning on the transistors 222 to 223 and 240 is input from the current setting signal input line 210. When these transistors are n-channel type, they are high (high voltage) signals. Then, a reference current flows from the reference current source 270 to the constant voltage source 281. At this time, the gates and drains of the drive transistors 202 to 203 are short-circuited. Therefore, when a signal that turns off the transistors 222 to 223 and 240 is input from the current setting signal input line 210 after the current reaches a steady value, the second and third bits are used as the gate voltages of the driving transistors 202 to 203. The reference current is stored.

  At the same time or at another timing, a signal for turning on the transistors 221 and 241 is input from the current setting signal input line 211. When these transistors are n-channel type, they are high (high voltage) signals. Then, a reference current flows from the reference current source 271 to the constant voltage source 281. At this time, the gate and drain of the driving transistor 201 are short-circuited. Therefore, when a signal that turns off the transistors 221 and 241 is input from the current setting signal input line 211 after the current has reached a steady value, the reference current of the first bit (MSB) is used as the gate voltage of the driving transistor 201. Remembered.

  This completes the setting of the reference current. However, since the leakage current from the gate node of the drive transistors 201 to 203 is very small, the setting of the reference current needs to be repeated periodically (or irregularly).

  After setting the reference current, a digital voltage signal corresponding to the image signal is input from the digital signal input lines 251 to 253. Digital signal input lines 251 to 253 correspond to the data input section of current output DA converter circuit 192. Since the DA switch transistors 261 to 263 are installed in parallel, the total current of the current sources of all the bits in which the DA switch is on is output from the output unit 282 as a result. Thus, the digital voltage data is converted into an analog current.

  In the current output DA converter circuit 292 of FIG. 2, if there are variations in the electrical characteristics such as the threshold voltage values and field effect mobility of the drive transistors 202 to 203, the display of the intermediate gradation may be inaccurate. is there. However, the above-described reference current setting ensures accurate display at the maximum gradation and the intermediate gradation of the MSB.

  Further, in the current output DA converter circuit 292 of FIG. 2, since the reference current setting is simultaneously performed for the second bit and the third bit, the complexity is eliminated as compared with the case of FIG. The

  The example of FIG. 2 is a DA converter circuit that reads data in a 3-bit digital voltage value format and outputs data in an analog current value format. However, the digital voltage value in N bits (N is an arbitrary integer greater than or equal to 2). The same configuration can be used for reading format data.

  In the example of FIG. 2, the drive transistors 201 to 203 are n-channel type and 281 is a low voltage source, but the same configuration is possible even if the drive transistors 201 to 203 are p-channel type and 281 is a high voltage source. Can be used. Even in another configuration, it has a plurality of drive transistors, the plurality of drive transistors electrically connecting gate electrodes to each other, and a switch between the gate electrode and each drain of the plurality of drive transistors. As long as it includes a current output circuit including

  Further, the position of the transistor 240 and the connection node of the capacitor 230 are not limited to the example of FIG. For example, it can be the same as the example of FIG. It is only necessary to be able to store the source-gate voltages of the drive transistors 202 to 203 when the reference current is set.

  In addition, the example of FIG. 2 has the same configuration as the example of FIG. 1 for 2 bits, and a configuration in which a reference current is set independently for the other 1 bit, but the example of FIG. 1 for the p bits. For the q bits, the reference current may be set independently (p and q are arbitrary integers of 2 or more). Furthermore, the x bit may have the same configuration as the example of FIG. 1, and the y bit may have the same configuration as the example of FIG.

  Since it is most convenient to process image data outside the panel as digital voltage data, the current output DA converter circuit 292 (FIG. 2) or 1335 (FIG. 11) in the current data output circuit of FIG. 11 is important. .

  However, for example, when the analog current to be output is zero or very small, a long setting time is required, which is inconvenient only with the current output DA converter circuit of FIG.

  In such a case, the voltage output function of the present invention is useful. Hereinafter, an operation of outputting a voltage using the voltage source switch transistors 1331 to 1332 and 1350 will be described.

  In FIG. 11, 1334 is a constant voltage source (constant voltage line). Since the current output DA converter circuit of FIG. 1 is a low voltage current output circuit, the analog current to be output is zero when the voltage is high. Therefore, it is convenient to use 1334 as a high voltage constant voltage. In this case, the voltage source switch transistors 1331 to 1332 may be connected in series as a p-channel type so that the voltage is output only when the digital voltage data is a low signal with all bits.

  Further, in FIG. 11, a transistor 1350 that is turned on / off by a signal on the control line 1351 is provided in series with the transistors 1331 to 1332. In this respect, FIG. 3 and FIG. 11 are different. In FIG. 11, a short circuit between the constant voltage line 1334 and the output unit 1341 can be limited to a certain period by a signal of the control line 1351. By doing so, it is possible to maintain a configuration in which an analog current is finally output regardless of the value of the digital voltage data.

  That is, with the configuration of FIG. 3, when the digital voltage data is a predetermined value (low signal for all bits), the output is no longer current but only the voltage of the constant voltage source 1334. However, with the structure in FIG. 11, even if the transistor 1350 is initially turned on and the constant voltage line 1334 and the output portion 1341 are short-circuited, the transistor 1350 can be turned off thereafter. Then, the final output becomes an analog current value. The constant voltage source 1334 is only used for assisting the output.

  The advantage that the final output can be an analog current value instead of the voltage of the constant voltage source 1334 is remarkable when the analog current to be output is a non-zero minute value.

  If the current is a minute value, it takes time to reach a steady output state. If the analog current to be output is zero, it is possible to reduce the time by flowing a large current by replacing the voltage-designated output. However, if the current is not zero, it is desirable to avoid completely switching to the voltage output because it causes a large error in the output. However, on the other hand, in order to reduce the time required to reach a steady output state, it is still indispensable to flow a large current with voltage designation. Therefore, it is possible to send a large current with a specified voltage only for a short period of time, and ultimately to ensure the accuracy of the output by specifying the current. This is an advantage when the current is a non-zero value. Become.

  In FIG. 11, the voltage source switch transistors 1331 to 1332 are p-channel type and 1350 is n-channel type. However, the present invention is not limited to this. Other channel type combinations can be used.

  Further, the voltage source switch may adopt another configuration other than the transistors 1331 to 1332 and 1350.

  In the above, 1342 corresponding to the current data output circuit 512 has been described.

(Embodiment 4)
In Embodiment Mode 4, some display devices and electronic devices of the present invention are illustrated.

  The electronic device and display device of the present invention include a monitor, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, an audio playback device (audio component, car audio, etc.), a notebook type personal computer, and a game device. , A portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), an image playback device equipped with a recording medium (specifically, a recording medium such as a Digital Versatile Disc (DVD), etc.) And a display device mounted on them. Specific examples of these electronic devices are shown in FIGS.

  FIG. 6A shows a monitor. This example includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The display device of the present invention can be used for the display portion 2003. The monitor includes all information display devices such as a personal computer, a TV broadcast receiver, and an advertisement display.

  FIG. 6B shows a digital still camera. This example includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. The display device of the present invention can be used for the display portion 2102.

  FIG. 6C illustrates a laptop personal computer. This example includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The display device of the present invention can be used for the display portion 2203.

  FIG. 6D illustrates a mobile computer. This example includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The display device of the present invention can be used for the display portion 2302.

  FIG. 6E shows a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium. This example includes a main body 2401, a housing 2402, a display portion A 2403, a display portion B 2404, a recording medium (DVD or the like) reading portion 2405, operation keys 2406, a speaker portion 2407, and the like. The display device of the present invention can be used for the display portion A 2403 and the display portion B 2404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

  FIG. 6F shows a goggle type display (head mounted display). This example includes a main body 2501, a display portion 2502, an arm portion 2503, and the like. The display device of the present invention can be used for the display portion 2502.

  FIG. 6G illustrates a video camera. This example includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, a voice input portion 2608, operation keys 2609, an eyepiece portion 2610, and the like. The display device of the present invention can be used for the display portion 2602.

  FIG. 6H illustrates a mobile phone. This example includes a main body 2701, a housing 2702, a display unit 2703, an audio input unit 2704, an audio output unit 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The display device of the present invention can be used for the display portion 2703. Note that the display portion 2703 can suppress power consumption of the mobile phone by displaying white characters on a black background.

  As described above, the application range of the present invention is extremely wide and can be used for electronic devices and the like in various fields.

The figure which shows the example of a current output circuit and a DA converter circuit. The figure which shows the example of a current output circuit and a DA converter circuit. The figure which shows the structural example of the data driver using the DA converter circuit of this invention. FIG. 9 illustrates a configuration example of a latch circuit. FIG. 6 is a diagram showing a panel configuration example of a display device. FIG. 6 illustrates examples of display devices and electronic devices. The figure which shows a current output circuit and a DA converter circuit. The figure which shows the structural example of the data driver using the conventional DA converter circuit. FIG. 6 is a diagram showing a panel configuration example of a display device. The figure which shows the example of a selector circuit. The figure which shows the structural example of the data driver using the DA converter circuit of this invention.

Claims (6)

A circuit including at least a current output DA converter circuit,
First to third drive transistors, first to eleventh transistors, first and second current sources, and first and second constant voltage sources;
In the first driving transistor, the gate is one of the source or the drain of the first transistor, the one of the source or the drain is the source or the drain of each of the second and third transistors, The other of the drains is electrically connected to the first constant voltage source;
In the second driving transistor, the gate is one of the source and the drain of the fourth transistor, the one of the source and the drain is the source or the drain of each of the fifth and sixth transistors, The other of the drains is electrically connected to the first constant voltage source;
In the third driving transistor, the gate is one of the source or the drain of the fourth transistor, the one of the source or the drain is the source or the drain of each of the seventh and the eighth transistors, The other of the drains is electrically connected to the first constant voltage source;
The gates of the first and second transistors are electrically connected to a first current setting signal input line,
The gates of the fourth, fifth, and seventh transistors are electrically connected to a second current setting signal input line,
The other of the source or drain of each of the first and second transistors is electrically connected to the first current source;
The other of the source or drain of each of the fourth, fifth, and seventh transistors is electrically connected to the second current source,
A gate of each of the third and ninth transistors is electrically connected to a first digital signal input line;
A gate of each of the sixth and tenth transistors is electrically connected to a second digital signal input line;
A gate of each of the eighth and eleventh transistors is electrically connected to a third digital signal input line;
The other of the source or drain of each of the third, sixth, and eighth transistors is electrically connected to the output unit,
One of the source and the drain of the ninth transistor is electrically connected to the output unit,
The other of the source and the drain of the ninth transistor is electrically connected to one of the source and the drain of the tenth transistor;
The other of the source and the drain of the tenth transistor is electrically connected to one of the source and the drain of the eleventh transistor;
The other of the source and the drain of the eleventh transistor is electrically connected to the second constant voltage source,
The digital signal input to the gates of the third and ninth transistors through the first digital signal input line is a most significant bit signal,
When the digital signal input through the first to third digital signal input lines has a predetermined value, the voltage value supplied from the second constant voltage source is output from the output unit, and When the digital signal is other than a predetermined value, an analog current converted corresponding to the digital signal is output from the output unit.
A circuit characterized by that. In claim 1,
A circuit in which all of the ninth to eleventh transistors are turned on when the digital signal input through the first to third digital signal input lines has a predetermined value. . In claim 1 or 2,
The first to third driving transistors are n-channel transistors,
The voltage value of the first constant voltage source is lower than the voltage value of the second constant voltage source. In any one of Claims 1 thru | or 3,
The ninth to eleventh transistors are p-channel transistors,
The voltage value of the second constant voltage source is higher than the voltage value of the first constant voltage source. A display device comprising the circuit according to claim 1. An electronic apparatus comprising the circuit according to claim 1.

Images