JP2011112721A - Timing controller and display device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timing controller for driving panels of various resolutions in a simple system. <P>SOLUTION: The timing controller 100 generates a plurality of driver control signals to be supplied to a source driver 4 and a gate driver 6. A resolution determination part 18 determines the resolution of the display panel 2 based on the data from an image source 8. A parameter operation part 20 calculates at least one parameter PRM necessary for generating each of the plurality of driver control signals using an operational expression predefined for every parameter based on the determined resolution RES. A timing signal generator 22 generates the corresponding driver control signal based on the parameter PRM. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display panel driving technique, and more particularly to a timing controller (LCD controller) for supplying signals to a scan driver (gate driver) and a data driver (source driver).

  FIG. 1 is a block diagram showing a configuration of a general liquid crystal display (LCD) 300. The LCD 300 includes an LCD panel 302, a source driver 304, a gate driver 306, and a timing controller 200. The LCD panel 302 includes a plurality of data lines DL, a plurality of scanning lines SL arranged so as to be orthogonal to the data lines DL, and a plurality of TFTs arranged in a matrix at intersections of the data lines DL and the scanning lines SL ( Thin Film Transistor). The source driver 304 applies a voltage corresponding to the luminance to each data line DL. The gate driver 306 selects a plurality of scanning lines SL in order.

  The timing controller 200 receives image data to be displayed on the LCD panel 302 from the image source 308. Then, a driver control signal (timing pulse) corresponding to the panel resolution is generated and supplied to the source driver 304 and the gate driver 306 together with the image data. The timing controller 200 includes an input interface unit 202, a logic unit 204, a timing signal generator 206, and output interface units 208 and 210.

  The input interface unit 202 is connected to an image source 308 such as a graphics processor via a serial bus BUS1. The input interface unit 202 receives a signal from the image source 308, receives differential RGB data RGBP / N of each pixel, differential format pixel clock CLKP / N, data enable signal DE, vertical synchronization signal Vsync, horizontal The synchronization signal Hsync is acquired and output to the logic unit 204. The logic unit 204 performs necessary signal processing on the image data RGBP / N and outputs the processed signal to the output interface unit 208. The output interface unit 208 is connected to the source driver 304 via an RSDS standard (Reduced Swing Differential Signaling) or LVDS standard (Low Voltage Differential Signaling) bus, and outputs image data.

The timing signal generator 206 receives the reference signal REF generated by the logic unit 204. The timing signal generator 206 generates, for example, the following driver control signal based on the reference signal REF.
・ Start pulse (STH)
・ Latch pulse (LOAD)
・ AC signal (POL)
・ Vertical shift direction input / output signal (STV)
・ Vertical transfer clock (CPV)
・ Output enable (OE)

  These driver control signals are supplied to the source driver 304 and the gate driver 306 via the output interface unit 210.

JP 2007-206231 A JP 2000-314868 A

  The pulse widths and generation timings of various driver control signals generated by the timing signal generator 206 are determined to specific values according to the panel resolution (SVGA, XGA, etc.). A conventional timing controller holds a table that defines the relationship between the resolution of each panel, the pulse width of each driver control signal, and the edge timing in an internal or external ROM (Read Only Memory) 212. The timing signal generator 206 receives a signal (resolution setting signal) RES indicating the resolution of the LCD panel 302, reads out data indicating the pulse width and edge timing by referring to the ROM 212, and generates each driver control signal. Was.

  However, in this configuration, since the resolution setting signal RES needs to be supplied from the outside, the number of terminals increases, and the resolution setting signal RES needs to be generated by a processor (microcomputer) external to the timing controller 200. There is a problem that the system becomes complicated. Such a problem may occur in all display devices having the same configuration as the LCD.

  The present invention has been made in view of such a situation, and one of exemplary purposes of an aspect thereof is to provide a timing controller capable of driving panels having various resolutions with a simple system.

  An aspect of the present invention relates to a timing controller that receives data from an image source and generates a plurality of driver control signals to be supplied to a data driver and a scan driver that drive a display panel. The timing controller includes a resolution determining unit that determines the resolution of the display panel based on data from the image source, and at least one parameter necessary for generating each of the plurality of driver control signals based on the determined resolution. And a timing signal generator for generating a corresponding driver control signal based on at least one parameter.

“At least one parameter necessary for generating the driver control signal” includes a pulse width of the driver control signal, a positive edge timing, a negative edge timing, a positive edge inclination, a negative edge inclination, and the like.
According to this aspect, the resolution is determined based on the data from the image source, and the driver control signal is generated by arithmetic processing using the resolution. Therefore, it is necessary when generating the driver control signal to the timing controller. Since it is not necessary to provide resolution information separately, the system can be simplified.

The resolution determination unit may determine the resolution of the display panel based on a period in which the data enable signal is active with reference to the data enable signal from the image source.
The data enable signal indicates active (assertion) during a period in which valid data excluding the blank period exists among image data for one row (one scanning line). Accordingly, the horizontal resolution of the display panel can be obtained by counting the period during which the data enable signal is asserted with reference to a certain clock signal.

The resolution determination unit may determine the resolution of the display panel by referring to the vertical synchronization signal from the image source and counting the number of vertical synchronization signals per frame.
By counting the number of vertical synchronization signals, the vertical resolution of the display panel can be obtained.

  Another aspect of the present invention is also a timing controller. This timing controller reads EDID (Extended Display Information Data) from a ROM (Read Only Memory) connected to the timing controller, refers to data indicating the resolution included in the EDID, and determines the resolution of the display panel. A resolution determination unit, a calculation unit that calculates at least one parameter necessary for generating each of the plurality of driver control signals based on a predetermined calculation formula for each parameter, based on the determined resolution; and at least one A timing signal generator for generating a corresponding driver control signal based on the parameter.

  The display device has a built-in ROM for storing EDID defined in the Video Electronics Standards Association (VESA) standard. When the display device is connected to an image source, the EDID stored in the ROM is used as a timing. In some cases, a mechanism for transferring to an image source via a controller is implemented. In this case, by referring to the EDID, the timing controller can omit the terminals conventionally provided for providing resolution information to the timing controller, thereby simplifying the system.

  Yet another embodiment of the present invention is a display device. The display device receives a data from a display panel, a data driver and a scan driver for driving the display panel, and an image source, generates a plurality of driver control signals, and supplies them to the data driver and the scan driver together with the image data. And a timing controller according to any one of the aspects.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the timing controller of an aspect of the present invention, panels with various resolutions can be driven with a simple system.

It is a block diagram which shows the structure of a general liquid crystal display. It is a block diagram which shows the structure of the display apparatus provided with the timing controller which concerns on 1st Embodiment. FIGS. 3A and 3B are tables showing driver control signal time charts and parameters defining their characteristics. It is a block diagram which shows the structure of the display apparatus provided with the timing controller which concerns on 2nd Embodiment.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are in an electrically connected state. Including the case of being indirectly connected through other members that do not affect the above. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 2 is a block diagram illustrating a configuration of the display device 1 including the timing controller 100 according to the first embodiment. The display device 1 includes an LCD panel 2, a source driver 4, a gate driver 6, and a timing controller 100.

  The LCD panel 2 includes a plurality of data lines DL, a plurality of scanning lines SL arranged so as to be orthogonal to the data lines DL, and a plurality of TFTs arranged in a matrix at intersections of the data lines DL and the scanning lines SL ( Thin Film Transistor). The source driver 4 applies a voltage corresponding to the luminance to each data line. The gate driver 6 selects a plurality of scanning lines in order.

  The display device 1 is connected to a graphics processor of a personal computer and an image source 8 including a tuner unit of a television receiver via a digital interface such as HDMI standard, DVI standard, DisplayPort standard. Then, image data to be displayed on the LCD panel 2 is transmitted from the image source 8 to the display device 1 by two-line serial transmission via the clock line and the data line.

  The timing controller 100 of the display device 1 receives image data to be displayed on the LCD panel 302 from the image source 8. The timing controller 100 generates a driver control signal (timing pulse) corresponding to the resolution of the LCD panel 2 and supplies it to the gate driver 6 and the source driver 4 together with the image data.

  The timing controller 100 includes an input interface unit 12, a logic unit 14, an image output interface unit 16, a resolution determination unit 18, a parameter calculation unit 20, a timing signal generator 22, and an output interface unit 24 for timing signals.

  The input interface unit 12 receives image data from the image source 8 and acquires RGB image data RGBP / N, a pixel clock CLKP / N, a data enable signal DE, a vertical synchronization signal Vsync, and a horizontal synchronization signal Hsync, They are output to the logic unit 14. The logic unit 14 performs necessary signal processing on the image data RGBP / N and outputs the processed signal to the output interface unit 16.

  The image output interface unit 16 is connected to the source driver 4 via an RSDS standard (Reduced Swing Differential Signaling) or LVDS standard (Low Voltage Differential Signaling) bus, and receives image data (RGB data) for each pixel. Output sequentially.

  The logic unit 14 generates a reference signal REF that is asserted at a predetermined timing of each frame based on the input signal, and outputs the reference signal REF to the timing signal generator 22.

  The timing signal generator 22 generates the following driver control signals. Those skilled in the art understand that the names and symbols of each driver control signal may vary from manufacturer to manufacturer.

1. Driver control signal for source driver 1.1 Start pulse (STH)
A plurality of source drivers 4 and gate drivers 6 are cascade-connected in accordance with the panel size (resolution) of the LCD panel 2. The image data and the driver control signal output from the timing controller 100 sequentially pass through the plurality of source drivers 4. The plurality of source drivers 4 sequentially advance the start pulse STH like a shift register. The source driver 4 to which the start pulse STH is input takes in the image data.

1.2 Latch pulse (LOAD)
The latch pulse LOAD is asserted for each scanning line. When the latch pulse LOAD is asserted, the source driver 4 captures image data for one scanning line.

1.3 AC signal (POL)
The source driver 4 drives the LCD panel 2 while inverting the polarity alternately. The polarity of the source driver 4 is determined by the AC signal POL.

2. Driver control signal for gate driver 2.1 Vertical shift direction input / output signal (STV)
It is supplied to a plurality of gate drivers 6 connected in cascade. The vertical shift direction input / output signal STV is sequentially shifted by the plurality of gate drivers 6.

2.2 Vertical transfer clock (CPV)
Each gate driver 6 takes in the inputted vertical shift direction input / output signal STV at the timing of the positive edge of the vertical transfer clock CPV.

2.3 Output enable (OE)
Data for controlling the state of the output terminal of the gate driver 6. When the output enable OE is asserted, a driving voltage is applied to the scanning line SL, and when negated, the potential of the scanning line SL is fixed.

  The pulse width and generation timing of the driver control signal are set to specific values according to the resolution of the panel. The driver control signal is supplied to the source driver 4 and the gate driver 6 via the output interface unit 24.

  The resolution determination unit 18 determines the resolution of the display panel 2 using at least one of the signals (CLKP / N, RGBP / N, DE, Hsync, Vsync) received from the image source 8 by the input interface unit 12. The resolution determination process by the resolution determination unit 18 may be executed at least once immediately after the display device 1 is turned on. Alternatively, the resolution determination unit 18 may determine the resolution every time a predetermined time elapses.

  For example, the resolution determination unit 18 may determine the resolution of the LCD panel 2 on the basis of a period in which the data enable signal DE is active with reference to the data enable signal DE. The data enable signal DE indicates active (assertion) during a period in which valid data other than the blank period exists among image data for one row (one scanning line). Therefore, the horizontal resolution of the image source 8 can be acquired by counting the period during which the data enable signal DE is asserted using the clock signal supplied to the timing controller 100.

  As a modification, the resolution determination unit 18 may determine the resolution of the LCD panel 2 by referring to the vertical synchronization signal VSYNC and counting the number of vertical synchronization signals VSYNC per frame. Alternatively, the resolution of the LCD panel 2 may be determined by using the monitoring of the data enable signal DE and the vertical synchronization signal VSYNC together.

  The resolution determination unit 18 outputs resolution information RES indicating the determined resolution to the parameter calculation unit 20. The parameter calculation unit 20 calculates at least one parameter PRM necessary for generating each of the plurality of driver control signals based on a calculation formula predetermined for each parameter PRM based on the resolution indicated by the resolution information RES.

  FIGS. 3A and 3B are tables showing driver control signal time charts and parameters defining their characteristics. Each parameter is defined in units of a cycle of the clock signal CLKP / N or one scanning time (Line). Time t0 indicates the timing at which the reference signal REF is asserted. The values in the table of FIG. 3B are examples, and the values are determined according to the characteristics of the LCD panel 2, the source driver 4, and the gate driver 6.

As an example, the resolution information RES is 2 bits, RES [1: 0] = [00] indicates SVGA, [01] indicates XGA, [10] indicates WSVGA1, and [11] indicates WSVGA2. In this case, for example, as an arithmetic expression for calculating the time t3 from the positive edge of the STH signal to the LOAD signal,
t3 = 807 + RES [1] · RES [0] · 224 (1)
Can be defined. Here, “·” is an operator indicating a logical product operation or multiplication.

Similarly, the interval t5 from the positive edge of the STH signal to the POL signal (1 line) can be defined as follows.
t5 = 300 + RES [1] · RES [0] · 90 (2)

  The parameter calculation unit 20 defines a calculation formula for each parameter. The parameter calculation unit 20 calculates each parameter PRM based on the resolution information RES [1: 0] and outputs it to the subsequent timing signal generator 22.

  The timing signal generator 22 generates a driver control signal using the parameter PRM from the parameter calculation unit 20. The timing signal generator 22 includes a counter (timer) that counts the clock signal CLKP / N.

  The output interface unit 24 outputs the driver control signal generated by the timing signal generator 22 to the source driver 4 and the gate driver 6.

  The above is the configuration of the timing controller 100. Next, the operation will be described. When the display device 1 and the image source 8 are powered on and the link between the display device 1 and the image source 8 is established, the timing controller 100 receives image data from the image source 8. The resolution determination unit 18 determines the resolution based on the signal received from the image source 8, and the parameter calculation unit 20 calculates the parameter PRM through calculation processing. Since the resolution of the LCD panel 2 is fixed in each display, the parameter calculation unit 20 calculates the parameter PRM only once, and then stores it in the memory for repeated use. That is, since the resolution determination unit 18 and the parameter calculation unit 20 need only be operated once at the time of activation, an increase in power consumption can be ignored.

  The timing signal generator 22 receives the calculated parameter PRM and repeatedly generates a driver control signal for each frame or line. Thus, the LCD panel 2 can be appropriately driven according to the resolution.

  Next, advantages of the timing controller 100 will be described. This advantage is further clarified by comparison with the timing controller of FIG.

  The timing controller 200 of FIG. 1 is provided with a terminal P1 for inputting data RES indicating resolution. Since the circuit area occupied by the terminal (pad) P1 is not small, the terminal P1 has been a restriction for downsizing the timing controller. Further, since it is necessary to give resolution information RES to the terminal P1 from a microcomputer or the like, the system is complicated. For example, there is a problem that it is necessary to determine a protocol for transmitting and receiving resolution information RES between the microcomputer and the timing controller, which reduces the general versatility of the system.

  On the other hand, in the timing controller 100 of FIG. 2, since the terminal P1 is not required, the circuit can be reduced in size. Since the added ALU (arithmetic logic unit) and counter (timer) constituting the resolution determination unit 18 and parameter calculation unit 20 can use the existing ALU and counter, the circuit area is not increased so much. . Further, since there is no need to determine a protocol with the microcomputer, the versatility of the system can be improved.

  Further, in the timing controller 200 of FIG. 1, the ROM 212 has a table showing the relationship between the resolution (Display Mode) and each parameter as shown in FIG. On the other hand, in the timing controller 100 of FIG. 2, since each parameter PRM is calculated by calculation, it is only necessary to store an arithmetic expression in the ROM, so that the size of the ROM can be reduced. This effect becomes more prominent as the number of resolution candidates increases.

  Further, the timing controller 200 of FIG. 1 can generate an appropriate driver control signal only for the resolution stored in the ROM, and cannot generate a driver control signal for other resolutions. There is. On the other hand, in the timing controller 100 of FIG. 1, by defining the arithmetic expression so as to correspond to all resolutions, it is freed from this restriction, and the versatility of the timing controller 100 can be enhanced.

  From another point of view, in the timing controller of FIG. 1, the capacity of the ROM 212 increases as the resolution that can be handled increases. On the other hand, the timing controller 100 of FIG. 2 has an advantage that the capacity of the ROM holding the arithmetic expression does not increase so much even if the resolution that can be handled is increased.

  FIG. 4 is a block diagram showing a configuration of the display device 1a including the timing controller 100a according to the second embodiment.

  The display device 1a is implemented with technologies called EDID and DDC (Display Data Channel) in order to realize a plug-and-play function with the image source 8. In order to realize plug and play, the image source 8 needs to know the resolution of the LCD panel 2. Therefore, in addition to the resolution, the display device 1a is provided with a ROM 3 for storing EDID describing characteristics unique to the display device 1a such as a manufacturer name (Vendor Id) and a model (Product ID).

  The image source 8 reads the EDID from the display device 1a using the SDA (Serial Data) and SCL (Serial Clock) in the serial bus BUS1 from the EDID stored in the ROM 3 when the system is started or the display is connected. That is, the resolution information included in EDID always passes through the timing controller 100a.

  Therefore, the timing controller 100a in FIG. 4 is configured to be able to acquire resolution information that passes through the timing controller 100a when the image source 8 accesses the EDID. For example, when the EDID passes through the logic unit 14a, a resolution determination unit 18a is provided inside the logic unit 14a. The resolution determination unit 18 a acquires resolution information when the logic unit 14 and the input interface unit 12 transfer EDID from the ROM 3 to the image source 8.

  The acquired resolution information is supplied to the parameter calculation unit 20. Others are the same as the timing controller 100 of FIG.

  The timing controller 100a of FIG. 4 can acquire the resolution without receiving resolution information from the microcomputer in a display device that supports EDID and DDC in order to support plug and play.

  Although the liquid crystal display has been described in the embodiment, the present invention can be widely applied to similar matrix type displays. The types of driver control signals are not limited to those described above. The type of driver control signal to be supplied differs depending on the type of data driver and scan driver, but these are naturally included in the scope of the present invention.

  Although the present invention has been described above based on the embodiments, it should be understood that the embodiments merely illustrate the principles and applications of the present invention, and the embodiments are within the scope of the claims. It goes without saying that many variations and changes in arrangement are possible without departing from the spirit of the present invention as defined.

DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 2 ... LCD panel, 3 ... ROM, 4 ... Source driver, 6 ... Gate driver, 8 ... Image source, 100 ... Timing controller, 12 ... Input interface part, 14 ... Logic part, 16 ... Output interface part , 18 ... resolution determination unit, 20 ... parameter calculation unit, 22 ... timing signal generator, 24 ... output interface unit.

Claims (5)

A timing controller for receiving data from an image source and generating a plurality of driver control signals to be supplied to a data driver and a scan driver for driving a display panel;
A resolution determination unit that determines the resolution of the display panel based on the data from the image source;
Based on the determined resolution, a calculation unit that calculates at least one parameter necessary for generating each of the plurality of driver control signals based on a predetermined calculation formula for each parameter;
A timing signal generator for generating a corresponding driver control signal based on the at least one parameter;
A timing controller comprising:   The timing according to claim 1, wherein the resolution determination unit refers to a data enable signal from the image source and determines the resolution of the display panel based on a period in which the data enable signal indicates active. controller.   2. The resolution determination unit according to claim 1, wherein the resolution determination unit determines the resolution of the display panel by referring to a vertical synchronization signal from the image source and counting the number of vertical synchronization signals per frame. The described timing controller. A timing controller for receiving data from an image source and generating a plurality of driver control signals to be supplied to a data driver and a scan driver for driving a display panel;
A resolution determination unit that reads out EDID (Extended Display Information Data) from a ROM (Read Only Memory) connected to the timing controller, refers to data indicating the resolution included in the EDID, and determines the resolution of the display panel; ,
Based on the determined resolution, a calculation unit that calculates at least one parameter necessary for generating each of the plurality of driver control signals based on a predetermined calculation formula for each parameter;
A timing signal generator for generating a corresponding driver control signal based on the at least one parameter;
A timing controller comprising: A display panel;
A data driver and a scan driver for driving the display panel;
5. The timing controller according to claim 1, which receives data from an image source, generates a plurality of driver control signals, and supplies the driver and the scan driver together with image data;
A display device comprising:

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