WO2010010898A1 - Display controller, display device, and portable electronic device - Google Patents

Abstract

A liquid crystal controller (15) controls a liquid crystal module (14).  The liquid crystal module (14) comprises a matrix LCD element in which display pixels are arranged in matrix and a drive circuit for driving the LCD element, and is provided with an operation mode for performing a new display operation and a suspend mode for suspending the display operation.  When receiving a suspend/operation signal indicating that either of the operation mode or the suspend mode is given from the liquid crystal module (14), the liquid crystal controller (15) controls to transmit display data and a plurality of control signals required to control the liquid crystal module (14) to the liquid crystal module (14) according to the received suspend/operation signal.

Description

Display controller, display device, and portable electronic device

The present invention includes a matrix-type display element in which display pixels are arranged in a matrix, and a drive circuit that drives the display element, and an operation mode in which a new display operation is performed, and the display operation is suspended. The present invention relates to a display controller that controls a display module having a sleep mode, a display device including the display module and the display controller, and a portable electronic device.

There are display devices that display a character, a symbol, a graphic, or the like on the display element by arranging a large number of signal lines in the row direction and the column direction with respect to the matrix display element and driving the signal lines. . As the matrix type display element, FPD (Flat Panel Display) such as LCD (Liquid Crystal Display), PDP (Plasma Display Panel), EL (Electroluminescence) display, FED (Field Emission Display) and the like are used. Since FPD can be made thinner and lighter than conventional CRT (Cathode Ray Ray Tube), it has recently been used in various display devices.

Generally, a display device includes a display module and a display controller. The display module includes the matrix display element and a drive circuit that drives the display element. On the other hand, the display controller transmits display data and various control signals for driving the display element to the display module.

The conventional display device is a continuous drive system that performs a display operation for each frame. For this reason, it is necessary for the display controller to read display data from the memory and transfer it to the display module for each frame, and to transmit various control signals to the display module, which is a cause of high power consumption of the display device. It was.

Therefore, so-called intermittent drive type display devices capable of pausing the display operation have been developed, and are described in Patent Documents 1 to 4, for example.

Japanese Patent Publication “Japanese Patent Laid-Open No. 2001-060079 (Publication Date: March 6, 2001)” Japanese Patent Publication “Japanese Patent Laid-Open No. 11-338425 (Publication Date: Dec. 10, 1999)” Japanese Patent Publication “Japanese Patent Laid-Open No. 2001-31253 (Publication Date: November 9, 2001)” Japanese Patent Publication “Japanese Patent Laid-Open No. 2002-123234 (Publication Date: April 26, 2002)”

In the matrix type display device described in Patent Document 1, a frame buffer is built in the signal electrode drive circuit of the LCD module. If the display data is not changed, the display data is not transferred from the module controller to the LCD module. Thereby, power consumption can be reduced. When the display data is changed, the display data is transferred with a low-frequency clock regardless of the liquid crystal display timing. As a result, the operation with the high-frequency clock becomes unnecessary, and the power consumption can be further reduced.

In the liquid crystal display device described in Patent Document 2, the liquid crystal driving circuit stops outputting pulses necessary for liquid crystal display when no video signal is input, and holds the current image displayed on the LCD panel. . By stopping the output of the pulse, power consumption can be reduced.

In the display device described in Patent Document 3, a scanning period and a non-scanning period are set. In the non-scanning period, the control IC does not input a signal other than the gate start pulse signal to the gate driver and the source driver. I am doing so. Accordingly, it is not necessary to operate the gate driver and the logic circuit inside the source driver in the non-scanning period, so that power consumption can be reduced.

Further, the image display device described in Patent Document 4 has a scanning mode in which a video signal is written in any of the display cells, and a holding mode in which no video signal is written in any of the display cells. In the holding mode, the data signal line driving circuit is configured not to output a signal to each data signal line. Thereby, the power consumption of the data signal line driving circuit can be reduced. On the other hand, the scanning signal line driving circuit outputs a non-scanning voltage (TFT off voltage) to all the scanning signal lines. As a result, the display is held by the charges accumulated in the pixel electrodes and the auxiliary capacitors in each display cell.

However, in Patent Documents 1 to 4, the display module does not know when the input of various signals is stopped. Therefore, when the input of various signals is resumed while the input of various signals is stopped. It is necessary to prepare for. As a result, the analog power supply in the display module cannot be stopped, and reduction of power consumption is suppressed.

The present invention has been made in view of the above problems, and an object thereof is to provide a display controller or the like that can further reduce power consumption.

A display controller according to the present invention includes a matrix display element in which display pixels are arranged in a matrix, and a drive circuit that drives the display element, and an operation mode for performing a new display operation, and the display A display controller for controlling a display module having a pause mode for pausing the operation, and in order to solve the above problem, a pause / operation signal indicating which of the operation mode and the sleep mode is set; Transmission of display data and a plurality of control signals necessary for controlling the display module to the display module based on a pause / operation signal received from the display module or transmitted to the display module. It is characterized by control.

According to the above configuration, in the sleep mode, the display controller can stop sending part or all of the display data and the plurality of control signals to the display module. At this time, the display controller can stop the circuit unit related to the signal whose transmission is stopped, while the display module does not need to operate the circuit unit related to the signal which has not been received. Therefore, power consumption in the display controller and the display module can be reduced.

The display controller controls transmission of the display data and control signal to the display module based on the pause / operation signal transmitted or received. Accordingly, the display module can prepare for display operation or pause from reception or transmission of the pause / operation signal to control of the transmission from the display controller. Accordingly, in the sleep mode, the display module does not need to wait for the display operation until the pause / operation signal is received or transmitted. Therefore, the analog power supply in the display module may be stopped. And power consumption can be further reduced.

Note that examples of the control signal include a transfer clock signal described later, a synchronization signal for vertical scanning and horizontal scanning, and the like. As will be described later, in the sleep mode, the display controller stops transmitting at least the display data and the transfer clock signal to the display module, while at least synchronizing signals for vertical scanning and horizontal scanning. It is preferable to transmit to the display module.

A display controller according to the present invention includes a matrix display element in which display pixels are arranged in a matrix, and a drive circuit that drives the display element, and an operation mode for performing a new display operation, and the display A display controller that controls a display module having a pause mode that pauses operation, and in order to solve the above-described problem, in the pause mode, at least display data and the display data are assigned to each display pixel. The transmission clock signal for transfer is stopped from being transmitted to the display module, while at least a synchronizing signal for vertical scanning and horizontal scanning is transmitted to the display module.

Here, examples of the synchronization signal for vertical scanning include a vertical synchronization signal and a gate start pulse signal. Examples of the synchronization signal for horizontal scanning include a horizontal synchronization signal and a gate clock signal.

According to the above configuration, in the sleep mode, the display module does not receive the display data and the transfer clock signal, so that the logic circuit related to the display data and the transfer clock signal does not need to operate. In the sleep mode, the display controller does not need to transmit the display data and the transfer clock signal to the display module, so that the logic circuit related to the display data and the transfer clock signal can be stopped.

Generally, the display data and the transfer clock signal have the highest frequency among signals transmitted from the display controller to the display module. The power consumption of the logic circuit is proportional to the frequency. Therefore, the display controller of the present invention can significantly reduce power consumption.

In addition, even in the sleep mode, a synchronization signal for vertical scanning and horizontal scanning is transmitted from the display controller to the display module. Thus, the transition from the pause mode to the operation mode can be performed based on the synchronization signals for the vertical scanning and horizontal scanning. Further, since the synchronization signal for horizontal scanning is generally higher in frequency than the synchronization signal for vertical scanning, the preparation for the transition is performed based on the synchronization signal for horizontal scanning, so that The transition can be reliably performed in synchronization with the synchronization signal for the vertical scanning.

In order for the display controller to determine whether the display module is in the operation mode or the sleep mode, the display module may notify the display controller of the state, or the display controller may indicate the state to the display module. You just have to point. Alternatively, the above pause / operation signal may be transmitted and received between the display controller and the display module.

In the display controller according to the present invention, in the pause mode, it is preferable to stop reading the display data from the storage means for storing the display data. In this case, since the frequency of access from the display controller to the storage means can be reduced, the access efficiency to the storage means from other devices, particularly a CPU (Central Processing Unit) is improved. Further, when the display controller and the storage means are electrically connected via a bus, the bus occupancy can be reduced, so that the frequency of use of the bus by other devices, particularly the CPU, is improved. Performance will be improved.

In addition, if it is a display apparatus provided with the display module of the said structure, the display controller of the said structure which controls this display module, and the clock apparatus which supplies a clock signal to this display controller, there exists an effect similar to the above-mentioned.

By the way, as described above, the signals having the highest frequency among the signals transmitted from the display controller to the display module are the display data and the transfer clock signal. Therefore, when the display controller stops transmitting at least the display data and the transfer clock signal to the display module in the sleep mode, the operating frequency of the display controller can be lowered.

Therefore, in the display device according to the present invention, the display controller transmits at least display data and a transfer clock signal for transferring the display data to each display pixel to the display module in the sleep mode. It is preferable that the frequency of the clock signal supplied to the display controller in the sleep mode is lower than that in the operation mode.

In this case, the operating frequency of the display controller is lowered, and the power consumption of the logic circuit is proportional to the frequency as described above. Therefore, the power consumption of the display controller can be further reduced.

The display element is preferably a liquid crystal display element, but may be another FPD such as a PDP, EL display, or FED.

In addition, if the portable electronic device includes the display device having the above-described configuration, the same effects as described above can be obtained.

As described above, the display controller according to the present invention can stop the circuit unit related to the signal for stopping transmission to the display module, while the display module does not need to operate the circuit unit related to the signal not received. The power consumption in the display controller and the display module can be reduced. Further, since the display module in the sleep mode may be prepared for display operation after receiving or transmitting the pause / operation signal, the display module until the display / operation signal is received or transmitted. The analog power supply can be stopped, and the power consumption can be further reduced.

In addition, as described above, the display controller according to the present invention does not need to operate the logic circuit related to the display data and the transfer clock signal in the sleep mode, so that the power consumption can be reduced. Furthermore, by sending a synchronization signal for vertical scanning and horizontal scanning to the display module, preparation for transition from the pause mode to the operation mode can be made based on the synchronization signal for horizontal scanning, There is an effect that the transition can be surely performed in synchronization with the synchronization signal for the vertical scanning.

It is a block diagram which shows schematic structure of the liquid crystal display device which is one Embodiment of this invention. FIG. 6 is a diagram showing a correspondence relationship between an operation mode and a pause mode of a liquid crystal module and an operation of a liquid crystal controller in the liquid crystal display device in a table format. It is a block diagram which shows schematic structure of the said liquid crystal module. It is a figure which shows the correspondence of the content of the mode instruction | indication signal which the said liquid crystal module receives, and the drive method of the said liquid crystal module in a table format. It is a timing chart which shows operation | movement of the said liquid crystal module, and operation | movement of various signals. It is a block diagram which shows schematic structure of the said liquid crystal controller. 6 is a timing chart showing the operation of various signals when the liquid crystal module operates in an intermittent drive system in the liquid crystal controller. It is a block diagram which shows schematic structure of the clock apparatus in the said liquid crystal display device.

An embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a schematic configuration of the liquid crystal display device of the present embodiment. The liquid crystal display device (display device) 10 is mounted as an image display device in a portable electronic device such as a mobile phone or an electronic dictionary. Portable electronic devices are required to reduce the power consumption of various configurations in order to extend the life of the battery on which they are mounted.

As shown in FIG. 1, the liquid crystal display device 10 includes a CPU 11, a bus 12, a memory (storage means) 13, a liquid crystal module (display module) 14, a liquid crystal controller (display controller) 15, and a clock device 16. .

The CPU 11 performs overall control of various components in the liquid crystal display device 10 via the bus 12 by executing a program stored in a storage element such as a RAM (Random Access Memory) or a flash memory. It is. Specifically, the CPU 11 performs operation setting of the liquid crystal controller 15 and writing of display data to the memory 13 via the bus 12.

The bus 12 is a common signal line for transmitting and receiving data between various components in the liquid crystal display device 10. The memory 13 is a VRAM (Video RAM) that functions as a buffer between the CPU 11 and the liquid crystal module 14 and stores display data DAT. The memory 13 temporarily stores data used for arithmetic processing of the CPU 11 and arithmetic results. It also functions as a so-called working memory.

The liquid crystal module 14 is a functional unit that displays images such as characters, symbols, and figures on a display element. The liquid crystal module 14 drives a matrix type LCD element (liquid crystal display element) in which display pixels are arranged in a matrix and the LCD element. Drive circuit.

The liquid crystal controller 15 controls the liquid crystal module 14. Specifically, the liquid crystal controller 15 transfers the display data DAT read from the memory 13 to the liquid crystal module 14 and transmits a plurality of control signals CNT necessary for display control of the liquid crystal module 14. Examples of the control signal CNT include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a transfer clock signal CLKf for transferring display data DAT to each display pixel of the LCD element, and the like.

The clock device 16 generates a clock signal CLK, which is a periodic signal used for measuring time intervals and synchronizing, and transmits the clock signal CLK to various configurations.

In the present embodiment, the liquid crystal module 14 has an operation mode Ma for performing a new display operation and a pause mode Mp for pausing the display operation. The operations of the liquid crystal controller 15 and the clock device 16 change depending on whether the liquid crystal module 14 is in the operation mode Ma or the sleep mode Mp. FIG. 2 shows a correspondence relationship between the operation mode and pause mode of the liquid crystal module 14 and the operation of the liquid crystal controller 15 in the present embodiment.

Specifically, the liquid crystal module 14 generates a pause / operation signal P / A indicating whether the operation mode Ma or the pause mode Mp is being transmitted to the liquid crystal controller 15. Thereby, the liquid crystal controller 15 can recognize whether the liquid crystal module 14 is in the operation mode Ma or the sleep mode Mp based on the received pause / operation signal P / A.

As shown in FIG. 2, in the sleep mode Mp, the liquid crystal controller 15 stops transmitting part or all of the display data DAT and the plurality of control signals CNT to the liquid crystal module 14. In this case, since the liquid crystal module 14 does not receive the signal for which the liquid crystal controller 15 has stopped the transmission, the circuit unit relating to the signal that has not been received does not need to operate. Further, since the liquid crystal controller 15 does not need to generate or process the signal for stopping the transmission, the liquid crystal controller 15 can stop the circuit unit related to the signal for stopping the transmission. As a result, the power consumption of the liquid crystal module 14 and the liquid crystal controller 15 can be reduced.

By the way, among the signals transmitted from the liquid crystal controller 15 to the liquid crystal module 14, the display data DAT and the transfer clock signal CLKf have higher frequencies than other signals. In general, the power consumption of the circuit is proportional to “voltage × load capacity × frequency”. Therefore, if the frequency is lowered, the power consumption can be reduced. Therefore, in the sleep mode Mp, the power consumption of the liquid crystal module 14 and the liquid crystal controller 15 can be greatly reduced rather than the liquid crystal controller 15 stopping transmitting the display data DAT and the transfer clock signal CLKf to the liquid crystal module 14. it can.

For example, when the total number of pixels of the liquid crystal module 14 is 480 × 320 dots and the frame frequency is 60 Hz, the maximum frequency of the display data DAT and the frequency of the transfer clock signal CLKf are about 9 MHz to 12 MHz. On the other hand, the frequency of the vertical synchronization signal Vsync is 60 Hz, which is the same as the frame frequency, and the frequency of the horizontal synchronization signal Hsync is 320 × 60 = 19.2 kHz. Even when the duty ratio of the horizontal synchronizing signal Hsync is 1: 9, the frequency of the clock signal necessary for generating and processing the horizontal synchronizing signal Hsync is 19.2 kHz × 10 = 192 kHz.

Accordingly, the frequency of the clock signal necessary for generating and processing the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync is the frequency necessary for processing the display data DAT and the transfer clock signal CLKf. It is about 1/40 or less of the frequency of the clock signal necessary for processing. From this, it can be understood that the power consumption of the liquid crystal module 14 and the liquid crystal controller 15 can be significantly reduced by stopping the transmission of the display data DAT and the transfer clock signal CLKf particularly in the case of the sleep mode Mp.

In this embodiment, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync are transmitted from the liquid crystal controller 15 to the liquid crystal module 14 even in the sleep mode Mp. Thereby, the transition from the sleep mode Mp to the operation mode Ma can be performed based on the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync. In the case of the above example, the liquid crystal controller 15 receives a horizontal synchronization signal Hsync of 480 pulses or more for one pulse of the vertical synchronization signal Vsync. Therefore, the liquid crystal controller 15 can reliably perform the transition in synchronism with the vertical synchronization signal Vsync by performing the preparation for the transition based on the horizontal synchronization signal Hsync.

Further, in the present embodiment, the liquid crystal module 14 in the sleep mode Mp may perform preparation for display operation after receiving or transmitting the pause / operation signal P / A. Therefore, the analog power supply in the liquid crystal module 14 can be stopped until the pause / operation signal P / A is received or transmitted, and the power consumption can be further reduced.

As shown in FIG. 2, in the sleep mode Mp, the liquid crystal controller 15 stops reading display data DAT from the memory 13 via the bus 12. In this case, since the frequency of access from the liquid crystal controller 15 to the memory 13 can be reduced, the access efficiency from other devices, particularly the CPU 11 to the memory 13 is improved. Further, since the occupation rate of the bus 12 can be reduced, the frequency of use of the bus 12 by other devices, particularly the CPU, is improved, and the performance is improved.

By the way, when a circuit unit that generates or transmits a signal having the highest frequency is stopped in a certain device, a clock signal supplied to the circuit unit becomes unnecessary. In this case, the device can operate even when a low-frequency clock signal is supplied.

Therefore, in the present embodiment, the liquid crystal controller 15 transmits a pause / operation signal P / A from the liquid crystal module 14 to the clock device 16. As a result, the clock device 16 can recognize whether the liquid crystal module 14 is in the operation mode Ma or the sleep mode Mp based on the received pause / operation signal P / A.

As shown in FIG. 2, the clock device 16 supplies a low-frequency clock signal CLK to the liquid crystal controller 15 in the sleep mode Mp. In this case, the operating frequency of the liquid crystal controller 15 is lowered, and the power consumption of the logic circuit is proportional to the frequency as described above, so that the power consumption of the liquid crystal controller 15 can be further reduced.

〔Example〕
Next, specific examples of the liquid crystal module 14, the liquid crystal controller 15, and the clock device 16 will be described with reference to FIGS. FIG. 3 shows a schematic configuration of the liquid crystal module 14. As illustrated, the liquid crystal module 14 includes a TFT panel (display element) 22, a scanning signal line driving circuit 25, a data signal line driving circuit 26, a counter electrode driving circuit 28, and a mode control circuit 29.

The TFT panel 22 includes i rows of scanning signal lines G1, G2,..., Gi (referred to collectively by reference numeral G) and j columns of data signal lines S1, S2,. The pixel electrode 23 is provided in a region partitioned by the reference symbol S). The transmissivity of the liquid crystal between the electrodes 23 and 24 is changed by the voltage held between the pixel electrode 23 and the counter electrode 24, whereby image display is performed. In FIG. 3, i = j = 4 is set for simplification of the drawing, but the present invention is not limited to this.

The scanning signal line G is connected to the scanning signal line driving circuit 25, and the data signal line S is connected to the data signal line driving circuit 26. The counter electrode 24 is electrically connected to the counter electrode drive circuit 28.

The scanning signal line driving circuit 25 receives the vertical synchronizing signal Vsync and the horizontal synchronizing signal Hsync, starts a driving operation to the scanning signal line G based on the vertical synchronizing signal Vsync, and performs horizontal scanning based on the horizontal synchronizing signal Hsync. The scanning signal lines G are sequentially driven every cycle. On the other hand, the data signal line driving circuit 26 receives the horizontal synchronization signal Hsync, the display data DAT, and the transfer clock signal CLKf, starts a driving operation to the data signal line S based on the horizontal synchronization signal Hsync, and transfers the transfer clock signal. A data signal obtained by dividing the display data DAT for each pixel is sequentially output to each data signal line S based on CLKf.

Thereby, a corresponding voltage is individually applied to each pixel electrode 23 through a TFT element (not shown) formed at each intersection of the scanning signal line G and the data signal line S. The counter electrode drive circuit 28 receives the horizontal synchronization signal Hsync and drives the counter electrode 24 based on the horizontal synchronization signal Hsync.

The mode control circuit 29 controls either the operation mode Ma in which the liquid crystal module 14 performs a new display operation or the pause mode Mp in which the display operation is paused. Specifically, the mode control circuit 29 selects either the operation mode Ma or the pause mode Mp based on the mode instruction signal MD from the CPU 11 via the liquid crystal controller 15, and the pause / operation signal indicating the selected mode. P / A is generated. The mode control circuit 29 transmits the generated pause / operation signal P / A to the data signal line driving circuit 26 and also to the external liquid crystal controller 15.

FIG. 4 shows the correspondence between the contents of the mode instruction signal MD and the driving method of the liquid crystal module 14. As shown in the figure, since the mode instruction signal MD is composed of 2 bits, four driving methods can be instructed. The first driving method is a continuous driving method in which the operation mode Ma is continuous.

Further, the remaining three driving methods are intermittent driving methods in which the operation mode Ma is followed by the sleep mode Mp. In other words, the second driving method is a 1: 1 intermittent driving method in which an operation mode Ma of 1 frame period (1/60 seconds) and a pause mode Mp of 1 frame period are alternately followed. The third driving method is a 1: 4 intermittent driving method in which an operation mode Ma of one frame cycle and a pause mode Mp of four frame cycles are alternately followed. The fourth driving method is a 1: 9 intermittent driving method in which an operation mode Ma having a 1-frame cycle and a pause mode Mp having a 9-frame cycle are alternately followed.

It should be noted that the 2-bit mode instruction signal MD may be transmitted separately from the liquid crystal controller 15 to the liquid crystal module 14 via two signal lines, or may be transmitted continuously via one signal line. In the example of FIG. 4, four drive methods are mentioned, but the present invention is not limited to these.

In this embodiment, the timing at which the mode control circuit 29 transmits the pause / operation signal P / A is the gate delay or the data transfer clock from the rising or falling edge of the vertical synchronization signal Vsync received by the liquid crystal module 14. It's a minute late. In order to avoid a problem due to this delay, the pause / operation signal P / A indicates whether the next frame period is the operation mode Ma or the pause mode Mp. Thereby, the liquid crystal module 14 and the liquid crystal controller 15 can operate as the sleep mode Mp or the operation mode Ma from the beginning of one frame period.

Referring back to FIG. 3, the data signal line driving circuit 26 stops the operation of the circuit unit related to the display data DAT and the transfer clock signal CLKf in the pause mode Mp. Thereby, power consumption can be reduced significantly.

In this embodiment, if the flicker is not a concern, the mode control circuit 29 transmits the pause / operation signal P / A to the scanning signal line driving circuit 25 and the counter electrode driving circuit 28, thereby scanning signal lines. All operations of the drive circuit 25, the data signal line drive circuit 26, and the counter electrode drive circuit 28 may be stopped.

FIG. 5 shows the operation of the liquid crystal module 14 of this embodiment and the operation of various signals. FIG. 5 shows operations of the vertical synchronization signal Vsync, the display units 22 to 24 of the liquid crystal module 14, and the pause / operation signal P / A in order from the top. In the present embodiment, the vertical synchronization signal Vsync is a negative logic signal. In the pause / operation signal P / A, the L level indicates the pause mode Mp, and the H level indicates the operation mode Ma. Further, in the example of FIG. 5, the delay due to the transmission of the signal line and the processing in the circuit is omitted.

As shown in FIG. 5, at a certain time point C <b> 10 when driving in the continuous driving method, the mode instruction signal MD indicating the 1: 1 intermittent driving method is sent from the CPU 11 to the mode control circuit 29 via the liquid crystal controller 15. Suppose that it was sent. At this time, in the mode control circuit 29, the mode instruction signal MD is processed in synchronization with the subsequent fall (C11) of the vertical synchronization signal Vsync, and the pause / operation signal P / A is the 1: 1 intermittent drive described above. It will be changed to one that follows the method. Thereby, the pause / operation signal P / A after the fall time point C11 is alternately switched between the H level (operation mode Ma) and the L level (pause mode Mp) in synchronization with the fall of the vertical synchronization signal Vsync. Will be repeated.

On the other hand, in the data signal line driving circuit 26, the pause / operation signal P / A is processed in synchronism with the fall of the next vertical synchronizing signal Vsync (C12), and the display units 22 to 24 have the above 1: 1 ratio. Driven according to the intermittent drive system. Thus, the display units 22 to 24 after the falling point C12 are alternately repeated with a new display operation and a pause of the display operation in synchronization with the falling of the vertical synchronization signal Vsync.

Then, it is assumed that the mode instruction signal MD indicating the continuous driving method is transmitted from the CPU 11 to the mode control circuit 29 via the liquid crystal controller 15 at a certain time C13 when the driving is performed by the 1: 1 intermittent driving method. At this time, in the mode control circuit 29, the mode instruction signal MD is processed in synchronization with the subsequent fall (C14) of the vertical synchronization signal Vsync, and the pause / operation signal P / A is changed to that in accordance with the continuous drive system. Is done. As a result, the pause / operation signal P / A after the time point C14 is kept at the H level (operation mode Ma).

On the other hand, in the data signal line driving circuit 26, the pause / operation signal P / A is processed in synchronization with the fall of the next vertical synchronizing signal Vsync (C15), and the display units 22 to 24 are driven according to the continuous driving method. Is done. As a result, the display units 22 to 24 after the falling point C15 repeat the new display operation in synchronization with the falling of the vertical synchronization signal Vsync.

FIG. 6 shows a schematic configuration of the liquid crystal controller 15. As illustrated, the liquid crystal controller 15 includes a control unit 30, a polarity selection unit 31, a synchronization unit 32, an operation selection unit 33, an access restriction unit 34, and a transmission restriction unit 35.

In FIG. 6, the signal act_en is a signal from the register act_en in which one of the continuous driving method and the intermittent driving method is set. The signal iact is a signal from the register iact in which the polarity of the pause / operation signal P / A is set. The signal ivs is a signal ivs from a register in which the polarity of the vertical synchronization signal Vsync is set. In FIG. 6, the mode instruction signal MD shown in FIG. 3 is omitted.

The control unit 30 generates and transmits a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a transfer clock signal CLKf based on the clock signal CLK from the clock device 16. Further, the control unit 30 reads the display data DAT from the memory 13 and transmits it to the liquid crystal module 14 in synchronization with the transfer clock signal CLKf.

That is, the control unit 30 of this embodiment corresponds to a conventional continuous drive type liquid crystal controller, and the liquid crystal controller 15 of this embodiment applies the present invention to the conventional continuous drive type liquid crystal controller. Therefore, some circuit components are added.

The polarity selector 31 changes the polarities of the vertical synchronization signal Vsync and the pause / operation signal P / A based on the settings of the registers ivs and iact. As shown in FIG. A selector is provided.

The synchronization unit 32 includes a latch circuit, and uses the trailing edge of the vertical synchronization signal Vsync output from the control unit 30 and before being output to the outside as a clock, as a pause / operation signal P / from the liquid crystal module 14. A is synchronized. The synchronization unit 32 transmits the synchronized signal active_i1 to the operation selection unit 33. As described above, the polarity of the pause / operation signal P / A is determined by the setting of the register iact, and the polarity of the clock (vertical synchronization signal Vsync) is determined by the setting of the register ivs.

The operation selection unit 33 selects whether the liquid crystal module 14 and the liquid crystal controller 15 operate in the continuous drive method or the intermittent drive method based on the signal act_en from the CPU 11. When the signal act_en is at the L (low) level, the continuous driving method is selected, and the output signal active_i2 is always at the H (high) level. On the other hand, when the signal act_en is at the H (high) level, the intermittent drive method is selected, and the output signal active_i2 is at the same level as the signal active_i1.

The access restriction unit 34 suppresses access from the control unit 30 to the memory 13 based on the signal active_i2. Specifically, the access restriction unit 34 restricts access to the memory 13 when the signal active_i2 is at the L level, and does not restrict access to the memory 13 in other cases.

The transmission restriction unit 35 restricts the transmission of the display data DAT and the transfer clock signal CLKf from the control unit 30 to the outside based on the signal active_i2. Specifically, when the signal active_i2 is at the L level, the transmission limiting unit 35 fixes the display data DAT and the transfer clock signal CLKf to the L level and transmits them to the liquid crystal module 14, while in other cases, the transmission limiting unit 35 transmits the signals as they are.

FIG. 7 shows the operation of various signals when the liquid crystal module 14 operates in the intermittent drive system in the liquid crystal controller 15 of the present embodiment. FIG. 7 shows operations of the signal active_i1, the signal active_i2, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the transfer clock signal CLKf, the display data DAT, and the pause / operation signal P / A in order from the top. In the example of FIG. 7, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync are negative logic signals. Further, in the example of FIG. 7, it is assumed that the polarity selection unit 31 does not change the polarity, and the operation selection unit 33 operates in the intermittent drive method. Further, in the example of FIG. 7, delay due to transmission of signal lines and processing in the circuit is omitted.

As shown in FIG. 7, the level of the pause / operation signal P / A transitions from the H level (operation mode Ma) to the L level (pause mode Mp) in synchronization with the fall (D10) of the vertical synchronization signal Vsync. . The level of the pause / operation signal P / A is input to the synchronization unit 32, and the signal active_i1 transitions to the L level in synchronization with the rising edge (D11) of the vertical synchronization signal Vsync.

The level of the signal active_i1 is input to the operation selection unit 33, and the signal active_i2 transitions to the L level in synchronization with the falling edge (D12) of the vertical synchronization signal Vsync. Thereby, access to the memory 13 by the access restriction unit 34 is restricted, and transmission of the display data DAT and the transfer clock signal CLKf by the transmission restriction unit 35 to the liquid crystal module 14 is restricted to L level transmission. Therefore, during one frame period Fp from the falling point D12, the display data DAT and the transfer clock signal CLKf are not transmitted to the liquid crystal module 14, and a new display operation is stopped in the liquid crystal module 14.

Further, as shown in FIG. 7, the level of the pause / operation signal P / A transitions from the L level to the H level in synchronization with the fall (D12) of the vertical synchronization signal Vsync. The level of the pause / operation signal P / A is input to the synchronization unit 32, and the signal active_i1 transitions to the H level in synchronization with the rising edge (D13) of the vertical synchronization signal Vsync.

The level of the signal active_i1 is input to the operation selection unit 33, and the signal active_i2 transitions to the H level in synchronization with the falling edge (D14) of the vertical synchronization signal Vsync. Thereby, access to the memory 13 by the access restriction unit 34 is not restricted, and transmission of the display data DAT and the transfer clock signal CLKf by the transmission restriction unit 35 to the liquid crystal module 14 is also not restricted. Accordingly, during one frame period Fa from the falling point D14, the display data DAT and the transfer clock signal CLKf are transmitted to the liquid crystal module 14, and a new display operation is performed in the liquid crystal module 14 (D15). .

FIG. 8 shows a schematic configuration of the clock device 16. As illustrated, the clock device 16 includes a crystal oscillation circuit 40, a 1/62 frequency divider circuit 41, a selector 42, and a timing adjustment circuit 43.

The crystal oscillation circuit 40 is an oscillation circuit that uses a crystal resonator as a resonator, and generates a 12 MHz clock signal in this embodiment. This is about 620 times the horizontal synchronizing signal Hsync (19.2 kHz) described above. The crystal oscillation circuit 40 transmits the generated 12 MHz clock signal to the 1/62 frequency divider circuit 41 and the selector 42.

The 1/62 frequency dividing circuit 41 divides the frequency of the received clock signal by 1/62. In this embodiment, the 12 MHz clock signal is converted into a 0.1935 MHz clock signal. This is about 10 times the horizontal synchronizing signal Hsync (19.2 kHz) described above. The 1/62 divider circuit 41 transmits the divided clock signal to the selector 42.

The timing adjustment circuit 43 adjusts the timing of the pause / operation signal P / A received from the liquid crystal controller 15 so as to be synchronized with the output timing of the selector 42. The timing adjustment circuit 43 transmits the pause / operation signal P / A whose timing is adjusted to the selector 42.

The selector 42 selects either the clock signal from the crystal oscillation circuit 40 or the clock signal from the 1/62 frequency divider circuit 41 based on the pause / operation signal P / A whose timing is adjusted by the timing adjustment circuit 43. Thus, it is output to the liquid crystal controller 15 as a clock signal CLK. Specifically, in the sleep mode Mp, the 0.1935 MHz clock signal from the 1/62 frequency divider 41 is output to the liquid crystal controller 15, while in the operation mode Ma, the 12 MHz clock signal from the crystal oscillation circuit 40 is output. A clock signal is output to the liquid crystal controller 15. As a result, in the sleep mode Mp, the operating frequency of the liquid crystal controller 15 is greatly reduced, so that power consumption can be greatly reduced.

The CPU 11 and other devices may be supplied with a 12 MHz clock signal from the crystal oscillation circuit 40 or may be supplied with a clock signal from the selector 42 as in the liquid crystal controller 15. When the clock signal is supplied from the selector 42, when the sleep mode Mp is entered, the operating frequency is lowered and the performance is lowered, but the power consumption can be further reduced.

The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope indicated in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

For example, in the above embodiment, the present invention is applied to an image display device of a portable electronic device, but the present invention may be applied to an electronic device other than a portable device such as a desktop PC (Personal Computer). In the above-described embodiment, the present invention is applied to an image display device including an LCD. However, the present invention can also be applied to an image display device including another FPD such as a PDP, an EL display, and an FED.

Moreover, in the said embodiment, although FIG. 3 is mentioned as an Example of the liquid crystal module 14 of an intermittent drive system, this invention is not limited to this, It applies to the liquid crystal module of a well-known intermittent drive system. Can do. In the above embodiment, the vertical synchronization signal Vsync is used. However, an arbitrary synchronization signal for vertical scanning such as a gate start pulse signal can be used. In the above embodiment, the horizontal synchronization signal Hsync is used. However, any synchronization signal for horizontal scanning, such as a gate clock signal, can be used.

In the above embodiment, the liquid crystal controller 15 transmits the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the transfer clock signal CLKf to the liquid crystal module 14, but the source start pulse signal, the data valid signal, etc. Others transmit other control signals. In this case, the power consumption of the liquid crystal module 14 and the liquid crystal controller 15 can be further reduced by stopping the generation and transmission of the other control signals in the pause mode Mp.

In the above embodiment, the periods of the sleep mode Mp and the operation mode Ma are one frame period or multiples thereof, but may be a period unrelated to one frame period.

As described above, in the case of the pause mode, the present invention stops the transmission of the display data and the transfer clock signal to reduce the power consumption, while continuing the transmission of the vertical synchronization signal and the horizontal synchronization signal from the pause mode. Since the preparation for shifting to the operation mode is performed based on the horizontal synchronization signal, the above-described transition can be surely performed in synchronization with the vertical synchronization signal, and thus can be applied to any matrix type display device.

10 Liquid crystal display device (display device)
11 CPU
12 bus 13 memory (storage means)
14 Liquid crystal module (display module)
15 LCD controller (display controller)
16 Clock device 22 TFT panel (display unit / display element)
23 Pixel electrode (display unit)
24 Counter electrode (display part)
25 scanning signal line drive circuit 26 data signal line drive circuit 28 counter electrode drive circuit 29 mode control circuit 30 control unit 31 polarity selection unit 32 synchronization unit 33 operation selection unit 34 access restriction unit 35 transmission restriction unit 40 crystal oscillation circuit 41 1 / 62 divider circuit 42 selector 43 timing adjustment circuit CLK clock signal CLKf transfer clock signal CNT control signal DAT display data Hsync horizontal synchronization signal MD mode instruction signal Ma operation mode Mp pause mode P / A pause / operation signal Vsync vertical synchronization signal

Claims (7)

1. A matrix type display element in which display pixels are arranged in a matrix and a drive circuit for driving the display element are provided, and an operation mode in which a new display operation is performed and a pause mode in which the display operation is suspended A display controller for controlling a display module having
   A pause / operation signal indicating whether the operation mode or the sleep mode is to be received from the display module or based on the pause / operation signal transmitted to the display module; A display controller that controls transmission to the display module with a plurality of control signals necessary for controlling the display module.
2. A matrix type display element in which display pixels are arranged in a matrix and a drive circuit for driving the display element are provided, and an operation mode in which a new display operation is performed and a pause mode in which the display operation is suspended A display controller for controlling a display module having
   In the case of the pause mode, at least the display data and the transfer clock signal for transferring the display data to each display pixel are stopped from being transmitted to the display module, while at least the vertical scanning and the horizontal scanning are performed. A display controller for transmitting a synchronization signal to the display module.
3. 3. The display controller according to claim 1, wherein in the pause mode, reading of the display data from the storage means for storing the display data is stopped.
4. A matrix type display element in which display pixels are arranged in a matrix and a drive circuit for driving the display element are provided, and an operation mode in which a new display operation is performed and a pause mode in which the display operation is suspended A display device comprising: a display module comprising: a display controller that controls the display module; and a clock device that supplies a clock signal to the display controller,
   The display device according to claim 1, wherein the display controller is the display controller according to claim 1.
5. In the case of the pause mode, the display controller stops transmitting at least display data and a transfer clock signal for transferring the display data to each display pixel to the display module,
   The display device according to claim 4, wherein the clock device has a lower frequency of a clock signal supplied to the display controller in the pause mode than in the operation mode.
6. The display device according to claim 4 or 5, wherein the display element is a liquid crystal display element.
7. A portable electronic device comprising the display device according to any one of claims 4 to 6.

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