JP2011109036A - Semiconductor device, and method for manufacturing the same - Google Patents

Semiconductor device, and method for manufacturing the same Download PDF

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Publication number
JP2011109036A
JP2011109036A JP2009265436A JP2009265436A JP2011109036A JP 2011109036 A JP2011109036 A JP 2011109036A JP 2009265436 A JP2009265436 A JP 2009265436A JP 2009265436 A JP2009265436 A JP 2009265436A JP 2011109036 A JP2011109036 A JP 2011109036A
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insulating film
interlayer insulating
region
hole
hole diameter
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JP2009265436A
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Toshinori Seo
俊紀 瀬尾
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Panasonic Corp
パナソニック株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • H01L23/53295Stacked insulating layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005Formation and after-treatment of dielectrics
    • H01L2221/1042Formation and after-treatment of dielectrics the dielectric comprising air gaps
    • H01L2221/1047Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In a semiconductor device including an interlayer insulating film, occurrence of film peeling and formation of a leak path are suppressed.
The semiconductor device includes an interlayer insulating film 16 including a plurality of holes. The interlayer insulating film 16 is a film having a single layer structure. In the interlayer insulating film 16, the hole diameter of the holes included in the lower surface region and the hole diameter of the holes included in the upper surface region are the hole diameters of the holes included in the central region interposed between the upper surface region and the lower surface region. Smaller than.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device including an interlayer insulating film including holes and a method for manufacturing the same.

  Along with miniaturization and high integration of semiconductor devices, delays in the propagation speed of electric signals due to increases in wiring resistance and inter-wiring capacitance have become serious problems.

  In particular, in a highly integrated semiconductor device, the operation speed of the semiconductor device is reduced due to an increase in inter-wiring capacitance. For this reason, a material having a low relative dielectric constant is used as the material of the interlayer insulating film, that is, a low dielectric constant interlayer insulating film is used to suppress an increase in inter-wiring capacitance.

  In recent years, development or practical application of a low dielectric constant interlayer insulating film in which the low dielectric constant interlayer insulating film is made porous to further reduce the relative dielectric constant has been studied.

  Hereinafter, a conventional method for manufacturing a semiconductor device using a low dielectric constant interlayer insulating film will be described with reference to FIGS. 9A to 9D (see, for example, Patent Document 1). 9A to 9D are cross-sectional views showing a conventional method of manufacturing a semiconductor device in the order of steps.

  First, as shown in FIG. 9A, on the substrate 100, a first interlayer insulating film for a porogen containing a skeleton structure made of an inorganic material is formed. Thereafter, the porogen contained in the first interlayer insulating film is decomposed and removed to form the first interlayer insulating film 101 including holes.

  Next, on the first interlayer insulating film 101, a second interlayer insulating film 102A containing a porogen P made of a hydrocarbon compound in a skeleton structure made of an inorganic material is formed. At this time, since the porogen P is made of a hydrocarbon compound, the carbon content in the second interlayer insulating film 102A is higher than the carbon content in the first interlayer insulating film 101. At this time, since the second interlayer insulating film 102A is a pseudo organic material film containing porogen P, it is between the first interlayer insulating film 101 and the second interlayer insulating film 102A. Then, an interface between the pseudo inorganic material film and the organic material film is formed.

  Next, as shown in FIG. 9B, a resist pattern Re1 having a wiring pattern is formed on the second interlayer insulating film 102A. Thereafter, a wiring groove 103 is formed in the second interlayer insulating film 102A by etching using the resist pattern Re1 as a mask. At this time, since the interface between the pseudo inorganic material film and the organic material film is formed between the first interlayer insulating film 101 and the second interlayer insulating film 102A, the first interlayer insulating film is formed. The etching selectivity of the second interlayer insulating film 102A to the film 101 can be increased. Therefore, the wiring trench 103 can be formed with high accuracy in the second interlayer insulating film 102A.

  Next, as shown in FIG. 9C, after removing the resist pattern Re1, a resist pattern Re2 having a via pattern is formed on the second interlayer insulating film 102A. Thereafter, a via hole 104 is formed in the first interlayer insulating film 101 by etching using the resist pattern Re2 as a mask.

  Next, as shown in FIG. 9 (d), after removing the resist pattern Re2, the porogen P contained in the second interlayer insulating film 102A is decomposed and removed, so that the second An interlayer insulating film 102 is formed.

  Thereafter, although not shown, a via is formed in the via hole 104 and a wiring connected to the via is formed in the wiring groove 103.

  As described above, a conventional semiconductor device is manufactured.

  Conventionally, vias and wirings are formed in a film having a stacked structure in which a first interlayer insulating film 101 and a second interlayer insulating film 102 are sequentially stacked. The interlayer insulating film in which the via is formed (first interlayer insulating film 101) and the interlayer insulating film in which the wiring is formed (second interlayer insulating film 102) are formed in different processes and have different film quality.

JP 2007-250706 A

  However, the conventional semiconductor device has the following problems.

  The via and the wiring are formed in a film having a stacked structure in which a first interlayer insulating film 101 and a second interlayer insulating film 102 are sequentially stacked. For this reason, the film interface existing between the first interlayer insulating film 101 and the second interlayer insulating film 102 intersects the wiring or via perpendicularly.

  For this reason, there is a problem in that film peeling occurs at the film interface, and a leak path is formed at the film interface, and a leak current is generated between the wiring and another wiring adjacent to the wiring. Here, “leakage path” refers to a leakage current path.

  In view of the above, an object of the present invention is to suppress the occurrence of film peeling and the formation of a leak path in a semiconductor device including an interlayer insulating film.

  In order to achieve the above object, a semiconductor device according to the present invention includes an interlayer insulating film including a plurality of vacancies, and the interlayer insulating film is a film having a single layer structure, and is provided in a lower surface region of the interlayer insulating film. The hole diameter of the included hole and the hole diameter of the hole included in the upper surface region are smaller than the hole diameter of the hole included in the central region interposed between the upper surface region and the lower surface region.

  According to the semiconductor device of the present invention, the interlayer insulating film is a single-layered film, in other words, a single continuous film, and there is no film interface in the interlayer insulating film. For this reason, film peeling does not occur at the film interface. In addition, since a leak path is not formed at the film interface, when a wiring is formed in the interlayer insulating film, a leak current is not generated between the wirings. Accordingly, the reliability of the semiconductor device can be improved.

  In addition, in the interlayer insulating film, the hole diameter of the holes included in the lower surface region is made smaller than the hole diameter of the holes included in the central region. As a result, when a film is formed on the lower surface of the interlayer insulating film, the contact area between the lower surface of the interlayer insulating film and the film can be increased, thereby improving the adhesion between the interlayer insulating film and the film. Can be made. Similarly, in the interlayer insulating film, the hole diameter of the holes included in the upper surface region is made smaller than the hole diameter of the holes included in the central region. As a result, when a film is formed on the upper surface of the interlayer insulating film, the contact area between the upper surface of the interlayer insulating film and the film can be increased, thereby improving the adhesion between the interlayer insulating film and the film. Can be made.

  In the semiconductor device according to the present invention, it is preferable that the plurality of holes have a hole diameter that decreases from the center toward the lower surface, while the hole diameter decreases from the center toward the upper surface.

  In the semiconductor device according to the present invention, when the thickness of the interlayer insulating film is t, the thickness of the upper surface region is 0.05 t or more and 0.3 t or less, and the thickness of the lower surface region is 0.05 t. It is preferable that it is above and below 0.3t.

  In the semiconductor device according to the present invention, the interlayer insulating film is located on the lower surface side, is located in the center, and includes a first region including a plurality of holes each having a first hole diameter, A second region including a plurality of holes having a second hole diameter larger than the hole diameter, and a plurality of holes located on the upper surface side and each having a third hole diameter smaller than the second hole diameter. A third region including a hole, and a first change region including a plurality of holes that are interposed between the first region and the second region and have a hole diameter that increases from the lower surface side toward the upper surface side; And a second change region including a plurality of holes that are interposed between the second region and the third region and whose hole diameter decreases from the lower surface side toward the upper surface side, and the first change The hole diameters of the plurality of holes included in the region are larger than the first hole diameter and smaller than the second hole diameter, and are included in the second change region. The plurality of holes has a hole diameter larger than the third hole diameter and smaller than the second hole diameter, and the lower surface region of the interlayer insulating film includes the first region and the first change region, The central region in the insulating film preferably includes the second region, and the upper surface region in the interlayer insulating film preferably includes the second change region and the third region.

  The semiconductor device according to the present invention preferably further includes a via formed below the interlayer insulating film and a wiring formed above the interlayer insulating film and connected to the via.

  In this way, in the interlayer insulating film, the hole diameters of the holes included in the central region (in other words, the region located within the range from the lower surface of the wiring to the center of the wiring) are set in each of the lower surface region and the upper surface region. It is made larger than the hole diameter of the included holes. Thereby, the capacity | capacitance between wiring can be reduced.

  In the semiconductor device according to the present invention, the hole diameter of the hole located near the lower part of the wiring is larger than the hole diameter of the hole located near the upper part of the wiring and the hole diameter of the hole located near the lower part of the via. It is preferable.

  The semiconductor device according to the present invention preferably further includes a first insulating film formed under the interlayer insulating film and a second insulating film formed over the interlayer insulating film.

  In the semiconductor device according to the present invention, the interlayer insulating film is a first interlayer insulating film, and further includes a second interlayer insulating film formed on the first interlayer insulating film and including a plurality of holes, In the first interlayer insulating film, the hole diameter of the holes included in the central region is x, the hole diameter of the holes included in the upper surface region is y, and the lower surface region and the upper surface region in the second interlayer insulating film are When the hole diameter of a hole included in the central region interposed between is v and the hole diameter of a hole included in the upper surface region is w, the rate of change x / y with respect to y is It is preferable that the rate of change is greater than v / w.

  In this case, the first interlayer insulating film (first interlayer insulating film close to the substrate) having a short inter-wiring distance is replaced with a film having a high rate of change x / y (in other words, a film considering reduction of inter-wiring capacitance). ). On the other hand, the second interlayer insulating film (second interlayer insulating film far from the substrate) having a long inter-wiring distance is a film having a small change rate v / w (in other words, a film that does not take into account the reduction of inter-wiring capacitance). be able to. Here, “a film having a short (long) distance between wirings” means a film having a short (long) distance between a plurality of wirings formed in the film.

  In the semiconductor device according to the present invention, the interlayer insulating film is a first interlayer insulating film, and further includes a second interlayer insulating film formed on the first interlayer insulating film and including a plurality of holes, In the second interlayer insulating film, the hole diameter of the hole included in the central region interposed between the lower surface region and the upper surface region is substantially equal to the hole diameter of the hole included in the upper surface region of the second interlayer insulating film. It is preferable that the hole diameter of the holes included in the central region in the second interlayer insulating film is smaller than the hole diameter of the holes included in the central region in the first interlayer insulating film.

  In this case, the first interlayer insulating film having a short inter-wiring distance is formed on the film in which the hole diameter of the hole included in the central region is larger than the hole diameter of the hole included in each of the lower surface region and the upper surface region ( In other words, the film can be a film that takes into account the reduction in inter-wiring capacitance. On the other hand, in the second interlayer insulating film having a long inter-wiring distance, the hole diameter of the holes included in the central region is substantially the same as the hole diameter of the holes included in the upper surface region (in other words, the inter-wiring capacitance A film that does not consider reduction).

In the semiconductor device according to the present invention, the interlayer insulating film is preferably a SiO 2 film, a SiOC film, an FSG film, or a BSG film.

  In the semiconductor device according to the present invention, the distance between the wirings is preferably 100 nm or less.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming an interlayer insulating film including a plurality of vacancies, and the interlayer insulating film is a film having a single layer structure, The step of forming the insulating film includes the step of forming the hole diameter of the holes included in the lower surface region and the hole diameter of the holes included in the upper surface region of the holes included in the central region interposed between the lower surface region and the upper surface region. It is a step of forming an interlayer insulating film so as to be smaller than the hole diameter.

  According to the semiconductor device manufacturing method of the present invention, the interlayer insulating film is a single-layered film, in other words, a single continuous film, and there is no film interface in the interlayer insulating film. For this reason, film peeling does not occur at the film interface. In addition, since a leak path is not formed at the film interface, when a wiring is formed in the interlayer insulating film, a leak current does not occur between the wirings. Accordingly, the reliability of the semiconductor device can be improved.

  Further, in the interlayer insulating film, the hole diameter of the holes included in the lower surface region is made smaller than the hole diameter of the holes included in the central region. As a result, when a film is formed on the lower surface of the interlayer insulating film, the contact area between the lower surface of the interlayer insulating film and the film can be increased, thereby improving the adhesion between the interlayer insulating film and the film. be able to. Similarly, in the interlayer insulating film, the hole diameter of the holes included in the upper surface region is made smaller than the hole diameter of the holes included in the central region. Thus, when a film is formed on the upper surface of the interlayer insulating film, the contact area between the upper surface of the interlayer insulating film and the film can be increased, so that the adhesion between the interlayer insulating film and the film is improved. be able to.

  In the method for manufacturing a semiconductor device according to the present invention, in the step of forming the interlayer insulating film, the plurality of holes have a hole diameter that decreases from the center toward the lower surface, while the hole diameter decreases from the center toward the upper surface. It is preferable that it is small.

  In the method for manufacturing a semiconductor device according to the present invention, the step of forming an interlayer insulating film includes the step of forming a film for an interlayer insulating film including a plurality of particles made of a pore forming agent by chemical vapor deposition (a). And a step (b) of forming a interlayer insulating film by removing a plurality of particles contained in the interlayer insulating film.

  In the method for manufacturing a semiconductor device according to the present invention, in the step (a), it is preferable to adjust the flow rates of the precursor and the hole forming agent that form the skeleton of the interlayer insulating film according to the film formation time.

  In this way, it is possible to form an interlayer insulating film including a plurality of holes whose hole diameter changes in a direction (film thickness direction) from the lower surface side to the upper surface side.

  In the method for manufacturing a semiconductor device according to the present invention, in the step (a), it is preferable to adjust the diameter of the particles made of the pore forming agent according to the film formation time.

  In this way, it is possible to form an interlayer insulating film including a plurality of holes whose hole diameter changes in the film thickness direction.

  In the method for manufacturing a semiconductor device according to the present invention, the step (b) is preferably a step of removing a plurality of particles contained in the interlayer insulating film by heat treatment, electron beam irradiation or ultraviolet irradiation.

  In the method of manufacturing a semiconductor device according to the present invention, the step of forming the interlayer insulating film includes the step of forming voids included in the region near the upper surface of the interlayer insulating film by heat treatment, electron beam irradiation or ultraviolet irradiation after step (b). It is preferable to further include a step (c) of reducing the pore diameter.

  In the method for manufacturing a semiconductor device according to the present invention, in the step (a), in the chamber, the precursor is flowed at the first precursor flow rate during the first time, and the holes are formed at the first pore forming agent flow rate. Flowing the forming agent to form the first region (a1), and flowing the precursor while changing the first precursor flow rate to the second precursor flow rate during the second time in the chamber; A step (a2) of forming a first change region on the first region by flowing the pore-former while changing the flow rate from the first pore-former flow rate to the second pore-former flow rate; In the chamber, during the third time, the precursor is flowed at the second precursor flow rate, the pore forming agent is flowed at the second pore forming agent flow rate, and the first change region is flown over the first change region. Step (a3) for forming the region 2; In the bar, during the fourth time, the precursor flows while changing from the second precursor flow rate to the third precursor flow rate, and also changes from the second pore formation agent flow rate to the third pore formation agent flow rate. And a step (a4) of forming a second change region on the second region by flowing a pore-forming agent, and a precursor at a third precursor flow rate for a fifth time in the chamber. And a step (a5) of forming a third region on the second change region by flowing a pore-forming agent at a third pore-forming agent flow rate, and in the step (a5) Forming an interlayer insulating film having a first region, a first change region, a second region, a second change region, and a third region, and forming a first hole with respect to a first precursor flow rate The agent flow rate is the second pore forming agent with respect to the second precursor flow rate. Less than the amount, the third pore forming agent flow rate for the third precursor flow rate is preferably smaller than the second pore-forming agent flow rate for the second precursor flow rates.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, since no film interface exists in the interlayer insulating film, it is possible to suppress the occurrence of film peeling and the formation of a leak path.

It is sectional drawing which shows the structure of the semiconductor device which concerns on one Embodiment of this invention. (a) is an expanded sectional view showing the structure of the second interlayer insulating film and its vicinity in the semiconductor device according to one embodiment of the present invention, and (b) is the fourth interlayer insulating film and its vicinity. It is an expanded sectional view which shows the structure. It is a figure which shows distribution of the hole diameter of the film thickness direction in a 2nd interlayer insulation film. (a)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention in process order. (a)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention in process order. (a)-(b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention in process order. (a)-(b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention in process order. It is a figure which shows an example of the timing chart of each flow volume of a precursor, a void | hole formation agent, and an oxidizing agent, and the power of high frequency electric power. (a)-(d) is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process.

  A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In the following description, the materials and numerical values merely exemplify preferable examples, and are not limited to the illustrated materials and numerical values. The present invention can be modified for convenience without departing from the scope of the technical idea of the present invention.

(One embodiment)
Hereinafter, the structure of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2 (a) to 2 (b). FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 1, a first interlayer insulating film 11 made of, for example, silicon oxide (SiO 2 ) is formed on a substrate 10 made of, for example, Si. A first wiring 14 is formed in the first interlayer insulating film 11.

  A first insulating film 15 made of, for example, silicon carbide (SiC) is formed on the first interlayer insulating film 11 so as to cover the first wiring 14. A second interlayer insulating film 16 made of carbon-containing silicon oxide (SiOC) having a plurality of holes (not shown) and having a relative dielectric constant of 3.0 or less is formed on the first insulating film 15. ing. A first via 21 is formed below the first insulating film 15 and the second interlayer insulating film 16. A second wiring 22 is formed on the second interlayer insulating film 16. The first wiring 14 and the second wiring 22 are electrically connected by the first via 21.

  A second insulating film 23 made of SiC, for example, is formed on the second interlayer insulating film 16 so as to cover the second wiring 22. On the second insulating film 23, a third interlayer insulating film 24 made of SiOC including a plurality of holes (not shown), for example, having a relative dielectric constant of 3.0 or less is formed. A second via 27 is formed below the second insulating film 23 and the third interlayer insulating film 24. A third wiring 28 is formed on the third interlayer insulating film 24. The second wiring 22 and the third wiring 28 are electrically connected by the second via 27.

  On the third interlayer insulating film 24, a third insulating film 29 made of, for example, SiC is formed so as to cover the third wiring 28. On the third insulating film 29, a fourth interlayer insulating film 30 made of SiOC including a plurality of holes (not shown), for example, having a relative dielectric constant of 3.0 or less is formed. A third via 33 is formed below the third insulating film 29 and the fourth interlayer insulating film 30. A fourth wiring 34 is formed on the fourth interlayer insulating film 30. The third wiring 28 and the fourth wiring 34 are electrically connected by the third via 33.

  A fourth insulating film 35 made of, for example, SiC is formed on the fourth interlayer insulating film 30 so as to cover the fourth wiring 34.

  The first wiring 14 includes a barrier metal film 12 made of, for example, tantalum nitride (TaN) formed on the bottom and wall surfaces of the wiring groove, and, for example, copper (Cu) embedded in the wiring groove via the barrier metal film 12. And a conductive film 13 made of

  The first, second, and third vias 21, 27, and 33 include barrier metal films 19a, 25a, and 31a made of, for example, TaN formed on the bottom and wall surfaces of the via holes, and barrier metal films 19a and 19a in the via holes. Conductive films 20a, 26a and 32a made of Cu, for example, embedded through 25a and 31a.

  The second, third, and fourth wirings 22, 28, and 34 include barrier metal films 19b, 25b, and 31b made of, for example, TaN formed on the bottom and wall surfaces of the wiring groove, and the barrier metal films 19b, Conductive films 20b, 26b, 32b made of Cu, for example, embedded through 25b, 31b.

  The first, second, and third insulating films 15, 23, and 29 function as a metal diffusion prevention film.

  The semiconductor device according to this embodiment includes four layers of first to fourth wiring layers. Here, the “first wiring layer” includes the first interlayer insulating film 11, the first wiring 14, and the like. The “second wiring layer” includes the second interlayer insulating film 16 and the second wiring 22. The “third wiring layer” includes the third interlayer insulating film 24, the third wiring 28, and the like. The “fourth wiring layer” includes the fourth interlayer insulating film 30, the fourth wiring 34, and the like.

  The second, third, and fourth interlayer insulating films will be described below.

<Second interlayer insulating film>
The structure of the second interlayer insulating film will be described below with reference to FIG. FIG. 2A is an enlarged cross-sectional view showing a second interlayer insulating film (characteristic constituent element) and a structure in the vicinity thereof in the semiconductor device according to the embodiment of the present invention.

  As shown in FIG. 2A, the second interlayer insulating film 16 is a film having a single layer structure, in other words, a single continuous film. That is, the second interlayer insulating film 16 is a film in which no film interface exists in the film. Here, the “film interface” refers to an interface existing between different films.

  As shown in FIG. 2A, the second interlayer insulating film 16 includes a plurality of holes. In the second interlayer insulating film 16, the hole diameter of each hole included in each of the lower surface region and the upper surface region is smaller than the hole diameter of the hole included in the central region.

  As shown in FIG. 2 (a), the plurality of holes included in the second interlayer insulating film 16 have a hole diameter that decreases from the center toward the bottom surface, while the hole diameter decreases from the center toward the top surface. It is getting smaller.

  As shown in FIG. 2A, the second interlayer insulating film 16 includes a first region Ra, a first change region Rb, a second region Rc, a second change region Rd, 3 regions Re.

  The first region Ra is located on the lower surface side, and includes a plurality of holes Ha each having a first hole diameter. The second region Rc is located in the center and includes a plurality of holes Hc each having a second hole diameter. The third region Re is located on the upper surface side and includes a plurality of holes He each having a third hole diameter. The first change region Rb is interposed between the first region Ra and the second region Rc, and includes a plurality of holes whose hole diameter increases from the lower surface side toward the upper surface side. The second change region Rd is interposed between the second region Rc and the third region Re, and includes a plurality of holes whose hole diameter decreases from the lower surface side toward the upper surface side.

  The second hole diameter of the hole Hc is larger than the first hole diameter of the hole Ha and the third hole diameter of the hole He. The hole diameter of the hole Hb included in the first change region Rb is larger than the first hole diameter and smaller than the second hole diameter. The hole diameter of the hole Hd included in the second change region Rd is larger than the third hole diameter and smaller than the second hole diameter.

  Here, the “lower surface region” refers to a region including the lower surface (for example, a region including the first region Ra and the first change region Rb). The “upper surface region” refers to a region including the upper surface (for example, a region including the second change region Rd and the third region Re). The “central region” refers to a region that is interposed between the lower surface region and the upper surface region and is located within the range from the lower surface of the second wiring 22 to the center of the second wiring 22 (for example, the second region). Refers to region Rc).

  Here, the first region Ra refers to a region located in a range from the lower surface of the second interlayer insulating film 16 to the center of the first via 21, for example. For example, the first change region Rb is a region located within a range from the center of the first via 21 to the lower surface of the second wiring 22. The second region Rc is, for example, a region located within a range from the lower surface of the second wiring 22 to the center of the second wiring 22. The region including the second change region Rd and the third region Re is, for example, a region located within a range from the center of the second wiring 22 to the upper surface of the second interlayer insulating film 16.

  Each of the first region Ra, the first change region Rb, the second region Rc, the second change region Rd, and the third region Re has different pore diameters as shown in FIG. Therefore, the film quality is different from each other.

  As shown in FIG. 2A, the hole diameter of a hole (for example, hole Hc included in the second region Rc) located near the lower part of the second wiring 22 is the upper part of the second wiring 22. The hole diameter in the vicinity (for example, the hole He included in the third region Re) and the hole in the vicinity of the lower portion of the first via 21 (for example, the hole included in the first region Ra). It is larger than the hole diameter of the hole Ha).

  The distribution of pore diameters in the film thickness direction in the second interlayer insulating film 16 will be described with reference to FIG. FIG. 3 is a diagram showing the hole diameters of the holes included in an arbitrary region in the second interlayer insulating film. Here, the “arbitrary region” refers to a sheet-like region separated from the lower surface by an arbitrary distance in the film thickness direction.

  As shown in FIG. 3, each of the plurality of holes included in the first region Ra has a first hole diameter (for example, about 1 nm or less). The plurality of holes included in the first change region Rb have a hole diameter that increases from the lower surface side toward the upper surface side. Each of the plurality of holes included in the second region Rc has a second hole diameter (for example, about 1 nm or more). The plurality of holes included in the second change region Rd have a hole diameter that decreases from the lower surface side toward the upper surface side. Each of the plurality of holes included in the third region Re has a third hole diameter (for example, about 1 nm or less).

<Third interlayer insulating film>
The structure of the third interlayer insulating film will be described below.

  The third interlayer insulating film 24 has the same structure as the second interlayer insulating film 16. That is, the hole diameter of the holes included in each of the lower surface region and the upper surface region in the third interlayer insulating film 24 is smaller than the hole diameter of the holes included in the central region.

<Fourth interlayer insulating film>
The structure of the fourth interlayer insulating film will be described below with reference to FIG. FIG. 2B is an enlarged cross-sectional view showing the fourth interlayer insulating film and the structure in the vicinity thereof in the semiconductor device according to the embodiment of the present invention.

  The fourth interlayer insulating film 30 includes a plurality of holes H. Each of the hole diameters of the plurality of holes H is substantially the same. The hole diameter of the hole H is smaller than, for example, the second hole diameter of the hole Hc included in the second region Rc shown in FIG.

  In the second interlayer insulating film 16, the hole diameter of the holes included in the central region is x, the hole diameter of the holes included in the upper surface region is y, and the holes are included in the central region of the fourth interlayer insulating film 30. Where v is the hole diameter of the holes to be included and w is the hole diameter of the holes included in the upper surface region, the rate of change of x with respect to y is x / y> 1, and the rate of change of v with respect to w is v / w = 1 and x / y is greater than v / w. Here, the “central region” in the fourth interlayer insulating film 30 refers to, for example, a region located within a range from the lower surface of the fourth wiring 34 to the center of the fourth wiring 34. The “lower surface region” in the fourth interlayer insulating film 30 refers to a region including the lower surface.

  4A to 4C, FIG. 5A to FIG. 5C, FIG. 6A to FIG. 6B, and FIG. 7 for a semiconductor device manufacturing method according to an embodiment of the present invention. Explanation will be made with reference to (a) to (b). FIG. 4A to FIG. 7B are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

First, as shown in FIG. 4A, a first interlayer insulating film 11 made of, for example, SiO 2 is formed on the substrate 10 by, eg, chemical vapor deposition (CVD). Thereafter, a resist (not shown) is applied on the first interlayer insulating film 11, and then a resist pattern (not shown) having a wiring groove pattern is formed by lithography. Thereafter, for example, dry etching is performed on the first interlayer insulating film 11 using the resist pattern as a mask. As a result, a wiring trench is formed in the first interlayer insulating film 11. Thereafter, the resist pattern is removed by ashing. Thereafter, a barrier metal film made of TaN, for example, is formed so as to cover the upper surface of the first interlayer insulating film 11 and the bottom surface and wall surface of the wiring trench by, for example, sputtering. Thereafter, a conductive film made of, for example, Cu is formed on the barrier metal film by, for example, electroplating so as to fill the wiring trench. Thereafter, portions (excess conductive film and barrier metal film) formed outside the wiring trench in the conductive film and the barrier metal film are sequentially removed by, for example, chemical mechanical polishing (CMP). Thereby, the first wiring 14 having the barrier metal film 12 and the conductive film 13 is formed.

  Next, as shown in FIG. 4B, the first wiring 14 is formed on the first interlayer insulating film 11 by, for example, CVD, atomic layer deposition (ALD), or sol-gel (SOD). A first insulating film 15 made of, for example, SiC is formed so as to cover the surface.

  Thereafter, a second interlayer insulating film 16A made of, for example, SiOC including a plurality of particles (not shown) made of a hole forming agent is formed on the first insulating film 15 by, eg, CVD.

  Specifically, the substrate 10 is transferred into a vacuum chamber (not shown), and the substrate 10 is placed on a stage (not shown) heated to 250 ° C., for example. Thereafter, a precursor containing carbon such as diethoxymethylsilane (DEMS) is used as a precursor for forming a film skeleton, a porogen such as α-terpinene is used as a pore forming agent, and oxygen is used as an oxidizing agent. A mixed gas containing DEMS, α-terpinene, and oxygen is flowed into the chamber together with a carrier gas such as helium, and high frequency power is applied. At this time, the flow rate of DEMS, α-terpinene and oxygen and the power of the high-frequency power are adjusted according to the film formation time.

  An example of a timing chart of each flow rate of DEMS, α-terpinene, oxygen, and high-frequency power will be described with reference to FIG. FIG. 8 is a diagram showing the relationship between the flow time of DEMS, α-terpinene, and oxygen and the flow rates of DEMS, α-terpinene, and oxygen, and the relationship between the time and the power of high-frequency power.

  As shown in FIG. 8, in the chamber, DEMS is flowed from time t1 to time t2 (during the first time), for example, 0.3 g / min (first precursor flow rate), for example, 0.25 g. Α terpinene is allowed to flow at / min (first pore forming agent flow rate), and oxygen is allowed to flow at 15 cc / min (standard state), for example, and high frequency power of 1500 W, for example, is applied. As a result, a first region ra having a first diameter and including a plurality of particles made of α-terpinene polymer (or α-terpinene) is formed on the first insulating film 15. Here, “α-terpinene polymer” refers to a polymer obtained by polymerizing α-terpinene. The first time is set according to the thickness of the first region ra.

  Next, as shown in FIG. 8, in the chamber, from time t2 to time t3 (during the second time), 0.3 g / min to 0.2 g / min (second precursor flow rate), for example. While flowing DEMS, changing α terpinene while changing from 0.25 g / min to 0.35 g / min (second pore forming agent flow rate), and from 15 cc / min to 12 cc / min (standard) Oxygen is allowed to flow while changing to (state), and high-frequency power is applied while changing from 1500 W to 400 W, for example. As a result, a first change region rb including a plurality of particles made of α-terpinene polymer is formed on the first region ra. At this time, the pore forming agent flow rate with respect to the precursor flow rate at time t2 is 0.25 / 0.3 (<1), and the pore forming agent flow rate with respect to the precursor flow rate at time t3 is 0. .35 / 0.2 (> 1), and the pore forming agent flow rate with respect to the precursor flow rate increases as time t2 elapses from time t2. For this reason, the plurality of particles included in the first change region rb increase in diameter from the lower surface side to the upper surface side. The second time is set according to the thickness of the first change region rb.

  Next, as shown in FIG. 8, DEMS is flowed at 0.2 g / min (second precursor flow rate) in the chamber from time t3 to time t4 (during the third time). Α terpinene is allowed to flow at 35 g / min (second pore forming agent flow rate), oxygen is allowed to flow at 12 cc / min, and high frequency power of 400 W is applied. As a result, a second region rc including a plurality of particles each having a second diameter and made of an α-terpinene polymer is formed on the first change region rb. At this time, the second pore forming agent flow rate with respect to the second precursor flow rate is 0.35 / 0.2, and the first pore forming agent flow rate with respect to the first precursor flow rate (0.25 / 0. Greater than 3). For this reason, the 2nd diameter of the particle | grains contained in 2nd area | region rc can be made larger than the 1st diameter of the particle | grains contained in 1st area | region ra. The third time is set according to the thickness of the second region rc.

  Next, as shown in FIG. 8, in the chamber, from time t4 to time t5 (during the fourth time), from 0.2 g / min to 0.3 g / min (third precursor flow rate), for example. While flowing DEMS, changing α terpinene from 0.35 g / min to 0.25 g / min (third pore-forming agent flow rate), and 12 cc / min to 15 cc / min (standard) Oxygen is allowed to flow while changing to (state), and high-frequency power is applied while changing from 400 W to, for example, 1500 W. Thereby, the second change region rd including a plurality of particles made of the α-terpinene polymer is formed on the second region rc. At this time, the pore forming agent flow rate with respect to the precursor flow rate at time t4 is 0.35 / 0.2 (> 1), and the pore forming agent flow rate with respect to the precursor flow rate at time t5 is 0. .25 / 0.3 (<1), and as the time t4 elapses from the time t4, the pore forming agent flow rate becomes smaller with respect to the precursor flow rate. For this reason, the plurality of particles included in the second change region rd have a diameter that decreases from the lower surface side toward the upper surface side. The fourth time is set according to the thickness of the second change region rd.

  Next, as shown in FIG. 8, DEMS is flowed at 0.3 g / min (third precursor flow rate) from time t5 to time t6 (during the fifth time) in the chamber. Α terpinene is allowed to flow at 25 g / min (third pore-forming agent flow rate), oxygen is allowed to flow at 15 cc / min, and 1500 W of high-frequency power is applied. As a result, a third region re having a plurality of particles each having a third diameter and made of α-terpinene polymer (or α-terpinene) is formed on the second change region rd. At this time, the third pore forming agent flow rate with respect to the third precursor flow rate is 0.25 / 0.3, and the second pore forming agent flow rate with respect to the second precursor flow rate (0.35 / 0. Smaller than 2). For this reason, the 3rd diameter of the particle | grains contained in 3rd area | region re can be made smaller than the 2nd diameter of the particle | grains contained in 2nd area | region rc. The fifth time is set according to the thickness of the third region re.

  In this way, as shown in FIG. 4B, the second region having the first region ra, the first change region rb, the second region rc, the second change region rd, and the third region re. The interlayer insulating film 16A is formed.

  Next, as shown in FIG. 4C, for example, the second interlayer insulating film 16A is irradiated with ultraviolet rays while the substrate 10 is heated. As a result, the plurality of particles contained in the second interlayer insulating film 16A are decomposed and removed to form the second interlayer insulating film 16 including a plurality of holes (not shown). At this time, the hole diameter of the holes included in each of the lower surface region and the upper surface region in the second interlayer insulating film 16 is smaller than the hole diameter of the holes included in the central region.

  Specifically, the substrate 10 is transferred into a vacuum chamber (not shown), and the substrate 10 is placed on a stage (not shown) heated to 400 ° C., for example. Thereafter, the second interlayer insulating film 16A is irradiated with, for example, ultraviolet rays of 200 to 400 nm. Thereby, the plurality of particles included in each of the first region ra, the first change region rb, the second region rc, the second change region rd, and the third region re are decomposed and removed. The second interlayer insulating film 16 having the first region Ra, the first change region Rb, the second region Rc, the second change region Rd, and the third region Re is formed. At this time, the hole diameter of the holes included in each of the first region Ra and the third region Re is, for example, about 1 nm or less. Moreover, the hole diameter of the hole contained in 2nd area | region Rc is about 1 nm or more, for example.

  Next, as shown in FIG. 5A, after applying a resist on the second interlayer insulating film 16, a resist pattern (not shown) having a via pattern is formed by lithography. Thereafter, for example, dry etching is performed on the second interlayer insulating film 16 using the resist pattern as a mask. As a result, a hole exposing the upper surface of the first insulating film 15 is formed under the second interlayer insulating film 16. Thereafter, the resist pattern is removed by ashing and cleaning. Then, after applying a resist on the second interlayer insulating film 16, a resist pattern (not shown) having a wiring pattern is formed by lithography. Thereafter, dry etching is performed on the second interlayer insulating film 16 using the resist pattern as a mask. As a result, a wiring groove 18 communicating with the hole formed in the lower portion of the second interlayer insulating film 16 is formed. Thereafter, the first insulating film 15 (first insulating film 15 on the first wiring 14) exposed in the hole is removed by, for example, dry etching, and the via hole 17 exposing the upper surface of the first wiring 14. Form.

  Next, as shown in FIG. 5B, for example, by sputtering, the top surface of the second interlayer insulating film 16, the bottom surface and wall surface of the via hole 17, and the bottom surface and wall surface of the wiring groove 18 are covered with, for example, TaN. A barrier metal film 19 made of is formed. Thereafter, a conductive film 20 made of, for example, Cu is formed on the barrier metal film 19 by, for example, electroplating so as to fill the via hole 17 and the wiring groove 18.

  Next, as shown in FIG. 5C, portions (excess conductive film 20 and barrier metal film 19) formed outside the wiring trench 18 in the conductive film 20 and barrier metal film 19 are sequentially formed by, for example, CMP. Remove. Thus, the first via 21 having the barrier metal film 19a and the conductive film 20a is formed, and the second wiring 22 having the barrier metal film 19b and the conductive film 20b is formed.

  Next, a step similar to the step shown in FIG. As a result, a second insulating film is formed on the second interlayer insulating film 16 so as to cover the second wiring 22. Thereafter, a third interlayer insulating film film including a plurality of particles made of a hole forming agent is formed on the second insulating film.

  Next, a step similar to the step shown in FIG. As a result, the plurality of particles contained in the third interlayer insulating film are decomposed and removed to form a third interlayer insulating film including a plurality of holes. At this time, the hole diameter of the hole included in each of the lower surface region and the upper surface region in the third interlayer insulating film is smaller than the hole diameter of the hole included in the central region.

  Next, a step similar to the step shown in FIG. Thereby, as shown in FIG. 6A, via holes are formed below the second insulating film 23 and the third interlayer insulating film 24, and via holes are formed above the third interlayer insulating film 24. A wiring groove that communicates is formed.

  Next, steps similar to those shown in FIGS. 5B to 5C are sequentially performed. Thereby, as shown in FIG. 6A, the second via 27 having the barrier metal film 25a and the conductive film 26a is formed in the via hole, and the barrier metal film 25b and the conductive film are formed in the wiring groove. And a third wiring 28 having 26b.

  Next, as shown in FIG. 6B, a first layer made of SiC, for example, is formed on the third interlayer insulating film 24 so as to cover the third wiring 28 by, eg, CVD, ALD, or SOD. 3 insulating film 29 is formed.

  Thereafter, a fourth interlayer insulating film 30A made of, for example, SiOC including a plurality of particles (not shown) made of a hole forming agent is formed on the third insulating film 29 by, eg, CVD.

  Specifically, the substrate 10 is transferred into a vacuum chamber, and the substrate 10 is placed on a stage heated to 250 ° C., for example. Then, in the chamber, DEMS is flowed at an arbitrary time, for example, 0.3 g / min, α-terpinene is flowed, for example, 0.25 g / min, oxygen is flowed, for example, 15 cc / min (standard state), for example, 1500 W Apply high frequency power. Thus, the fourth interlayer insulating film 30A including a plurality of particles made of α-terpinene polymer (or α-terpinene) is formed. At this time, the pore forming agent flow rate with respect to the precursor flow rate is kept constant during the time for flowing DEMS, α-terpinene, and oxygen. For this reason, each of the diameters of the plurality of particles included in the fourth interlayer insulating film 30A is substantially the same.

  Next, as shown in FIG. 7A, the fourth interlayer insulating film 30A is irradiated with, for example, ultraviolet rays while the substrate 10 is heated. As a result, the plurality of particles contained in the fourth interlayer insulating film 30A are decomposed and removed to form the fourth interlayer insulating film 30 including a plurality of holes (not shown). At this time, the hole diameters of the plurality of holes included in the fourth interlayer insulating film 30 are substantially the same.

  Specifically, the substrate 10 is transferred into a vacuum chamber (not shown), and the substrate 10 is placed on a stage (not shown) heated to 400 ° C., for example. Thereafter, the fourth interlayer insulating film 30A is irradiated with, for example, ultraviolet rays of 200 to 400 nm. Thus, the fourth interlayer insulating film 30 is formed by decomposing and removing the plurality of particles contained in the fourth interlayer insulating film 30A. At this time, the hole diameter of the holes included in the fourth interlayer insulating film 30 is, for example, about 1 nm or less.

  Next, a step similar to the step shown in FIG. As a result, as shown in FIG. 7B, via holes are formed below the third insulating film 29 and the fourth interlayer insulating film 30, and wiring trenches are formed above the fourth interlayer insulating film 30. Form.

  Next, steps similar to those shown in FIGS. 5B to 5C are sequentially performed. Thereby, as shown in FIG. 7B, the third via 33 having the barrier metal film 31a and the conductive film 32a is formed in the via hole, and the barrier metal film 31b and the conductive film 32b are formed in the wiring groove. The 4th wiring 34 which has is formed.

  Next, as shown in FIG. 7B, the first wiring made of SiC, for example, is formed on the fourth interlayer insulating film 30 so as to cover the fourth wiring 34 by, for example, CVD, ALD, or SOD. 4 insulating film 35 is formed.

  As described above, the semiconductor device according to this embodiment can be manufactured.

  According to the present embodiment, the second interlayer insulating film 16 is a film having a single layer structure, in other words, a single continuous film. That is, the second interlayer insulating film 16 is a continuous body formed by removing a plurality of particles contained in a continuous film (second interlayer insulating film 16A) formed continuously in the same chamber. There is no film interface in the second interlayer insulating film 16. For this reason, film peeling does not occur at the film interface. In addition, since a leak path is not formed at the film interface, no leak current is generated between the second wiring 22 and a wiring of a different potential adjacent to the second wiring 22 (not shown). . Accordingly, the reliability of the semiconductor device can be improved.

  In the second interlayer insulating film 16, the hole diameter of the holes included in the lower surface region is made smaller than the hole diameter of the holes included in the central region. Thereby, the contact area between the lower surface of the second interlayer insulating film 16 and the first insulating film 15 can be increased, so that the second interlayer insulating film 16 and the first insulating film 15 are in close contact with each other. Can be improved. Similarly, in the second interlayer insulating film 16, the hole diameter of the holes included in the upper surface region is made smaller than the hole diameter of the holes included in the central region. As a result, the contact area between the upper surface of the second interlayer insulating film 16 and the second insulating film 23 can be increased, so that the adhesion between the second interlayer insulating film 16 and the second insulating film 23 is increased. Can be improved.

  When the film thickness of the second interlayer insulating film 16 is t, in order to improve the adhesion between the second interlayer insulating film 16 and the first insulating film 15, a lower surface region (for example, the first region) The thickness of the region including Ra and the first change region Rb is preferably about 0.05 t or more. Similarly, in order to improve the adhesion between the second interlayer insulating film 16 and the second insulating film 23, the upper surface region (for example, the region including the second change region Rd and the third region Re) is improved. The thickness is preferably about 0.05 t or more. In addition, the upper limit of the thickness of the lower surface and the upper surface region is about 0.3 t. The reason is as follows. By setting the thickness to about 0.3 t, the adhesion can be sufficiently improved. In other words, no significant improvement in adhesion can be expected even if the thickness is greater than about 0.3 t.

  In the second interlayer insulating film 16, the hole diameter of the holes included in the central region (in other words, the region located within the range from the lower surface of the second wiring 22 to the center of the second wiring 22) is set to the lower surface. It is made larger than the hole diameter of the hole included in each of the region and the upper surface region. Thereby, the capacity | capacitance between wiring can be reduced.

  When the thickness of the second interlayer insulating film 16 is t, the thickness of the central region (for example, the second region Rc) is made thicker than about 0.4 t in order to reduce the inter-wiring capacitance. Is preferred.

  By the way, generally, when the porosity of a low dielectric constant film including pores is increased, the mechanical strength of the low dielectric constant film tends to be lowered. For this reason, when a low dielectric constant film containing pores is polished by, for example, a CMP method, there is a possibility that scratches (polishing scratches) may occur on the polished surface.

  Therefore, in the present embodiment, in the second interlayer insulating film 16, the hole diameter of the holes included in the upper surface region is made smaller than the hole diameter of the holes included in the central region. Thereby, the mechanical strength of the upper surface region can be improved more than the mechanical strength of the central region. For this reason, as shown in FIG. 5C, it is possible to suppress the occurrence of scratches on the upper surface (polished surface) when the second interlayer insulating film 16 is polished by the CMP method.

  In general, when the relative dielectric constant of the low dielectric constant film decreases, the polishing rate of the low dielectric constant film tends to increase. For this reason, when the low dielectric constant film is polished by the CMP method, the upper surface of the low dielectric constant film is positioned lower than the upper surface of the wiring formed in the low dielectric constant film due to erosion. There is a possibility that a step is generated between the film and the wiring. Here, “erosion” means that a portion that should not be polished is polished when the film is polished by the CMP method.

  Therefore, in the present embodiment, in the second interlayer insulating film 16, the hole diameter of the holes included in the upper surface region is made smaller than the hole diameter of the holes included in the central region. Thereby, the polishing rate of the upper surface region can be made lower than the polishing rate of the central region. For this reason, it is possible to suppress the occurrence of a step between the second interlayer insulating film 16 and the second wiring 22 due to erosion.

  The third interlayer insulating film 24 has the same structure as the second interlayer insulating film 16. Therefore, an effect similar to the above effect can be obtained.

  In this embodiment, the case where DEMS is used as the precursor and a porogen such as α-terpinene is used as the pore forming agent has been described as a specific example. However, the present invention is not limited to this.

  In the present embodiment, as shown in FIG. 8, the second, third and third flow rates are changed by changing the flow rates of the precursor, the hole forming agent and the oxidizing agent, and the power of the high frequency power according to the film formation time. The case where the interlayer insulating films 16 and 24 are formed is described as a specific example, but the present invention is not limited to this.

  First, for example, if the flow rate of at least one of the precursor and the hole forming agent is changed according to the film formation time, the hole diameters of the holes included in each of the lower surface region and the upper surface region are changed to the central region. It is possible to form the second and third interlayer insulating films smaller than the hole diameter of the included holes.

  Secondly, for example, by using several types of hole forming agents as the hole forming agent, and by changing the type of the hole forming agent flowing in the chamber according to the film formation time, the lower surface region and the upper surface region can be changed. You may form the 2nd, 3rd interlayer insulation film in which the hole diameter of the hole contained in each is smaller than the hole diameter of the hole contained in a center area | region.

  In this embodiment, the case where a plurality of particles contained in the second, third, and fourth interlayer insulating films are decomposed and removed by ultraviolet irradiation, for example, has been described as a specific example. It is not limited to this. For example, the plurality of particles contained in the second, third, and fourth interlayer insulating film may be decomposed and removed by electron beam irradiation or heat treatment.

  In the present embodiment, a plurality of particles contained in the second and third interlayer insulating films are decomposed and removed by ultraviolet irradiation, electron beam irradiation or heat treatment, and the second and third interlayer insulating films are formed. After the formation, the hole diameter of the holes included in the region near the upper surface in the second and third interlayer insulating films may be subsequently reduced by ultraviolet irradiation, electron beam irradiation, or heat treatment. Here, the region in the vicinity of the upper surface where the hole diameter is reduced by ultraviolet irradiation, electron beam irradiation, or heat treatment is, for example, a region in the vicinity of the upper surface of about 0.05 t to 0.3 t.

In the present embodiment, the case where the SiO 2 film is used as the first interlayer insulating film 11 has been described as a specific example. However, instead of this, a SiOC film, an FSG film, or a BSG film may be used. . Further, the case where the SiOC film is used as the second, third, and fourth interlayer insulating films 16, 24, and 30 has been described as a specific example. However, instead of this, a SiO 2 film, an FSG film, or a BSG film is used. May be used.

  In the present embodiment, the third interlayer insulating film 24 has a structure similar to that of the second interlayer insulating film 16 (the third interlayer insulating film 24 is formed in each of the lower surface region and the upper surface region. Although the case where the hole diameter of the included holes is a film smaller than the hole diameter of the holes included in the central region is described as a specific example, the present invention is not limited to this. First, for example, the third interlayer insulating film may have the same structure as the fourth interlayer insulating film 30 shown in FIG. Second, for example, the third interlayer insulating film may be a film that does not include holes.

  In the present embodiment, as shown in FIG. 2B, the fourth interlayer insulating film 30 has a plurality of holes each having substantially the same hole diameter and smaller than the second hole diameter. Although the case where it is the film | membrane containing was mentioned as a specific example and demonstrated, this invention is not limited to this. First, for example, the fourth interlayer insulating film may have a structure similar to that of the second interlayer insulating film 16 shown in FIG. Second, for example, the fourth interlayer insulating film may be a film that does not include holes.

  In general, the wiring layer close to the substrate has a short distance between adjacent wirings and a high wiring capacity. On the other hand, in the wiring layer far from the substrate, the distance between adjacent wirings is long and the capacitance between the wirings is low.

  The distance between the wirings included in the wiring layer close to the substrate 10 (second and third wiring layers including the second and third interlayer insulating films 16 and 24 and the second and third wirings 22 and 28) is For example, when the thickness is 100 nm or less, as shown in FIG. 2 (a), the hole diameters of the holes included in the central region of the second and third interlayer insulating films 16 and 24 are lower surface regions and upper surface regions. It is preferable to use a film that is larger than the pore diameter of the pores contained in each.

  On the other hand, if the distance between the wirings included in the wiring layer far from the substrate 10 (fourth wiring layer including the fourth interlayer insulating film 30 and the fourth wiring 34) is larger than 100 nm, for example, As the interlayer insulating film 30, as shown in FIG. 2B, a film having a plurality of holes each having substantially the same hole diameter and smaller than the second hole diameter may be used, or You may use the film | membrane which does not contain a void | hole.

  In the present embodiment, a semiconductor device having a four-layer multilayer wiring structure has been described as a specific example. However, the present invention is not limited to this, and for example, a multilayer wiring structure having five or more layers or three A semiconductor device having a multilayer wiring structure with no more than one layer may be used.

  In the present embodiment, the case where TaN is used as the material of the barrier metal films 12, 19a, 19b, 25a, 25b, 31a, 31b has been described as a specific example. However, the present invention is limited to this. Instead, for example, tantalum (Ta), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), or ruthenium nitride (RuN) may be used instead of TaN.

  In the present embodiment, the case where Cu is used as the material of the conductive films 13, 20a, 20b, 26a, 26b, 32a, and 32b has been described as a specific example. However, the present invention is not limited to this. Absent.

  In general, when Cu having a resistivity lower than that of aluminum (Al) is used, it is difficult to form a wiring by patterning a conductive film (Cu film) made of Cu by dry etching. For this reason, a damascene method is generally applied in which a wiring groove is formed, a Cu film is embedded in the wiring groove, and an extra Cu film is removed by CMP to form a wiring. In particular, as in this embodiment, a dual damascene method is used in which a via hole and a wiring groove are formed, a Cu film is embedded in the via hole and the wiring groove, and an excess Cu film is removed by CMP to form a via and a wiring. By doing so, the number of steps can be reduced.

  As described above, according to the present invention, since there is no film interface in the interlayer insulating film, it is possible to suppress the occurrence of film peeling and the formation of a leak path. For this reason, it is useful for the semiconductor device provided with the interlayer insulation film, and its manufacturing method.

10 substrate 11 first interlayer insulating film 12 barrier metal film 13 conductive film 14 first wiring 15 first insulating film 16A second interlayer insulating film 16 second interlayer insulating film 17 via hole 18 wiring groove 19, 19a, 19b Barrier metal films 20, 20a, 20b Conductive film 21 First via 22 First wiring 23 Second insulating film 24 Third interlayer insulating film 25a, 25b Barrier metal films 26a, 26b Conductive film 27 Second Via 28 Third wiring 29 Third insulating film 30A Fourth interlayer insulating film 30 Fourth interlayer insulating films 31a and 31b Barrier metal films 32a and 32b Conductive film 33 Third via 34 Fourth wiring 35 4th insulating film Ra, ra 1st area | region Rb, rb 1st change area | region Rc, rc 2nd area | region Rd, rd 2nd change area | region Re, re 3rd area | region Ha, Hb, Hc, Hd , H , H vacancies

Claims (19)

  1. An interlayer insulating film including a plurality of holes is provided,
    The interlayer insulating film is a film having a single layer structure,
    In the interlayer insulating film, the hole diameter of the hole included in the lower surface region and the hole diameter of the hole included in the upper surface region are included in the central region interposed between the upper surface region and the lower surface region. A semiconductor device characterized by being smaller than a hole diameter of a hole.
  2.   2. The semiconductor device according to claim 1, wherein each of the plurality of holes has a hole diameter that decreases from the center toward the lower surface, while the hole diameter decreases from the center toward the upper surface.
  3. When the thickness of the interlayer insulating film is t,
    The thickness of the upper surface region is 0.05 t or more and 0.3 t or less,
    The semiconductor device according to claim 1, wherein a thickness of the lower surface region is 0.05 t or more and 0.3 t or less.
  4. The interlayer insulating film is
    A first region that is located on the lower surface side and includes a plurality of the holes each having a first hole diameter;
    A second region including a plurality of the holes located in the center and each having a second hole diameter larger than the first hole diameter;
    A third region including a plurality of the holes located on the upper surface side, each having a third hole diameter smaller than the second hole diameter;
    A first change region including a plurality of the pores interposed between the first region and the second region and having a pore diameter that increases from the lower surface side toward the upper surface side;
    A second change region that includes a plurality of the voids interposed between the second region and the third region and having a pore diameter that decreases from the lower surface side toward the upper surface side;
    The hole diameters of the plurality of holes included in the first change region are larger than the first hole diameter and smaller than the second hole diameter,
    The hole diameters of the plurality of holes included in the second change region are larger than the third hole diameter and smaller than the second hole diameter,
    The lower surface region in the interlayer insulating film includes the first region and the first change region,
    The central region in the interlayer insulating film includes the second region,
    The semiconductor device according to claim 1, wherein the upper surface region in the interlayer insulating film includes the second change region and the third region.
  5. Vias formed under the interlayer insulating film;
    The semiconductor device according to claim 1, further comprising a wiring formed on the interlayer insulating film and connected to the via.
  6.   The hole diameter of the hole located near the lower part of the wiring is larger than the hole diameter of the hole located near the upper part of the wiring and the hole diameter of the hole located near the lower part of the via. 6. The semiconductor device according to claim 5, wherein:
  7. A first insulating film formed under the interlayer insulating film;
    The semiconductor device according to claim 1, further comprising a second insulating film formed on the interlayer insulating film.
  8. The interlayer insulating film is a first interlayer insulating film,
    A second interlayer insulating film formed on the first interlayer insulating film and including a plurality of holes;
    In the first interlayer insulating film, the hole diameter of the hole included in the central region is x, the hole diameter of the hole included in the upper surface region is y,
    In the second interlayer insulating film, the hole diameter of the hole included in the central region interposed between the lower surface region and the upper surface region is v, and the hole diameter of the hole included in the upper surface region is w. if you did this,
    The semiconductor device according to claim 1, wherein a rate of change x / y of x with respect to y is greater than a rate of change of v with respect to w, v / w.
  9. The interlayer insulating film is a first interlayer insulating film,
    A second interlayer insulating film formed on the first interlayer insulating film and including a plurality of holes;
    In the second interlayer insulating film, the hole diameter of the hole included in the central region interposed between the lower surface region and the upper surface region is equal to the hole included in the upper surface region of the second interlayer insulating film. Is substantially the same as the hole diameter of
    The hole diameter of the hole included in the central region of the second interlayer insulating film is smaller than the hole diameter of the hole included in the central region of the first interlayer insulating film. The semiconductor device according to claim 1.
  10. The semiconductor device according to claim 1, wherein the interlayer insulating film is a SiO 2 film, a SiOC film, an FSG film, or a BSG film.
  11.   The semiconductor device according to claim 5, wherein a distance between the wirings is 100 nm or less.
  12. Comprising a step of forming an interlayer insulating film including a plurality of holes,
    The interlayer insulating film is a film having a single layer structure,
    The step of forming the interlayer insulating film includes a central region in which the hole diameter of the hole included in the lower surface region and the hole diameter of the hole included in the upper surface region are interposed between the lower surface region and the upper surface region. A method for manufacturing a semiconductor device, comprising the step of forming the interlayer insulating film so as to be smaller than a hole diameter of the holes included in the substrate.
  13.   In the step of forming the interlayer insulating film, the plurality of holes have a hole diameter that decreases from the center toward the lower surface, while a hole diameter decreases from the center toward the upper surface. A method for manufacturing a semiconductor device according to claim 12.
  14. The step of forming the interlayer insulating film includes:
    A step (a) of forming a film for an interlayer insulating film containing a plurality of particles made of a pore forming agent by chemical vapor deposition;
    14. The method of manufacturing a semiconductor device according to claim 12, further comprising a step (b) of forming the interlayer insulating film by removing the plurality of particles contained in the interlayer insulating film. .
  15.   15. The process for manufacturing a semiconductor device according to claim 14, wherein in the step (a), the flow rate of the precursor that forms the skeleton of the interlayer insulating film and the pore forming agent is adjusted according to the film formation time. Method.
  16.   15. The method of manufacturing a semiconductor device according to claim 14, wherein, in the step (a), the diameter of the particles made of the pore forming agent is adjusted according to the film formation time.
  17.   The step (b) is a step of removing the plurality of particles contained in the interlayer insulating film by heat treatment, electron beam irradiation or ultraviolet irradiation. 2. A method for manufacturing a semiconductor device according to item 1.
  18. The step of forming the interlayer insulating film includes:
    After the step (b), the method further includes a step (c) of reducing the hole diameter of the holes included in the region near the upper surface of the interlayer insulating film by heat treatment, electron beam irradiation or ultraviolet irradiation. The manufacturing method of the semiconductor device of any one of 14-17.
  19. The step (a)
    In the chamber, a first region is formed by flowing the precursor at a first precursor flow rate and flowing the pore-forming agent at a first pore-former flow rate for a first time in the chamber ( a1)
    In the chamber, during the second time, the precursor flows while changing from the first precursor flow rate to the second precursor flow rate, and the second hole formation from the first pore forming agent flow rate. A step (a2) of forming a first change region on the first region by flowing the pore-forming agent while changing the agent flow rate;
    In the chamber, during the third time, the precursor flows at the second precursor flow rate, and the hole forming agent flows at the second pore formation agent flow rate, so that the first change region A step (a3) of forming a second region on the substrate;
    In the chamber, during the fourth time, the precursor flows while changing from the second precursor flow rate to the third precursor flow rate, and the third hole formation from the second pore forming agent flow rate. Flowing the pore-forming agent while changing the agent flow rate to form a second change region on the second region (a4);
    In the chamber, during the fifth time, the precursor flows at the third precursor flow rate, and the hole forming agent flows at the third pore formation agent flow rate, so that the second change region And (a5) forming a third region on the substrate,
    In the step (a5), the interlayer insulating film having the first region, the first change region, the second region, the second change region, and the third region is formed,
    The first pore forming agent flow rate with respect to the first precursor flow rate is smaller than the second pore forming agent flow rate with respect to the second precursor flow rate,
    16. The semiconductor device according to claim 15, wherein the third hole forming agent flow rate with respect to the third precursor flow rate is smaller than the second hole forming agent flow rate with respect to the second precursor flow rate. Manufacturing method.
JP2009265436A 2009-11-20 2009-11-20 Semiconductor device, and method for manufacturing the same Pending JP2011109036A (en)

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JP2001351916A (en) * 2000-06-07 2001-12-21 Matsushita Electric Ind Co Ltd Method of forming silicon oxide film
JP2003273216A (en) * 2002-03-18 2003-09-26 Sony Corp Semiconductor device and its manufacturing method
JP4493278B2 (en) * 2003-02-20 2010-06-30 富士通株式会社 Porous resin insulation film, electronic device, and method for manufacturing the same
JP2006223931A (en) * 2005-02-15 2006-08-31 Soken Chem & Eng Co Ltd Two-dimensional particle aligned member, two-dimensional void aligned porous member and manufacturing method of them
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US9355955B2 (en) 2012-06-21 2016-05-31 Renesas Electronics Corporation Semiconductor device
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