JP2011108828A - Ferroelectric memory, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric memory that achieves low-temperature heat treatment in a manufacturing process while preventing degradation of memory characteristics due to shortage of heat treatment of baking densification to crystallize a ferroelectric film, especially degradation of residual polarization characteristics of the ferroelectric film. <P>SOLUTION: The ferroelectric memory includes a ferroelectric capacitor on which a lower electrode 10, capacitance insulation film 12 composed of the ferroelectric film with a perovskite-type crystal structure, and an upper electrode 13 are formed to be laminated in this order on a p-type semiconductor substrate 1. Furthermore, the memory includes a convex lens 14 that is formed on the upper electrode 13 to selectively heat the ferroelectric film by concentrating light. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a ferroelectric memory device and a method for manufacturing the same. In particular, in a ferroelectric memory device in which a ferroelectric memory portion and a logic circuit portion are mixedly mounted, good ferroelectric electric characteristics can be obtained even when the temperature required for crystallization of the ferroelectric thin film is lowered. The present invention relates to a ferroelectric memory device that can be manufactured and a method of manufacturing the same.

  2. Description of the Related Art In recent years, a social infrastructure environment that provides an electronic service that can authenticate an individual using a driver's license or a passport embedded with a semiconductor chip has been established. IC cards and embedded chips that realize these applications are required to be downsized and have high security. The mounted nonvolatile semiconductor memory includes a memory circuit and a logic circuit that processes complex encryption at high speed. It is necessary to load them together. In recent years, ferroelectric memory devices have attracted attention as this nonvolatile semiconductor memory.

  A ferroelectric memory device is a non-volatile memory device capable of high-speed rewriting utilizing high-speed polarization reversal and remanent polarization of a ferroelectric thin film. Among ferroelectric memory devices, FeRAM (Ferroelectric random access memory) is particularly promising as a semiconductor memory device that consumes less power and can be operated at high speed. On the other hand, as described above, in order to mount a logic circuit that processes a complicated cipher at high speed, the circuit scale of the transistor inevitably increases. As one of the solutions, there is a general measure to reduce the size and speed of the IC circuit by changing the process, that is, by reducing the transistor dimensions. For this reason, while realizing low power consumption and high-speed operation, technological development for improving cost competitiveness by reducing the chip size by advancing the miniaturization of the transistor circuit of the FeRAM embedded IC has been actively performed.

  However, with the miniaturization of the transistor dimensions, it is necessary to avoid the heat treatment after the transistor formation as much as possible, so that the heat treatment process needs to be lowered. This is because the electrical characteristics of the transistor shift due to the high-temperature heat treatment after the transistor is formed, or a malfunction due to disconnection occurs at the PN boundary of the thin line portion.

  According to a conventional example of a method for manufacturing a field transistor having a fine source / drain structure (see, for example, Patent Document 1), an insulated gate field effect transistor constituting an ultra-high density integrated circuit device, particularly a MOS (Metal Oxide Semiconductor). The miniaturization of the field effect transistor is progressing based on the scaling law (see paragraph [0002] of the same document), and optimization of the lateral extension of the low concentration region in the diffusion layer for the source and drain is important. (See paragraph [0023] of the same document). In addition, by selectively melting and recrystallizing an amorphous layer formed during ion implantation for forming diffusion layers for source and drain by laser light irradiation, diffusion for shallow junction source and drain In order to reduce the resistance of the layer, in order to prevent the occurrence of defects such as a short circuit at the overlapping portion of the molten region and the gate electrode, the ion implantation is performed after the gate sidewall insulating film is formed on the side surface of the gate electrode. By doing so, it is disclosed to realize a structure in which the amorphous layer does not overlap with the gate electrode (see FIG. 7 of the same reference and the corresponding explanation part). In this way, selective melting and recrystallization of the amorphous layer can be realized without causing the short-circuit failure, and the lateral extension of the low concentration region in the diffusion layer for the source and drain can be suppressed and good. Transistor characteristics.

  On the other hand, according to a conventional example of a semiconductor device including a capacitor having an oxide dielectric film having a perovskite crystal structure using PZT as a ferroelectric material and a method for manufacturing the same (see, for example, Patent Document 2), the ferroelectric film It is disclosed that a ferroelectric film needs to be baked in order to extract the characteristics as described above. This is because, when a perovskite oxide dielectric is simply formed, the oxide dielectric may be in an amorphous phase, insufficiently crystallized, or may be deficient in oxygen. Therefore, it cannot be used as a useful oxide dielectric, and it is necessary to perform high-temperature heat treatment in an oxidizing atmosphere after film formation.

Specifically, a lower electrode made of a laminated film of a titanium layer and a platinum layer, a dielectric film made of PZT, and an upper electrode made of platinum are formed on the oxygen shielding insulating film by sputtering. The dielectric film made of PZT is in an amorphous phase and does not have polarization characteristics as it is deposited. Therefore, heat treatment is performed in an oxygen atmosphere after depositing the dielectric film from PZT and before or after depositing the upper electrode. Specifically, this heat treatment is a high-temperature heat treatment at 850 ° C. for about 5 seconds in an oxygen atmosphere of 1 atm using a rapid thermal heat treatment (RTA) apparatus. It is disclosed that high temperature heat treatment may be performed at 800 ° C. or higher for 10 minutes or longer (for example, about 30 minutes) using a resistance furnace instead of RTA. By such high-temperature heat treatment in an oxygen atmosphere, the dielectric film made of PZT is polycrystallized, and exhibits a residual polarizability of, for example, about 30 μC / cm ² .

  As described above, in order to bring out the characteristics as a ferroelectric film, a ferroelectric baking process is necessary. However, it is difficult to sufficiently bake the ferroelectric film at a low temperature, The remanent polarization characteristic of the film is deteriorated.

JP 2003-229568 A Japanese Patent Laid-Open No. 11-054716

  As described above, in order to ensure the characteristics of an insulated gate field effect transistor, particularly a MOS field effect transistor, low temperature heat treatment in the manufacturing process is required, while in order to ensure the residual polarization characteristics of the ferroelectric film. Requires a high-temperature heat treatment of the manufacturing process. Such incompatible requirements are a major problem in the progress of miniaturization of transistor circuits of FeRAM-embedded ICs.

  In view of the above, an object of the present invention is to prevent a deterioration in memory characteristics due to insufficient heat treatment due to baking for crystallization of a ferroelectric film, particularly in a manufacturing process while preventing a decrease in residual polarization characteristics of the ferroelectric film. It is an object of the present invention to provide a ferroelectric memory device that can realize low-temperature heat treatment and a method for manufacturing the same.

  In order to achieve the above object, a ferroelectric capacitor is formed by laminating a lower electrode, a ferroelectric film having a perovskite crystal structure, and an upper electrode in this order on a semiconductor substrate. A convex lens that is formed on the surface and selectively heats the ferroelectric film by condensing is further provided.

  In the ferroelectric memory device according to one aspect of the present invention, the convex lens may be in direct contact with the upper electrode.

  In the ferroelectric memory device according to one aspect of the present invention, the convex lens may be made of a high refractive index material having a refractive index of 1.46 or more.

  In the ferroelectric memory device according to one aspect of the present invention, the convex lens may be formed of a silicon nitride film, a silicon oxynitride film, or a silicon oxide film.

  The ferroelectric memory device according to one aspect of the present invention includes a plurality of ferroelectric capacitors, and a surface of an interlayer insulating film that fills between the adjacent ferroelectric capacitors is formed on the adjacent ferroelectric capacitors. It may be formed in a concave surface shape so as to be continuous with the convex surface shape of the formed convex lens.

  In this case, the semiconductor substrate may further include a hydrogen barrier film formed so as to continuously cover the ferroelectric capacitors adjacent to each other and the interlayer insulating film filling the space between the adjacent ferroelectric capacitors. Good.

  According to one aspect of the present invention, a ferroelectric memory device manufacturing method forms a ferroelectric capacitor by laminating a lower electrode, a ferroelectric film having a perovskite crystal structure, and an upper electrode in this order on a semiconductor substrate. After the step (a), the step (b) of forming a convex lens on the upper electrode, and the step (b), a step of performing a heat treatment for crystallizing the ferroelectric film using a rapid thermal annealing method ( c), and the step (c) includes a step of selectively heating the ferroelectric film by condensing the light used in the rapid thermal annealing method onto the ferroelectric film using a convex lens. Including.

  In the method for manufacturing a ferroelectric memory device according to one aspect of the present invention, the step (b) may include a step of forming a convex lens so as to be in direct contact with the upper electrode.

  The method for manufacturing a ferroelectric memory device according to one aspect of the present invention further includes, before the step (c), a step (d) of forming a transistor constituting the logic circuit portion on the semiconductor substrate, the step (c) ) May include a step of performing heat treatment so as not to substantially change the effective channel length of the transistor.

  In the method of manufacturing a ferroelectric memory device according to one aspect of the present invention, the step (a) includes a step of forming a plurality of ferroelectric capacitors on a semiconductor substrate, and a plurality of ferroelectric capacitors are formed before the step (b). A step (e) of forming an interlayer insulating film filling the space between the ferroelectric capacitors, wherein the step (b) includes forming the surface of the interlayer insulating film filling the space between the adjacent ferroelectric capacitors with the adjacent ferroelectric materials; A step of forming a concave surface shape so as to be continuous with the convex surface shape of the convex lens formed on the capacitor may be included.

  In this case, after the step (c), a step (f) of forming a hydrogen barrier film so as to continuously cover the ferroelectric capacitors adjacent to each other and the interlayer insulating film filling the space between the adjacent ferroelectric capacitors. May be further provided.

  In the method for manufacturing a ferroelectric memory device according to one aspect of the present invention, the convex lens may be made of a high refractive index material having a refractive index of 1.46 or more.

  In the method for manufacturing a ferroelectric memory device according to one aspect of the present invention, the convex lens may be formed of a silicon nitride film, a silicon oxynitride film, or a silicon oxide film.

  According to the ferroelectric memory device and the manufacturing method thereof according to one aspect of the present invention, the convex lens is formed on the upper electrode constituting the ferroelectric capacitor. For this reason, the ferroelectric film is selectively and efficiently heated by the light condensing effect of the convex lens. Therefore, the heat treatment for crystallization of the ferroelectric film in the ferroelectric memory portion is a high temperature heat treatment as compared with the transistor in the logic circuit portion. As a result, excellent ferroelectric electric characteristics can be obtained while maintaining the characteristics of the miniaturized transistor in the logic circuit portion.

FIG. 1 is a cross-sectional view showing the structure of a ferroelectric memory device according to an embodiment of the present invention. 2A to 2C are cross-sectional views showing a method of manufacturing a ferroelectric memory device according to one embodiment of the present invention in the order of steps. 3A and 3B are cross-sectional views showing a method of manufacturing a ferroelectric memory device according to one embodiment of the present invention in the order of steps. FIG. 4 is a cross-sectional view schematically showing a rapid thermal heat treatment apparatus used in the method for manufacturing a ferroelectric memory device according to one embodiment of the present invention. FIG. 5A shows a target effective channel length (Lg-efl) and an actual effective channel length (Lg-eff) of the transistor structure of the logic circuit portion in the ferroelectric memory device according to the embodiment of the present invention. FIG. 5B is a graph showing the dependency of the threshold voltage (V _T ) on the heat treatment temperature (° C.). FIG. 6 is a graph showing the polarization amount of the ferroelectric capacitor in the ferroelectric memory device according to the embodiment of the present invention. FIG. 7A is a cross-sectional view showing the shape between adjacent ferroelectric capacitors in the ferroelectric memory device according to one embodiment of the present invention, and FIG. 7B shows a conventional ferroelectric memory. It is sectional drawing which shows the shape between the adjacent ferroelectric capacitors in an apparatus.

  The technical idea of the present invention will be clearly described below with reference to the drawings and detailed description. Any person skilled in the art will understand the present invention after understanding the preferred embodiments of the present invention. Modifications and additions can be made according to the disclosed technology, which does not depart from the technical idea and scope of the present invention.

(One embodiment)
FIG. 1 shows the structure of a ferroelectric memory device according to an embodiment of the present invention. FIG. 1 shows a ferroelectric memory unit 1A and a logic circuit unit 1B in the ferroelectric memory device.

  As shown in FIG. 1, on the main surface of a p-type semiconductor substrate 1 made of, for example, silicon (Si), a plurality of element formation regions partitioned by an element isolation region 2 made of, for example, STI (Shallow Trench Isolation) are formed. In FIG. 1, the element isolation region 2 partitions the ferroelectric memory portion 1A and the logic circuit portion 1B. In the ferroelectric memory portion 1A and the logic circuit portion 1B, a gate insulating film 4a made of, for example, silicon oxide is interposed on the active region 3 in the p-type semiconductor substrate 1 to form a polycrystal having a thickness of about 150 to 250 nm, for example. A gate electrode 4b made of silicon and having a gate width of 180 nm is formed. A side wall 4c made of, for example, a silicon nitride film is formed on the side surface of the gate electrode 4b. A shallow source / drain region 5a is formed in a region lateral to the gate electrode 4b in the p-type semiconductor substrate 1, and a deep source / drain region 6a is formed in a region outside the sidewall 4c in the p-type semiconductor substrate 1. Is formed. The source / drain region is composed of a shallow source / drain region 5a and a deep source / drain region 6a. An interlayer insulating film 7 having a thickness of 500 nm made of, for example, a BPSG (Boron-Phospho Silicate Glass) film is formed on the entire surface of the p-type semiconductor substrate 1 so as to cover the gate electrode 4b and the sidewall 4c. . In the interlayer insulating film 7, a contact plug 9a (plug diameter: 150 to 300 nm) made of, for example, tungsten (W), which is electrically connected to the source / drain region is formed.

Further, on the interlayer insulating film 7 in the ferroelectric memory unit 1A, for example, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film (alumina), a titanium oxide aluminum film, a tantalum aluminum oxide film, a titanium oxide silicon film, And a lower hydrogen barrier film 8 having a thickness of 100 nm made of any one material or a plurality of materials selected from the group of tantalum silicon oxide film and the like. In the lower hydrogen barrier film 8 and the interlayer insulating film 7, a contact plug 9b (plug diameter: 150 to 300 nm) made of, for example, tungsten is formed so as to penetrate these and electrically connect to the source / drain region. On the lower hydrogen barrier film 8, a lower electrode 10 having a film thickness of 50 nm made of, for example, platinum, whose lower surface is connected to the contact plug 9b is formed. The lower electrode 10 is preferably an oxygen shielding insulating film, for example, a film having a laminated structure with an iridium or iridium oxide film. On the lower hydrogen barrier film 8 and on the side surface of the lower electrode 10, a spacer insulating film 11 made of, for example, a BPSG film and having a thickness of 500 nm is formed. A lead-based perovskite such as PbTiO ₃ , Pb (Zr ₂ Ti _1-x ) O ₃ or Pb _y La _1-y (Zr _x Ti _1-x ) O ₃ is formed on the lower electrode 10 and the spacer insulating film 11. Type composite oxides, barium-based perovskite type complex oxides such as Ba _x Sr _1-x TiO ₃ , or ferroelectrics composed of bismuth-based layered complex compounds such as SrBi ₂ Ta ₂ O ₉ or Bi ₄ Ti ₃ O ₁₂ A capacitive insulating film 12 having a thickness of 100 nm constituting the film is formed. On the capacitor insulating film 12, an upper electrode 13 made of, for example, platinum and having a film thickness of 50 nm is formed. The lower electrode 10, the capacitive insulating film 12, and the upper electrode 13 constitute a ferroelectric capacitor.

  A convex lens 14 is formed on the upper electrode 13 constituting the ferroelectric capacitor, and the convex lens 14 is preferably made of a high refractive index material having a refractive index of 1.46 or more. Specifically, it is represented by a silicon nitride film (refractive index 2.0 to 2.2), a silicon oxynitride film (refractive index 1.6 to 1.8), a silicon oxide film (refractive index 1.46), or the like. It is preferable to use a material having a high refractive index and having a high affinity with a semiconductor process and being easy to dry-etch. The film thickness of the convex lens 14 is 300 nm to 700 nm at the thickest part of the convex shape. The convex lens 14 is preferably formed so as to be in direct contact with the upper electrode 13. On the lower hydrogen barrier film 8, for example, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film (alumina), a titanium oxide aluminum so as to cover the spacer insulating film 11, the ferroelectric capacitor, and the convex lens 14. An upper hydrogen barrier film 15 having a film thickness of about 10 to 100 nm made of any one material or a plurality of materials selected from the group consisting of a film, a tantalum aluminum oxide film, a titanium oxide silicon film, and a tantalum silicon oxide film is formed. ing. Thus, the periphery of the ferroelectric capacitor is completely covered with the lower hydrogen barrier film 8 and the upper hydrogen barrier film 15 connected to each other. Although the film thickness of the upper hydrogen barrier film 15 will be described in detail with reference to FIG. 6 described later, high hydrogen barrier performance is realized even if it is several nm.

  In the ferroelectric memory unit 1A and the logic circuit unit 1B, an interlayer having a film thickness of 2000 nm made of, for example, a BPSG film is formed on the interlayer insulating film 7 so as to cover the lower hydrogen barrier film 8 and the upper hydrogen barrier film 15. An insulating film 16 is formed. In the ferroelectric memory portion 1A, the interlayer insulating film 16 is connected to the contact plug 9a through the interlayer insulating film 16 and electrically connected to the source / drain region of the memory transistor of the ferroelectric memory portion 1A. For example, contact plugs 17 (plug diameter 150 to 300 nm) made of tungsten are formed. In the logic circuit portion 1B, the contact plug 17 (plug diameter 150) made of, for example, tungsten is connected to the contact plug 9a through the interlayer insulating film 16 and electrically connected to the source / drain region of the transistor of the logic circuit portion 1B. ~ 300 nm) is formed. On the interlayer insulating film 16, a bonding pad 19 made of, for example, aluminum or copper and connected to the contact plug 17 in the ferroelectric memory portion 1A and having a film thickness of about 400 nm and a width of 70 μm or more is formed on the interlayer insulating film 16. A wiring layer 18 having a thickness of about 400 nm and a width of 250 nm or more connected to the contact plug 17 in the portion 1B is formed. On the interlayer insulating film 16, an 800 nm-thick interlayer insulating film 20 made of, for example, a BPSG film is formed so as to cover the wiring layer 18 and the bonding pad 19.

  The ferroelectric memory device according to this embodiment having the above-described structure includes a convex lens 14 on the ferroelectric capacitor in the ferroelectric memory unit 1A. As a result, as described in detail in the manufacturing method of the ferroelectric memory device below, even if the convex lens 14 is formed and then heat treatment is performed at a temperature lower than that of the prior art using the rapid thermal heat treatment method, the convex type Since the focusing effect of the lens 14 allows only the ferroelectric capacitor region to be selectively and efficiently baked and crystallized, the capacitor insulation made of a ferroelectric film having sufficient remanent polarization in the ferroelectric memory portion 1A. The film 12 can be formed. As a result, it is possible to improve that the ferroelectric memory characteristics cannot be sufficiently obtained due to insufficient heat treatment during crystallization of the ferroelectric film. On the other hand, in the logic circuit portion 1B, only the low-temperature heat treatment is performed in the baking process as compared with the prior art, so that the low-temperature heat treatment of the manufacturing process required for securing the transistor characteristics is satisfied. Can do. As a result, the characteristics of the miniaturized transistor can be maintained.

  Next, a method for manufacturing a ferroelectric memory device according to an embodiment of the present invention will be described.

  2A to 2C and FIGS. 3A and 3B show a method of manufacturing a ferroelectric memory device according to an embodiment of the present invention in the order of steps. 2 and 3, the ferroelectric memory unit 1A and the logic circuit unit 1B in the ferroelectric memory device are shown.

  First, as shown in FIG. 2A, for example, by selectively forming the element isolation region 2 on the main surface of the p-type semiconductor substrate 1 by, for example, the STI method, the main surface of the p-type semiconductor substrate 1 is formed. In the figure, the device is divided into a plurality of element formation regions, and in the figure, the element isolation region 2 is divided into a ferroelectric memory portion 1A and a logic circuit portion 1B. Subsequently, a gate insulating film formation film made of, for example, silicon oxide and a gate electrode formation film made of, for example, polysilicon having a film thickness of about 150 to 250 nm are sequentially deposited on the entire surface of the p-type semiconductor substrate 1, and then photolithography and drying are performed. By selectively etching using an etching method, the gate insulating film 4a and the gate electrode 4b having a gate width of 180 nm are formed. Subsequently, by performing desired ion implantation using the gate electrode 4b as a mask, a shallow source / drain region 5a is formed in a region below the side of the gate electrode 4b in the p-type semiconductor substrate 1. Subsequently, a silicon nitride film having a film thickness of 120 nm, for example, is deposited on the entire surface of the p-type semiconductor substrate 1 by a chemical vapor deposition (CVD) method or the like, and then the deposited silicon nitride film is different from the deposited silicon nitride film. Isotropic etching is performed to form sidewalls 4c on the side surfaces of the gate electrode 4b and the gate insulating film 4a. Subsequently, a deep source / drain region 6 a is formed in a region outside the sidewall 4 c in the p-type semiconductor substrate 1. The source / drain region is constituted by a shallow source / drain region 5a and a deep source / drain region 6a.

  Subsequently, an interlayer insulating film 7 made of, for example, a BPSG film or the like is deposited on the entire surface of the p-type semiconductor substrate 1 by a CVD method so as to cover the gate electrode 4b and the sidewall 4c. The surface of 7 is flattened by a chemical mechanical polishing (CMP) method. Subsequently, after a contact hole exposing the source / drain region is formed in the interlayer insulating film 7 by lithography and dry etching, the lower end is formed by using a CVD method and an etch back method, or a combination of the CVD method and the CMP method. A contact plug 9a (plug diameter: 150 to 350 nm) made of, for example, tungsten connected to the source / drain region is formed.

  Subsequently, on the interlayer insulating film 7 in the ferroelectric memory unit 1A, for example, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film (alumina), a titanium oxide aluminum film, for example, by a CVD method, a lithography method, and a dry etching method. A lower hydrogen barrier film 8 having a thickness of 150 nm is selectively formed of any one material or a plurality of materials selected from the group consisting of a film, a tantalum aluminum oxide film, a titanium oxide silicon film, and a tantalum silicon oxide film. .

  Subsequently, a contact hole that opens the source / drain region is formed in the lower hydrogen barrier film 8 and the interlayer insulating film 7 by a lithography method and a dry etching method, and then a CVD method and an etch back method, or a CVD method and a CMP method are used. Using the combination, a contact plug 9b (plug diameter: 150 to 350 nm) made of, for example, tungsten, whose lower end is connected to the source / drain region is formed.

  Subsequently, the lower electrode 10 having a thickness of 50 nm and made of platinum or the like whose lower surface is connected to the upper end of the contact plug 9b is formed on the lower hydrogen barrier film 8 by sputtering or CVD. The lower electrode 10 is preferably an oxygen shielding insulating film, for example, a film having a laminated structure with an iridium or iridium oxide film. Subsequently, an interlayer insulating film made of, for example, a BPSG film having a thickness of 500 nm is deposited on the interlayer insulating film 7 and the lower hydrogen barrier film 8 by the CVD method so as to cover the lower electrode 10. The spacer insulating film 11 is formed on the lower hydrogen barrier film 8 and on the side surface of the lower electrode 10 by polishing the surface of the lower electrode 10 until the surface of the lower electrode 10 is exposed.

Subsequently, for example, PbTiO ₃ , Pb (Zr ₂ Ti _1-x ) is formed on the entire surface of the p-type semiconductor substrate 1 by an organic metal decomposition (MOD) method, a metal organic chemical vapor deposition (MOCVD) method, or a sputtering method. Lead-based perovskite complex oxides such as O ₃ or Pb _y La _1-y (Zr _x Ti _1-x ) O ₃ , barium-based perovskite complex oxides such as Ba _x Sr _1-x TiO ₃ , or SrBi consists ₂ Ta ₂ O ₉ or _Bi 4 _Ti 3 _O bismuth-based layered composite compounds such as _12, to form a capacitor insulating film forming film having a thickness of 100 to 200 nm. Subsequently, an upper electrode forming film made of, for example, Pt and having a thickness of 50 to 200 nm is formed on the capacitor insulating film forming film by sputtering. Subsequently, the upper electrode forming film and the capacitor insulating film forming film are patterned by lithography and dry etching to form the upper electrode 13 from the upper electrode forming film, and the capacitor insulating film 12 from the capacitor insulating film forming film. Form. In this way, a ferroelectric capacitor including the lower electrode 10, the capacitor insulating film 12, and the upper electrode 13 is formed. As shown in the figure, when the cross-sectional areas of the capacitive insulating film 12 and the upper electrode 13 are larger than the cross-sectional area of the lower electrode 10, the spacer insulating film 11 filling the periphery of the lower electrode 10 as described above. Is preferably formed.

Next, as shown in FIG. 2B, in order to focus the light incident on the upper electrode 13 toward the center of the capacitor insulating film 12, only a convex lens (micro-lens) is formed on the upper electrode 12 of each capacitor. Lens) 14 is provided. Here, the method for forming the convex lens 14 is generally the same as the method for producing a microlens of a solid-state imaging device, and is a mixture of oxygen (O ₂ ) and tetrafluoromethane (CF ₄ ). Using the gas as an etching gas, the lens material is formed into a convex shape by dry etching. Specifically, a lens material made of a silicon oxide film or the like is deposited on the upper electrode 10 by a CVD method, and a resist is applied thereon to form a resist layer. Subsequently, the resist layer is patterned into a rectangular shape, a square shape, a circular shape or the like corresponding to each capacitor. Subsequently, the resist layer is melted at a temperature of about 100 ° C. to 250 ° C. and then solidified, thereby generating a resist pattern having a convex spherical shape on a lens material having a convex lens shape. Subsequently, the convex lens 14 is formed by etching the lens material having a convex lens shape using the convex spherical resist pattern as a mask. The convex lens 14 is preferably formed so that the focal point of the convex lens 14 coincides with the center of the capacitive insulating film 12. This is to maximize the light condensing effect of the convex lens 14. The convex lens 14 is preferably formed so as to be in direct contact with the upper electrode 13.

Here, the material of the convex lens 14 is preferably made of a high refractive index material having a refractive index of 1.46 or more, specifically, a silicon nitride film (refractive index 2.0 to 2.2), an acid A film having a high refractive index typified by a silicon nitride film (refractive index: 1.6 to 1.8) or a silicon oxide film (refractive index: 1.46) and having high affinity with a semiconductor process. In addition, it is preferable to use a material that is easy to dry-etch. In the present embodiment, the film thickness of the convex lens 14 is 300 nm to 700 nm at the thickest portion of the convex shape. Further, as a mixed gas used when forming the convex lens 14, when the material of the convex lens 14 is a silicon oxide film, a mixed gas composed of tetraethoxysilane (TEOS) and ozone (O ₃ ), convex When the material of the mold lens 14 is a silicon nitride film, a mixed gas composed of silane (SiH ₄ ), ammonia (NH ₃ ), and nitrous oxide (N ₂ O), and the material of the convex lens 14 is silicon oxynitride In the case of a film, it is preferable to use a mixed gas composed of silane (SiH ₄ ), ammonia (NH ₃ ), nitrous oxide (N ₂ O) and oxygen) O ₂ ).

  Next, as shown in FIG. 2C, a crystallization heat treatment is performed on the ferroelectric film constituting the capacitive insulating film 12 using a rapid thermal heat treatment method. FIG. 2C schematically shows the optical path 2L in the rapid thermal heat treatment. As shown in the figure, in the ferroelectric memory unit 1A, since the convex lens 14 is formed, the optical path 2L is condensed by the convex lens 14 in the rapid thermal heat treatment, and the capacitive insulating film 12 is selectively formed. To be heated. On the other hand, since the logic circuit portion 1B does not have the light condensing function by the lens as described above, as a result, the capacitor insulating film 12 is heat-treated at a higher temperature than the transistor of the logic circuit portion 1B. Therefore, since the capacitor insulating film 12 can be selectively and efficiently crystallized, it is improved that the ferroelectric memory characteristics cannot be sufficiently obtained due to insufficient heat treatment during crystallization of the ferroelectric film. Can do.

  Here, the influence of rapid thermal heat treatment on transistor characteristics and ferroelectric memory characteristics in this step will be described.

  Table 1 below shows an example of rapid thermal heat treatment conditions in the present embodiment.

  In the present embodiment, strontium bismuth oxide is used as a representative example of the ferroelectric film constituting the capacitive insulating film 12, and the crystal is formed under the conditions that oxygen is 3000 sccm (3 mL / min), temperature is 700 ° C., and time is 30 seconds. A heat treatment is performed.

  FIG. 4 schematically shows the structure of a rapid thermal heat treatment apparatus used when rapid thermal heat treatment is performed under the conditions shown in Table 1 above.

  As shown in FIG. 4, a susceptor 102 on which a semiconductor substrate 101 (corresponding to the p-type semiconductor substrate 1 in FIG. 1) is mounted is provided inside a quartz chamber 103, and the inside thereof is under atmospheric pressure. It has a structure. The semiconductor substrate 101 is heated to a predetermined temperature using a heating lamp 104 as a light source, oxygen is introduced into the interior from the gas inlet 105 under the conditions shown in Table 1 above, and is exhausted to the outside from the gas outlet 106. The Note that although the case where heat treatment is performed using the heating lamp 104 has been described with reference to FIG. 4, rapid thermal heat treatment of a hot wall heater heating method using a heater instead of the heating lamp 104 can be performed.

  The crystallization heat treatment includes a variety of rapid thermal heat treatment methods such as a batch type or a single wafer type, and the optimum processing conditions may be used for various semiconductor devices. At this time, the temperature and time of the rapid thermal heat treatment apparatus may be adjusted so that the residual polarization amount of the ferroelectric film is maximized. Thus, it goes without saying that the rapid thermal heat treatment conditions are not limited to the example shown in Table 1 above.

  FIG. 5A shows a target effective channel length (Lg-efl) and an actual channel length (Lg-efl) of the transistor (MOS field effect transistor) structure of the logic circuit unit 1B in the ferroelectric memory device according to the present embodiment. Lg-eff). In general, the effective channel length Lg-eff of a MOS transistor is determined by the distance between the shallow source / drain regions 5a facing each other via the gate electrode 4b. The length Lg-eff will change. Specifically, as shown in FIG. 5A, the target effective channel length Lg-efl, which was the initial target, is shortened through the heat treatment step, and becomes the effective channel length Lg-eff. As a result, transistor characteristics shift.

FIG. 5B shows the heat treatment temperature dependence of the threshold voltage (V _T ), which is one of the transistor characteristics of the MOS field effect transistor.

As shown in FIG. 5B, when a heat treatment at 700 ° C. or lower is performed after the transistor is formed, the threshold voltage (V _T ) is a value between V _T = −0.55 V to −0.45 V, which is a desired value. The threshold voltage is maintained. However, when the heat treatment at 800 ° C. is performed, the threshold voltage (V _T ) becomes a value between V _T = −0.4 V to −0.3 V, which is greatly shifted from the desired threshold voltage. As described with reference to FIG. 5A, this is considered to be a result of the transistor characteristics being shifted because the effective channel length Lg-eff is shortened when the heat treatment temperature is too high.

  Therefore, if the ferroelectric film is crystallized under the rapid thermal heat treatment conditions in the present embodiment shown in Table 1 above, the crystallization temperature can be lowered to 700 ° C. Therefore, before and after the heat treatment, the effective channel length Lg− It is possible to prevent a shift in transistor characteristics without substantially changing eff. At the same time, since the capacitive insulating film 12 can be selectively and efficiently crystallized by the convex lens 14 as described above, even when the ferroelectric film is crystallized even at a crystallization temperature of 700 ° C. It can be improved that the ferroelectric memory characteristics cannot be sufficiently obtained due to insufficient heat treatment.

  FIG. 6 is a hysteresis curve showing the polarization amount of the ferroelectric capacitor in the ferroelectric memory device according to the embodiment of the present invention.

As an example, the ferroelectric capacitor used in the evaluation of FIG. 6 has a projected surface area (not shown) of 0.7 μm ² as viewed from above the lower electrode 10, and the X-axis length of the lower electrode 10 made of platinum. This sample is 0.835 μm, the length of the Y-axis is 0.835 μm, and the thickness of the capacitive insulating film 12 is 100 nm.

  As shown in FIG. 6, by providing the convex lens 14 in the ferroelectric capacitor, the amount of ferroelectric polarization is about 1.67 times that in the case where the convex lens 14 is not provided. I understand.

  As described above, according to the manufacturing method of the ferroelectric device according to the present embodiment, the mixed mounting of the ferroelectric memory and the transistor can be easily integrated, and both the ferroelectric characteristics and the transistor characteristics can be realized. it can. For this reason, for example, when there is a transistor of a large-scale logic circuit part used in an SRAM circuit or an encryption circuit for storing cache data as a transistor, the characteristic shift of the transistor is reduced even if the process is miniaturized. Therefore, a great effect such as reduction of chip cost due to area reduction can be obtained.

  Next, as shown in FIG. 3A, for example, the CVD method is used to cover the interlayer insulating film 11, the ferroelectric capacitor, and the convex lens 14 on the lower hydrogen barrier film 8, for example, One or more materials selected from the group consisting of silicon nitride film, silicon oxynitride film, aluminum oxide film (alumina), titanium aluminum oxide film, tantalum aluminum oxide film, titanium oxide silicon film, tantalum silicon oxide film, etc. An upper hydrogen barrier film 15 made of the above material and having a thickness of 10 to 100 nm is formed. In this way, the periphery of the ferroelectric capacitor is completely covered with the lower hydrogen barrier film 8 and the upper hydrogen barrier film 15 connected to each other.

  Here, in the structure portion where the plurality of ferroelectric memory devices in the ferroelectric memory portion 1A of the present embodiment are adjacent to each other, as shown in FIG. 7A, the upper electrode 13, the upper hydrogen barrier film 15, and the like. Convex lenses 14 are formed between the two. Therefore, when the convex lens 14 is formed, the surface of the interlayer insulating film 13 between the ferroelectric capacitors is etched in a concave shape by about 30 to 100 nm. As a result, the convex shape without the angular portion of the convex lens 14 is formed on the ferroelectric capacitor, and the convex of the convex lens 14 is formed on the interlayer insulating film 13 between the ferroelectric capacitors. Continuing with the shape of the mold, a concave, gently inclined surface is formed. Therefore, since the upper hydrogen barrier film 15 can be formed on the continuous gentle uneven shape, the coverage can be improved. Therefore, even if the upper hydrogen barrier film 15 is formed thin, high hydrogen barrier properties can be maintained and characteristic deterioration of the ferroelectric film can be prevented. In the present embodiment, the film thickness of the upper hydrogen barrier film 15 is described as an example in the range of 10 to 100 nm. However, according to the knowledge obtained by the present inventors, the film thickness of the upper hydrogen barrier film 15 is described. Is known to be able to sufficiently block hydrogen with a few nm.

  On the other hand, as shown in FIG. 7B, in the ferroelectric memory device adjacent to each other, the conventional structure in which the convex lens 14 is not provided between the upper electrode 13 and the upper hydrogen burr film 15, respectively. Since the upper hydrogen barrier film 15 is formed on the structure in which the upper electrodes 13 having a flat upper surface shape and the end surface shape being nearly vertical are formed adjacent to each other, the upper hydrogen barrier film 15 is formed. The coverage of the film 15 is deteriorated. As a result, when the thickness of the upper hydrogen barrier film 15 is reduced, the hydrogen barrier property is lowered and the characteristic deterioration of the ferroelectric film is increased.

  Next, as shown in FIG. 3B, in the ferroelectric memory unit 1A and the logic circuit unit 1B, the ferroelectric capacitor is covered on the interlayer insulating film 7 and the lower hydrogen barrier film 8, for example, After the interlayer insulating film 16 made of a BPSG film having a thickness of 1500 to 2500 nm is formed, the surface thereof is flattened using the CMP method, and finally the total thickness of the interlayer insulating film 16 and the interlayer insulating film 7 is 1300. Adjust to ˜2500 nm. Subsequently, a contact hole that penetrates the interlayer insulating film 16 and exposes the contact plug 9a is formed in the interlayer insulating film 16 in the ferroelectric memory portion 1A, and then contact is made by, for example, burying tungsten in the contact hole. A contact plug 17 (plug diameter 150 to 350 nm) is formed which is connected to the plug 9a and electrically connected to the source / drain region of the memory transistor of the ferroelectric memory unit 1A. At the same time, a contact hole that penetrates the interlayer insulating film 16 and exposes the contact plug 9a is formed in the interlayer insulating film 16 in the logic circuit portion 1B, and the contact plug is filled with tungsten, for example. A contact plug 17 (plug diameter 150 to 350 nm) is formed which is connected to 9a and is connected to the contact plug 9a through the interlayer insulating film 16 and electrically connected to the source / drain region of the transistor of the logic circuit portion 1B. To do. Subsequently, on the interlayer insulating film 16, a bonding pad made of, for example, aluminum or copper using a known technique and having a thickness of about 400 nm and a width of 70 μm connected to the contact plug 17 in the ferroelectric memory portion 1A. 18 and a wiring layer 19 having a thickness of about 400 nm and a width of 250 nm or more connected to the contact plug 17 (diameter 150 to 350 nm) in the logic circuit portion 1B. Further, an 800 nm thick interlayer made of, for example, a BPSG film having a planarized surface so as to cover the wiring layer 18 and the bonding pad 19 on the interlayer insulating film 16 by a known technique using the CVD method and the CMP method. An insulating film 20 is formed.

  As described above, the ferroelectric memory device according to this embodiment is completed.

  The present invention is useful for a ferroelectric memory device in which a ferroelectric memory portion and a logic circuit portion are mixedly mounted.

DESCRIPTION OF SYMBOLS 1A Ferroelectric memory part 1B Logic circuit part 1 P-type semiconductor substrate 2 Element isolation region 2L Optical path 3 Active region 4a Gate insulating film 4b Gate electrode 4c Side wall 5a Shallow source / drain region 6a Deep source / drain region 7 Interlayer insulating film 7A, 7B region 8 lower hydrogen barrier film 9a contact plug 9b contact plug 10 lower electrode 11 spacer insulating film 12 capacitive insulating film 13 upper electrode 14 convex lens 15 upper hydrogen barrier film 16 interlayer insulating film 17 contact plug 18 wiring layer 19 bonding pad 20 Interlayer insulating film 101 Semiconductor substrate 102 Susceptor 103 Quartz chamber 104 Lamp 105 Gas inlet 106 Gas outlet Lg-eff Effective channel length Lg-efl Target effective channel length

Claims (13)

On the semiconductor substrate, there is provided a ferroelectric capacitor in which a lower electrode, a ferroelectric film having a perovskite crystal structure, and an upper electrode are laminated in this order,
A ferroelectric memory device, further comprising a convex lens formed on the upper electrode and selectively heating the ferroelectric film by condensing. The ferroelectric memory device according to claim 1,
The ferroelectric memory device, wherein the convex lens is in direct contact with the upper electrode. The ferroelectric memory device according to claim 1 or 2,
The convex lens is a ferroelectric memory device made of a high refractive index material having a refractive index of 1.46 or more. The ferroelectric memory device according to any one of claims 1 to 3,
In the ferroelectric memory device, the convex lens is made of a silicon nitride film, a silicon oxynitride film, or a silicon oxide film. The ferroelectric memory device according to any one of claims 1 to 4,
A plurality of the ferroelectric capacitors,
The surface of the interlayer insulating film that fills between the adjacent ferroelectric capacitors has a concave surface shape that is continuous with the convex surface shape of the convex lens formed on the adjacent ferroelectric capacitors. A ferroelectric memory device formed on the substrate. The ferroelectric memory device according to claim 5,
A hydrogen barrier film formed on the semiconductor substrate so as to continuously cover the ferroelectric capacitors adjacent to each other and an interlayer insulating film filling the space between the adjacent ferroelectric capacitors; Ferroelectric memory device. (A) forming a ferroelectric capacitor by laminating a lower electrode, a ferroelectric film having a perovskite crystal structure, and an upper electrode in this order on a semiconductor substrate;
Forming a convex lens on the upper electrode (b);
A step (c) of performing a heat treatment for crystallizing the ferroelectric film using a rapid thermal annealing method after the step (b);
The step (c) includes a step of selectively heating the ferroelectric film by condensing the light used in the rapid thermal annealing method onto the ferroelectric film using the convex lens. And manufacturing method of ferroelectric memory device. The method of manufacturing a ferroelectric memory device according to claim 7,
The method of manufacturing a ferroelectric memory device, wherein the step (b) includes a step of forming the convex lens so as to be in direct contact with the upper electrode. The method of manufacturing a ferroelectric memory device according to claim 7 or 8,
Before the step (c), the method further includes a step (d) of forming a transistor constituting a logic circuit portion on the semiconductor substrate.
The step (c) includes a step of performing the heat treatment so as not to substantially change the effective channel length of the transistor. In the manufacturing method of the ferroelectric memory device according to any one of claims 7 to 9,
The step (a) includes a step of forming a plurality of the ferroelectric capacitors on the semiconductor substrate,
Before the step (b), the method further comprises a step (e) of forming an interlayer insulating film filling the space between the plurality of ferroelectric capacitors,
In the step (b), the surface of the interlayer insulating film filling the space between the adjacent ferroelectric capacitors is defined as the convex surface shape of the convex lens formed on the adjacent ferroelectric capacitors. A method for manufacturing a ferroelectric memory device, comprising a step of forming a concave surface shape so as to be continuous. The method of manufacturing a ferroelectric memory device according to claim 10,
After the step (c), a step (f) of forming a hydrogen barrier film so as to continuously cover the ferroelectric capacitors adjacent to each other and the interlayer insulating film filling the space between the adjacent ferroelectric capacitors. A method for manufacturing a ferroelectric memory device, further comprising: In the manufacturing method of the ferroelectric memory device according to any one of claims 7 to 11,
The method for manufacturing a ferroelectric memory device, wherein the convex lens is made of a high refractive index material having a refractive index of 1.46 or more. The method of manufacturing a ferroelectric memory device according to any one of claims 7 to 12,
The method of manufacturing a ferroelectric memory device, wherein the convex lens is made of a silicon nitride film, a silicon oxynitride film, or a silicon oxide film.

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