JP2011108779A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an influence on a circuit on a semiconductor chip by a magnetic field generated by an inductor element, in a semiconductor device composed by integrating the semiconductor chip and the inductor element. <P>SOLUTION: The semiconductor device includes a first chip 2, a second chip 4 laminated on the first chip 2, and the inductor element 1 loaded on either one of the first chip and the second chip 4 and provided with an inductor. The inductor element 1 generates a magnetic field in a direction roughly parallel to both of the main surface of the first chip and the main surface of the second chip 4 on the inner side of the inductor, and the second chip 4 is not disposed in the direction of the magnetic field generated on the inner side of the inductor in the view from the inductor element 1 on the first chip 2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The technology disclosed in this specification relates to a semiconductor device having a three-dimensional chip stack structure in which a plurality of integrated circuit chips are stacked and having an inductor.

  In recent years, mobile communication devices such as mobile phones have been downsized. In order to reduce the size of equipment, there is an increasing demand for analog high-frequency circuits to be integrated into a silicon integrated circuit on a single chip. In addition to transistors, resistors, and capacitors, high-frequency circuits require inductor elements such as coils and transformers, and methods for forming inductor elements along with integrated circuits using transistors and resistors on a semiconductor substrate have been developed. Yes.

  On the other hand, a semiconductor integrated circuit is divided into a plurality of chips for each functional circuit such as an inductor element, a logic circuit, an analog circuit, and a memory circuit, and by stacking these chips, the chip cost can be reduced and the entire semiconductor module can be reduced. It has been proposed to reduce the size.

  For example, Patent Document 1 discloses a technique for three-dimensionally stacking a plurality of semiconductor chips each having a through electrode formed on a circuit board, and a method for forming a through electrode that penetrates from the top surface to the back surface of each chip. ing. Patent Document 2 discloses a configuration in which a semiconductor chip is mounted on a ferrite substrate on which a planar coil is formed. In the configurations shown in these patent documents, a chip is provided for each of various functional circuits, and these chips are integrated to form one integrated circuit module. Therefore, all functions are integrated on one chip. The chip manufacturing cost can be reduced by optimizing the manufacturing process of each chip as compared with the case. Further, the integrated circuit module can be reduced in size as a whole.

Japanese Patent Laying-Open No. 2003-243396 (page 3, FIG. 6) JP 2002-353030 A (page 8, FIG. 8)

  However, in the conventional semiconductor device disclosed in Patent Document 2, when a high-frequency current is passed through the inductor element, an eddy current that prevents a change in magnetic flux is generated in the semiconductor chip. For this reason, there is a problem in that power loss occurs in the inductor element itself, and a potential difference is generated on the semiconductor chip due to eddy current, causing noise in the semiconductor chip and circuit malfunction. With the miniaturization of integrated circuits and the improvement in the degree of integration, integrated circuits on a semiconductor chip are easily affected by magnetism, but it is difficult to miniaturize an inductor element to ensure a predetermined inductance. For this reason, the generation of noise and malfunction in integrated circuits has become a bigger issue.

  An object of the present invention is to reduce the influence of a magnetic field generated by an inductor element on a circuit on the semiconductor chip in a semiconductor device in which a semiconductor chip and an inductor element are integrated.

  A semiconductor device according to an example of the present invention includes a first chip having a main surface on which an integrated circuit is formed, and at least one first chip having a main surface stacked on the first chip and having an integrated circuit formed thereon. 2 chips and an inductor element mounted on any one of the first chip and the second chip and having an inductor. Further, in the semiconductor device, the inductor element generates a magnetic field in a direction substantially parallel to both the main surface of the first chip and the main surface of the second chip inside the inductor, The second chip is not arranged on the first chip in the direction of the magnetic field generated inside the inductor when viewed from the inductor element.

  According to this configuration, since both the first chip and the second chip do not enter the region where the magnetic flux density is high in the region where the magnetic field is generated by the operation of the inductor element, the loss due to the eddy current is greatly reduced. be able to. In addition, malfunction of the integrated circuit provided over the first chip and the second chip can be prevented. Furthermore, since the first chip and the second chip are stacked, for example, an integrated circuit having separate functions can be provided in the first chip and the second chip. In this case, 1 As a result, the manufacturing cost of the semiconductor device can be reduced as compared with the case where a circuit having a plurality of functions is integrated on one chip, and the performance of each circuit can be easily exhibited.

  The inductor element is mounted on the first chip, and a magnetic field in a direction substantially parallel to an end face of the second chip facing the inductor element is generated inside the inductor. preferable.

  If the inductor is composed of one or more turns, a magnetic field having a desired strength can be generated.

  A plurality of inductor elements may be mounted on any one of the first chip and the second chip, or a plurality of inductors may be provided on one inductor element. Also good.

  According to the semiconductor device according to the example of the present invention, the influence of the first chip and the second chip stacked on the first chip due to the magnetic field is greatly reduced, so that the loss due to the eddy current is suppressed. This makes it possible to prevent malfunctions of the integrated circuits provided in the first chip and the second chip.

1 is a perspective view showing a semiconductor device according to a first embodiment of the present invention. It is a 3rd page figure showing an example of the structure of the inductor element mounted in the semiconductor device concerning each embodiment. It is a perspective view which shows the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a perspective view which shows the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a perspective view which shows the semiconductor device which concerns on the 4th Embodiment of this invention. It is a perspective view which shows the semiconductor device which concerns on the 5th Embodiment of this invention. It is a perspective view which shows the semiconductor device which concerns on the 6th Embodiment of this invention. (A)-(c) is a figure which shows the example of the inductor element 1 which functions as the transformer 57 in the semiconductor device which concerns on each embodiment. FIG. 5 is a perspective view showing an example in which a plurality of inductor elements 1 constituting a transformer 57 are provided in a semiconductor device according to an embodiment of the present invention. (A), (b) is the top view and sectional drawing which show the inductor element 1 which functions as a differential inductor in the semiconductor device which concerns on each embodiment. 1 is a perspective view showing an example in which a plurality of inductor elements 1 constituting a differential inductor are provided in a semiconductor device according to an embodiment of the present invention. (A)-(d) is a figure which shows the inductor element 1 which has the inductor formed on the semiconductor substrate. FIG. 10 is a perspective view (upper view), a schematic side view (middle view), and a schematic front view (lower view) showing a semiconductor device according to a seventh embodiment of the present invention. It is the front view, side view, and bottom view which show the inductor element in the semiconductor device which concerns on 7th Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. Note that in the drawings illustrating the semiconductor device according to each embodiment, the constituent elements denoted by the same reference numerals perform the same operation, and thus the description thereof may be omitted.

(First embodiment)
FIG. 1 is a perspective view showing a semiconductor device according to the first embodiment of the present invention.

  As shown in the figure, the semiconductor device of this embodiment includes a logic circuit chip (first chip) 2, an analog circuit chip (second chip) 4 mounted on the logic circuit chip 2, and a logic circuit. A chip-shaped inductor element 1 mounted on the chip 2 is provided.

  In the example shown in FIG. 1, the area of the logic circuit chip 2 is larger than that of the analog circuit chip 4, and the planar shape of each chip including the logic circuit chip 2 is a quadrilateral shape. In the peripheral part of the logic circuit chip 2, bonding pads 3 are provided for exchanging signals with external circuits and devices, and for connecting wirings for transmitting a power supply voltage supplied from the outside. In one main surface (circuit formation surface) of the logic circuit chip 2, a connection pad (not shown) electrically connected to the bonding pad 3 is provided in a region where the analog circuit chip 4 is mounted.

  The logic circuit chip 2 and the analog circuit chip 4 exchange necessary electric signals by the connection pads on the logic circuit chip 2 and the connection pads arranged on the analog circuit chip 4. A power supply voltage is supplied to the chip 4. The circuit formation surface of the analog circuit chip 4 is provided with, for example, circuit elements and metal wiring, as well as connection pads and bumps connected thereto, and the circuit formation surface of the analog circuit chip 4 is the circuit of the logic circuit chip 2. It connects so that a formation surface may be opposed. Of course, the analog circuit chip 4 has a through electrode penetrating the semiconductor substrate and a connection pad connected to the through electrode and provided on the back surface of the semiconductor substrate, and the connection pad of the analog circuit chip 4 is a logic circuit chip. 2 may be connected to the connection pads on the 2 by bumps or the like.

  As will be described later, the inductor element 1 has a copper thin film as a wiring spirally formed on one main surface thereof. In the inductor element 1 during operation, the inductor element 1 passes through the center of the vortex of the copper thin film and is formed on the main surface. On the other hand, magnetism is generated in a direction perpendicular to the direction (arrow direction shown in FIG. 1).

  In the example shown in FIG. 1, the first chip is the logic circuit chip 2 and the second chip is the analog circuit chip 4. However, the function of the circuit provided on each chip is not limited to this. Absent. For example, the first chip may be an analog circuit chip, and the second chip on the first chip may be a logic circuit chip. Further, the first chip may be a logic circuit chip including an analog circuit, and the second chip may be a memory circuit chip.

  Next, an example of the structure of the inductor element 1 will be described with reference to the drawings. FIG. 2 is a three-view diagram illustrating an example of the structure of a relatively large inductor element. The side view drawn on the left side shows a cross section through the gold bump 15 and the copper thin film 13 shown in the front view. In FIG. 2, the surface on which the spiral copper thin film 12 is provided is shown as the front surface, and the surface connected to the logic circuit chip 2 is shown as the bottom surface.

  The inductor element 1 shown in FIG. 2 is provided on an insulating substrate 11, a spiral copper thin film (winding) 12 provided on one main surface of the insulating substrate 11, and the other main surface of the insulating substrate 11. A copper thin film 13 formed thereon. In the following description, the coil provided in the inductor element 1 is referred to as an inductor. Here, the copper thin films 12 and 13 constitute a surface mount type inductor. Although FIG. 2 shows an example in which the number of turns of the copper thin film 12 is 3 turns, if the number of turns of the copper thin film 12 is at least one turn, a desired function can be exhibited as an inductor.

  A through hole is formed in the insulating substrate 11 at the position of the inner end of the spiral formed by the copper thin film 12, and the copper thin film 12 and the copper thin film 13 are connected by a through hole plating 14 embedded in the through hole. Has been. A connection pad 16 a that penetrates through the insulating substrate 11 and functions as a connection terminal is connected to an end portion of the copper thin film 13 on the bottom surface side of the insulating substrate 11. A connection pad 16b that is exposed on the bottom surface of the substrate 11 and functions as a connection terminal is connected. Therefore, the connection pad 16b and the connection pad 16a are electrically connected via the copper thin films 12 and 13. The connection pads 16 a and 16 b are connected to connection pads (not shown) disposed on the logic circuit chip 2 via connection members such as gold bumps 15.

  The main surface of the insulating substrate 11 is, for example, a square having a side of about 500 μm, and the thickness of the resin substrate 11 is, for example, about 100 μm. Moreover, the thickness of the copper thin films 12 and 13 is, for example, 40 μm.

  Inside the inductor, a current flows between the connection pad 16 a and the connection pad 16 b, thereby generating a magnetic field in a direction perpendicular to the winding surface of the copper thin film 12, that is, in the front direction or the back direction of the inductor element 1. In other words, the direction perpendicular to the winding surface of the copper thin film 12 can be said to be the axial direction of the inductor composed of the copper thin films 12 and 13. Here, the “winding surface” represents a plane in which magnetic lines of force induced by the inductor element are orthogonal. In this embodiment, the winding surface of the copper thin film 12 is the same surface as the main surface of the insulating substrate 11 on which the copper thin film 12 is provided.

  In the semiconductor device of this embodiment, the main surface (the winding surface of the copper thin film 12) on which the copper thin film of the insulating substrate 11 is provided is the circuit forming surface of another chip (here, the logic circuit chip 2 and the analog circuit chip 4). Unlike the conventional semiconductor device, the inductor element 1 is disposed so as to be substantially perpendicular to the semiconductor device. Here, “substantially perpendicular to the circuit formation surface of another chip” means not only the case where the main surface provided with the copper thin film is perpendicular to the circuit formation surface of the other chip, but also other chips. This includes the case where the position is slightly deviated from the vertical as long as it does not affect the range. Further, the main surface of the inductor element 1 is also substantially perpendicular to a chip provided on the same chip, that is, an end surface (side surface) of the analog circuit chip 4 facing the inductor element 1.

  In the semiconductor device of the present embodiment having the above configuration, the direction of the magnetic lines passing through the inside of the vortex formed by the copper thin film 12 is substantially parallel to the circuit formation surface of the logic circuit chip 2 and the analog circuit chip 4. This is also substantially parallel to the end face facing the inductor element 1. Therefore, the logic circuit chip 2 and the analog circuit chip 4 do not enter the region where the magnetic flux density is high in the region where the magnetic field is generated by the inductor element 1, and the loss due to the eddy current can be greatly reduced.

  Furthermore, according to the semiconductor device of this embodiment, malfunctions in the logic circuit chip 2 and the analog circuit chip 4 can be prevented, and when a memory circuit chip is stacked on the logic circuit chip 2, the occurrence of a soft error can be suppressed. it can. As described above, the type of circuit formed on the chip to be stacked is not limited, but analog circuits are more susceptible to eddy currents compared to logic circuits and memories in which constituent elements (transistors, etc.) have operating thresholds. The configuration described in this embodiment is particularly effective when the analog circuit chip 4 and the inductor element 1 are provided in the same package.

  In addition, when integrating devices with different structures such as CMOS logic circuits, analog circuits, and flash memories on a single substrate, the manufacturing process of the integrated circuit becomes complicated and the manufacturing cost increases, and each circuit element In many cases, it is difficult to maximize the performance. On the other hand, in the semiconductor device of this embodiment, after the circuit elements having different structures are formed on separate chips, these chips are bonded to each other, so that the manufacturing cost of each chip can be reduced. As a result, the manufacturing cost of the entire semiconductor device can be reduced. Furthermore, it becomes easier to maximize the performance of each circuit element. Further, the yield can be improved as compared with the case where various circuits are integrated on one chip.

  Usually, in order to provide the spiral copper thin film of the inductor element, an area of about 100 μm or more is required. Therefore, in a conventional semiconductor device, a circuit is provided below the inductor element to prevent malfunction of the circuit due to eddy current. It was necessary to consider such things as not providing. On the other hand, in the semiconductor device of the present embodiment, the influence of the magnetic field generated by the inductor element 1 is very small, so that the chip located below the inductor element 1 (logic circuit chip 2 in the example of FIG. 1). The degree of freedom in circuit arrangement is greatly improved, and circuit elements can be arranged at higher density. Therefore, the configuration of this embodiment also contributes to a reduction in chip area.

  When a current flows through the inductor element 1, a magnetic field in a direction parallel to the vortex axis of the copper thin film 12 is generated inside the inductor formed by the copper thin film 12. A magnetic field in the opposite direction to the inside is generated. Here, “the side of the inductor element 1” means a side direction when the directions in which both main surfaces of the insulating substrate 11 face are the front and the back. However, since the magnetic flux density of the magnetic field on the side of the inductor element 1 is very small compared to the magnetic flux density of the magnetic field directed from the inside of the vortex formed by the copper thin film 12 to the front direction of the inductor element 1, The influence of the magnetic field on the circuit on the logic circuit chip 2 positioned below and the circuit on the analog circuit chip 4 arranged on the same chip as the inductor element 1 is extremely small compared to the conventional semiconductor device.

  In addition, chips such as the analog circuit chip 4 and the logic circuit chip 2 do not have to be arranged in a region where the magnetic flux density of the magnetic field generated by the inductor element 1 is large. That is, if it is not arranged in the direction of the magnetic field generated inside the inductor composed of the copper thin film 12, the influence of the eddy current due to the magnetic field can be suppressed. When an AC voltage is applied to the inductor element 1, a magnetic field in a direction opposite to 180 degrees from the arrow shown in FIG.

  In the semiconductor device of the present embodiment, the inductor element 1 is not limited to the one in which the spiral copper thin film 12 is formed on the main surface of the insulating substrate 11, and the spiral copper thin film 12 is formed on the wiring layer inside the insulating substrate 11. Alternatively, a spiral metal wiring may be formed on a high-resistance silicon substrate by a semiconductor process. Further, as will be described later, a coil made of a metal wire may be used as the inductor element instead of the inductor formed on the plane.

  The copper thin film 12 constituting the inductor does not necessarily need to be made of copper, and may be a spiral wiring made of metal.

  In the semiconductor device of this embodiment, the analog circuit chip 4 is stacked on the logic circuit chip 2, but a chip in which another semiconductor integrated circuit is formed may be sandwiched between the two chips. A circuit board may be sandwiched.

(Second Embodiment)
FIG. 3 is a perspective view showing a semiconductor device according to the second embodiment of the present invention.

  As shown in the figure, the semiconductor device of this embodiment includes a logic circuit chip 2, an analog circuit chip 4 mounted on the logic circuit chip 2, and an inductor element 1 mounted on the analog circuit chip 4. I have. The semiconductor device of this embodiment is different from the semiconductor device of the first embodiment in that the inductor element 1 is disposed on an analog circuit chip 4 stacked on a logic circuit chip 2.

  A spiral copper thin film 12 is provided on one main surface of the inductor element 1, and the main surface of the inductor element 1 (or insulating substrate) is a circuit forming surface (one main surface) of the analog circuit chip 4. The inductor element 1 is provided on the analog circuit chip 4 so as to be vertical. Therefore, the direction of the magnetic field generated inside the spiral copper thin film 12 (that is, the inductor) of the inductor element 1 is set to one main surface (circuit formation surface) of the logic circuit chip 2 and one main surface (circuit formation surface) ( It is almost parallel to the circuit forming surface).

  According to the semiconductor device according to the present embodiment, similarly to the semiconductor device according to the first embodiment, the influence of the magnetic field generated by the inductor element 1 on the logic circuit chip 2 and the analog circuit chip 4 is reduced, and the circuit malfunctions. The occurrence of problems such as these can be suppressed. Furthermore, since the inductor element 1 is disposed on the analog circuit chip 4 stacked on the logic circuit chip 2, the area of the analog circuit chip 4 can be increased as compared with the semiconductor device according to the first embodiment. Thus, the integration degree of the analog circuit can be improved. In addition, since it is not necessary to provide a region for mounting the inductor element 1 on the logic circuit chip 2, it is possible to reduce the plane area as compared with the semiconductor device of the first embodiment.

  The semiconductor device of the first embodiment can be preferably used when the thickness of the semiconductor device as a whole is smaller than the reduction of the planar area because the thickness of the entire semiconductor device can be reduced as compared with the semiconductor device of the present embodiment.

  Furthermore, in the semiconductor device of this embodiment, since the inductor element 1 is directly connected to the analog circuit chip 4 that requires the inductor element 1, the connection wiring length between the analog circuit chip 4 and the inductor element 1 can be shortened. . Therefore, parasitic capacitance such as wiring for connecting the inductor element 1 and the analog circuit chip 4 can be minimized, and loss can be reduced and high-frequency characteristics can be improved.

  If, for example, a chip in which a high frequency output circuit is formed on a substrate made of a compound semiconductor is used as the analog circuit chip 4, three-dimensional integration with the logic circuit chip 2 having a silicon substrate can be easily performed.

  In the semiconductor device of this embodiment, the arrangement and size of the analog circuit chip 4 and the logic circuit chip 2 are interchanged, or a chip having another function such as a memory circuit chip is used instead of these chips. it can.

(Third embodiment)
FIG. 4 is a perspective view showing a semiconductor device according to the third embodiment of the present invention.

  As shown in the figure, the semiconductor device of this embodiment includes a logic circuit chip 2, an analog circuit chip 4, a memory circuit chip 5, and an inductor element 1 mounted on the logic circuit chip 2, respectively. .

  In the semiconductor device of this embodiment, the main surface (the winding surface of the copper thin film 12) on which the copper thin film 12 of the insulating substrate 11 is provided is not limited to the circuit formation surfaces of the logic circuit chip 2 and the analog circuit chip 4. The inductor element 1 is arranged so as to be substantially perpendicular to the circuit formation surface of the memory circuit chip 5.

  With the above configuration, the direction of the magnetic field generated inside the spiral formed of the copper thin film 12 when the inductor element 1 is operated depends on the circuit formation surface of the logic circuit chip 2 and the circuit formation surface of the analog circuit chip 4; It is substantially parallel to the circuit formation surface of the memory circuit chip 5. The direction of the magnetic field generated inside the spiral formed of the copper thin film 12 is also substantially parallel to each end face of the analog circuit chip 4 and the memory circuit chip 5 facing the inductor element 1.

  Therefore, the logic circuit chip 2, the analog circuit chip 4 and the memory circuit chip 5 do not enter the region where the magnetic flux density is high in the region where the magnetic field is generated by the inductor element 1, and the loss due to the eddy current can be greatly reduced. it can. Furthermore, in the semiconductor device of this embodiment, it is possible to prevent malfunction of circuits on each chip. In particular, the memory circuit chip 5 can effectively prevent the occurrence of a soft error or the like.

(Fourth embodiment)
FIG. 5 is a perspective view showing a semiconductor device according to the fourth embodiment of the present invention.

  As shown in the figure, the semiconductor device of the present embodiment has a configuration in which the analog circuit chip 4 is stacked on the memory circuit chip 5 in the semiconductor device according to the third embodiment.

  Also in the semiconductor device of the present embodiment, as in the semiconductor device of the third embodiment, the direction of the magnetic field generated inside the spiral formed of the copper thin film 12 when the inductor element 1 is operated is the logic circuit chip. 2, the circuit formation surface of the analog circuit chip 4, and the circuit formation surface of the memory circuit chip 5, and each end surface facing the inductor element 1 of the analog circuit chip 4 and the memory circuit chip 5. It is almost parallel to. Therefore, the logic circuit chip 2, the analog circuit chip 4, and the memory circuit chip 5 do not enter the region where the magnetic flux density is high in the region where the magnetic field is generated by the inductor element 1, and the loss due to the eddy current is greatly reduced. Can do. Furthermore, also in the semiconductor device of this embodiment, malfunction of circuits on each chip can be prevented.

  In addition, since the planar area of the analog circuit chip 4 and the memory circuit chip can be increased as compared with the semiconductor device of the third embodiment, the degree of circuit integration in both chips can be improved.

(Fifth embodiment)
FIG. 6 is a perspective view showing a semiconductor device according to the fifth embodiment of the present invention.

  As shown in the figure, the semiconductor device according to the present embodiment increases the planar area of the memory circuit chip 5 in the semiconductor device according to the fourth embodiment, so that the inductor element 1 is not on the logic circuit chip 2 but on the memory circuit chip 5. It is arranged in.

  Also in the semiconductor device of this embodiment, the main surface of the insulating substrate 11 on which the copper thin film 12 is provided is substantially perpendicular to the circuit formation surfaces of the logic circuit chip 2, the analog circuit chip 4, and the memory circuit chip 5. In addition, the inductor element 1 is disposed so as to be substantially perpendicular to the end face of the analog circuit chip 4 facing the inductor element 1.

  With the above configuration, the direction of the magnetic field generated inside the spiral formed of the copper thin film 12 when the inductor element 1 is operated depends on the circuit formation surface of the logic circuit chip 2 and the circuit formation surface of the analog circuit chip 4; It is substantially parallel to the circuit formation surface of the memory circuit chip 5. Further, the direction of the magnetic field generated inside the inductor constituted by the copper thin film 12 is substantially parallel to the end face of the analog circuit chip 4 facing the inductor element 1.

  Therefore, the logic circuit chip 2, the analog circuit chip 4 and the memory circuit chip 5 do not enter the region where the magnetic flux density is high in the region where the magnetic field is generated by the inductor element 1, and the loss due to the eddy current can be greatly reduced. it can. Furthermore, also in the semiconductor device of this embodiment, malfunction of circuits on each chip can be prevented.

  According to the semiconductor device of this embodiment, the memory circuit chip 5 and the analog circuit chip 4 are stacked on the logic circuit chip 2 as compared with the semiconductor device according to the third embodiment. The planar area of the circuit chip 5 can be increased, and the degree of integration of circuits provided on the analog circuit chip 4 and the memory circuit chip 5 can be improved. Further, since the planar area of the memory circuit chip 5 can be increased as compared with the fourth semiconductor device, the configuration of this embodiment is preferably applied particularly when a large-capacity memory is formed on the memory circuit chip 5. it can.

(Sixth embodiment)
FIG. 7 is a perspective view showing a semiconductor device according to the sixth embodiment of the present invention.

  As shown in the figure, the semiconductor device according to the present embodiment is the same as the semiconductor device according to the fifth embodiment in that the planar area of the analog circuit chip 4 is increased and the inductor element 1 is not on the memory circuit chip 5 but on the analog circuit chip. 4 is arranged on top.

  Also in the semiconductor device of this embodiment, the main surface on which the copper thin film 12 of the insulating substrate 11 is provided is substantially perpendicular to the circuit formation surfaces of the logic circuit chip 2, the memory circuit chip, and the analog circuit chip 4. ing. The direction of the magnetic field generated inside the inductor constituted by the copper thin film 12 when the inductor element 1 is operated is the circuit formation surface of the logic circuit chip 2, the circuit formation surface of the memory circuit chip 5, and the analog circuit chip 4. It is almost parallel to the circuit formation surface.

  Therefore, the logic circuit chip 2, the analog circuit chip 4 and the memory circuit chip 5 do not enter the region where the magnetic flux density is high in the region where the magnetic field is generated by the inductor element 1, and the loss due to the eddy current can be greatly reduced. it can. Furthermore, also in the semiconductor device of this embodiment, malfunction of circuits on each chip can be prevented.

  In the semiconductor device of this embodiment, the analog circuit chip 4 and the memory circuit chip 5 are stacked vertically on the logic circuit chip 2, and the inductor element 1 is disposed on the analog circuit chip 4. Compared with the semiconductor device of this embodiment, the degree of circuit integration in each chip can be improved. In particular, the degree of circuit integration on the analog circuit chip 4 can be improved as compared with the semiconductor device of the fifth embodiment.

  The types and number of chips to be stacked are not limited to the example shown in FIG. 7, and a plurality of chips may be stacked from the bottom to the top, and the inductor element 1 may be disposed on the topmost chip. The same effect as that of the semiconductor device of this embodiment can be obtained.

  In addition, in the semiconductor device according to this embodiment and the other embodiments described so far, the inductor element 1 in which one inductor is provided on one substrate is used, but a plurality of inductors are provided on one substrate. The provided inductor element 1 may be provided.

  An example of such an inductor element 1 is a transformer.

  8A to 8C are diagrams illustrating examples of the inductor element 1 that functions as the transformer 57 in the semiconductor device according to each embodiment. As shown in FIGS. 5A to 5C, the transformer 57 includes, for example, a primary coil 57a and a secondary coil 57b having different inductances, and the primary coil 57a and the secondary coil 57b are inductively coupled. Are arranged as follows. As shown in FIGS. 8A to 8C, the primary coil 57 a and the secondary coil 57 b may be surface mount coils made of copper thin films formed on different wiring layers of the same insulating substrate 11. . Here, reference numeral 105 denotes a connection pad. The transformer is not limited to two coils, and may be composed of three or more coils.

  FIG. 9 is a perspective view showing an example in which a plurality of inductor elements 1 constituting the transformer 57 are provided in the semiconductor device according to the embodiment of the present invention. As shown in the figure, a plurality of inductor elements 1 provided on stacked chips may constitute a transformer. In this case, the transformer 57 is arranged such that the main surfaces of the plurality of insulating substrates 11 (inductor elements 1) each forming one coil (inductor) face the same direction. Any of the above-described transformers can be used in the semiconductor device according to the embodiment of the present application.

  In the semiconductor device of this embodiment, a plurality of inductor elements 1 arranged so as not to cause inductive coupling may be provided. For example, one end of two inductors having the same gain may be connected to each other and both inductors may be arranged in parallel to function as a differential inductor.

  FIGS. 10A and 10B are a plan view showing an inductor element 1 functioning as a differential inductor and a cross-sectional view taken along line Xb-Xb in the semiconductor device according to each embodiment. In this example, the connection pad 105 c is connected to the midpoint of the inductor 107 formed of a copper thin film or the like, and the connection pads 105 are provided at both ends of the inductor 107. Since the inductor element 1 has such a configuration, it can be used as a differential inductor.

  When the inductor 107 shown in FIGS. 10A and 10B is used in a differential circuit, the power supply voltage Vdd is input to the midpoint of the inductor 107. In this case, the inductor 107 is composed of two inductors with the middle point in between. These two inductors are provided close to each other, and currents flowing in opposite directions flow, so that they are affected by a magnetic field. However, when the inductor 107 is used in a resonance circuit, current in the same direction flows through two adjacent inductors, so that inductive coupling does not occur.

  Thus, the differential inductor may be composed of a plurality of surface mount type inductors formed on one substrate.

  FIG. 11 is a perspective view showing an example in which a plurality of inductor elements 1 constituting a differential inductor are provided in the semiconductor device according to the embodiment of the present invention. As shown in the figure, a plurality of inductor elements 1 (inductors provided therein) may be arranged to constitute a differential inductor. In this example, the two inductor elements 1 are arranged so that their main surfaces are oriented in the same direction and the side surfaces face each other, and the magnetic field generated by the operation of one inductor element 1 is applied to the other inductor element 1. Does not generate electromotive force.

  12A to 12D are views showing an inductor element 1 having an inductor formed on a semiconductor substrate. FIG. 12A is a front view showing an inductor, and FIGS. 12B to 12D are plan views showing the inductor.

  As shown in FIG. 12A, the inductor element 1 used in the semiconductor device of each embodiment has an inductor (spiral wiring 121) manufactured on a semiconductor substrate 102 using a known semiconductor manufacturing process. May be. The spiral wiring 121 is composed of, for example, a first layer wiring 130 formed on the interlayer insulating film 114 and a second layer wiring 132 connected to the first layer wiring 130 via a plug. Is provided in a spiral shape. In the semiconductor device described so far, the inductor element 1 may be configured as shown in FIG. In addition, a semiconductor device may be provided in which the differential inductor 126 is configured by connecting one ends of spiral wires 121a and 121b arranged so as not to be inductively coupled. Alternatively, as shown in FIG. 12D, a transformer 127 including inductors 125c and 125d arranged so as to be inductively coupled may be provided in the semiconductor device.

  An LC resonance circuit is an example including one or more inductor elements 1. The LC resonance circuit is, for example, a circuit having a plurality of inductor elements and a capacitive element and having a predetermined frequency as a resonance frequency. Even in this case, the inductor element 1 can be arranged on the chip as described above.

  As described above, the number and type of inductor elements 1 used in the semiconductor device of this embodiment are not limited.

  Further, the connection between the conductor pad on the chip and the inductor element 1 in each embodiment of the present invention is not limited to a connection method such as a connection via a bump or a connection using a wire. In the embodiment of the present invention, the pattern structure such as the number of turns and the number of layers of the inductor element 1 is not particularly limited. Furthermore, in the embodiment of the present invention, the element structure of various integrated circuit chips provided on the semiconductor substrate, the wiring layer, the constituent material of each layer, the film thickness of each member, the formation conditions, etc. are directly related to the arrangement of the inductor element 1. There is no particular limitation on the structure and manufacturing method.

(Seventh embodiment)
FIG. 13 is a perspective view (upper view), a schematic side view (middle view), and a schematic front view (lower view) showing a semiconductor device according to a seventh embodiment of the present invention.

  As shown in the figure, the semiconductor device of this embodiment is similar in configuration to the semiconductor device of the second embodiment, but the inductor element 1 is not on the circuit formation surface of the analog circuit chip 4 but on the end surface. It is different in the arrangement.

  Further, the inductor element 1 may be a surface mount type coil composed of an insulating substrate 11 on which a copper thin film 12 is formed. However, as shown in FIG. 13, the inductor element 1 is formed by winding a metal wire for one turn or more. An air core or an iron core coil may be used.

  The inductor element 1 is pressure-bonded to a connection pad (not shown) provided on the upper end surface of the analog circuit chip 4 using, for example, copper bumps.

  Next, an example of a structure in which a surface mount type coil is used as the inductor element 1 will be described with reference to FIG.

  FIG. 14 is a front view, a side view, and a bottom view showing the inductor element 1 in the semiconductor device of this embodiment. The inductor element 1 shown in the figure has substantially the same structure as the inductor element 1 (see FIG. 2) described in the first embodiment, but the inductor element 1 is attached to the analog circuit chip 4. The configuration of the conductor pads is different. Here, both terminals of the inductor element 1 are arranged on both sides of the insulating substrate 11 of the inductor element 1. That is, the connecting portion between the inductor element 1 and the analog circuit chip (second chip) 4 is provided with two conductor pads separated from each other by a distance corresponding to the insulating substrate 11 on the upper end surface of the analog circuit chip 4. The conductor pad is connected to the connection surface 17 of the inductor element 1.

  According to this configuration, in addition to the effects described in the second embodiment, it is possible to reduce the height of the package when the entire chip is finally incorporated into the package. Further, there is an advantage that a heat radiating plate for releasing heat generated when the analog circuit chip operates at a high frequency can be attached at a short distance from the chip.

  The present invention is not limited to the embodiment described above, and various modifications are possible, and these are also included in the scope of the present invention.

  Moreover, you may combine arbitrarily the component of embodiment demonstrated above in the range which does not deviate from the meaning of this invention.

  A semiconductor device which is an example of the present invention can be used for various electronic devices as a semiconductor device in which an inductor element is mounted and an integrated circuit chip is stacked.

DESCRIPTION OF SYMBOLS 1 Inductor element 2 Logic circuit chip 3 Bonding pad 4 Analog circuit chip 5 Memory circuit chip 11 Insulating substrate 12, 13 Copper thin film 14 Through-hole plating 15 Gold bump 16a, 16b Connection pad 17 Connection surface 57, 127 Transformer 57a Primary coil 57b Two Next coil 102 Semiconductor substrate 105, 105c Connection pad 107, 125c, 125d Inductor 114 Interlayer insulating film 121 Spiral wiring 121a, 121b Spiral wiring 126 Differential inductor 130 First layer wiring 132 Second layer wiring

Claims (15)

A first chip having a main surface on which an integrated circuit is formed;
At least one second chip having a main surface on which the integrated circuit is formed and being stacked on the first chip;
An inductor element mounted on any one of the first chip and the second chip and having an inductor;
The inductor element generates a magnetic field in a direction substantially parallel to both the main surface of the first chip and the main surface of the second chip inside the inductor,
The semiconductor device in which the second chip is not arranged on the first chip in a direction of a magnetic field generated inside the inductor when viewed from the inductor element. The semiconductor device according to claim 1,
The inductor element is mounted on the first chip, and generates a magnetic field in a direction substantially parallel to an end face of the second chip facing the inductor element inside the inductor. A semiconductor device characterized by the above. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the inductor element is mounted on a chip located at an uppermost portion of the second chip. The semiconductor device according to any one of claims 1 to 3,
A chip on which the inductor element is mounted is electrically connected to both terminals of the inductor. The semiconductor device according to claim 4,
Two conductor pads are provided on the main surface of the chip on which the inductor element is mounted,
Both terminals of the inductor are connected to conductor pads corresponding to the two conductor pads, respectively. The semiconductor device according to claim 4,
Two conductor pads are provided on the upper end surface of the chip on which the inductor element is mounted,
Both terminals of the inductor are connected to conductor pads corresponding to the two conductor pads, respectively. In the semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the inductor is constituted by a winding of one turn or more. In the semiconductor device according to any one of claims 1 to 7,
A semiconductor device, wherein a plurality of the inductor elements are mounted on any one of the first chip and the second chip. The semiconductor device according to claim 8,
The plurality of inductor elements are arranged so as not to cause inductive coupling. The semiconductor device according to claim 9.
The semiconductor device, wherein the plurality of inductor elements constitute a differential inductor. The semiconductor device according to claim 8,
The semiconductor device, wherein the plurality of inductor elements are arranged so that inductive coupling occurs. The semiconductor device according to claim 11,
The semiconductor device, wherein the inductors of the plurality of inductor elements constitute a transformer. In the semiconductor device according to any one of claims 1 to 7,
The inductor device has a plurality of the inductors. The semiconductor device according to claim 13,
The plurality of inductors constitute a differential inductor. The semiconductor device according to claim 13,
The plurality of inductors included in the inductor element constitute a transformer.

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