JPWO2020084928A1 - Inductor elements and semiconductor devices - Google Patents

Abstract

Provided are an inductor element and a semiconductor device capable of miniaturization. The inductor element is arranged so as to face the first semiconductor chip having the first inductor and the first semiconductor chip, and is placed on at least one of the second semiconductor chip having the second inductor and the first semiconductor chip or the second semiconductor chip. It is provided and includes a connection portion for electrically connecting the first inductor and the second inductor. The first inductor and the second inductor face each other. The direction in which the current flows in the first inductor and the direction in which the current flows in the second inductor are the same directions.

Description

The present disclosure relates to inductor elements and semiconductor devices.

Patent Document 1 discloses that the high frequency characteristics (Q factor) of the inductor is improved by utilizing the wafer level package technology and applying the differential inductor to the rewiring layer.

Japanese Unexamined Patent Publication No. 2004-335761

In order to increase the inductance of the inductor, it is necessary to increase the number of turns of the inductor and increase the size of the inductor. In an inductor element or a semiconductor device including an inductor, if the area of the inductor increases, miniaturization may be hindered.

The present disclosure has been made in view of such circumstances, and an object of the present invention is to provide an inductor element and a semiconductor device capable of miniaturization.

One aspect of the present disclosure is an aspect of a first semiconductor chip having a first inductor, a second semiconductor chip arranged to face the first semiconductor chip and having a second inductor, and the first semiconductor chip or the second semiconductor chip. A connection portion provided on at least one of the semiconductor chips and electrically connecting the first inductor and the second inductor is provided, and the direction in which the current flows in the first inductor and the current in the second inductor are provided. The flow directions are inductor elements that are in the same direction as each other.

According to this, the direction of the magnetic flux generated by the current flowing through the first inductor and the direction of the magnetic flux generated by the current flowing through the second inductor are the same directions. As a result, a stack structure inductor in which the first inductor of the first semiconductor chip and the second inductor of the second semiconductor chip are magnetically coupled is formed in the inductor element.

The stacked structure inductor can reduce the area in a plan view from the thickness direction as compared with the non-stack structure inductor. Further, the inductance is increased by magnetically coupling the first inductor and the second inductor. As a result, the inductor element can reduce the area per unit inductance, so that the inductor element can be miniaturized.

The first inductor and the second inductor have the same single-layer winding ratio per unit area (for example, the first inductor and the second inductor are made of the same material, have the same shape, and are the same. In the case of having a size), when the first inductor and the second inductor are magnetically coupled, the inductance of the magnetically coupled inductor is ideally squared (n ² ) times the number of stacks n. For example, when the second inductor is stacked on the first inductor to form a stack structure inductor, the number of stacks n is 2. In this case, when the first inductor and the second inductor are magnetically coupled, the inductance of the stack structure inductor, ideally, the 4 (= 2 ²⁾ times the inductance of the first inductor. This means that the area per unit inductance is ideally 1/4 times the area of the first inductor.

Further, when the second inductor and the third inductor are stacked on the first inductor to form a stack structure inductor, the number of stacks n is 3. In this case, when the first inductor and the second inductor and the third inductor are magnetically coupled, the inductance of the stack structure inductor, ideally, the 9 (= 3 ²⁾ times the inductance of the first inductor. This means that the area per unit inductance is ideally 1/9 times the area of the first inductor.

Another aspect of the present disclosure is a second semiconductor chip having a first inductor and a first semiconductor element, and a second semiconductor chip arranged to face the first semiconductor chip and having a second inductor and a second semiconductor element. And a connection portion provided on at least one of the first semiconductor chip or the second semiconductor chip and electrically connecting the first inductor and the second inductor, the first inductor and the first inductor. A semiconductor device in which the two inductors face each other and the direction in which the current flows in the first inductor and the direction in which the current flows in the second inductor are the same as each other.

According to this, the direction of the magnetic flux generated by the current flowing through the first inductor and the direction of the magnetic flux generated by the current flowing through the second inductor are the same directions. As a result, a stack structure inductor in which the first inductor of the first semiconductor chip and the second inductor of the second semiconductor chip are magnetically coupled is formed in the semiconductor device. The stacked structure inductor can reduce the area in a plan view from the thickness direction as compared with the non-stack structure inductor. Further, the inductance of the inductor increases due to the magnetic field coupling between the first inductor and the second inductor. As a result, the semiconductor device can reduce the area per unit inductance. Therefore, the semiconductor device can be miniaturized.

FIG. 1 is a perspective view schematically showing a configuration example of an inductor element according to the first embodiment of the present disclosure. FIG. 2 is a perspective view schematically showing the stack structure inductor according to the first embodiment of the present disclosure. FIG. 3A is a plan view showing a configuration example of the second inductor according to the first embodiment of the present disclosure. FIG. 3B is a plan view showing a configuration example of the first inductor according to the first embodiment of the present disclosure. FIG. 4 is a cross-sectional view showing a configuration example of the inductor element according to the first embodiment of the present disclosure. FIG. 5 is a cross-sectional view showing a configuration example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 6 is a cross-sectional view showing a configuration example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 7 is a plan view showing a configuration example 1 of the connection portion according to the first embodiment of the present disclosure. FIG. 8 is a plan view showing a configuration example 2 of the connection portion according to the first embodiment of the present disclosure. FIG. 9A is a plan view showing a modification 1 of the second inductor according to the first embodiment of the present disclosure. FIG. 9B is a plan view showing a modification 1 of the first inductor according to the first embodiment of the present disclosure. FIG. 10A is a plan view showing a modification 2 of the second inductor according to the first embodiment of the present disclosure. FIG. 10B is a plan view showing a modification 2 of the first inductor according to the first embodiment of the present disclosure. FIG. 11A is a plan view showing a modification 3 of the second inductor according to the first embodiment of the present disclosure. FIG. 11B is a plan view showing a modification 3 of the first inductor according to the first embodiment of the present disclosure. FIG. 12A is a plan view showing a modification 4 of the second inductor according to the first embodiment of the present disclosure. FIG. 12B is a plan view showing a modification 4 of the first inductor according to the first embodiment of the present disclosure. FIG. 13 is a cross-sectional view showing a modification 4 of the inductor element according to the first embodiment of the present disclosure. FIG. 14A is a plan view showing a modification 5 of the second inductor according to the first embodiment of the present disclosure. FIG. 14B is a plan view showing a modification 5 of the first inductor according to the first embodiment of the present disclosure. FIG. 15 is a plan view showing a modification 6 of the first inductor according to the first embodiment of the present disclosure. FIG. 16 is a plan view showing a modification 7 of the first inductor according to the first embodiment of the present disclosure. FIG. 17 is a perspective view schematically showing a configuration example of the inductor element according to the second embodiment of the present disclosure. FIG. 18 is a cross-sectional view showing a configuration example of the inductor element according to the second embodiment of the present disclosure. FIG. 19 is a cross-sectional view showing a configuration example of the inductor element according to the second embodiment of the present disclosure. FIG. 20 is a perspective view schematically showing a configuration example of the inductor element according to the third embodiment of the present disclosure. FIG. 21 is a cross-sectional view showing a configuration example of the inductor element according to the third embodiment of the present disclosure. FIG. 22 is a cross-sectional view showing a configuration example of the inductor element according to the third embodiment of the present disclosure. FIG. 23A is a plan view showing a configuration example of the second inductor according to the fourth embodiment of the present disclosure. FIG. 23B is a plan view showing a configuration example of the first inductor according to the fourth embodiment of the present disclosure. FIG. 24 is a diagram showing a connection example of the first inductor 10, the second inductor 20, and the third inductor 30 according to other embodiments of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each layer, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that the drawings include parts having different dimensional relationships and ratios from each other.

Further, the definition of the vertical direction in the following description is merely a definition for convenience of explanation, and does not limit the technical idea of the present disclosure. For example, if the object is rotated by 90 ° and observed, the top and bottom are converted to left and right and read, and if the object is rotated by 180 ° and observed, the top and bottom are reversed and read.

Further, in the following description, the direction may be described by using the wording in the X-axis direction, the Y-axis direction, and the Z-axis direction. For example, the X-axis direction and the Y-axis direction are directions parallel to the front surface 1a (see FIGS. 1 and 4) of the first semiconductor chip 1 described later. Further, the X-axis direction and the Y-axis direction are also directions parallel to the front surface 2a (see FIGS. 1 and 4) of the second semiconductor chip 2 described later. The Z-axis direction is the normal direction of the front surface 1a and also the normal direction of the front surface 2a. The Z-axis direction is also the thickness direction of the inductor element. The Z-axis direction is orthogonal to the X-axis direction, the Y-axis direction, and the Z-axis direction. Further, in the following description, "planar view" means viewing from the Z-axis direction.

(Embodiment 1)
FIG. 1 is a perspective view schematically showing a configuration example of an inductor element according to the first embodiment of the present disclosure. FIG. 2 is a perspective view schematically showing the stack structure inductor according to the first embodiment of the present disclosure. FIG. 3A is a plan view showing a configuration example of the second inductor according to the first embodiment of the present disclosure. FIG. 3B is a plan view showing a configuration example of the first inductor according to the first embodiment of the present disclosure. FIG. 4 is a cross-sectional view showing a configuration example of the inductor element according to the first embodiment of the present disclosure. FIG. 4 corresponds to a cross section obtained by cutting each of the figures shown in FIGS. 3A and 3B along the A1-A2 line.

As shown in FIG. 1, the inductor element 100 according to the first embodiment includes a first semiconductor chip 1 having a first inductor 10 and a second semiconductor chip 2 having a second inductor 20. The first inductor 10 and the second inductor 20 are made of a metal such as copper (Cu). The inductor element 100 is formed by joining the front surface (upper surface in FIG. 1) 1a of the first semiconductor chip 1 and the front surface (lower surface (lower surface) 2a in FIG. 1) of the second semiconductor chip 2 to each other. It is formed.

In each of the figures described in the embodiments of the present disclosure, the first semiconductor chip 1 is located on the lower side and the second semiconductor chip 2 is located on the upper side. Therefore, the first semiconductor chip 1 may be referred to as a lower semiconductor chip, and the second semiconductor chip 2 may be referred to as an upper semiconductor chip. Further, for the same reason, the first inductor 10 may be referred to as a lower inductor, and the second inductor 20 may be referred to as an upper inductor.

As shown in FIG. 2, the inductor element 100 includes a connection portion CT that electrically and physically connects the first inductor 10 and the second inductor 20. "Electrically and physically connected" means that the objects are connected to each other in a conductive state and fixed to each other. The connecting portion CT includes a connecting portion 14 (see FIG. 4) and a connecting portion 24 (see FIG. 4) that electrically and physically connects the connecting portion 14. The connecting portion CT is made of a metal such as copper (Cu). The joining of the connecting portions 14 and 24 is, for example, a Cu-Cu joining. In the inductor element 100 according to the first embodiment, the first inductor 10 of the first semiconductor chip 1 and the second inductor 20 of the second semiconductor chip 2 are connected in series via the connection portion CT, whereby the first inductor is connected. A two-layer winding stack structure inductor 50 in which the 10 and the second inductor 20 are stacked is formed.

As shown in FIGS. 2 and 3B, the shape of the first inductor 10 in a plan view (hereinafter referred to as a plan shape) is a square spiral shape. The first inductor 10 has a conducting wire portion P10, an end portion P11 located at one end of the conducting wire portion P10, and an end portion P12 located at the other end of the conducting wire portion P10. In a plan view, the end portion P11 is located on the outer peripheral side of the first inductor 10, and the end portion P12 is located near the center portion of the first inductor 10. The connecting portion 14 extends from the end portion P12 in the positive direction of the Z axis (that is, in the direction of the arrow).

As shown in FIGS. 2 and 3A, the planar shape of the second inductor 20 is a square spiral shape. The second inductor 20 has a conducting wire portion P20, an end portion P21 located at one end of the conducting wire portion P20, and an end portion P22 located at the other end of the conducting wire portion P20. In a plan view, the end portion P21 is located near the center of the second inductor 20, and the end portion P22 is located on the outer peripheral side of the second inductor 20. The connecting portion 24 extends from the end portion P21 in the negative direction of the Z axis (that is, in the direction opposite to the arrow).

In the inductor element 100, for example, a positive bias is applied to the end P11 of the first inductor 10, and a ground potential or a negative bias is applied to the end P22 of the second inductor 20. As a result, the current I flows from the end P11 of the first inductor 10 to the end P22 of the second inductor 20 via the connection CT. In the first inductor 10 and the second inductor 20, the current I flows in the same direction as each other. As a result, the direction of the magnetic flux B1 generated by the current I flowing through the first inductor 10 and the direction of the magnetic flux B2 generated by the current I flowing through the second inductor 20 are the same.

For example, FIG. 2 shows a case where the current I flows clockwise in the first inductor 10 and the second inductor 20, respectively. In this case, the direction of the magnetic flux B1 generated at the center of the spiral of the first inductor 10 and the direction of the magnetic flux B2 generated at the center of the spiral of the second inductor 20 are negative directions of the Z axis, respectively.

Further, FIGS. 3A and 3B show a case where the current I flows counterclockwise in the first inductor 10 and the second inductor 20, respectively. In this case, the direction of the magnetic flux B1 generated at the center of the spiral of the first inductor 10 and the direction of the magnetic flux B2 generated at the center of the spiral of the second inductor 20 are each in the positive direction of the Z axis.

As shown in FIG. 4, in the inductor element 100, the first semiconductor chip 1 includes a semiconductor substrate 11 and an insulating film 12 provided on the front surface 11a (upper surface in FIG. 4) side of the semiconductor substrate 11. The first semiconductor 10 is electrically and physically connected to the first inductor 10 provided on the insulating film 12, the insulating film 13 provided on the insulating film 12 and covering the first inductor 10, and the first inductor 10. It has a connecting portion 14 exposed on the front surface 1a of the chip 1. The side surface of the connecting portion 14 is covered with the insulating film 13. The semiconductor substrate 11 is a single crystal silicon substrate. The insulating films 12 and 13 are silicon oxide films. The first inductor 10 and the connecting portion 14 may be formed by a single damascene method or a dual damascene method.

The second semiconductor chip 2 includes a semiconductor substrate 21, an insulating film 22 provided on the front surface 21a (lower surface in FIG. 4) side of the semiconductor substrate 21, and a second inductor 20 provided on the insulating film 22. The insulating film 23 provided on the insulating film 22 and covering the second inductor 20 and the second inductor 20 are electrically and physically connected to each other, and the front surface 2a of the second semiconductor chip 2 (in FIG. 4). , The lower surface) has a connecting portion 24 exposed. The side surface of the connecting portion 24 is covered with the insulating film 23. The semiconductor substrate 21 is a single crystal silicon substrate. The insulating films 22 and 23 are silicon oxide films. The second inductor 20 and the connection portion 24 may be formed by a single damascene method or a dual damascene method.

As shown in FIGS. 3A to 4, the first inductor 10 and the second inductor 20 face each other in the Z-axis direction. Further, the first inductor 10 and the second inductor 20 are electrically connected via the connection portion CT. Further, in the first inductor 10 and the second inductor 20, the directions in which the current I flows are the same as each other. As a result, the magnetic fluxes B1 and B2 generated by electromagnetic induction are oriented in the same direction, and the first inductor 10 and the second inductor 20 are magnetically coupled.

As shown in FIG. 4, the wire width W1 of the conductor portion P10 of the first inductor 10 and the wire width W2 of the conductor portion P20 of the second inductor 20 have the same length (W1 = W2). Further, the distance S1 between one adjacent conductor P10 and the other conductor P10 and the distance S2 between one adjacent conductor P20 and the other conductor P20 also have the same length. Yes (S1 = S2). Since the conducting wire portion P10 and the conducting wire portion P20 have L / S (Line & Space) aligned, it is easy to face each other. It is easy to design the inductor element 100 so that the conductor portion P10 and the conductor portion P20 face each other.

5 and 6 are cross-sectional views showing a configuration example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 5 shows a state before the first semiconductor chip 1 and the second semiconductor chip 2 are joined. FIG. 6 shows a state after the first semiconductor chip 1 and the second semiconductor chip 2 are joined.

As shown in FIGS. 5 and 6, the semiconductor device 200 according to the first embodiment includes a first semiconductor chip 1 and a second semiconductor chip 2. In the semiconductor device 200, the first semiconductor chip 1 has a transistor Tr1, a wiring layer 15, and a dummy electrode 16. For example, the transistor Tr1 is provided on the front surface 11a (upper surface in FIGS. 5 and 6) of the semiconductor substrate 11. The insulating film 12 is composed of a plurality of layers, and a wiring layer 15 is arranged between the layers.

The insulating film 13 is composed of a plurality of layers. The connecting portion 14 is also composed of a plurality of conductive layers 141, 142, 143, 144. The conductive layers 141, 142, 143, 144 are electrically and physically connected to each other. Conductive layers 141, 142, and 143 are arranged between the layers constituting the insulating film 13. The conductive layer 144, which is the uppermost layer of the connecting portion 14, is exposed from the front surface 1a of the first semiconductor chip 1.

The dummy electrode 16 is exposed from the front surface 1a of the first semiconductor chip 1. The dummy electrode 16 is a floating electrode that is not electrically connected to anything. Alternatively, the dummy electrode 16 may be fixed to the ground potential via a wiring (not shown). The conductive layer 144 and the dummy electrode 16 are made of the same material and are provided in the same layer. The conductive layer 144 and the dummy electrode 16 may be formed at the same time in the same step.

Similarly, in the semiconductor device 200, the second semiconductor chip 2 has a transistor Tr2, a wiring layer 25, and a dummy electrode 26. For example, the transistor Tr2 is provided on the front surface (lower surface in FIGS. 5 and 6) 21a side of the semiconductor substrate 21. The insulating film 22 is composed of a plurality of layers, and a wiring layer 25 is arranged between the layers.

The insulating film 23 is composed of a plurality of layers. The connecting portion 24 is also composed of a plurality of conductive layers 241, 242, 243, and 244. The conductive layers 241, 242, 243, and 244 are electrically and mechanically connected to each other. Conductive layers 241 and 242, 243 are arranged between the layers constituting the insulating film 13. The conductive layer 244, which is the uppermost layer of the connecting portion 24, is exposed from the front surface 1a of the first semiconductor chip 1.

The dummy electrode 26 is exposed from the front surface 1a of the first semiconductor chip 1. The dummy electrode 26 is a floating electrode that is not electrically connected to anything. Alternatively, the dummy electrode 26 may be fixed to the ground potential via a wiring (not shown). The conductive layer 244 and the dummy electrode 26 are made of the same material and are provided in the same layer. The conductive layer 244 and the dummy electrode 26 are formed at the same time in the same process.

As shown in FIG. 6, also in the semiconductor device 200, the front surface 1a of the first semiconductor chip 1 and the front surface 2a of the second semiconductor chip 2 are joined to each other, and the first semiconductor chip 1 and the first semiconductor chip 1 and the first semiconductor chip 2 are joined to each other. 2 The semiconductor chip 2 is integrated.

For example, the bonding device makes the front surface 1a of the first semiconductor chip 1 and the front surface 2a of the second semiconductor chip 2 face each other. Then, in the manufacturing apparatus, the first semiconductor chip 1 and the second semiconductor chip 2 are brought into close contact with each other and heat-treated. As a result, the insulating films 13 and 23 are joined in close contact with each other, and the connecting portions 14 and 24 are also joined in close contact with each other. The connecting portions 14 and 24 are electrically and mechanically joined to each other to form a connecting portion CT. Further, the dummy electrodes 16 and 26 are also joined in close contact with each other. The joints of the connecting portions 14 and 24 are Cu-Cu joints. The bonding of the dummy electrodes 16 and 26 is also a Cu-Cu bonding. Since not only the connecting portions 14 and 24 but also the dummy electrodes 16 and 26 are Cu-Cu bonded, the bonding strength between the first semiconductor chip 1 and the second semiconductor chip 2 is higher than that in the case where the dummy electrodes 16 and 26 are not provided. Can be improved.

The semiconductor device 200 is, for example, a back-illuminated CMOS solid-state image sensor. In this case, the second semiconductor chip 2 may be a pixel chip and the first semiconductor chip 1 may be a logic chip. The transistor Tr2 included in the second semiconductor chip 2 may be a pixel transistor included in the pixels. The transistor Tr1 included in the first semiconductor chip 1 may be a transistor included in the control circuit. A color filter or an on-chip lens may be arranged on the back surface 2b side of the second semiconductor chip 2.

Further, the semiconductor device 200 is not limited to the solid-state image sensor. The semiconductor device 200 may be a device other than the solid-state image pickup device, such as a display device.

FIG. 7 is a plan view showing a configuration example 1 of the connection portion according to the first embodiment of the present disclosure. FIG. 8 is a plan view showing a configuration example 2 of the connection portion according to the first embodiment of the present disclosure. 7 and 8 show the region AR1 including the connection portion 14 shown in FIG. As shown in FIGS. 7 and 8, there may be a plurality of connecting portions 14 that are electrically connected to the first inductor 10. Similarly, there may be a plurality of connection portions 24 that are electrically connected to the second inductor 20. By increasing the number of the connecting portions 14 and 24 (that is, the connecting portion CT) or increasing the diameter thereof, the connection resistance between the first inductor 10 and the second inductor 20 can be reduced. By reducing the connection resistance between the first inductor 10 and the second inductor 20, the Q value (Quality Factor: quality coefficient) of the inductor element 100 can be increased.

As described above, the inductor element 100 according to the first embodiment of the present disclosure is arranged so as to face the first semiconductor chip 1 having the first inductor 10 and the first semiconductor chip 1 and has the second inductor 20. A connection portion CT provided on at least one of the second semiconductor chip 2 and the first semiconductor chip 1 or the second semiconductor chip 2 and electrically connecting the first inductor and the second inductor 20 is provided. The first inductor 10 and the second inductor 20 face each other. The direction in which the current I flows in the first inductor 10 and the direction in which the current I flows in the second inductor 20 are the same directions.

According to this, the direction of the magnetic flux B1 generated by the current flowing through the first inductor 10 and the direction of the magnetic flux B2 generated by the current I flowing through the second inductor 20 are the same directions. As a result, the stack structure inductor 50 in which the first inductor 10 of the first semiconductor chip 1 and the second inductor 20 of the second semiconductor chip 2 are magnetically coupled is formed in the inductor element 100. The stacked structure inductor 50 can reduce the area in a plan view from the Z-axis direction as compared with the non-stack structure inductor 50. Further, the inductance is increased by magnetically coupling the first inductor 10 and the second inductor 20. As a result, the inductor element 100 can be reduced in size because the area per unit inductance can be reduced.

For example, the equation (i) holds between the inductance L1 of the first inductor 10 and the inductance L2 of the second inductor 20 and the inductance L2 of the stack structure inductor 50.

Ltotal = L1 + L2 + 2M ... (i)
2M: Mutual inductance

In the stack structure inductor 50, when the first inductor 10 and the second inductor 20 are magnetically coupled, the mutual inductance of the equation (i) can be brought close to the value of L1 + L2 (2M≈L1 + L2). As a result, the inductor element 100 can bring the inductance close to four times without increasing the occupied area of the inductor. This means that the occupied area of the inductor can be reduced to nearly 1/4 times without reducing the inductance. Therefore, the inductor element 50 can be miniaturized and the semiconductor device 200 can be miniaturized.

Further, the connection portion CT is provided on the first semiconductor chip 1 and is provided on the first connection portion (for example, the connection portion 14) electrically connected to the first inductor 10 and the second semiconductor chip 2 and is provided on the second semiconductor chip 2. It has a second connection portion (for example, a connection portion 24) that is electrically connected to the inductor 20. The connecting portion 24 is exposed from the front surface 1a of the first semiconductor chip 1. The connecting portion 24 is exposed from the front surface 2a of the second semiconductor chip 2. The front surfaces 1a and 2a face each other. The connecting portions 14 and 24 are joined to each other. According to this, the connection portion CT can be formed by using the wiring technique of the wafer process or the rewiring technique of the wafer level package.

Further, the connecting portions 14 and 24 are composed of the same metal element (for example, Cu) as each other.
According to this, since the bonding between the connecting portions 14 and 24 can be a Cu-Cu bonding, it is possible to improve the bonding strength between the connecting portions 14 and 24.

(Modification example)
In the first embodiment described above, it has been described that the planar shapes of the first inductor 10 and the second inductor 20 are square spiral shapes. However, in the embodiment of the present disclosure, the planar shapes of the first inductor 10 and the second inductor 20 are not limited to this.

FIG. 9A is a plan view showing a modification 1 of the second inductor according to the first embodiment of the present disclosure. FIG. 9B is a plan view showing a modification 1 of the first inductor according to the first embodiment of the present disclosure. As shown in FIG. 9A, the planar shape of the second inductor 20 may be an octagonal spiral shape. As shown in FIG. 9B, the planar shape of the first inductor 10 may also be an octagonal spiral shape. The first inductor 10 and the second inductor 20, which have the same or substantially the same planar shape, can face each other, and the directions of the magnetic fluxes B1 and B2 generated by electromagnetic induction can be the same.

FIG. 10A is a plan view showing a modification 2 of the second inductor according to the first embodiment of the present disclosure. FIG. 10B is a plan view showing a modification 2 of the first inductor according to the first embodiment of the present disclosure. As shown in FIG. 10A, the planar shape of the second inductor 20 may be a hexagonal spiral shape. As shown in FIG. 10B, the planar shape of the first inductor 10 may also be a hexagonal spiral shape. The first inductor 10 and the second inductor 20, which have the same or substantially the same planar shape, can face each other, and the directions of the magnetic fluxes B1 and B2 generated by electromagnetic induction can be the same.

FIG. 11A is a plan view showing a modification 3 of the second inductor according to the first embodiment of the present disclosure. FIG. 11B is a plan view showing a modification 3 of the first inductor according to the first embodiment of the present disclosure. As shown in FIG. 11A, the planar shape of the second inductor 20 may be a circular spiral shape. As shown in FIG. 11B, the planar shape of the first inductor 10 may also be a circular spiral shape. The first inductor 10 and the second inductor 20, which have the same or substantially the same planar shape, can face each other, and the directions of the magnetic fluxes B1 and B2 generated by electromagnetic induction can be the same.

Further, in the embodiment of the present disclosure, the planar shape of the first inductor 10 and the second inductor 20 may be a loop shape instead of a spiral shape.

FIG. 12A is a plan view showing a modification 4 of the second inductor according to the first embodiment of the present disclosure. FIG. 12B is a plan view showing a modification 4 of the first inductor according to the first embodiment of the present disclosure. As shown in FIG. 12A, the planar shape of the second inductor 20 is an Arabic numeral eight, and the first loop R21 and the second loop R22 may be arranged adjacent to each other. The second inductor 20 has a conducting wire portion P20A composed of only the second metal layer 202, and a conducting wire portion P20B composed of the first metal layer 201 and the second metal layer 202. The end P21 is located at one end of the conductor P20A, and the end P23 is located at the other end of the conductor P20A. The end P22 is located at one end of the conductor P20B, and the end P24 is located at the other end of the conductor P20B. The conductor portion P20A and the conductor portion P20B intersect at two points. In the conductor portion P20B, the portion intersecting with the conductor portion P20A is composed of the first metal layer 201, and the other portion is composed of the second metal layer 202.

As shown in FIG. 12B, the planar shape of the first inductor 10 is also an Arabic numeral eight shape, and the first loop R11 and the second loop R12 may be arranged adjacent to each other. The first inductor 10 has a conducting wire portion P10 composed of a first metal layer 101 and a second metal layer 102. The end P11 is located at one end of the conductor P10, and the end P12 is located at the other end of the conductor P10. The end portion P11 of the first inductor 10 is electrically connected to the end portion P21 of the second inductor 10 via the connection portion CT. The end portion P12 of the first inductor 10 is electrically connected to the end portion P22 of the second inductor 10 via the connection portion CT.

FIG. 13 is a cross-sectional view showing a modification 4 of the inductor element according to the first embodiment of the present disclosure. FIG. 13 corresponds to a cross section obtained by cutting each of the figures shown in FIGS. 12A and 12B along the B1-B2 line. As shown in FIG. 13, the insulating film 13 of the first semiconductor chip 1 is provided on the first insulating film 131, which is provided on the insulating film 12 and covers the first metal layer 101, and on the first insulating film 131. It has a second insulating film 132 that covers the second metal layer 102. The first insulating film 131 is provided with a through hole H131. The second metal layer 102 is electrically connected to the first metal layer 101 through the through hole H131. As shown in FIG. 13, the first insulating film 131 is arranged between the first metal layer 101 and the second metal layer 102 in the region where the conducting wire portions P10 intersect. This prevents the upper and lower conductors P10 from being short-circuited in the region where the conductors P10 intersect.

As shown in FIG. 13, the insulating film 23 is provided on the insulating film 22 (lower in FIG. 13) and covers the first metal layer 201 and the first insulating film 231 and the first insulating film 231 (FIG. 13). Then, it has a second insulating film 232 provided on the lower side) and covering the second metal layer 202. The first insulating film 231 is provided with a through hole H231. The second metal layer 202 is electrically connected to the first metal layer 201 through the through hole H231. As shown in FIG. 23, in the region where the conductor portion P20A and the conductor portion P20B intersect, between the second metal layer 202 constituting the conductor portion P20A and the first metal layer 201 constituting the conductor portion P20B. , The first insulating film 231 is arranged. This prevents the conductor portion P20A and the conductor portion P20B from being short-circuited in the region where the conductor portion P20A and the conductor portion P20B intersect.

In the embodiment shown in FIGS. 12A to 13, for example, a positive bias is applied to the end P23 of the second inductor 20, and a ground potential or a negative bias is applied to the end P24. As a result, the current I flows from the end portion P23 of the second inductor 20 to the end portion P11 of the first inductor 10 via the conductor portion P20A, the end portion P21, and the connection portion CT. Further, a current flows from the end portion P11 of the first inductor to the end portion P22 of the second inductor via the conductor portion P10, the end portion P12, and the connection portion CT. A current flows from the end P22 of the second inductor 20 to the end P24 via the conductor P20B.

In the embodiment shown in FIGS. 12A to 13, the first loop R11 of the first inductor 10 and the first loop R21 of the second inductor 20 face each other in the Z-axis direction. In the first loop R11 and the second loop R12, the directions in which the current flows are the same and are clockwise. Therefore, the direction of the magnetic flux B11 generated in the central portion of the first loop R11 by electromagnetic induction and the direction of the magnetic flux B21 generated in the central portion of the first loop R21 by electromagnetic induction are in the same direction (negative direction of the Z axis). Become.

Similarly, in the embodiment shown in FIGS. 12A to 13, the second loop R12 of the first inductor 10 and the second loop R22 of the second inductor 20 face each other in the Z-axis direction. In the second loops R12 and R22, the directions in which the current flows are the same as each other and are in the counterclockwise direction. Therefore, the direction of the magnetic flux B12 generated in the central portion of the second loop R12 by the electromagnetic induction and the direction of the magnetic flux B22 generated in the central portion of the second loop R22 by the electromagnetic induction are the same directions (the positive direction of the Z axis). Become.

FIG. 14A is a plan view showing a modification 5 of the second inductor according to the first embodiment of the present disclosure. FIG. 14B is a plan view showing a modification 5 of the first inductor according to the first embodiment of the present disclosure. As shown in FIG. 14A, the second inductor 20 may be a differential inductor. As shown in FIG. 14B, the first inductor 10 may also be a differential inductor. The differential inductor has a structure in which the conducting wires are symmetrical, and the electrical characteristics are also symmetrical. Even when the first inductor 10 and the second inductor 20 are differential inductors, if the planar shapes of the first inductor 10 and the second inductor 20 are the same or substantially the same, they face each other in the Z-axis direction. Can be done. As a result, the directions of the magnetic fluxes B1 and B2 generated by electromagnetic induction are the same as each other.

FIG. 15 is a plan view showing a modification 6 of the first inductor according to the first embodiment of the present disclosure. As shown in FIG. 15, the center tap 103 may be electrically connected to the first inductor 10. The center tap 103 is a wiring for pulling out. One end of the center tap 103 is electrically connected to the intermediate position (neutral point) P10C in the current path of the conducting wire portion P10. According to this, the first inductor 10 has two inductors having the same characteristics built-in between the end portion P11 and the intermediate position P10C and between the intermediate position P10C and the end portion P12. Therefore, the occupied area of the inductor in the first semiconductor chip 1 can be reduced as compared with the case where two inductors having the same characteristics are separately arranged on the first semiconductor chip 1.

The center tap may also be electrically connected to the second inductor 20 (see FIG. 1). Further, even if one end of a third inductor prepared separately from the first inductor 10 and the second inductor 20 is connected to the center tap 103 connected to the first inductor 10 and the center tap connected to the second inductor 20. good.

FIG. 16 is a plan view showing a modification 7 of the first inductor according to the first embodiment of the present disclosure. As shown in FIG. 16, in the planar shape of the first inductor 10, four loops (first loop R11, second loop R12, third loop R13, and fourth loop R14) are arranged next to each other like a clover leaf. It may have a different shape. The first inductor 10 has a conducting wire portion P10 composed of a first metal layer 101 and a second metal layer 102. The end P11 is located at one end of the conductor P10, and the end P12 is located at the other end of the conductor P10.

Further, the planar shape of the second inductor 20 (see FIG. 2) may also be a shape in which four loops are arranged adjacent to each other like a leaf of a clover, similarly to the first inductor 10. In this case, the end P12 of the first inductor 10 is electrically connected to the end P21 (see FIG. 2) of the second inductor 20 via the connection CT (see FIG. 2).

In the embodiment shown in FIG. 16, the first loop R11 of the first inductor 10 and the first loop of the second inductor 20 face each other in the Z-axis direction. In the first loop R11 of the first inductor 10 and the first loop of the second inductor 20, the directions in which currents flow are the same and clockwise. Therefore, the direction of the magnetic flux B11 generated in the center of the first loop R11 by electromagnetic induction and the direction of the magnetic flux generated in the center of the first loop of the second inductor by electromagnetic induction are in the same direction (negative direction of the Z axis). It becomes.

Similarly, the second loop R12 of the first inductor 10 and the second loop of the second inductor 20 face each other in the Z-axis direction. In the second loop R12 of the first inductor 10 and the second loop of the second inductor 20, the directions in which currents flow are the same and counterclockwise. Therefore, the direction of the magnetic flux B12 generated in the center of the second loop R12 by electromagnetic induction and the direction of the magnetic flux generated in the center of the second loop of the second inductor by electromagnetic induction are in the same direction (positive direction of the Z axis). It becomes.

The third loop R13 of the first inductor 10 and the third loop of the second inductor 20 face each other in the Z-axis direction. In the third loop R13 of the first inductor 10 and the third loop of the second inductor 20, the directions in which currents flow are the same and clockwise. Therefore, the direction of the magnetic flux B13 generated in the center of the third loop R13 by electromagnetic induction and the direction of the magnetic flux generated in the center of the third loop of the second inductor by electromagnetic induction are in the same direction (negative direction of the Z axis). It becomes.

The fourth loop R14 of the first inductor 10 and the fourth loop of the second inductor 20 face each other in the Z-axis direction. In the fourth loop R14 of the first inductor 10 and the fourth loop of the second inductor 20, the directions in which currents flow are the same and counterclockwise. Therefore, the direction of the magnetic flux B14 generated in the center of the fourth loop R14 by electromagnetic induction and the direction of the magnetic flux generated in the center of the fourth loop of the second inductor by electromagnetic induction are in the same direction (positive direction of the Z axis). It becomes.

(Embodiment 2)
In the first embodiment, the first inductor 10 of the first semiconductor chip 1 and the second inductor 20 of the second semiconductor chip 2 are connected in series via the connection portion CT, whereby a two-layer winding stack structure is formed. It has been described that the inductor 50 is formed. However, in the embodiment of the present disclosure, the number of turns of the stack structure inductor is not limited to two layers, and may be three or more layers.

FIG. 17 is a perspective view schematically showing a configuration example of the inductor element according to the second embodiment of the present disclosure. 18 and 19 are cross-sectional views showing a configuration example of the inductor element according to the second embodiment of the present disclosure. FIG. 18 shows a state before the first semiconductor chip 1A and the second semiconductor chip 2 are joined. FIG. 19 shows a state after the first semiconductor chip 1A and the second semiconductor chip 2 are joined.

As shown in FIG. 17, the inductor element 100A according to the second embodiment includes a first semiconductor chip 1A having a first inductor 10 and a rewiring layer inductor 18, a second semiconductor chip 2 having a second inductor 20, and the like. To be equipped. The rewiring layer inductor 18 is formed by utilizing the rewiring layer of the first semiconductor chip 1A, and is made of a metal such as copper (Cu), for example. The planar shape of the rewiring layer inductor 18 is the same as or substantially the same as the planar shape of the first inductor 10. For example, when the planar shape of the first inductor 10 is a square spiral shape, the planar shape of the rewiring layer inductor 18 is also a square spiral shape. In the Z-axis direction, the first inductor 10, the rewiring layer inductor 18, and the second inductor 20 face each other.

As shown in FIGS. 18 and 19, the rewiring layer inductor 18 is provided on the insulating film 13 that covers the first inductor 10. Further, the first semiconductor chip 1A includes an insulating layer 17 provided on the insulating film 13 and covering the side surface of the rewiring layer inductor 18. The insulating layer 17 is made of a resin such as polyimide. The upper surface of the rewiring layer inductor 18 is exposed from the insulating layer 17.

The inductor element 100A is formed by joining the front surface (upper surface in FIG. 18) 1Aa of the first semiconductor chip 1A and the front surface (lower surface in FIG. 18) 2a of the second semiconductor chip 2 to each other. It is formed. In the inductor element 100A, the connection portion 14 of the first semiconductor chip 1A is joined to the rewiring layer inductor 18. The junction between the connection portion 14 and the rewiring layer inductor 18 is, for example, a Cu—Cu junction. Further, the connecting portion 24 of the second semiconductor chip 2 is joined to the rewiring layer inductor 18. The junction between the connection portion 24 and the rewiring layer inductor 18 is, for example, a Cu—Cu junction.

In the inductor element 100A, the first inductor 10 of the first semiconductor chip 1 and the rewiring layer inductor 18 are connected in series via a connecting portion 14. Further, the rewiring layer inductor 18 of the first semiconductor chip 1 and the second inductor 20 of the second semiconductor chip 2 are connected in series via the connecting portion 24. As a result, a three-layer winding stack structure inductor 50A in which the first inductor 10 and the rewiring layer inductor 18 laminated in the first semiconductor chip 1 and the second inductor 20 of the second semiconductor chip are stacked is configured. Has been done.

In the three-layer wound stack structure inductor 50A, the direction in which the current I flows in the first inductor 10, the direction in which the current I flows in the rewiring layer inductor 18, and the direction in which the current I flows in the second inductor 20 are the same. It is the direction.

As described above, according to the inductor element 100A according to the second embodiment, the first semiconductor chip 1 is arranged between the first inductor 10 and the second inductor 20, and the first inductor 10 and the second inductor 20 are arranged. It has a fourth inductor (for example, a rewiring layer inductor 18) that faces each other. As a result, the number of inductor stacks n in the inductor element 100A becomes 3. Further, the direction of the magnetic flux generated in the rewiring layer inductor 18 by electromagnetic induction is the same as the direction of the magnetic flux of the first inductor 10 and the direction of the magnetic flux of the second inductor 20. Therefore, the inductance of the stack structure inductor 50A, can be brought close to the inductance of 9 (= ^{3 2)} times the value of the first inductor 10. Since the occupied area of the inductor can be reduced to nearly 1/9 times without reducing the inductance, the inductor element 100A can be further miniaturized.

In the second embodiment, the rewiring layer inductor may be provided on the second semiconductor chip 20 instead of the first semiconductor chip 10. Further, the rewiring layer inductor may be provided on both the first semiconductor chip 10 and the second semiconductor chip 20. Even in such an embodiment, the number of inductors to be magnetically coupled can be increased. The occupied area of the inductor can be reduced according to the number of inductors to be magnetically coupled, and the inductor element can be further miniaturized.

(Embodiment 3)
In the first embodiment described above, it has been described that the first semiconductor chip having the first inductor and the second semiconductor chip having the second inductor are joined to form a stack structure inductor. However, in the embodiments of the present disclosure, the number of semiconductor chips stacked is not limited to two. In the embodiment of the present disclosure, three or more semiconductor chips having an inductor may be stacked to form a stack structure inductor having three or more layers. Further, the connection between the inductors is not limited to the Cu-Cu junction, and may be performed via a TSV (copper silicon via: Si through electrode), a bump electrode, or a micro bump electrode.

FIG. 20 is a perspective view schematically showing a configuration example of the inductor element according to the third embodiment of the present disclosure. 21 and 22 are cross-sectional views showing a configuration example of the inductor element according to the third embodiment of the present disclosure. FIG. 21 shows a state before the first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3 are joined. FIG. 22 shows a state after the first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3 are joined.

As shown in FIG. 20, the inductor element 100B according to the third embodiment has a first semiconductor chip 1 having a first inductor 10, a second semiconductor chip 2 having a second inductor 20, and a third inductor 30. A third semiconductor chip 3 is provided.

As shown in FIGS. 21 and 22, the third semiconductor chip 3 includes a semiconductor substrate 31, an insulating film 32 provided on the front surface 31a (upper surface in FIG. 21) side of the semiconductor substrate 31, and an insulating film. The third inductor 30 is provided on the insulating film 32, the insulating film 33 is provided on the insulating film 32 and covers the side surface of the third inductor 30, and the semiconductor substrate 31 and the insulating film 32 are penetrated into the third inductor 30. It has a through electrode 34 to be connected. The through silicon via 34 is electrically and physically connected to the third inductor 30. The third inductor 30 is exposed on the front surface 3a of the third semiconductor chip 3. The through electrode 34 is exposed on the back surface 3b of the third semiconductor chip 3. The semiconductor substrate 31 is a single crystal silicon substrate. The insulating films 32 and 33 are silicon oxide films.

The third inductor 30 is made of a metal such as copper (Cu). The third inductor 30 may be formed by the single damascene method. The planar shape of the third inductor 30 is the same as or substantially the same as the planar shape of the first inductor 10. For example, when the planar shape of the first inductor 10 is a square spiral shape, the planar shape of the third inductor 30 is also a square spiral shape. In the Z-axis direction, the first inductor 10, the second inductor 20, and the third inductor 30 face each other.

In the inductor element 100B, the front surface (upper surface in FIG. 21) 1a of the first semiconductor chip 1 and the back surface 3b (lower surface in FIG. 21) of the third semiconductor chip 3 are connected to each other, and the third semiconductor It is formed by connecting the front surface 3a of the chip (upper surface in FIG. 21) and the front surface of the second semiconductor chip 2 (lower surface in FIG. 21) to each other.

In the inductor element 100B, the connection portion 14 of the first semiconductor chip 1 and the through electrode 34 of the third semiconductor chip 3 are joined to form the connection portion CT. The bonding between the connecting portion 14 and the through electrode 34 is, for example, a Cu-Cu bonding. Further, the connecting portion 24 of the second semiconductor chip 2 is joined to the third inductor 30 of the third semiconductor chip 3. The bonding between the connecting portion 24 and the third inductor 30 is, for example, a Cu-Cu bonding.

In the inductor element 100B, the first inductor 10 of the first semiconductor chip 1 and the third inductor 30 of the third semiconductor chip 3 are connected in series via the connection portion CT. Further, the third inductor 30 of the third semiconductor chip 3 and the second inductor 20 of the second semiconductor chip 2 are connected in series via the connecting portion 24. As a result, a three-layer winding stack structure inductor 50B in which the first inductor 10, the second inductor 20, and the third inductor 30 are stacked is configured.

In the three-layer wound stack structure inductor 50B, the direction in which the current I flows in the first inductor 10, the direction in which the current I flows in the third inductor 30, and the direction in which the current I flows in the second inductor 20 are the same directions. It has become.

According to the inductor element 100B according to the third embodiment, the number of stacks n of the inductors is 3. Further, the direction of the magnetic flux generated by the third inductor 30 by electromagnetic induction is the same as the direction of the magnetic flux of the first inductor 10 and the direction of the magnetic flux of the second inductor 20. Therefore, the inductance of the stack structure inductor 50B, the inductance of 9 of the first inductor 10 (= ^{3 2)} can be brought close to the fold. Since the occupied area of the inductor can be reduced to nearly 1/9 times without reducing the inductance, the inductor element 100B can be further miniaturized.

(Embodiment 4)
In the embodiment of the present disclosure, electrodes surrounding the inductor from the outside may be arranged in a plan view. The electrodes may be connected to a fixed potential (eg, ground potential). FIG. 23A is a plan view showing a configuration example of the second inductor according to the fourth embodiment of the present disclosure. FIG. 23B is a plan view showing a configuration example of the first inductor according to the fourth embodiment of the present disclosure. As shown in FIG. 23A, the second semiconductor chip 2 has an annular second electrode 29 that surrounds the second inductor 20 from the outside in a plan view. The second electrode 29 is made of the same material as the second inductor 20, and is provided on the same layer as the second inductor 20. The second electrode 29 is formed at the same time as the second inductor 20 in the same process. The second electrode 29 can block electromagnetic noise around the second inductor 20.

Further, as shown in FIG. 23B, the first semiconductor chip 1 has an annular first electrode 19 that surrounds the first inductor 10 from the outside in a plan view. The first electrode 19 is made of the same material as the first inductor 10, and is provided on the same layer as the first inductor 10. The first electrode 19 is formed at the same time as the first inductor 10 in the same process.

According to the fourth embodiment, the annular second electrode 29 can block electromagnetic noise between the second inductor 20 and the outside of the second inductor 20. The annular first electrode 19 can block electromagnetic noise between the first inductor 10 and the outside of the first inductor 10.

(Other embodiments)
As mentioned above, this disclosure has been described by embodiments and variations, but the statements and drawings that form part of this disclosure should not be understood to limit this disclosure. Various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art from this disclosure.

For example, in the above-described first to third embodiments, it has been described that the first inductor 10, the rewiring layer inductor 18, the second inductor 20, and the third inductor 30 are each composed of Cu. However, in the embodiment of the present disclosure, the materials constituting the first inductor 10, the rewiring layer inductor 18, the second inductor 20, and the third inductor 30 are not limited to Cu. The material constituting the first inductor 10, the rewiring layer inductor 18, the second inductor 20, and the third inductor 30 may be a Cu alloy containing Cu and other elements, or may be aluminum (Al) or an Al alloy. May be good.

Further, in the second embodiment, it has been described that the first inductor 10, the rewiring layer inductor 18, and the second inductor 20 are connected in series. Further, in the third embodiment, it has been described that the first inductor 10, the second inductor 20, and the third inductor 30 are connected in series. However, in the embodiments of the present disclosure, the connection of three or more inductors is not limited to series.

FIG. 24 is a diagram showing a connection example of the first inductor 10, the second inductor 20, and the third inductor 30 according to other embodiments of the present disclosure. As shown in FIG. 24, even if the three first inductor 10, the second inductor 20, and the third inductor 30 (or the first inductor 10, the rewiring layer inductor 18, and the second inductor 20) are star-connected. good. Even in such a case, by arranging the three first inductors 10, the second inductor 20, and the third inductor 30 so as to face each other, the three first inductors 10, the second inductor 20, and the third inductor 30 can be arranged. It can be electrically coupled and magnetically coupled.

As described above, it goes without saying that the present technology includes various embodiments not described here. At least one of the various omissions, substitutions and modifications of the components may be made without departing from the gist of the embodiments and modifications described above. Further, the effects described in the present specification are merely examples and are not limited, and other effects may be obtained. The technical scope of the present disclosure is defined only by the matters specifying the invention relating to the reasonable claims from the above description.

The present disclosure may also have the following structure.
(1) A first semiconductor chip having a first inductor and
A second semiconductor chip, which is arranged to face the first semiconductor chip and has a second inductor,
A connection portion provided on at least one of the first semiconductor chip or the second semiconductor chip and electrically connecting the first inductor and the second inductor is provided.
The first inductor and the second inductor face each other,
An inductor element in which the direction in which a current flows in the first inductor and the direction in which a current flows in the second inductor are the same.
(2) The inductor according to (1) above, wherein the direction of the magnetic flux generated by the current flowing through the first inductor and the direction of the magnetic flux generated by the current flowing through the second inductor are the same directions. element.
(3) The inductor element according to (1) or (2) above, wherein the line width of the first inductor and the line width of the second inductor are the same length as each other.
(4) The connection portion includes a first connection portion provided on the first semiconductor chip and electrically connected to the first inductor.
It has a second connection portion provided on the second semiconductor chip and electrically connected to the second inductor.
The first connection portion is exposed from the first surface of the first semiconductor chip, and is exposed.
The second connection portion is exposed from the second surface of the second semiconductor chip, and the first surface and the second surface face each other.
The inductor element according to any one of (1) to (3) above, wherein the first connecting portion and the second connecting portion are joined to each other.
(5) The inductor element according to (4), wherein the first connection portion and the second connection portion are made of the same metal element.
(6) A third semiconductor chip arranged between the first semiconductor chip and the second semiconductor chip is further provided.
The third semiconductor chip is
It has a third inductor that faces the first inductor and the second inductor, respectively.
The direction in which the current flows in the first inductor, the direction in which the current flows in the second inductor, and the direction in which the current flows in the third inductor are the same directions as any of the above (1) to (5). The inductor element according to item 1.
(7) The direction of the magnetic flux generated by the current flowing through the third inductor is
The inductor element according to (6), wherein the direction of the magnetic flux generated by the current flowing through the first inductor and the direction of the magnetic flux generated by the current flowing through the second inductor are the same.
(8) At least one of the first semiconductor chip and the second semiconductor chip
Further having a fourth inductor disposed between the first inductor and the second inductor and facing the first inductor and the second inductor, respectively.
One of claims 1 to 7, wherein the direction in which the current flows in the first inductor, the direction in which the current flows in the second inductor, and the direction in which the current flows in the fourth inductor are the same. The inductor element described in.
(9) The first semiconductor chip is
It is provided on the same layer as the first inductor and has a first electrode that surrounds the first inductor from the outside.
The second semiconductor chip is
It is provided on the same layer as the second inductor and has a second electrode that surrounds the second inductor from the outside.
The inductor element according to any one of (1) to (8), wherein the first electrode and the second electrode are each connected to a fixed potential.
(10) A first semiconductor chip having a first inductor and a first semiconductor element,
A second semiconductor chip, which is arranged to face the first semiconductor chip and has a second inductor and a second semiconductor element,
A connection portion provided on at least one of the first semiconductor chip or the second semiconductor chip and electrically connecting the first inductor and the second inductor is provided.
The first inductor and the second inductor face each other,
A semiconductor device in which the direction in which a current flows in the first inductor and the direction in which a current flows in the second inductor are the same directions.

1 1st semiconductor chip 2 2nd semiconductor chip 3 3rd semiconductor chip 10 1st inductor 11, 21 Semiconductor substrate 12, 13, 22, 23, 32, 33 Insulation film 14, 24 Connection part 15, 25 Wiring layer 16, 26 Dummy electrode 17 Insulation layer 18 Rewiring layer Inductor 19 1st electrode 20 2nd inductor 29 2nd electrode 30 3rd inductor 31 Semiconductor substrate 34 Through electrodes 50, 50A, 50B Stack structure inductors 100, 100A, 100B Inductor elements 101, 201 1st metal layer 102, 202 2nd metal layer 103 Center tap 131, 231 1st insulating film 132, 232 2nd insulating film 141, 142, 143, 144, 241, 242, 243,] 244 Conductive layer 200 Semiconductor device AR1 Regions B1, B2, B11, B12, B13, B14, B21, B22 Magnetic flux CT connection part H131, H231 Through hole P10 Conductor part P10C Intermediate position (neutral point)
P11, P12, P21, P22, P23, P24 Ends P20, P20A, P20B Leads R11, R21 1st loop R12, R22 2nd loop R13 3rd loop R14 4th loop S1, S2 Distance Tr1, Tr2 Transistor W1, W2 line width

Claims (10)

A first semiconductor chip having a first inductor and
A second semiconductor chip, which is arranged to face the first semiconductor chip and has a second inductor,
A connection portion provided on at least one of the first semiconductor chip or the second semiconductor chip and electrically connecting the first inductor and the second inductor is provided.
The first inductor and the second inductor face each other,
The direction in which the current flows in the first inductor and the direction in which the current flows in the second inductor are the same directions.
Inductor element. The direction of the magnetic flux generated by the current flowing through the first inductor and the direction of the magnetic flux generated by the current flowing through the second inductor are the same directions.
The inductor element according to claim 1. The inductor element according to claim 1, wherein the line width of the first inductor and the line width of the second inductor are the same length as each other. The connection part
A first connection portion provided on the first semiconductor chip and electrically connected to the first inductor,
It has a second connection portion provided on the second semiconductor chip and electrically connected to the second inductor.
The first connection portion is exposed from the first surface of the first semiconductor chip, and is exposed.
The second connection portion is exposed from the second surface of the second semiconductor chip, and is exposed.
The first surface and the second surface face each other,
The first connection portion and the second connection portion are joined to each other.
The inductor element according to claim 1. The first connection portion and the second connection portion are composed of the same metal element as each other.
The inductor element according to claim 4. A third semiconductor chip arranged between the first semiconductor chip and the second semiconductor chip is further provided.
The third semiconductor chip is
It has a third inductor that faces the first inductor and the second inductor, respectively.
The direction in which the current flows in the first inductor, the direction in which the current flows in the second inductor, and the direction in which the current flows in the third inductor are the same directions.
The inductor element according to claim 1. The direction of the magnetic flux generated by the current flowing through the third inductor is
The directions of the magnetic flux generated by the current flowing through the first inductor and the directions of the magnetic flux generated by the current flowing through the second inductor are the same.
The inductor element according to claim 6. At least one of the first semiconductor chip and the second semiconductor chip
Further having a fourth inductor disposed between the first inductor and the second inductor and facing the first inductor and the second inductor, respectively.
The direction in which the current flows in the first inductor, the direction in which the current flows in the second inductor, and the direction in which the current flows in the fourth inductor are the same directions.
The inductor element according to claim 1. The first semiconductor chip is
It is provided on the same layer as the first inductor and has a first electrode that surrounds the first inductor from the outside.
The second semiconductor chip is
It is provided on the same layer as the second inductor and has a second electrode that surrounds the second inductor from the outside.
The first electrode and the second electrode are each connected to a fixed potential.
The inductor element according to claim 1. A first semiconductor chip having a first inductor and a first semiconductor element,
A second semiconductor chip, which is arranged to face the first semiconductor chip and has a second inductor and a second semiconductor element,
A connection portion provided on at least one of the first semiconductor chip or the second semiconductor chip and electrically connecting the first inductor and the second inductor is provided.
The first inductor and the second inductor face each other,
The direction in which the current flows in the first inductor and the direction in which the current flows in the second inductor are the same directions.
Semiconductor device.

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