TWI646652B - Inductance combination and its circuit structure - Google Patents

Abstract

An inductance combination is a combination of three sets of coils with four conductive ports, and optionally two conductive ports as input and output ports to provide a variety of inductance patterns, and the inductance combination is lined to become part of the circuit structure.

Description

Inductor combination and its circuit structure

The present invention relates to a circuit structure, and more particularly to a circuit structure with inductance.

With the development of mobile communication devices in recent years, in addition to improving the performance of electronic components and reducing the size of components, such as chips with low noise characteristics or integrating passive components on the substrate to filter out noise To achieve the balance of semiconductor components.

At present, the integration of multi-functional or system components on the packaging substrate is a trend in the field of semiconductor packaging. Therefore, how to reduce costs is a very important issue for current development. Therefore, it is more feasible to reduce costs by using the same distributed components.

As shown in FIG. 1, in the conventional semiconductor package 1, a semiconductor wafer 11 and a passive element 12 (such as an inductor, a capacitor, or a resistor) are arranged on a packaging substrate 10, and the semiconductor wafer 11 is bonded with a bonding wire 110. The electrical contact pads 100 of the packaging substrate 10 are electrically connected, and the semiconductor wafer 11, the passive components 12 and the bonding wires 110 are covered with a packaging gel 13. Thereafter, the semiconductor package 1 is mounted on a circuit board 9 by a plurality of solder balls 90.

However, in the conventional semiconductor package 1, if the same decentralized component (such as a plurality of passive components 12) is used to provide multiple inductance values, the layout area of the package substrate 10 needs to be increased, which will increase the semiconductor package. The volume of the component 1; however, if the layout area of the package substrate 10 is not increased, the area occupied by the passive component 12 will be increased, which will lead to a smaller wiring space and limited electrical functions.

Therefore, how to overcome the various problems in the conventional technology has become an urgent problem to be solved.

In view of the lack of the above-mentioned conventional technology, the present invention provides an inductor combination including: a first coil; a second coil electrically connected to the first coil; a third coil electrically connected to the second coil; a first The conductive port is electrically connected to the first coil; the second conductive port is electrically connected to the second coil; the third conductive port is electrically connected to the third coil; and the fourth conductive port is electrically connected The first coil.

In the aforementioned inductance combination, one end of the third coil is connected to the second coil.

In the aforementioned inductance combination, two of the first to fourth conductive ports are used as a signal input port and a signal output port.

In the aforementioned inductance combination, the third coil and the second coil are located on the same layer, and the first coil is stacked on the second coil and the third coil.

In the aforementioned inductance combination, the second coil is connected to the first coil by a conductor.

In the aforementioned inductive combination, the first conductive port is connected by the first conductive portion. Connected to the first coil, the second conductive port is connected to the second coil through a second conductive portion, the third conductive port is connected to the third coil through a third conductive portion, and the fourth conductive port It is connected to the first coil through a fourth conductive portion.

In the aforementioned inductance combination, the first to fourth conductive ports are located on the periphery of the first to third coils.

In the aforementioned inductance combination, the first to fourth conductive ports are conductive pillars, and the conductive pillars serving as the first conductive ports are connected to the first coil with the upper end surface thereof through the first conductive portion as the first conductive port. The conductive pillar of the second conductive port is connected to the second coil by its upper end through the second conductive part, and the conductive pillar of the third conductive port is connected to the third coil by its upper end through the third conductive part. And the conductive pillar as the fourth conductive port is connected to the first coil with a lower end surface through a fourth conductive portion.

The invention also provides a circuit structure, which includes: an insulator; and the aforementioned inductance combination, which is formed by wiring in the insulator.

In the aforementioned circuit structure, the first to fourth conductive ports are conductive pillars formed in the insulator.

In the aforementioned circuit structure, the first to third coils are conductive traces formed in the insulator.

In the aforementioned circuit structure, the first conductive portion is a conductive trace formed in the insulator.

In the aforementioned circuit structure, the second to fourth conductive portions are conductive traces and conductive blind holes formed in the insulator.

In the aforementioned circuit structure, the conductive system is formed in the insulator. Conductive blind hole.

In the aforementioned circuit structure, a first circuit layer and a second circuit layer including the first to third coils and the first to fourth conductive portions are formed in the insulator.

As can be seen from the above, the inductor combination and the circuit structure of the present invention mainly include three sets of coils and four conductive ports, and optionally two conductive ports are used as input ports and output ports to provide a variety of inductance patterns, and The combination of inductors becomes a part of the circuit structure, so there is no need to increase the layout area of the packaging substrate, and it will not affect the wiring space. Therefore, compared with the conventional technology, the circuit structure of the present invention does not increase the volume of the package, and Will reduce the electrical functionality of the chip.

1‧‧‧ semiconductor package

10‧‧‧ package substrate

100‧‧‧electric contact pad

11‧‧‧Semiconductor wafer

110‧‧‧ welding wire

12‧‧‧ Passive components

13‧‧‧ encapsulated colloid

2,4‧‧‧line structure

2a‧‧‧Inductor combination

20‧‧‧ insulator

20a, 20b‧‧‧ Insulation

21‧‧‧First port

21a, 22a, 23a, 24a

21b, 22b, 23b, 24b

22‧‧‧Second conductive port

23‧‧‧Third conductive port

24‧‧‧ Fourth port

30,321,331,341‧‧‧Conductors

31‧‧‧The first conductive part

32‧‧‧ the second conductive part

320,330,340‧‧‧ conductive traces

33‧‧‧ the third conductive part

34‧‧‧ Fourth conductive section

40‧‧‧First insulating material

40’‧‧‧second insulating material

40 ”‧‧‧third insulating material

41‧‧‧First circuit layer

42‧‧‧Second circuit layer

420‧‧‧Conductive blind hole

43‧‧‧ conductive post

9‧‧‧Circuit Board

90‧‧‧ solder ball

L1‧‧‧First coil

L2‧‧‧Second Coil

L3‧‧‧Third Coil

L30‧‧‧End

S1, S2‧‧‧Signal path

T1, T2, T3‧‧‧thickness

Figure 1 is a schematic cross-sectional view of a conventional semiconductor package; Figure 2A is a schematic plan view of the inductor assembly of the present invention after wiring; Figure 2B is a perspective schematic corresponding to Figure 2A; and Figure 3A is Partial cross-sectional schematic diagram of the circuit structure of the present invention; FIG. 3B is a schematic cross-sectional schematic diagram of another part of the circuit structure of the present invention;

The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand the content disclosed in this specification. Learn about other advantages and effects of the present invention.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. The limited conditions are not technically significant. Any modification of the structure, change of the proportional relationship, or adjustment of the size shall still fall within the scope of this invention without affecting the effects and goals that the invention can produce. The technical content disclosed by the invention can be covered. At the same time, the terms such as "first", "second", "third", "up", "down" and "one" cited in this specification are only for the convenience of description, and are not intended to be used. To limit the scope of the present invention that can be implemented, changes or adjustments to its relative relationship, without substantial changes in the technical content, should also be considered as the scope of the present invention that can be implemented.

As shown in Figures 2A, 2B, 3A, and 3B, the circuit structure 2 of the present invention includes an insulator 20 and an inductor combination 2a formed in a line in the insulator 20, and the inductor combination 2a includes a first coil. L1, second coil L2, third coil L3, first conductive port 21, second conductive port 22, third conductive port 23, and fourth conductive port 24.

In this embodiment, the circuit structure 2 is applicable to a package substrate for carrying a chip.

The insulator 20 includes a plurality of insulating layers 20a, 20b stacked on each other.

The first coil L1 is lined to become a conductive trace of a circuit layer, and is located on one of the insulating layers 20a (such as an upper insulating layer) of the insulator 20.

The second coil L2 is lined to become a conductive trace of a circuit layer, and is located on another insulating layer 20b of the insulator 20 (as an insulating layer below), so that the first coil L1 is stacked on the second coil. L2, and one end of the second coil L2 is connected to the first coil L1 through a conductor 30.

The third coil L3 is lined to become a conductive trace of a circuit layer, and is located in the same insulating layer 20b (as the lower layer) with the second coil L2, and one end portion L30 of the third coil L3 is connected to the Second coil L2.

The first conductive port 21 is lined to become a conductive pillar, and is connected to the first coil L1 through a first conductive portion 31 (such as a conductive trace) through an upper end surface 21a thereof.

The second conductive port 22 is lined to become a conductive pillar, and is connected to the second coil L2 through a second conductive portion 32 (such as a conductive trace 320 and a conductive body 321) on an upper end surface 22a thereof.

The third conductive port 23 is lined into a conductive pillar, and is connected to the third coil L3 through a third conductive portion 33 (such as the conductive trace 330 and the conductive body 331) on the upper end surface 23a thereof.

The fourth conductive port 24 is circuitized to become a conductive pillar, and is connected to the first coil L1 through a fourth conductive portion 34 (such as a conductive trace 340 and a conductive body 341) on its lower end surface 24b.

In this embodiment, the upper end faces 21a, 22a, 23a, 24a and the lower end faces 21b, 22b, 23b, 24b of the first to fourth conductive ports 21, 22, 23, 24 are located in the insulator 20 and are located in The periphery of the first to third coils L1, L2, L3.

In addition, the first conductive port 21, the second conductive port 22, the third conductive port 23, and the fourth conductive port 24 are selected as signal outputs according to requirements. The input port and the signal output port will generate six types of inductance, for example, the first conductive port 21 cooperates with the second conductive port 22, the first conductive port 21 cooperates with the third conductive port 23, and the first conductive port 21 With the fourth conductive port 24, the second conductive port 22 with the third conductive port 23, the second conductive port 22 with the fourth conductive port 24, and the third conductive port 23 with the fourth conductive port 24 . Specifically, as follows:

The first inductance state is shown in Figures 2B, 3A, and 3B. The first conductive port 21 is used as a signal input port, and the second conductive port 22 is used as a signal output port, so that the first coil L1 and the second coil The coil L2 is used as an inductor, and the current of the signal path S1 is the first conductive port 21, the first conductive portion 31, the first coil L1, the conductor 30, the second coil L2, the second conductive portion 32, and the first conductive port in this order.二 电 通 槽 22。 Two conductive port 22. It should be understood that the current in the signal path S1 may flow in the reverse direction.

The second inductance state is shown in Figures 2B, 3A, and 3B. The first conductive port 21 is used as a signal input port, and the third conductive port 23 is used as a signal output port. The first coil L1, the second The coil L2 and the third coil L3 serve as inductors, and the currents of the signal paths are in sequence the first conducting port 21, the first conductive portion 31, the first coil L1, the conductor 30, the second coil L2, and the third coil L3. A third conductive portion 33 and the third conductive port 23. It should be understood that the current of the signal path may flow in the reverse direction.

The third type of inductance is shown in Figures 2B and 3A. The first conductive port 21 is used as a signal input port, and the fourth conductive port 24 is used as a signal output port. The first coil L1 is used as an inductor, and its signal The current in the path S1 is the first conductive port 21, the first conductive portion 31, the first coil L1, in this order. The fourth conductive portion 34 and the fourth conductive port 24. It should be understood that the current of the signal path may flow in the reverse direction.

The fourth type of inductance is shown in Figs. 2B and 3B. The second conductive port 22 is used as a signal input port, and the third conductive port 23 is used as a signal output port, so that the second coil L2 and the third coil L3 are used. As the inductor, the current of its signal path S2 is the second conductive port 22, the second conductive portion 32, the second coil L2, the third coil L3, the third conductive portion 33, and the third conductive port 23 in this order. It should be understood that the current in the signal path S2 may flow reversely.

The fifth inductance state is shown in Figures 2B, 3A, and 3B. The second conductive port 22 is used as a signal input port, and the fourth conductive port 24 is used as a signal output port, so that the second coil L2 and the first The coil L1 is used as an inductor, and the current of its signal path is the second conduction port 22, the second conductive portion 32, the second coil L2, the conductor 30, the first coil L1, the fourth conductive portion 34, and the fourth conduction in order. Port 24. It should be understood that the current of the signal path may flow in the reverse direction.

The sixth inductance state is shown in Figures 2B, 3A, and 3B. The third conductive port 23 is used as a signal input port, and the fourth conductive port 24 is used as a signal output port. The first coil L1, the first The two coils L2 and the third coil L3 serve as inductors, and the currents of their signal paths are in sequence the third conductive port 23, the third conductive portion 33, the third coil L3, the second coil L2, the conductor 30, and the first coil. L1, the fourth conductive portion 34 and the fourth conductive port 24. It should be understood that the current of the signal path may flow in the reverse direction.

In addition, the circuit structure 2 of the present invention can be used, for example, to produce a package substrate with a core layer or a coreless package substrate by using two layers. Redistribution layer (RDL) manufacturing process.

Specifically, as shown in FIG. 4A, a first insulating material 40 is formed on a carrier (not shown), and a first circuit layer 41 is formed on the first insulating material 40; then, as shown in FIG. 4B A second insulating material 40 'is formed on the first insulating material 40 and the first circuit layer 41, a plurality of conductive blind holes 420 are formed in the second insulating material 40', and then the second insulating material 40 'is formed. A second circuit layer 42 is formed on the conductive blind hole 420, and a third insulating material 40 "is formed on the second insulating material 40 'and the second circuit layer 42. Then, as shown in FIG. 4C, A plurality of conductive pillars 43 are formed in the first to third insulating materials 40, 40 ′, 40 ″, and the carrier is removed to obtain the circuit structure 4.

The first insulating material 40 may be, for example, an insulating layer 20b under the insulator 20 shown in FIG. 3A.

The second insulating material 40 'may be, for example, an insulating layer 20a on the insulator 20 shown in FIG. 3A.

The third insulating material 40 ″ can be used as other parts of the insulator 20 shown in FIG. 3A.

In this embodiment, the thickness T3 of the third insulating material 40 "is greater than the thickness T1 of the first insulating material 40, and the thickness T1 of the first insulating material 40 is greater than the thickness T2 of the second insulating material 40 '.

Furthermore, the materials forming the first to third insulating materials 40, 40 ', 40 "may be inorganic materials (such as silicon dioxide, silicon nitride, aluminum oxide, silicon carbide, GaAs, GaP, etc.) or organic materials ( (Such as dielectric).

The first circuit layer 41 may include conductive traces 340 of the second coil L2, the third coil L3, and the fourth conductive portion 34.

The second circuit layer 42 may include the first coil L1, the first conductive portion 31, the conductive trace 320 of the second conductive portion 32, and the conductive trace 330 of the third conductive portion 33.

The conductive blind hole 420 may include a conductive body 30, a conductive body 321 of the second conductive portion 32, a conductive body 331 of the third conductive portion 33, and a conductive body 341 of the fourth conductive portion 34.

The conductive pillar 43 may include a first conductive port 21, a second conductive port 22, a third conductive port 23, and a fourth conductive port 24.

In this embodiment, the conductive post 43 can be used as a signal input port (such as the first conductive port 21, the second conductive port 22, the third conductive port 23, or the fourth conductive port 24), and connected to the circuit of the substrate (such as The electrical contact pad 100 of the package substrate 10 shown in FIG. 1) is used to receive signals from the chip (such as the semiconductor wafer 11 shown in FIG. 1), and the conductive pillar 43 can also be used as a signal output port (such as the first Conductive port 21, second conductive port 22, third conductive port 23, or fourth conductive port 24), and can be connected to the circuit on the substrate to output signals to external components (such as the circuit board 9 shown in FIG. 1) ).

In summary, the circuit structure 2, 4 and the inductor combination 2a of the present invention are made by selecting two conductive ports (such as the first conductive port 21, the second conductive port 22, the third conductive port 23, and the fourth conductive port). Two of the conducting ports 24) are used as input ports and output ports to provide various inductance states (such as six inductance values), and the inductance combination 2a is lined into a part of the line structure 2,4, so there is no need to increase The layout area of the package substrate does not affect the wiring space. Compared with the conventional technology, the circuit structure 2, 4 of the present invention does not increase the volume of the package, and does not reduce the electrical functions of the chip. Select electricity The Q value (quality factor) in the sensory combination 2a is matched with the electrical function of the chip.

The above embodiments are used to exemplify the principle of the present invention and its effects, but not to limit the present invention. Anyone skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

Claims (13)

An inductor combination includes: a first coil; a second coil electrically connected to the first coil; a third coil electrically connected to the second coil; and one end of the third coil is connected to the second coil A coil; a first conducting port electrically connected to the first coil; a second conducting port electrically connected to the second coil; a third conducting port electrically connected to the third coil; and a fourth conducting port, Is electrically connected to the first coil, wherein the first conductive port is connected to the first coil through a first conductive portion, and the second conductive port is connected to the second coil through a second conductive portion, the The third conductive port is connected to the third coil through a third conductive portion, and the fourth conductive port is connected to the first coil through a fourth conductive portion. The inductance combination according to item 1 of the scope of patent application, wherein two of the first to fourth conducting ports are used as a signal input port and a signal output port, respectively. The inductance combination according to item 1 of the scope of the patent application, wherein the third coil and the second coil are located on the same layer, and the first coil is stacked on the second coil and the third coil. The inductance combination according to item 1 of the patent application scope, wherein the second coil is connected to the first coil by a conductor. The inductance combination according to item 1 of the patent application scope, wherein the first to fourth conductive ports are located on the periphery of the first to third coils. The inductance combination according to item 1 of the patent application scope, wherein the first to fourth conductive ports are conductive pillars, and the conductive pillars serving as the first conductive port are connected by a first conductive portion with an upper end surface thereof. To the first coil, the conductive post serving as the second conductive port is connected to the second coil through its upper end surface through the second conductive portion, and the conductive post serving as the third conductive port is based on its upper end surface through the third The conductive portion is connected to the third coil, and the conductive post serving as the fourth conductive port is connected to the first coil through the fourth conductive portion by its lower end surface. A circuit structure includes: an insulator; and the inductor combination according to one of claims 1 to 6 of the scope of patent application, formed in the insulator. The circuit structure according to item 7 of the scope of the patent application, wherein the first to fourth conductive ports are conductive pillars formed in the insulator. The circuit structure according to item 7 of the scope of patent application, wherein the first to third coils are conductive traces formed in the insulator. The circuit structure according to item 7 of the scope of patent application, wherein the first conductive portion is a conductive trace formed in the insulator. The circuit structure according to item 7 of the scope of the patent application, wherein the second to fourth conductive portions are conductive traces and conductive blind holes formed in the insulator. The circuit structure according to item 7 of the scope of the patent application, wherein the second coil is connected to the first coil by a conductor, and the conductive system is a conductive blind hole formed in the insulator. The circuit structure according to item 7 of the scope of patent application, wherein the insulator is formed with a first circuit layer and a second circuit layer including the first to third coils and the first to fourth conductive portions.