JP2011103478A - Semiconductor device and power converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device by preventing deterioration of a field plate due to voltage application. <P>SOLUTION: In the semiconductor device, a field limiting ring 114 and field plates 111 and 115 are formed in a termination region formed adjacent to an active region where a current is allowed to flow. Each field plate is a resistor, has a resistivity of 5×10<SP>-3</SP>Ωcm or more, and is made of a polycrystalline silicon. An insulator layer is formed between the field plate and the field limiting ring to insulate the field limiting ring from the field plate. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device used for a power conversion device such as an inverter, and more particularly to a semiconductor device provided with a field plate.

  Currently, IGBTs are widely used for power control. IGBTs are easy to control, can handle large amounts of power, and can be used in a wide range of frequencies from several Hz to several kHz, so they can control factory motors and elevator motors from small power sources such as home air conditioners and microwave ovens. It is widely used up to large power.

  In the high power application, a high voltage of 300V to 1200V is applied to the IGBT. In order to withstand this voltage, a termination region for relaxing the electric field is provided in the peripheral portion of the IGBT chip. There is a structure in which a field limiting ring and a field plate are combined in the structure of the termination of the prior art IGBT. The details are described in Corona Power Device Power IC Handbook p59.

  FIG. 2 shows a cross-sectional structure example of a conventional termination in which a field limiting ring and a field plate are combined. The left side of FIG. 2 is an active region that is a current application region, and the right side is a termination region. In FIG. 2, reference numeral 101 denotes a high-concentration p-conductivity type collector layer, 102 denotes a high-concentration n-conduction buffer layer, 103 denotes a low-concentration n-conduction drift layer, 104 denotes a p-conduction type base layer, and 105. Is a high concentration p conductivity type contact layer, 106 is a high concentration n conductivity type emitter layer, 107 is a p conductivity type well layer, 108 is a gate oxide film, 109 is a polycrystalline silicon gate, 110 is an interlayer insulation film , 111 is a field plate, 112 is a surface protection film, 113 is a field oxide film, 114 is a field limiting ring layer, 115 is a field plate, 116 is a guard ring, 117 is a high-concentration n-conductivity type channel stopper layer, 118 Denotes a collector electrode, and 119 denotes an emitter electrode.

  The operation of the structure of FIG. 2 will be briefly described. The potential of the emitter electrode 119 is set to 0 potential (ground potential), the potential of the polycrystalline silicon gate 109 is equal to or lower than the potential of the emitter electrode 119, for example, −15 V, and the collector electrode 118 is positively connected. When a voltage is applied, the depletion layer expands from the pn junction formed between the base layer 104 and the well layer 107 and the drift layer 103.

  When the depletion layer reaches the field limiting ring 114, the field limiting ring 114 and the aluminum field plate 201 work to further extend the depletion layer to the outer periphery of the chip (right side in FIG. 2) to concentrate the electric field. Relax and prevent surrender. In addition, an aluminum guard ring 202 is provided to prevent the depletion layer from extending too much and grounding to the end of the chip to flow current, and the potential of the collector electrode 118 is guarded through the channel stopper layer 117. This is transmitted to the ring 202 to suppress the extension of the depletion layer.

  However, the above prior art has the following problems. An equivalent circuit of the structure of FIG. 2 is shown in FIG. In FIG. 3, reference numeral 301 denotes a capacitance Cpn1 and 302 of the junction between the well layer 107 and the drift layer 103, and drift layer resistances Rd1 and 303 between the well layer 107 and the field limiting ring 114 denote field limiting rings. The contact resistance Rcnt, 304 between the field plate 201 and the polycrystalline silicon field plate 201 is a resistance Rfp of the field plate 201, and the capacitance Cfp, 306 formed between the field plate 201 and the drift layer 103 is field limiting. Capacitances Cpn2 and 307 between the ring 114 and the drift layer 103 are the resistance Rd2 of the drift layer 103.

  When a high voltage is suddenly applied to the termination region, the depletion layer expands rapidly. When the voltage increases, Cpn1 is charged first. At this time, the potential from the node A to the collector in FIG. 3 is the same potential, and the voltage is applied to Cpn1. Next, when the depletion layer reaches the field limiting ring 114, charging of Cpn2 and Cfp starts, and the depletion layer starts to spread from the field limiting ring 114. At this time, the node B is at the collector potential. A current for charging the capacitor flows through Cpn2 and Cfp. The charging current of Cfp flows through the field plate 201 and flows into the field limiting layer 114.

  When the field plate 201 is formed of a metal electrode such as aluminum or tungsten, Rfp can be regarded as almost zero because of its low resistivity. The field limiting ring 114 is formed of a high concentration p-type impurity to widen the depletion layer. Since the contact resistance between the field limiting layer 114 and the field plate is sufficiently small, Rcnt can be regarded as almost zero. . Since Cpn2 becomes smaller as the depletion layer expands, it becomes sufficiently smaller than Cfp when the voltage increases and the depletion layer expands.

For this reason, a large current flows in Cfp as the depletion layer spreads, and there are cases where the current density is as high as 1 × 10 ⁵ A / cm ² for a short time. When a current with such a large current density occurs, an electromigration phenomenon occurs in which aluminum atoms move in the direction of electron flow due to the kinetic energy of the electrons, creating gaps in the aluminum or disconnecting the aluminum. Problems arise. Further, when migration occurs, peeling between the field plate 201 and the field oxide film 113 or between the field plate 201 and the surface protective film 112 is caused, which causes a problem of lowering the breakdown voltage.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems, and to provide a highly reliable semiconductor device that prevents field plate deterioration due to voltage application.

A semiconductor device according to the present invention includes an active region through which a current is passed and a termination region formed adjacent to the active region to relieve an electric field. The termination region includes a field limiting ring and the field limiting. A field plate is formed in contact with the ring to relieve an electric field. The field plate is a resistor, and the resistivity of the field plate is 5 × 10 ⁻³ Ωcm or more.

  In the semiconductor device of the present invention, the field plate is polycrystalline silicon, and an insulating layer is formed between the field plate and the field limiting ring to insulate the field limiting ring from the field plate.

  A semiconductor device of the present invention includes a one-conductivity-type semiconductor substrate having a pair of main surfaces, an active region formed adjacent to one main surface of the semiconductor substrate, and energized with one of the semiconductor substrates. And a field limiting layer of the other conductivity type formed in the semiconductor substrate surrounding the active region and in contact with the field limiting layer, and one main surface of the semiconductor substrate And a field plate made of a resistor formed in contact with the field limiting layer and extending on the semiconductor substrate via an insulating film.

  As described above, according to the present invention, the current flowing in the field plate when a sudden voltage is applied to the termination region is reduced, and the electromigration phenomenon or the separation of the field plate and the field oxide film, the field plate and the surface protection film is peeled off. Can be prevented, and the lifetime of the element can be improved. Further, by suppressing the increase rate of the voltage applied to the element, noise generated from the element can be reduced, and the power converter can be reduced in size and cost.

1 is a cross-sectional view of Example 1. FIG. It is sectional drawing of the termination area | region of a prior art. It is an equivalent circuit of the termination area | region of a prior art. It is a top view of the present Example 2. It is sectional drawing of AB of FIG. It is sectional drawing of CD of FIG. 6 is a cross-sectional view of Example 3. FIG. 6 is a plan view of Example 4. FIG. FIG. 6 is a circuit diagram of Example 4.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings for explaining the respective embodiments, the same reference numerals are used for those having the same function. Hereinafter, embodiments of the present invention will be described by taking an IGBT as an example. However, the semiconductor device is not limited to an IGBT, and can be similarly applied to a MOSFET having a field limiting ring and a field plate and other semiconductor devices. .

Example 1
FIG. 1 shows this embodiment. In FIG. 1, reference numerals 111 and 115 denote polycrystalline silicon field plates, and 116 denotes a polycrystalline silicon guard ring.

In this embodiment, polycrystalline silicon is used for the field plate. This polycrystalline silicon is a film deposited on the surface of a silicon substrate by a chemical deposition method. When the film is deposited, impurities are mixed and the electrical resistivity of the film is 500 × 10 ⁻⁶ Ωcm to 1 Ωcm. The size can be 10 times or more that of a metal electrode such as chromium. Further, when the impurity concentration is adjusted to increase the resistivity, the resistance Rfp of the field plate increases. When the resistance Rfp of the field plate increases, it becomes difficult for the current to flow through the field plate, so that the inrush current that flows through the field plate when applying a sudden high voltage is suppressed.

The electromigration phenomenon occurs when the density of current flowing through the field plate reaches 1 × 10 ⁵ A / cm ² . It has already been found that electromigration does not occur when the current density is less than about 1/10 of this value. Therefore, if the resistance Rfp of the field plate is 10 times that of the metal electrode and the inrush current density is suppressed to 1/10 as described above, the electromigration phenomenon can be prevented. Therefore, in this embodiment, the resistivity of the polycrystalline silicon of the field plate is set to 5 × 10 ⁻³ Ωcm or more. In this embodiment, the resistivity of the field plate may be the same as that of the metal electrode, and the thickness may be 1/10 or less of the metal electrode.

  Furthermore, in this embodiment, since the charging current of the electrostatic capacitance Cfp formed between the field plate and the drift layer when the depletion layer is expanded is suppressed, the speed at which the depletion layer spreads decreases. When the speed at which the depletion layer spreads decreases, the increase in the voltage applied to both IGBT main terminals slows down, and noise generated due to voltage changes is reduced.

(Example 2)
FIG. 4 shows a planar structure of this embodiment. 5 and 6 show a cross section AB and a cross section CD in FIG. 4, respectively. 4 to 6, the same components as those in FIGS. 1 to 3 are denoted by the same reference numerals. In FIG. 4, reference numeral 401 denotes an aluminum contact electrode, and 402 denotes a contact.

  In this embodiment, the connection between the polycrystalline silicon field plate 115 and the field limiting layer 114 is limited to the contact 402 portion of the aluminum contact electrode 401. In the configuration of this embodiment, since the connection area between the polycrystalline silicon field plate 115 and the field limiting ring 114 is small, the distance between the contact point between the field plate and silicon can be increased, and the resistance Rfp shown in FIG. Can be big.

  In addition, since the area of the contact point is small in the configuration of this embodiment, Rcnt shown in FIG. 3 can be increased and the resistance can be further increased. Thus, according to the present embodiment, the plane layout can be changed to increase Rfp and Rcnt, thereby preventing the electromigration phenomenon. In addition, according to the configuration of the present embodiment, Rfp and Rcnt can be increased only by changing the planar layout, and therefore electromigration can be prevented without changing the manufacturing process such as adjusting the impurity concentration or changing the thickness of the electrode. . In the present embodiment, similarly to the first embodiment, the increase rate of the voltage applied to the IGBT main terminals is suppressed, and noise is reduced.

(Example 3)
FIG. 7 shows a cross-sectional structure of this embodiment. FIG. 8 shows an equivalent circuit of FIG. 7 and 8, the same components as those in FIGS. 1 to 6 are denoted by the same reference numerals. Reference numeral 801 in FIG. 8 denotes a capacitance Ccnt formed between the polycrystalline silicon field plate 115 and the field limiting ring 114.

  In this embodiment, a capacitance Ccnt is formed by the gate oxide film 108 between the polycrystalline silicon field plate 115 and the field limiting ring 114. When Ccnt is inserted in series with Cfp, the total capacitance Call of the path from the drift layer 103 through the polycrystalline silicon field plate 115 to the field limiting ring 114 is reduced as shown in the equation (1). .

Call = Cfp × Ccnt / (Cfp + Ccnt) (Equation 1)
The current Ifp flowing in the field plate 115 can be expressed by the formula (2).

Ifp = dQ / dt
= D (Ca11V) / dt
= CalldV / dt + Vd (Call) / dt (Equation 2)
In the equation (2), V is a potential difference between the drift layer 103 and the field limiting layer 114. Here, since the total capacitance Call is the capacitance of the oxide film and does not change, the Vd (Call) / dt term in the equation (2) is 0, and the equation (2) is expressed by the equation (3). It becomes an expression.

Ifp = CalldV / dt (Equation 3)
If Ccnt is inserted in series with Cfp as shown in (Expression 1) to reduce the total capacitance Ca11, Ifp can be reduced as shown in (Expression 3).

  As described above, in this embodiment, the capacitor Ccnt is formed of the insulating film between the polycrystalline silicon field plate 115 and the field limiting ring 114 to reduce Ifp and prevent the electromigration phenomenon.

  Further, Cfp itself may be reduced to reduce the total capacitance Call. Here, Cfp can be expressed as shown in (Expression 4).

Cfp = εSiO × A / d (Expression 4)
In (Equation 4), εSiO represents the dielectric constant of the oxide film, A represents the area where the polycrystalline silicon field plate 115 and the drift layer 103 are opposed, and d represents the thickness of the field oxide film 113. From the equation (4), any one of reducing the dielectric constant of the oxide film, reducing the area where the field oxide film 113 and the drift layer 103 face each other, and reducing the thickness of the field oxide film 113. Cfp can be reduced by performing one or more of them.

  In the present embodiment, the configuration in which the gate oxide film 108 is disposed between the polycrystalline silicon field plate 115 and the field limiting ring 114 to form the capacitance Ccnt has been described. However, the oxide film that forms Ccnt is described below. Not only the gate oxide film 108 but also the field oxide film 113 may be used. Since the field oxide film 113 is thicker than the gate oxide film 108, the capacitance is small, and Call can be further reduced. However, if the capacitance Ccnt is made too small, the potential difference between the field limiting ring layer 114 and the polycrystalline silicon field plate 115 becomes large and the expected field plate effect cannot be obtained. The oxide film to be formed is preferably the same as or thinner than the field oxide film 113.

  In the present embodiment, similarly to the first embodiment, the increase rate of the voltage applied to the IGBT main terminals is suppressed, and noise is reduced.

Example 4
In this embodiment, the IGBTs of Embodiments 1 to 3 are applied to an inverter device that is a power converter. Although the inverter device of the present embodiment is not illustrated, a converter unit that receives an AC power supply and converts it to DC, a smoothing capacitor that smoothes the DC output from the converter unit, an inverter unit that converts DC to three-phase AC, The control part which controls a converter part and an inverter part is provided. The inverter unit receives the output signal of the control unit, performs pulse width modulation (PWM) on the gate signal, and controls the output of the IGBT.

  FIG. 9 shows an equivalent circuit diagram of the IGBT module part of the inverter part of this embodiment. In FIG. 9, reference numerals 901 to 906 denote IGBTs of the present invention, 907 to 912 denote IGBT gate terminals, 913 to 914 denote DC input terminals, and 915 to 917 denote AC output terminals.

  In the inverter device of this embodiment, the generated noise is small because the IGBTs of Embodiments 1 to 3 are applied. For this reason, noise filters and bulkheads and containers for preventing leakage of noise from the inverter, which are indispensable for conventional inverter devices, can be eliminated depending on the conditions of use. it can.

  The inverter device according to the present embodiment may be configured to omit the converter unit when a DC power source can be used. The inverter device according to the present embodiment has a long element life and generates less noise. Therefore, the inverter device is suitable for applications such as trains and automobiles that are used for a long period of about 10 years.

  Although the inverter device has been described in the present embodiment, the IGBT of the present invention can be similarly applied to a converter device and a semiconductor power conversion device such as a chopper.

  DESCRIPTION OF SYMBOLS 101 ... Collator layer, 102 ... Buffer layer, 103 ... Drift layer, 104 ... Base layer, 105 ... Contact layer, 106 ... Emitter layer, 107 ... Well layer, 108 ... Gate oxide film, 109 ... Polycrystalline silicon gate, 110 ... Interlayer insulating film 111 ... Field plate 112 ... Surface protective film 113 ... Field oxide film 114 ... Field limiting ring 115 ... Field plate 116 116Guard ring 117 ... Channel stopper layer 118 ... Collector electrode 119 ... emitter electrode, 201 ... field plate, 202 ... guard ring, 401 ... aluminum contact electrode, 402 ... contact, 901-906 ... IGBT, 907-912 ... gate terminal, 913-914 ... input terminal, 915-917 ... output terminal .

Claims (4)

In a semiconductor device comprising an active region that conducts current to the main surface of a semiconductor substrate, and a termination region that is formed adjacent to the active region and relaxes an electric field,
A field limiting ring provided in the termination region;
A field plate provided in the active area;
A field plate that relaxes the electric field formed in the termination region separately from the field plate of the active region;
A field oxide film formed between the field plate and the field limiting ring;
The field plate of the termination region is formed of polycrystalline silicon. The semiconductor device according to claim 1,
A field plate provided in the active region is electrically connected to an electrode in the active region. The semiconductor device according to claim 1,
A resistivity of the field plate in the termination region is 5 × 10 ⁻³ Ωcm or more. A parallel circuit consisting of a pair of DC terminals, an AC terminal of the same number as the number of phases of AC output, and a pair of DC terminals connected in series, each consisting of two parallel circuits of switching elements and diodes of opposite polarity. In the power conversion apparatus comprising the same number of inverter units as the number of phases of AC output connected to AC terminals having different interconnection points,
The power conversion device, wherein the switching element is the semiconductor device according to claim 1.

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