JP2011091759A - Current source, amplifier circuit, electronic circuit, integrated circuit device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a current source which can reduce variation in temperature change; an electronic circuit; an amplifier circuit; an integrated circuit device; and an electronic apparatus. <P>SOLUTION: The current source includes a resistor R having one end connected to a first power source node VSS, and a depression type transistor TR in which the other end of the resistor R is connected to a source and the first power source node VSS is connected to a gate, wherein the threshold voltage of the transistor TR has negative temperature characteristics and the resistance value of the resistor R has positive temperature characteristics. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a current source, an amplifier circuit, an electronic circuit, an integrated circuit device, an electronic device, and the like.

  An amplifier circuit that performs small signal amplification is provided with a current source that generates a tail current. For example, Patent Document 1 discloses a regulator that adjusts the voltage of an external power supply voltage and supplies the adjusted voltage to an internal circuit. The amplifier circuit included in the regulator is provided with a current source that generates a tail current.

  In a current source provided in such an amplifier circuit, a method of generating a tail current by providing a reference voltage generation circuit separately and inputting the reference voltage generated by the reference voltage generation circuit to the gate electrode of the transistor is generally used. Is.

  However, this method requires a separate reference voltage generation circuit in addition to the amplifier circuit, so that the number of current paths increases by the number of current paths flowing in this reference voltage generation circuit, resulting in low power consumption. There is a problem of becoming an obstacle.

  Further, Patent Document 2 discloses a current source having a depletion type transistor having a gate and a source connected, and a resistance element that is inserted between the source of the depletion type transistor and a ground potential and supplies a back gate bias voltage. It is disclosed. In the prior art disclosed in Patent Document 2, a voltage drop generated in a resistance element is applied as a back gate bias voltage to the source of a depletion type transistor, so that a threshold voltage caused by a variation in manufacturing process is applied. Can be reduced.

  However, with the current source of Patent Document 2, it is possible to reduce variations in threshold voltage, but no consideration is given to reducing variations in temperature.

JP 2001-92544 A JP 63-169113 A

  According to some embodiments of the present invention, it is possible to provide a current source, an electronic circuit, an amplifier circuit, an integrated circuit device, an electronic device, and the like that can reduce variation in temperature.

  One embodiment of the present invention includes a resistor having one end connected to a first power supply node, and a depletion type transistor having a source connected to the other end of the resistor and a gate connected to the first power supply node. In addition, the threshold voltage of the transistor has a negative temperature characteristic, and the resistance value of the resistor is related to a current source having a positive temperature characteristic.

  In one embodiment of the present invention, a resistor is provided between the source of the depletion type transistor and the first power supply node, and the gate of the depletion type transistor is connected to the first power supply node. According to the current source having such a configuration, since a negative feedback is provided in a circuit by a resistor provided at the source of the depletion type transistor, a stable constant current can be generated. Further, in one embodiment of the present invention, the threshold voltage of the transistor has a negative temperature characteristic, and the resistance value of the resistor has a positive temperature characteristic. Therefore, by canceling the negative temperature characteristic of the threshold voltage and the positive temperature characteristic of the resistance value, the temperature dependence of the tail current can be reduced, and variation in temperature fluctuation can be reduced.

  In the aspect of the invention, the resistor may be an N well resistor formed by an N well.

  In this way, the resistance value of the resistance of the current source can have a positive temperature characteristic.

  Another aspect of the present invention relates to an amplifier circuit including the current source described above, an amplifying unit provided in series with the current source, and a load unit provided in series with the amplifying unit.

  According to another aspect of the present invention, since a circuit for generating a reference voltage for generating a tail current of a current source can be eliminated, a current path is provided in an amplifier circuit having a current source, an amplifier, and a load. The number of can be reduced.

  Another aspect of the present invention includes a differential unit having the current source described above and an output unit connected to an output node of the differential unit, wherein the differential unit includes a first differential unit. The present invention relates to an amplifier circuit including a transistor and a second differential transistor, and a current mirror circuit provided between the first differential transistor, the second differential transistor, and a second power supply node.

  According to another aspect of the present invention, since a circuit for generating a reference voltage for generating a tail current of a current source can be eliminated, the number of current paths in an amplifier circuit having a differential unit and an output unit is eliminated. Can be reduced.

  In another aspect of the invention, the output section includes a drive transistor controlled by an output node of the differential section, and a second current source provided between the drive transistor and the first power supply node. The second current source includes a second resistor having one end connected to the first power supply node, a source connected to the other end of the second resistor, and a gate connected to the first power source. A depletion-type second transistor to which a node is connected, the threshold voltage of the second transistor having a negative temperature characteristic, and the resistance value of the second resistor having a positive temperature characteristic. May be.

  This makes it possible to reduce the temperature dependence of the tail current of the current source of the output unit.

  In another aspect of the invention, the differential section may have an offset voltage between the non-inverting input terminal and the inverting input terminal.

  In this way, various operational amplification processes using this offset voltage can be realized.

  In another aspect of the present invention, the offset voltage is set by making the conductivity of the gate electrode of the first differential transistor different from the conductivity of the gate electrode of the second differential transistor. Also good.

  In this way, the offset voltage can be set by the work function difference voltage obtained by making the conductivity of the gate electrodes of the first and second differential transistors different.

  In another aspect of the present invention, the first differential transistor may be a depletion type transistor, and the first power supply node may be connected to a gate electrode of the first differential transistor.

  In this way, generation of a reference voltage or the like for flowing a current through the first differential transistor can be eliminated.

  In another aspect of the present invention, the W / L ratio of the first differential transistor is different from the W / L ratio of the second differential transistor, or the first mirror constituting the current mirror circuit is configured. The offset voltage may be set by making the W / L ratio of the current mirror transistor different from the W / L ratio of the second current mirror transistor constituting the current mirror circuit.

  In this way, the offset voltage can be set by changing the W / L ratio of the first and second differential transistors or by changing the W / L ratio of the first and second current mirror transistors. become able to.

  Another aspect of the present invention includes the amplifier circuit according to any one of the above and an operational amplification circuit element, wherein the resistor of the current source is an N well resistor formed by an N well, The present invention relates to an electronic circuit in which the operational amplification circuit element is laid out on the formation region of the resistor which is a well resistor.

  In this way, the layout efficiency can be improved because the N-well resistor that is the resistance of the current source and the operational amplification circuit element can be laid out in one area.

  In another aspect of the present invention, the operational amplification circuit element includes a poly resistor formed of a polysilicon layer, and the operational amplification circuit element is formed on the formation region of the resistor which is the N well resistor. Poly resistors may be laid out.

  In this way, the layout efficiency can be improved because the N-well resistance that is the resistance of the current source and the poly resistance that is the operational amplification circuit element can be laid out using one region.

  In another aspect of the present invention, the operational amplification circuit element includes a capacitor in which a first electrode is formed of a first polysilicon layer and a second electrode is formed of a second polysilicon layer, The capacitor, which is an operational amplification circuit element, may be laid out on the formation region of the resistor, which is the N well resistor.

  In this way, the layout efficiency can be improved because the N well resistor as the current source resistor and the capacitor as the operational amplification circuit element can be laid out in a single area.

  Another aspect of the present invention relates to an integrated circuit device including any of the amplifier circuits described above.

  Another aspect of the invention relates to an integrated circuit device including any of the electronic circuits described above.

  Another aspect of the invention relates to an electronic apparatus including the integrated circuit device described above.

The structural example of the current source of this embodiment. 1 is a first configuration example of an amplifier circuit including a current source according to the present embodiment. 5 is a second configuration example of a differential amplifier circuit including a current source according to the present embodiment. The 3rd structural example of the differential type amplifier circuit containing the current source of this embodiment. Explanatory drawing of a work function difference voltage. The structural example of the regulator which is an electronic circuit using the current source of this embodiment. The detailed structural example of the regulator which is an electronic circuit using the current source of this embodiment. The structural example of the comparative example of a regulator. FIG. 9A and FIG. 9B are diagrams comparing the temperature dependence of the tail current. FIGS. 10A and 10B are diagrams comparing variations in tail current values. FIG. 11A and FIG. 11B are layout examples of resistors. 2 is a configuration example of a constant current generation circuit that is an electronic circuit using the current source of the present embodiment. 3 is a detailed configuration example of a constant current generation circuit that is an electronic circuit using the current source of the present embodiment. FIG. 14A and FIG. 14B are other configuration examples of an electronic circuit using the current source of this embodiment. FIG. 15A and FIG. 15B are other examples of the electronic circuit using the current source of this embodiment. 2 shows a configuration example of an integrated circuit device. Configuration example of an electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Current Source FIG. 1 shows a configuration example of a current source according to this embodiment. As shown in FIG. 1, the current source of this embodiment includes a depletion type transistor TR and a resistor R. One end of the resistor R is connected to the VSS node (first power supply node in a broad sense). The depletion type N-type transistor TR is a transistor (NMOS transistor) in which the other end of the resistor R is connected to the source and the VSS node (first power supply node) is connected to the gate. By using a current source having such a configuration, a stable tail current ITL can be generated.

  For example, when the tail current ITL flowing through TR decreases due to an increase in the threshold voltage of the transistor TR, the voltage of the source node N1 of TR decreases. When the voltage at the source node N1 of the transistor TR is lowered, the voltage between the gate and the source of the TR is increased, so that the current flowing through the TR is increased, so that the tail current ITL flowing through the TR is kept constant. .

  On the other hand, when the tail current ITL flowing through TR increases due to a decrease in the threshold voltage of the transistor TR or the like, the voltage of the source node N1 of TR increases. When the voltage at the source node N1 of the transistor TR is increased, the voltage between the gate and the source of the TR is decreased, so that the tail current ITL flowing through the TR is reduced, and thereby the tail current ITL flowing through the TR is kept constant. Be drunk.

  As described above, the current source having the configuration of FIG. 1 has a configuration in which a current is generated in a self-contained manner to generate a voltage, and a negative feedback is applied in a circuit by a source resistance R provided in the source. Yes. Therefore, even when the transistor TR and the resistance R are varied, the generated tail current ITL is smaller than the transistor TR and the resistance R. Therefore, a stable tail current can be generated.

  In FIG. 1, the transistor TR is a depletion type N-type transistor, and the voltage of VSS (the voltage of the first power supply node, the ground voltage) is set to the gate electrode. That is, since the transistor TR is a depletion type N-type transistor, a current flows even when VSS is set to its gate electrode. Therefore, it is only necessary to set the gate electrode of the transistor TR to VSS, and it is not necessary to prepare a separate circuit for generating a reference voltage set to the gate electrode, so that the number of current paths can be reduced. That is, since the number of current paths can be reduced by the number of current paths of the reference voltage generation circuit, power consumption can be reduced.

  Further, the threshold voltage of the transistor TR has a negative temperature characteristic, and the resistance value of the resistor R has a positive temperature characteristic. For example, the resistor R is an N well resistor formed by an N well, and this N well resistor has a positive temperature characteristic. Therefore, as the temperature rises, the threshold voltage of the transistor TR decreases, while the resistance value of the resistor R increases, so that the tail current ITL flowing through the current source is kept substantially constant. When the temperature decreases, the threshold voltage of the transistor TR increases while the resistance value of the resistor R decreases. Therefore, the tail current ITL flowing through the current source is kept almost constant. Therefore, the temperature characteristic of the tail current ITL can be brought close to a flat characteristic.

  In other words, only the configuration in which negative feedback is provided by the resistor R cannot reduce the temperature variation, but the transistor TR has a negative temperature characteristic, while the resistor R has a positive temperature characteristic, thereby reducing the temperature variation. Reduction can also be realized.

2. Amplifier Circuit FIG. 2 shows a first configuration example of an amplifier circuit including a current source according to the present embodiment. FIG. 2 shows a configuration example of a single-ended amplifier circuit. This amplifier circuit includes the current source IS described with reference to FIG. 1, the amplifier section AP, and the load section LD.

  The amplification unit AP is provided in series with the current source IS. In FIG. 2, the amplification unit AP is configured by an N-type transistor TRA (NMOS transistor) whose input signal IN is input to its gate electrode. The source of the transistor TRA is connected to the drain of the depletion type transistor TR of the current source IS.

  The current source IS includes an N-type transistor TR whose gate electrode is connected to the VSS node, and a resistor R provided between the source of TR and the VSS node. The depletion type transistor TR has a negative temperature characteristic, and the resistor R has a positive temperature characteristic. The resistor R is formed by, for example, an N well resistor.

  The load unit LD is provided in series with the amplification unit AP. In FIG. 2, the load part LD is constituted by a P-type transistor TRL (PMOS transistor) to which the gate electrode and drain are connected. The drain of the transistor TRL is connected to the drain of the transistor TRA of the amplification unit AP, and an output signal Q obtained by amplifying the input signal IN is output from a connection node N3 of these drains.

  According to the configuration of FIG. 2, it is not necessary to separately provide a circuit for generating a reference voltage for generating the tail current ITL of the current source IS. Therefore, the number of current paths can be reduced by the number of current paths of the reference voltage generation circuit, so that power consumption can be reduced. Then, the small signal amplification processing of the input signal IN can be realized by using the tail current ITL of the current source IS.

  FIG. 3 shows a second configuration example of the amplifier circuit including the current source of the present embodiment. FIG. 3 shows a configuration example of a differential amplifier circuit. This amplifier circuit includes a differential section DF and an output section QB connected to the output node NC1 of the differential section DF.

  The differential unit DF includes first and second differential transistors TC1 and TC2, a current mirror circuit including transistors TC4 and TC5, and a current source ISC1.

  The differential transistor TC1 is provided between the current mirror transistor TC4 and the current source IS, and a non-inverted differential input signal INP (first differential input signal in a broad sense) is input to the gate electrode thereof. The The gate electrode of the differential transistor TC1 becomes a non-inverting input terminal (first differential input terminal in a broad sense).

  The differential transistor TC2 is provided between the current mirror transistor TC5 and the current source IS, and an inverted differential input signal INN (second differential input signal in a broad sense) is input to the gate electrode thereof. . The gate electrode of the differential transistor TC2 becomes an inverting input terminal (second differential input terminal in a broad sense).

  The current source ISC1 includes an N-type transistor TC3 whose gate electrode is connected to the VSS node, and a resistor RC1 provided between the source of the TC3 and the VSS node. The depletion type transistor TC3 has a negative temperature characteristic, and the resistor RC1 has a positive temperature characteristic. This resistor RC1 is formed by, for example, an N-well resistor.

  The P-type transistors TC4 and TC5 for the current mirror are provided between the N-type differential transistors TC1 and TC2 and the VDD node (second power supply node in a broad sense). Transistors TC4 and TC5 have their gate electrodes connected to node NC2, thereby forming a current mirror circuit.

  The output unit QB includes a drive transistor TDRC and a second current source ISC2 provided in series. The driving transistor TDRC is controlled by the output node NC1 of the differential section DF. Specifically, the output node NC1 of the differential section DF is connected to the gate electrode of the driving transistor TDRC. A node NC4 between the driving transistor TDRC and the current source ISC becomes an output node of the output signal Q of the amplifier circuit.

  The current source ISC2 includes an N-type transistor TC6 whose gate electrode is connected to the VSS node, and a resistor RC2 provided between the source of the TC6 and the VSS node. The depletion type transistor TC6 has a negative temperature characteristic, and the resistor RC2 has a positive temperature characteristic. The resistor RC2 is formed by an N well resistor, for example.

  According to the configuration of FIG. 3, it is not necessary to separately provide a circuit for generating a reference voltage for generating the tail currents ITL1 and ITL2 of the current sources ISC1 and ISC2. Therefore, the number of current paths can be reduced by the number of current paths of the reference voltage generation circuit, so that power consumption can be reduced. Then, the small signal differential amplification processing of the differential input signals INP and INN can be realized using the tail currents of the current sources ISC1 and ISC2. Note that the configuration of FIG. 3 may be used as a comparator instead of a normal operational amplifier.

  FIG. 4 shows a third configuration example of the amplifier circuit including the current source of the present embodiment. 4 differs from FIG. 3 in that the amplifier circuit of FIG. 4 has an offset voltage VOFF between the non-inverting input terminal and the inverting input terminal. Specifically, the work function difference voltage VWD which is the offset voltage VOFF is set by making the conductivity of the gate electrode of the differential transistor TC1 different from the conductivity of the gate electrode of the differential transistor TC2.

  For example, when the gate electrode of the differential transistor TC1 is N-type, the gate electrode of the differential transistor TC2 is P-type. TC1 is, for example, a depletion type N-type transistor (NMOS transistor), and TC2 is, for example, an enhancement type N-type transistor. For example, the differential transistors TC1 and TC2 have the same substrate impurity concentration and channel impurity concentration, but have different gate electrode conductivity and different gate electrode impurity concentrations.

Specifically, the threshold voltage of the MOS transistor can be expressed as Vth = φ _MS −Q _SS / C _OX + 2φ _F + Q _D / C _OX . Here, φ _MS is a work function difference between the gate electrode and the substrate (P well), Q _SS is a fixed charge in the oxide film, C _OX is a capacity per unit area of the gate oxide film, and φ _F Is the Fermi level, and Q _D is the charge in the depletion layer. Depending on the setting of the impurity concentration of the N-type gate electrode of the differential transistor TC1 and the impurity concentration of the P-type gate electrode of the differential transistor TC2, the threshold voltage of the differential transistor TC1 is, for example, about −0.2V to −0.5V. The threshold voltage of the differential transistor TC2 can be set to about 0.5V to 0.8V, for example.

  In FIG. 4, the transistor TC1 is a depletion type N-type transistor. The gate electrode of the transistor TC1 is set to the VSS voltage (the voltage of the first power supply node, the ground voltage). That is, since the transistor TC1 is a depletion type N-type transistor, a current flows even if VSS is set to its gate electrode. Accordingly, there is no need to separately provide a reference voltage generation circuit set for the gate electrode of the transistor TC1, so that the number of current paths can be reduced, and power consumption can be reduced.

  FIG. 5 is a band diagram for explaining the work function difference voltage. As shown in FIG. 5, the work function of the N-type gate electrode and the P well of the differential transistor TC1 on the non-inverting input terminal side and the P-type gate electrode and the P well of the differential transistor TC2 on the inverting input terminal side The work function difference becomes the work function difference voltage VWD.

  Note that the offset voltage between the non-inverting input terminal and the inverting input terminal of the differential section DF (the offset voltage between the first and second differential input terminals) is set other than the work function difference voltage as shown in FIG. May be. For example, the offset voltage may be set by changing the W / L ratio (current supply capability) of the differential transistor TC1 and the W / L ratio of the differential transistor TC2. Alternatively, the offset voltage can be changed by making the W / L ratio of the first current mirror transistor TC4 constituting the current mirror circuit different from the W / L ratio of the second current mirror transistor TC5 constituting the current mirror circuit. May be set.

  If the W / L ratio (current supply capability) of the differential transistor and the current mirror transistor is set in addition to the setting of the work function difference voltage VWD as described above, the offset voltage VOFF can be finely adjusted. For example, when the work function difference voltage VWD is about 0.9V and the offset voltage of 1V is to be used, a voltage of 0.1V, which is the difference between 1.0V and 0.9V, is applied to the differential transistor or current mirror. It is set by adjusting the W / L ratio of the transistor for use differently. In this way, the offset voltage VOFF can be finely adjusted, for example, a constant voltage generated by a regulator as described later can be finely adjusted, or a constant current generated by a constant current generating circuit can be finely adjusted. become.

3. Electronic Circuit, Regulator Hereinafter, an electronic circuit including the amplifier circuit of this embodiment will be described. This electronic circuit includes an amplifier circuit including the current source of the present embodiment and a circuit element for operational amplification. The operational amplification circuit element is a circuit element used for operational amplification processing using an amplification circuit, and is a passive element such as a resistor, a capacitor, or an inductor.

  In the present embodiment, for example, N-well resistors formed by N-wells are used as the resistors (resistors R, RC1, and RC2 in FIGS. 1 to 4) constituting the current source. Then, as shown in FIGS. 11A and 11B, which will be described later, an operational amplification circuit element is laid out on the N well resistance formation region. For example, when the operational amplification circuit element is a poly resistor formed of a polysilicon layer, the operational amplifier circuit element poly resistor is laid out on the formation region of the N-well resistance that is the current source resistance. To do. Further, when the operational amplification circuit element is a capacitor in which the first electrode is formed of the first polysilicon layer and the second electrode is formed of the second polysilicon layer, the N-well resistor is formed. A capacitor, which is a circuit element for operational amplification, is laid out on the region. In this way, various operational amplification processes can be realized with a small layout area.

  FIG. 6 shows a configuration example of a regulator (constant voltage generation circuit) which is an example of such an electronic circuit. The regulator includes an amplifier circuit AM and first and second resistors RB1 and RB2. Further, a phase compensation capacitor C0 is included.

  The amplifier circuit AM is a differential amplifier circuit (op-amp) having an offset voltage VOFF between a non-inverting input terminal (first differential input terminal) and an inverting input terminal (second differential input terminal). . That is, in a general differential amplifier circuit, the voltage difference between the non-inverting input terminal and the inverting input terminal is approximately 0 V in the case of virtual ground, but in the amplifier circuit AM of FIG. An offset voltage VOFF due to a work function difference voltage or the like is set between the inverting input terminals.

  The resistors RB1 and RB2 are provided in series between the output node NQ1 of the amplifier circuit AM and the VSS node (first power supply node). The voltage of output node NQ1 is voltage-divided by resistors RB1 and RB2, and a divided voltage is generated at connection node NQ2.

  The phase compensation capacitor C0 is a capacitor having one end connected to a connection node NQ2 between the resistors RB1 and RB2. In FIG. 6, the other end of the phase compensation capacitor C0 is connected to the VSS node. Note that the other end of the capacitor C0 may be connected to a VDD node (second power supply node) or the like. The capacitor C0 can be realized by, for example, a capacitor having a structure composed of a first layer of polysilicon and a second layer of polysilicon, a capacitor having an MIM (Metal-Insulator-Metal) structure, a gate capacitor, or the like.

  In the regulator of FIG. 6, the signal (voltage) at the connection node NQ2 of the resistors RB1 and RB2 is fed back (positive feedback) to the non-inverting input terminal (positive side terminal) of the amplifier circuit AM. The signal (voltage) at the output node NQ1 of the amplifier circuit AM is fed back (negative feedback) to the inverting input terminal (negative terminal) of the amplifier circuit AM. Specifically, the connection node NQ2 is connected to the non-inverting input terminal of the amplifier circuit AM, and the output node NQ1 is connected to the inverting input terminal of the amplifier circuit AM.

  For example, in a general differential amplifier circuit, a connection for feeding back a signal to both the non-inverting input terminal and the inverting input terminal is not performed. In this regard, since the amplifier circuit AM in FIG. 6 is an amplifier circuit having an offset voltage VOFF between the non-inverting input terminal and the inverting input terminal, such feedback connection is possible. By adopting such a feedback connection, the negative feedback becomes a voltage follower, and the positive feedback can determine the output voltage by adjusting the feedback amount by resistance division.

  Specifically, the resistance values of the resistors RB1 and RB2 are R1 and R2. Then, the regulator of FIG. 6 generates a constant voltage of Q1 = VREG = VOFF × {(R1 + R2) / R1}.

  For example, a conventional regulator requires a circuit for generating a reference voltage for generating a constant voltage. Accordingly, since there is a current path in the reference voltage generation circuit, power is wasted for the current path.

  On the other hand, in the regulator of FIG. 6, even if such a reference voltage generation circuit is not provided, the offset voltage VOFF of the amplifier circuit AM is used as a reference voltage, and Q1 = VREG = VOFF × {(R1 + R2) / R1} is constant. A voltage is generated. Accordingly, the number of current paths is reduced by the number of current paths of the reference voltage generation circuit, so that low power consumption can be realized.

  In FIG. 6, the signal at the output node NQ1 of the amplifier circuit AM is fed back (negative feedback) to the inverting input terminal of the amplifier circuit AM, and the signal at the connection node NQ2 of the resistors RB1 and RB2 is fed back to the non-inverting input terminal (positive). (Return). A phase compensation capacitor C0 is provided for this connection node NQ2. By doing so, it is possible to prevent oscillation of the circuit and realize stable operation of the circuit. Therefore, according to the regulator of FIG. 6, it is possible to achieve both stable operation of the circuit and low power consumption.

  Moreover, in a general regulator design method, an operational amplification circuit for voltage generation performs operational amplification (for example, 1.5 times operational amplification) based on some reference voltage (for example, 1V), A voltage (for example, 1.5V) is generated. A buffering amplifier circuit (for example, a voltage follower-connected amplifier circuit) performs buffering of the voltage after the operational amplification, thereby ensuring the current supply capability of the regulator.

  According to this method, design can be performed in two stages such as an operational amplification part and a buffering part, so that the design can be facilitated. That is, the circuit configuration of performing buffering while performing operational amplification is very difficult to design from the viewpoint of circuit stabilization. When performing operational amplification, negative feedback via a feedback resistor is required, but the design should be made while ensuring both stability against phase lag caused by the feedback resistor and feedback capacitance and current supply capability. This is because it is extremely difficult.

  In this regard, the regulator of FIG. 6 is configured to realize operational amplification and buffering with a single amplifier circuit. That is, the viewpoint of design for operational amplification is brought to the positive feedback side, and the viewpoint of design for buffering is brought to the negative feedback side, which is different from the conventional general regulator design method. Yes.

  FIG. 7 shows a detailed configuration example of the regulator of FIG. As shown in FIG. 7, the amplifier circuit AM includes a differential unit DF and an output unit QB connected to the output node NB1 of the differential unit DF. Furthermore, a capacitor CC and a resistor RC for phase compensation can be included.

  The differential unit DF includes first and second differential transistors TB1 and TB2, a current mirror circuit composed of transistors TB4 and TB5, and a current source ISB1. The gate electrode of the differential transistor TB1 is connected to a connection node NQ2 between the resistors RB1 and RB2. The gate electrode of differential transistor TB2 is connected to output node NQ1. The differential transistors TB1 and TB2 have different gate electrode conductivities, and the difference between the threshold voltages of these TB1 and TB2 becomes the work function difference voltage VWD.

  The output part QB includes a drive transistor TDR and a second current source ISB2 provided in series. Then, the signal of the connection node NQ1 between the driving transistor TDR and the second current source ISB2 is input to the inverting input terminal (second differential input terminal) which is the gate electrode of the transistor TB2 of the differential section DF and fed back. Is done. The signal at the connection node NQ2 between the resistors RB1 and RB2 is input to the non-inverting input terminal (first differential input terminal) that is the gate electrode of the transistor TB1 of the differential section DF and fed back. The phase compensation capacitor CC and resistor RC are provided between the output node NB1 of the differential section DF and the output node NQ1 of the output section QB.

  The resistors RB1 and RB2 are provided between the output node NQ1 and the VSS node of the output unit QB. The phase compensation capacitor C0 is provided between the connection node NQ2 of the resistors RB1 and RB2 and the VSS node.

  The first current source ISB1 includes a first current source resistor RB3 and a first current source transistor TB3. One end of the current source resistor RB3 is connected to the VSS node (first power supply node). The current source transistor TB3 is a depletion type transistor (NMOS transistor) having a source connected to the other end of the current source resistor RB3 and a gate connected to the VSS node.

  Similarly, the second current source ISB2 includes a second current source resistor RB4 and a second current source transistor TB6. One end of the current source resistor RB4 is connected to the VSS node (first power supply node). The current source transistor TB6 is a depletion type transistor (NMOS transistor) having a source connected to the other end of the current source resistor RB4 and a gate connected to the VSS node.

  As described above, in FIG. 7, the current sources described in FIG. 1 and the like are used as the current sources ISB1 and ISB2. In this way, even when there are temperature fluctuations and manufacturing process fluctuations, variations in the tail currents ITL1 and ITL2 flowing through the current sources ISB1 and ISB2 can be minimized, and the stable tail currents ITL1 and ITL2 are stable. Can be generated.

Further, when each transistor is modeled for small signal analysis in the circuit of FIG. 7 and the transfer function H1 (S) from the input to Q1 is solved, the poles and zeros are obtained by the following equations (1) to (6). . Note that gm _TDR and rds _TDR are gm and rds of the small signal analysis model of the driving transistor TDR, and R1 and R2 are resistance values of the resistors RB1 and RB2. For the transistors TB4 and TB5 in FIG. 7, a model having rds and gate / source capacitance in addition to the gm element is used. In addition, regarding the solution of the pole, if the mathematical expression is solved as it is, it becomes too complicated. Therefore, an operation that simplifies the portion that has little influence even if it is simplified is performed. That is, a simplified operation for extracting and rewriting the main term from the numerator / denominator is performed, for example, in the following equations (1) and (2). In FIG. 7, it is assumed that the differential transistors TB1 and TB2 have the same size, and the transistors TB4 and TB5 constituting the current mirror circuit also have the same size. Therefore, in the following formulas (1) to (6), an operation of replacing one of these with the other is appropriately performed.

  Thus, in the transfer function H1 (S) from the input to the Q1 when the phase compensation capacitor C0 is provided, the poles are P1, P2, and P3 of the above equations (1), (2), and (3). The zeros are Z1, Z2, and Z3 in the above equations (4), (5), and (6). On the other hand, in the transfer function H2 (S) to Q2, the poles are P1, P2, and P3, the zero points are Z1 and Z3, and the zero point Z2 does not exist.

Since the pole P3 and the zero point Z1 are close in frequency, and the negative pole and the negative zero point cancel each other in both the gain and phase frequency characteristics, the pole P3 and the zero point Z1 can be ignored. It is. Furthermore, the zero point Z3 can be skipped to a high frequency by setting the resistance value of the resistor RC so that gm _TDR · RC = 1.

  Thus, the pole P3 and the zeros Z1 and Z3 can be excluded from the analysis target. Accordingly, in the transfer function H1 (S) to Q1, only the poles P1 and P2 of the above equations (1) and (2) and the zero point Z2 of the above equation (5) need to be considered, and Q2 where the zero point Z2 does not exist In the transfer function H2 (S), only the poles P1 and P2 of the above equations (1) and (2) need be considered.

In the transfer function H1 (S) to Q1 when the phase compensation capacitor C0 is provided, the phase is delayed by 90 degrees due to the pole P1. The phase is also delayed by 90 degrees due to the pole P2, and this can be offset by the zero point Z2 by adjusting the gm _TDR and selecting the resistance value of the RB1. Specifically, it can be adjusted by sufficiently increasing the resistance value R1 of RB1 and increasing gm _TDR (increasing current, increasing W / L ratio). As a result, the phase is only 90 degrees delayed by the pole P1.

  On the other hand, in the transfer function H2 (S) to Q2 when the capacitor C0 is provided, the phase is delayed by 90 degrees due to the pole P1. Although the phase is also delayed by 90 degrees due to the pole P2, unlike the case of the transfer function H1 (S) to Q1, the phase is delayed by 180 degrees because the zero point Z2 does not exist.

  As described above, by providing the capacitor C0 and canceling out the phase delay due to the pole P2 at the zero point Z2, the transfer function to Q1 has a phase delay of 90 degrees due to the pole P1. Therefore, by returning Q1 to the inverting input terminal as shown in FIG. 7, oscillation is prevented and the circuit operation becomes stable. That is, in the negative feedback that is feedback to the inverting input terminal, if the phase delay is about 120 degrees or less, the phase margin is 60 degrees or more, so that the stable operation of the circuit can be secured. Therefore, by negatively feeding back the output Q1 having a phase delay of 90 degrees to the inverting input terminal, the oscillation operation of the circuit can be prevented and the stable operation of the circuit can be ensured.

  Also, by providing the capacitor C0, the transfer function to Q2 is 180 degrees behind the phase due to the poles P1 and P2. Therefore, as shown in FIG. 7, by positively feeding back the output Q2 having a phase delay of 180 degrees to the non-inverting input terminal, oscillation is prevented and the circuit operation is stabilized.

In this case, in FIG. 7, by increasing the resistance value of RB1 (necessarily increasing the resistance value of RB2), the current consumption flowing from the node NQ1 to VSS is reduced, and gm _TDR is increased. Realizes stable operation of the circuit.

  For example, the current path in the regulator of FIG. 7 is the path of the current source ISB1, the path of the current source ISB2, and the paths of the resistors RB1 and RB2. Among these, for the paths of the resistors RB1 and RB2, by forming the RB1 and RB2 with, for example, a high-resistance polysilicon resistor and setting the resistance value to, for example, 50 M ohms or more, the current flowing through the current path is reduced as much as possible. it can. Further, by increasing the resistance value R1 of RB1, the phase delay due to the pole P2 can be canceled at the zero point Z2 as described above to return the phase, and the circuit operation can be stabilized.

Further, in order to cancel the phase delay due to the pole P2 at the zero point Z2, it is necessary to increase the gm _{TDR of the} driving transistor TDR. For this reason, the consumption current of the regulator in FIG. 7 is the tail current flowing in the current source ISB2. ITL2 becomes dominant. That is, since the tail current ITL1 and the current flowing through RB1 and RB2 can be sufficiently reduced, the tail current ITL2 becomes dominant in the overall consumption current.

  On the other hand, in FIG. 7, the current source ISB2 includes a depletion type transistor TB6 having a negative temperature characteristic and a P-well resistor RB4 having a positive temperature characteristic. Accordingly, as shown in FIGS. 9A to 10B, which will be described later, variations in the tail current ITL2 due to temperature fluctuations, power supply voltage fluctuations, and process fluctuations can be reduced. Therefore, it is not necessary to take a wide design margin, so that the value of the tail current ITL2 that is dominant in the entire current consumption can be made sufficiently close to the low current consumption side. As a result, the current consumption of the regulator can be further reduced.

  FIG. 8 shows a configuration example of a regulator as a comparative example of the regulator of FIG. In this comparative example, the configurations of the current sources ISB1 and ISB2 are different from those in FIG.

  In the comparative example of FIG. 8, the reference voltage VR is generated by the reference voltage generation circuit REFG configured by the transistors TG1 and TG2. The reference voltage VR is input to the gate electrodes of the transistors TG3 and TG4, thereby generating tail currents ITL1 and ITL2 in the current sources ISB1 and ISB2.

  In the comparative example of FIG. 8, the number of current paths is larger than that of FIG. 7 by the amount of the current path of the current IRG in the reference voltage generation circuit REFG. Therefore, current consumption increases. On the other hand, the regulator of FIG. 7 can reduce the number of current paths compared to FIG.

  9A and 9B show the temperature dependence and power supply voltage dependence of the tail current generated by the current source having the configuration of the present embodiment and the tail current generated by the current source having the configuration of FIG. It is the figure which compared sex.

  In FIGS. 9A and 9B, the resistances RB3 and RB4 of the current sources ISB1 and ISB2 in FIG. 7 are N-well resistors having positive temperature characteristics and those having flat temperature characteristics. The case of resistance is shown in comparison.

  As shown in FIG. 9A, when the current sources ISB1 and ISB2 are configured by the depletion type transistors TB3 and TB6 and the N-well resistors RB3 and RB4, the temperature characteristics of the tail current ITL (ITL1, ITL2) are substantially flat. can do. Therefore, fluctuations in the tail current ITL due to temperature fluctuations can be suppressed.

  On the other hand, if the current source is configured as in the comparative example of FIG. 8, the temperature characteristics of the tail current ITL (ITL1, ITL2) are not flat, and the tail current ITL also varies due to temperature variation. The same applies when the resistors RB3 and RB4 are made of poly resistors.

  As shown in FIG. 9B, when the current sources ISB1 and ISB2 are configured by the depletion type transistors TB3 and TB6 and the resistors RB3 and RB4, the tail current ITL can be kept substantially constant even when the power supply voltage changes. Therefore, the fluctuation of the tail current ITL due to the fluctuation of the power supply voltage can be suppressed. This is the same when the resistors RB3 and RB4 are made of poly resistors.

  On the other hand, if a current source is configured as in the comparative example of FIG. 8, when the power supply voltage changes, the tail current ITL also changes. Therefore, fluctuations in the tail current ITL due to fluctuations in the power supply voltage cannot be suppressed, and the current source having the configuration of this embodiment is more advantageous in this respect.

  FIG. 10A is a histogram comparing the tail current generated by the current source having the configuration of the present embodiment and the tail current generated by the current source having the configuration of the comparative example of FIG. In FIG. 10A, a histogram is created using the Monte Carlo method. FIG. 10B shows the average value, maximum value, minimum value, and variance of the tail current.

  As shown in FIG. 10A, according to the current source having the configuration of the present embodiment, due to resistance feedback, it is caused by variations in the manufacturing process such as variations in the threshold voltage of the transistor and variations in the gate length. Variation in tail current can be suppressed. Therefore, it is possible to generate a tail current with high accuracy.

4). Layout Arrangement FIGS. 11A and 11B show examples of resistor layout arrangement. FIG. 11A is a plan view, and FIG. 11B is a cross-sectional view.

  In FIG. 7, the resistors RB1 and RB2 (operational amplification circuit elements in a broad sense) are formed of poly resistors, while the resistors RB3 and RB4 for the current sources of the differential unit DF and the output unit QB are positive. N-well resistors having the following temperature characteristics. By forming RB3 and RB4 with N-well resistors to have a positive temperature characteristic, it becomes possible to cancel out the negative temperature characteristic of the threshold voltage of the depletion type transistors TB3 and TB6, and the current source The temperature characteristics of the tail currents ITL1 and ITL2 of ISB1 and ISB2 can be made flat.

  On the other hand, in order to reduce power consumption, it is necessary to reduce the current values of the currents flowing through RB1 and RB2 and the tail currents ITL1 and ITL2 flowing through the current sources ISB1 and ISB2, and to reduce these current values. Therefore, it is necessary to increase the resistance values of the resistors RB1, RB2, RB3, and RB4.

  However, if the resistance values of the resistors RB1 to RB4 are to be increased, the layout area of the resistors RB1 to RB4 is increased, leading to an increase in the scale of the integrated circuit device.

  Therefore, in the present embodiment, the layout method shown in FIGS. 11A and 11B is employed.

  That is, in FIG. 11A, resistors RB1 and RB2 in FIG. 7 are poly resistors formed by a polysilicon layer, and resistors RB3 and RB4 are N well resistors formed by an N well. . Then, as shown in FIG. 11A, the resistors RB1 and RB2 which are poly resistors are laid out on the formation region of the resistors RB3 and RB4 which are N well resistors. In other words, the resistors RB3 and RB4 that are N-well resistors and the resistors RB1 and RB2 that are poly resistors are laid out so as to overlap in plan view.

  Specifically, in FIG. 11A, the resistors RB1 and RB2 are formed of a plurality of poly resistor units. That is, a plurality of poly resistance units are arranged in a snake shape, and adjacent poly resistance units are connected via metal wiring and contacts. One end of the resistors RB1 and RB2 becomes the tap TPP1, and the other end becomes the tap TPP2. Taking FIG. 7 as an example, in the resistor RB1, the node NQ1 is connected to the tap TPP1, and the node NQ2 is connected to the tap TPP2. In the resistor RB2, the node NQ2 is connected to the tap TPP1, and VSS is connected to the tap TPP2.

  The resistors RB3 and RB4 are constituted by a plurality of N-well resistor units. That is, a plurality of N-well resistance units are arranged in a snake shape, and adjacent N-well resistance units are connected via metal wiring and contacts. One end of the resistors RB3 and RB4 is a tap TPN1, and the other end is a tap TPN2. Taking FIG. 7 as an example, in the resistor RB3, the source of the transistor TB3 is connected to the tap TPN1, and VSS is connected to the tap TPN2. In the resistor RB4, the source of the transistor TB6 is connected to the tap TPN1, and VSS is connected to the tap TPN2. Note that the layout arrangement of the poly resistors and the N well resistors is not limited to that shown in FIG. 11A, and various modifications can be made.

  In FIG. 11A, the poly resistance units are arranged such that the longitudinal direction thereof is in the lateral direction (first direction) with respect to the paper surface, and the N well resistance units are arranged with the longitudinal direction perpendicular to the paper surface. It arrange | positions so that it may become a direction (2nd direction orthogonal to a 1st direction). In this way, the tap TPP1 and TPP2 take-out location and the tap TPN1 and TPN2 take-out location can be made different, so that the layout of the signal wiring can be simplified and made more efficient.

  11A and 11B, the resistors RB1 and RB3 and RB2 and RB4 can be laid out using one region of the integrated circuit device. Therefore, the layout efficiency can be improved and the area of the integrated circuit device can be reduced.

  11A and 11B, since two resistors (poly resistor and N well resistor) can be arranged in one region, the layout area of each resistor is increased in order to increase the resistance value of each resistor. Even if the size is increased, the increase in the overall layout area can be minimized. Therefore, it is easy to reduce the power consumption of the circuit by increasing the resistance value of each resistor.

  In particular, in the present embodiment, attention is paid to the fact that if the resistors RB3 and RB4 are formed of N-well resistors, another circuit element can be laid out thereon. Therefore, the resistors RB3 and RB4 having positive temperature characteristics are realized by N-well resistors, the resistors RB1 and RB2 are realized by poly resistors, and a poly resistor is formed on the N well resistors, thereby reducing the layout area. Plan

  In this case, if the N-well resistor and the poly resistor are laid out in the same place, the resistance value of the other resistor may be changed by the voltage from one resistor. However, the accuracy of the N-well resistor is not emphasized, and it is sufficient that the resistance value is high. Therefore, the resistance value variation due to the voltage from the poly resistor is not a problem. On the other hand, when the resistance value of the poly resistor is increased, the resistance of the resistance value due to the voltage from the upper and lower elements becomes more susceptible. However, since the voltages applied to the N-well resistors RB3 and RB4 in FIG. 7 are close to 0V, there is an advantage that the adverse effect on the poly-resistance is not so problematic.

5). Constant Current Generation Circuit FIG. 12 shows a configuration example of a constant current generation circuit which is an example of an electronic circuit. The constant current generation circuit includes a differential unit DF and an output unit QB.

  In the differential section DF, transistors TA1 and TA2 are provided as first and second differential transistors. For example, the gate electrode of the transistor TA1 becomes the non-inverting input terminal (first differential input terminal) of the differential unit DF, and the gate electrode of the transistor TA2 becomes the inverting input terminal (second differential input) of the differential unit DF. Input terminal).

  The output unit QB includes a resistor RA1 and a drive transistor TDR (PMOS transistor) provided in series with the resistor RA1. That is, the P-type driving transistor TDR and the resistor RA1 are provided in series between VDD and VSS.

  In FIG. 12, the non-inverting input terminal (first differential input terminal) of the differential section DF is set to the first reference voltage VRF1. The signal (voltage) at the connection node NA4 between the driving transistor TDR of the output unit QB and the resistor RA1 is fed back to the inverting input terminal (second differential input terminal) of the differential unit DF. The drive transistor TDR is controlled by the output node NA1 of the differential section DF. For example, the current IA1 flowing through the resistor RA1 is controlled by controlling the gate electrode of the driving transistor TDR by the output node NA1 of the differential section DF.

  According to the configuration of FIG. 12, a voltage corresponding to the work function difference voltage VWD is applied to the resistor RA1. Since the work function difference voltage VWD has negative temperature characteristics and the resistance value of the resistor RA1 also has negative temperature characteristics, the temperature dependence of the current IA1 flowing through the resistor RA1 can be reduced. Accordingly, it is possible to generate a constant current IREF having a flatter temperature characteristic.

  In the configuration of FIG. 12, the voltage at the node NA4 is fed back to the differential section DF, and the gate electrode of the drive transistor TDR is controlled. Therefore, for example, even when there is a power supply voltage fluctuation or a manufacturing process variation, the feedback control is performed by the signal of the node NA4, whereby the variation of the constant current IREF can be reduced.

  FIG. 13 shows a more detailed configuration example of the constant current generation circuit of FIG. In FIG. 13, the differential section DF includes a current source ISA, transistors TA1 and TA2 that are first and second differential transistors, and transistors TA4 and TA5 that form a current mirror circuit.

  The output unit QB includes a drive transistor TDR and a resistor RA1 provided in series, and transistors TA6 and TA7 provided in series. A signal at the connection node NA4 between the driving transistor TDR and the resistor RA1 is input to the inverting input terminal (second differential input terminal) which is the gate electrode of the transistor TA2 of the differential section DF and fed back. The non-inverting input terminal (first differential input terminal) which is the gate electrode of the transistor TA1 of the differential section DF is set to VSS (voltage of the first power supply node).

  The gate electrodes of the P-type transistors TDR and TA6 of the output unit QB are controlled by the signal of the output node NA1 between the transistors TA1 and TA4 of the differential unit DF. Here, the ratio of the current IA1 flowing through the resistor RA1 and the constant current IREF is set by setting the transistor ratio (W / L) of the transistors TDR and TA6.

  The N-type transistor TA7 has its gate and drain connected to the node NA5, and the bias voltage VBS from the node NA5 is supplied to each analog circuit of the integrated circuit device. Each analog circuit can obtain a constant current corresponding to the constant current IREF by using the bias voltage VBS.

  In the circuit of FIG. 13, the signal at the node NA4 is fed back to the gate electrode of the transistor TA2. Accordingly, since the gate electrode of the transistor TA1 is set to VSS, the gate electrode of the driving transistor TDR is feedback controlled by the output node NA1 of the differential section DF so that the voltage of the node NA4 becomes the work function difference voltage VWD. Is done. Therefore, the constant current IREF with high accuracy can be generated even when the power supply voltage fluctuates.

  In FIG. 13, the current source ISA includes a transistor TA3 and a resistor RA2, and is a current source having the configuration of this embodiment described with reference to FIG. The transistors TA1 and TA3 are depletion type N-type transistors, and the voltage of VSS is set to these gate electrodes. That is, since TA1 and TA3 are depletion type N-type transistors, a current flows even when VSS is set to the gate electrode. Therefore, it is only necessary to set the gate electrodes of the transistors TA1 and TA3 to VSS, and it is not necessary to separately provide a reference voltage generation circuit set for these gate electrodes, so that the number of current paths can be reduced. That is, since the number of current paths can be reduced by the number of current paths of the reference voltage generation circuit, power consumption can be reduced.

  In the constant current generating circuit of FIG. 13, the resistor RA2 constituting the current source ISA can be formed by an N-well resistor having a positive temperature characteristic. On the other hand, the resistor RA1 (circuit element for operational amplification in a broad sense) can be formed by, for example, a polysilicon resistor having negative temperature characteristics. Then, as described with reference to FIGS. 11A and 11B, the poly resistor RA1, which is a circuit element for operational amplification, is laid out on the formation region of the N well resistor RA2.

  That is, in the circuit of FIG. 13, both a resistor RA1 having a negative temperature characteristic and a resistor RA2 having a positive temperature characteristic are necessary. Therefore, the resistor RA2 having a positive temperature characteristic is realized by an N-well resistor, and the resistor RA1 having a negative temperature characteristic is realized by a poly resistor. Then, a poly resistor RA1 is laid out on the N well resistor RA2 so as to overlap in plan view. In this way, since both the resistors RA1 and RA2 can be laid out using one region of the integrated circuit device, the layout area can be reduced. Further, since the voltage applied to the N-well resistor RA2 in FIG. 13 is close to 0V, there is an advantage that the adverse effect of the voltage of the N-well resistor RA2 on the poly resistor RA1 does not matter so much.

6). Other Configuration Examples of Electronic Circuit As an electronic circuit to which the amplifier circuit of this embodiment can be applied, various circuits can be considered in addition to the regulators of FIGS. 6 and 7 and the constant current generation circuits of FIGS.

  For example, FIG. 14A illustrates a configuration example of an inverting amplifier circuit which is one of electronic circuits. This inverting amplifier circuit includes an amplifier circuit AM and resistors RD1 and RD2 which are circuit elements for operational amplification. Specifically, a resistor RD1 is provided between the node of the input signal IN and the node ND1 of the inverting input terminal of the amplifier circuit AM, and a resistor RD2 is provided between the node ND1 and the node ND2 of the output signal Q.

  As the amplifier circuit AM, the amplifier circuit having the configuration shown in FIG. 3 can be used. The amplifier circuit AM includes a current source ISC1 having the configuration of this embodiment, and the resistor RC1 of the current source ISC1 is formed of an N-well resistor. The resistors RD1 and RD2, which are circuit elements for operational amplification, are formed of polysilicon resistors. Then, as described with reference to FIGS. 11A and 11B, the poly-resistors RD1 and RD2, which are operational amplification circuit elements, are laid out on the formation region of the N-well resistor RC1, thereby reducing the layout area. Can be made compact.

  FIG. 14B illustrates a configuration example of an integration circuit which is one of electronic circuits. This integrating circuit includes an amplifier circuit AM, a resistor RE1 which is a circuit element for operational amplification, and a capacitor CE1. Specifically, a resistor RE1 is provided between the node of the input signal IN and the node NE1 of the inverting input terminal of the amplifier circuit AM, and a capacitor CE1 is provided between the node NE1 and the node NE2 of the output signal Q.

  As the amplifier circuit AM, the amplifier circuit having the configuration shown in FIG. 3 can be used. The amplifier circuit AM includes a current source ISC1 having an N-well resistor RC1. The resistor RE1 that is an operational amplification circuit element is formed of a polysilicon resistor, and the capacitor CE1 that is an operational amplification circuit element has a first electrode formed of a first polysilicon layer and a second electrode thereof. Is formed of a second polysilicon layer.

  As described with reference to FIGS. 11A and 11B, the layout area is obtained by laying out the poly resistor RE1 and the capacitor CE1 which are circuit elements for operational amplification on the formation region of the N well resistor RC1. Can be made compact.

  FIG. 15A illustrates another configuration example of a regulator that is one of electronic circuits. This regulator includes an amplifier circuit AM, a driving transistor TF1, and resistors RF1 and RF2 which are circuit elements for operational amplification. The voltage dividing node NF1 of the resistors RF1 and RF2 is fed back to the inverting input terminal of the amplifier circuit AM, and the gate electrode of the driving transistor TF1 is controlled by the output node NF2 of the amplifier circuit AM, so that the output signal Q is constant at the node NF3. A voltage is generated.

  As the amplifier circuit AM, the amplifier circuit having the configuration shown in FIG. 3 can be used. The amplifier circuit AM includes a current source ISC1 having an N-well resistor RC1. The resistors RF1 and RF1, which are operational amplification circuit elements, are formed of polysilicon resistors.

  As described with reference to FIGS. 11A and 11B, the layout resistance of the poly-resistors RF1 and RF2, which are operational amplification circuit elements, is laid out on the formation region of the N-well resistor RC1. Can be made compact.

  FIG. 15B illustrates a configuration example of a low-pass filter that is one of electronic circuits. This low-pass filter includes an amplifier circuit AM, resistors RH1 and RH2, and a capacitor CH1. Specifically, a resistor RH1 is provided between the node of the input signal IN and the node NH1 of the non-inverting input terminal of the amplifier circuit AM, and a capacitor CH1 is provided between the node NH1 and the VSS node, thereby inverting the amplifier circuit AM. A resistor RH2 is provided between the node NH2 of the input terminal and the node NH3 of the output signal Q.

  As the amplifier circuit AM, the amplifier circuit having the configuration shown in FIG. 3 can be used. The amplifier circuit AM includes a current source ISC1 having an N-well resistor RC1. The resistors RH1 and RH1 that are operational amplification circuit elements are formed of polysilicon resistors, and the capacitor CH1 that is an operational amplification circuit element has a first electrode formed of a first polysilicon layer, and a second Are formed of the second polysilicon layer.

  11A and 11B, the poly resistors RH1 and RH2 and the capacitor CH1 which are operational amplification circuit elements are laid out on the formation region of the N well resistor RC1, The layout area can be made compact.

  Note that the electronic circuit to which this embodiment is applied is not limited to the circuit having the configuration shown in FIGS. 6, 7, 12, 13, 13, 14A to 15B, and at least in FIG. Any circuit using a current source as shown may be used.

7). Integrated Circuit Device FIG. 16 shows a configuration example of an integrated circuit device including the amplifier circuit and electronic circuit of this embodiment. FIG. 17 shows an example in which the integrated circuit device is an RF wireless communication IC. The integrated circuit device includes a reception circuit 30, a demodulation circuit 36, a transmission circuit 40, a modulation circuit 46, a clock generation circuit 48, a control circuit 50, a constant current generation circuit 60, a regulator 100, and a power-on reset circuit 110.

  The receiving circuit 30 includes a low noise amplifier LNA, a mixer 32, and a filter unit 34. The low noise amplifier LNA performs processing for amplifying an RF reception signal input from the antenna ANT with low noise. The mixer 32 performs a down conversion by performing a mixing process of the amplified received signal and the local signal (local frequency signal) from the clock generation circuit 48. The filter unit 34 performs a filtering process on the received signal after the down conversion. Specifically, the filter unit 34 performs bandpass filter processing realized by a complex filter or the like, and extracts a baseband signal while performing image removal.

  The demodulation circuit 36 performs demodulation processing based on the signal from the reception circuit 30. For example, demodulation processing of a signal modulated by FSK (frequency shift keying) is performed on the transmission side, and the demodulated reception signal is output to the control circuit 50.

  The modulation circuit 46 performs a modulation process on the transmission signal from the control circuit 50. For example, the transmission signal is modulated by FSK, and the modulated transmission signal is output to the transmission circuit 40. Then, the transmission circuit 40 outputs the transmission signal amplified by the power amplifier PA to the antenna ANT.

  The clock generation circuit 48 includes a PLL circuit configured by a VCO (voltage controlled oscillator) or the like, and generates various clock signals, local signals to the mixer 32, and the like.

  The control circuit 50 (logic circuit) performs overall control of the integrated circuit device, digital processing in the baseband, and the like. The control circuit 50 includes, for example, a link layer circuit 52 and a host I / F (interface) 54, and executes link layer protocol processing, interface processing with an external host, and the like.

  The constant current generation circuit 60 is a circuit having the configuration described with reference to FIGS. 12 and 13, for example, and supplies a constant current to each analog circuit in the integrated circuit device such as the reception circuit 30, the transmission circuit 40, and the clock generation circuit 48. Supply. Each analog circuit performs various types of analog processing such as signal amplification processing, signal detection processing, or signal filtering processing, using the supplied constant current.

  In this way, each analog circuit can perform analog processing using the constant current having a stable temperature characteristic generated by the constant current generation circuit 60 of the present embodiment, so that the characteristics of the analog processing are improved. Can be planned. If the configurations shown in FIGS. 12 and 13 are employed as the constant current generation circuit 60, for example, the number of current paths can be reduced, so that power consumption during standby can be minimized.

  For example, the regulator 100 is a circuit having the configuration described with reference to FIGS. 6 and 7, and receives the external power supply voltage VDDE and supplies the power supply voltage VDDA after voltage adjustment to the power-on reset circuit 110 and the control circuit 50. The power-on reset circuit 110 outputs a power-on reset signal XRST to the control circuit 50 when the external power supply voltage VDDE is turned on. As a comparator included in the power-on reset circuit 110, for example, a circuit having a configuration as shown in FIG. 4 can be used.

  For example, in FIG. 16, the standby mode (sleep mode) is realized by stopping the clock supply to the control circuit 50 and the like, and setting the operations of the reception circuit 30 and the transmission circuit 40 to the disable state. In this standby mode, power consumption in the regulator 100 and the power-on reset circuit 110 is dominant in power consumption of the integrated circuit device.

  In this regard, according to the present embodiment, the number of current paths in the regulator 100 and the power-on reset circuit 110 can be minimized. Therefore, power consumption in the regulator 100 and the power-on reset circuit 110 can be minimized, and power consumption in the standby mode of the integrated circuit device can be reduced.

  The integrated circuit device to which the amplifier circuit and the electronic circuit of this embodiment are applied is not limited to the wireless communication IC as shown in FIG. 16, and can be applied to various types of integrated circuit devices. For example, the present invention can be applied to a detection device that detects a desired signal from a sensor signal from a sensor. Examples of such a detection device include a device that detects a physical quantity such as angular velocity information and acceleration information using a vibrator.

8). Electronic Device FIG. 17 shows a configuration example of an electronic device including the integrated circuit device 310 of this embodiment. The electronic device includes an antenna ANT, an integrated circuit device 310, a host 320, a detection device 330, a sensor 340, and a power supply unit 350. Note that the electronic apparatus of the present embodiment is not limited to the configuration shown in FIG. 17, and some of the components (for example, a detection device, a sensor, and a power supply unit) are omitted, or other components (for example, an operation unit and an output unit) are omitted. Various modifications such as addition of) are possible.

  The integrated circuit device 310 is a wireless circuit device implemented with a circuit configuration as shown in FIG. 16, and performs a signal reception process from the antenna ANT and a signal transmission process to the antenna ANT. The host 320 controls the entire electronic device, and controls the integrated circuit device 310 and the detection device 330. The detection device 330 performs various detection processes (physical quantity detection processes) based on sensor signals from the sensor 340 (physical quantity transducer). For example, processing for detecting a desired signal from the sensor signal is performed, and the digital data after A / D conversion is output to the host 320. The sensor 340 is, for example, a smoke sensor, an optical sensor, a human sensor, a pressure sensor, a biological sensor, a gyro sensor, or the like. The power supply unit 350 supplies power to the integrated circuit device 310, the host 320, the detection device 330, and the like. For example, the power supply unit 350 supplies power using a dry battery (such as a round battery) or a battery.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, different terms having a broader meaning or the same meaning (first differential input terminal, second differential input terminal, first power supply node, second power supply node, operational amplification) The terms (non-inverting input terminal, inverting input terminal, VSS node, VDD node, resistor / capacitor, etc.) described together with the circuit element, etc. can be replaced with the different terms in any part of the specification or the drawings. . The configurations and operations of the current source, the amplifier circuit, the electronic circuit, the integrated circuit device, and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

TR transistor, R resistance, ITL tail current, IS current source,
AP amplifier, LD load, AM amplifier, DF differential, QB output,
TC1, TC2 first and second differential transistors,
TDRC drive transistor, ISC1, ISC2 current source,
30 receiving circuit, 32 mixer, 34 filter section,
36 demodulation circuit, 40 transmission circuit, 46 modulation circuit, 48 clock generation circuit,
50 control circuit, 52 link layer circuit, 54 host I / F, 60 constant current generation circuit,
100 regulator, 110 power-on reset circuit, 120 logic circuit,
310 integrated circuit device, 320 host, 330 detection device,
340 sensor, 350 power supply

Claims (15)

A resistor having one end connected to the first power supply node;
A depletion type transistor having a source connected to the other end of the resistor and a gate connected to the first power supply node;
The threshold voltage of the transistor has a negative temperature characteristic,
The current source characterized in that the resistance value of the resistor has a positive temperature characteristic. In claim 1,
The current source is an N well resistor formed by an N well. A current source according to claim 1 or 2;
An amplifier provided in series with the current source;
An amplifier circuit comprising: a load unit provided in series with the amplifier unit. A differential unit having the current source according to claim 1 or 2;
An output unit connected to an output node of the differential unit,
The differential unit is
A first differential transistor and a second differential transistor;
An amplifier circuit comprising a current mirror circuit provided between the first differential transistor, the second differential transistor and a second power supply node. In claim 4,
The output unit is
A driving transistor controlled by an output node of the differential section;
A second current source provided between the driving transistor and the first power supply node;
The second current source is
A second resistor having one end connected to the first power supply node;
A depletion type second transistor having a source connected to the other end of the second resistor and a gate connected to the first power supply node;
The threshold voltage of the second transistor has a negative temperature characteristic;
An amplifying circuit, wherein the resistance value of the second resistor has a positive temperature characteristic. In claim 4 or 5,
The differential circuit has an offset voltage between a non-inverting input terminal and an inverting input terminal. In claim 6,
An amplifier circuit, wherein the offset voltage is set by making the conductivity of the gate electrode of the first differential transistor different from the conductivity of the gate electrode of the second differential transistor. In claim 7,
The first differential transistor is a depletion type transistor,
The amplifier circuit, wherein the first power supply node is connected to a gate electrode of the first differential transistor. In any of claims 6 to 8,
The W / L ratio of the first differential transistor is different from the W / L ratio of the second differential transistor, or the W / L ratio of the first current mirror transistor constituting the current mirror circuit. The offset voltage is set by making the W / L ratio of the second current mirror transistor that constitutes the current mirror circuit different from each other. An amplifier circuit according to any one of claims 3 to 9,
Including circuit elements for operational amplification,
The resistor of the current source is an N-well resistor formed by an N-well;
An electronic circuit, wherein the operational amplification circuit element is laid out on a formation region of the resistor which is the N well resistor. In claim 10,
As a circuit element for operational amplification, including a poly resistor formed of a polysilicon layer,
An electronic circuit, wherein the poly resistors as operational amplification circuit elements are laid out on a formation region of the resistors as the N well resistors. In claim 10 or 11,
A circuit element for operational amplification includes a capacitor in which a first electrode is formed of a first polysilicon layer and a second electrode is formed of a second polysilicon layer,
An electronic circuit, wherein the capacitor, which is an operational amplification circuit element, is laid out on a region where the resistor, which is the N-well resistor, is formed.   An integrated circuit device comprising the amplifier circuit according to claim 3.   An integrated circuit device comprising the electronic circuit according to claim 10.   An electronic apparatus comprising the integrated circuit device according to claim 13.

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