JP2000075941A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make obtainable a desired voltage at a load terminal even when wiring resistance is large by providing a step-down circuit whose output voltage rises as a load current increases. SOLUTION: The step-down circuit VREG has double-end type differential amplifiers (M1 to M5) and circuits (M6 to M9) which convert their two outputs into single-end push-pull outputs. As a current IL flows to a load, a current kIL which is proportional to the IL flows to an output transistor M10 and an M12 having its gate and source connected in common. Since M13 to M15 are connected in a current-mirror type, currents nIL and mIL, which are proportional to the IL, flow thereto. Since the M14 is connected to the output of the outputs of the push-pull converting circuits, when the IL increases, its node potential is lowered. Consequently, the gate-source voltage of the M10 rises and the level of the output out rises.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage conversion circuit, and more particularly, to a power supply voltage of 2.5 V which is incorporated in a semiconductor chip.
The present invention relates to a technology for compensating for a voltage drop when a load current is large below V and a wiring resistance to a load is large, thereby enabling a high-speed operation of the load.

[0002]

2. Description of the Related Art A circuit shown in FIG. 1 of JP-A-10-64261 is known as one of voltage conversion circuits for stepping down a power supply voltage supplied from the outside and using it as an internal voltage. .

[0003]

In recent years, in a semiconductor device such as a memory or a microprocessor, a power supply voltage is reduced in a chip in order to provide a user-friendly external single power supply, improve element performance, and reduce power consumption. Circuits are increasingly provided. The step-down circuit usually has a negative feedback loop so as to maintain a substantially constant voltage with respect to a change in load current. In these step-down circuits, demands for higher accuracy and a reduction in voltage drop during load operation have become stricter due to a reduction in operation voltage accompanying miniaturization and higher integration of devices. However, with the miniaturization and high integration of devices,
Conversely, the voltage drop due to the power supply wiring inside the chip has increased, and it has become difficult to reduce the amount of voltage drop at the load end even if the supply capability of those step-down circuits is improved.
In particular, since the sense amplifier of the DRAM employs a so-called half precharge method of precharging at a voltage half the bit line amplitude, there is a problem that the operating speed is reduced due to the voltage drop. For this reason, the inventors of the present application have clarified that a power supply method in which the voltage drop at the sense amplifier end due to the power supply wiring resistance is small is required.

FIG. 4 shows an example of the step-down circuit shown in FIG. 1 of Japanese Patent Laid-Open No. 10-64261. This circuit includes an error amplifier (M
1 to M9) and buffer circuits (M10, M11). The error amplifying unit is usually composed of a differential amplifier because of its good accuracy and stability. The differential amplifier detects and amplifies a difference between the reference voltage VR and the output voltage out, and transmits the difference to the buffer circuit. As a result, the level of out becomes out> V
Once at R, the differential amplifier amplifies this difference and the voltage at its output node (M8 drain) rises. As a result, the gate-source voltage of M10 decreases, the supply current decreases, and out decreases. If out> VR, on the contrary, the output node of the differential amplifier goes down, the driving capability of M10 increases, and out rises. Since this is automatically repeated, out is substantially maintained at VR even if the load current IL fluctuates.
Therefore, this is also called a voltage conversion circuit (voltage regulator).

FIG. 5 shows the relationship between a step-down circuit and a load circuit in a semiconductor chip studied by the present inventors.
Normally, only a few step-down circuits are arranged on a chip due to the relationship between power consumption and occupied area. For this reason, it is necessary to connect the Al wiring from there to the load. The chip size of the memory is 10 to 20 mm, and the sheet resistance of the Al wiring is about 0.1 Ω / □, so that the power wiring has a resistance of about 10 Ω. Therefore, if a current of, for example, 50 mA flows, a voltage drop of 0.5 V will occur.
Since current consumption and resistance tend to increase further due to miniaturization of elements and reduction in power supply voltage, the voltage drop also increases, and the rate of the drop increases more and more. Further, since the step-down circuit also has an output resistance as shown in FIG. 3, this amount further increases. This causes a decrease in the operation speed of the load.

As described above, in the step-down circuit of FIG. 3, a voltage drop occurs due to the output resistance and the wiring resistance to the load, and at the load end, the voltage drops below a desired voltage level, resulting in a decrease in operating speed. An object of the present invention is to obtain a desired voltage at a load terminal even when wiring resistance is large.

[0007]

A typical means for solving the above problems is achieved by providing a step-down circuit having a characteristic that the output voltage increases as the load current increases.

[0008]

FIG. 1 shows a first embodiment of the present invention. A feature of the present invention is that when the load current increases, a current proportional to the load current is applied to the gate of the output transistor M10 to reduce the gate voltage of the output transistor M10.
This means that the transistor M14 flowing toward SS is connected.

The operation of the circuit will be described below. This circuit comprises a double-ended differential amplifier (M1 to M5), a circuit for converting the two outputs to a single-ended push-pull output (M6 to M9), an output transistor M10, and an output current monitor circuit (M12, 13). And current control transistors M14 and M15. First, it is assumed that the current IL flows through the load. Then, M10 and the gate,
A current kIL proportional to IL flows through M12 whose sources are commonly connected. Here, since M13, M14, and M15 are current mirror-connected, a current proportional to IL, nIL, and mIL, flow through them. Here, since M14 is connected to the output of the push-pull conversion circuit,
Increases, the node potential is lowered. For this reason,
The gate-source voltage of M10 increases and the level of output out increases. Here, M15 is connected to the common source of the input transistors of the differential amplifier,
This is because when L increases, the currents of the differential amplifier and the push-pull conversion circuit are increased, and their response speed is increased. Normally, an increase in IL inside the LSI means that the fluctuation increases, and therefore, the increase in the differential amplifier current has an effect of reducing the amount of transient fluctuation of out. As described above, according to this embodiment, when the load current increases, the output voltage increases, so that it is possible to compensate for the voltage drop due to the wiring resistance from the step-down circuit to the load circuit and the ON resistance of the output transistor. Also,
Since the differential amplifier current of the step-down circuit is also increased in accordance with the increase of the load current, the fluctuation of the output voltage becomes small even if the load current fluctuates.

FIG. 2 shows a second embodiment of the present invention. A feature of the present invention is that a current sink type step-down circuit is connected in addition to the current source type step-down circuit shown in the first embodiment of the present invention. Further, the latter has a sense level slightly higher than the former, and becomes higher as IL increases as in the former. As a result, it is possible to prevent a through current from M10 to M25 and prevent the out level from remaining at the original high level even if the load current decreases rapidly.

The operation of this circuit is as follows. In the figure, LM1 in the upper half of the circuit is the same as VREG in FIG. In the lower half LM2, M16 to M24,
Up to M26 and M27, M1 to M9, M14, and M in FIG.
This is the same circuit configuration as 15. Here, the channel width W of the transistor is W (M2)> W (M1) or W (M1).
16)> W (M17). These measures, L
By setting the sense level of M2 slightly higher than that of LM1, a through current between M10 and M25 caused by the finite offset and gain of the amplifier is prevented. Now, when IL increases, the output voltage of LM1 increases as described above. On the other hand, M2 of LM2
6, the same current as M14 and M15 in proportion to IL flows through M27. The current in M26 acts to lower the gate voltage of M25. This amount is the same as LM1. As a result, the current of M25 decreases and its output level increases. That is, the sense level increases. Here, if the gm of M25 is the same as that of M10, LM1
The sense level rises by the same amount as the rise in the output level of. Therefore, no matter how the load current fluctuates, M1
No through current flows between 0 and M25. In addition, if the load current decreases rapidly, the level of out must also be reduced accordingly, but in LM1 it must be done with a current of several μA flowing through M11. So you can't reduce that level quickly. However, the addition of LM2 makes this possible, so that even if the load current changes rapidly, an output voltage characteristic proportional to the desired load current can be obtained.

FIG. 3 compares the load current dependence of the present invention and the circuit of FIG. 4 in a step-down circuit. In the circuit of FIG. 4, when the load current increases, the output impedance takes a finite value, so that the output impedance gradually decreases. However, in the present invention, the output voltage can be increased when the load current increases as described above. The rate of increase depends on the mirror ratio k between M10 and M12 in FIG. That is, as k is increased, it can be increased.

FIG. 6 shows the load current dependency of the step-down circuit in consideration of the power supply wiring resistance. In the circuit of FIG. 4, at the output end, the output impedance drops, and at the load end, the power supply wiring resistance lowers. Normally, even if the load current is lowered, the integration degree is high, so that the load current does not change from the previous generation or conversely increases. For this reason, the fluctuation rate increases as the voltage decreases. For this reason, if the circuit of FIG. 4 is used, the operation speed is reduced. on the other hand,
In the step-down circuit according to the present invention, the voltage increases at the output terminal in proportion to the load current. For this reason, a desired voltage is obtained at the load end. Therefore, the speed does not decrease.

FIG. 7 shows an example of application of the DRAM of the present invention to a memory array. In a DRAM, when reading a signal from a memory cell, one of the word lines Wi (i = 0 to n) is selected, and a signal is read from all the memory cells attached thereto at one time. Then, those signals are amplified at once by the sense amplifier SA. At this time, 1000 or more bit lines (Bi, / Bi; i = 0 to n) are charged and discharged at a time. The capacity of the charged / discharged bit line is several hundred pF in total, and several thousand pF in the whole chip. At this time, the charging current flows from VREG to the drive transistor MP of the sense amplifier via the power supply line LP, and from the sense amplifier to the bit line. On the other hand, the discharge current is
It flows from the bit line to VSS via the sense amplifier, the drive transistor MN of the sense amplifier, and the power supply line LN. Here, the power supply lines LP and LN are provided with a parasitic resistance Rp. For this reason, the nodes N2 and N4 immediately after the operation of the sense amplifier cause a large voltage drop and a rise as shown by a broken line in FIG. For this reason, the voltage applied to the transistor constituting the sense amplifier is reduced, and the operation speed is reduced. In particular, since the sense amplifier of the DRAM employs a so-called half precharge method of precharging at a voltage half the bit line amplitude, the operation speed is significantly reduced due to the voltage drop. This voltage drop becomes more remarkable as the degree of integration increases and as the memory capacity increases.

When the circuit of FIG. 4 is used for VREG in this memory array, the output impedance is added in addition to Rp, so that the voltage drop is further increased.
On the other hand, when the step-down circuit of the present invention is employed for VREG, the voltage can be increased at the output terminal by the drop due to the wiring resistance as shown by the solid line in FIG. , N4 can be made almost desired values. Therefore, the speed of the sense amplifier hardly decreases. As described above, by applying the present invention to a memory array of a DRAM, a voltage drop due to wiring resistance can be compensated, so that a sense amplifier can be operated at higher speed.

FIG. 9 shows a third embodiment of the present invention. The feature of this circuit is that positive feedback transistors MA, MB, MC, MD are provided in the differential amplifier section of the step-down circuit by the circuit shown in FIG.
Is added. Since the loop gain becomes extremely high due to the positive feedback, the accuracy of the output voltage is improved as shown in FIG. 10, and the current dependency on the load can be reduced. Therefore, if this is applied to the above-described circuit in the sense amplifier LSI chip of the DRAM, the voltage drop at the load terminal can be reduced, and the load can be operated at high speed. Here, MA, MD, MB
And MC are connected in series, and a capacitor is added at the midpoint of this in order to lower the gain of the differential amplifier in the high frequency region and to stabilize the loop. As a result, oscillation and overshoot caused by increasing the gain of the step-down circuit can be prevented. In FIGS. 1, 2, 4, and 9, a resistor Rc and a capacitor Cc connected in series are added to the output terminal. To cancel the phase rotation and reduce the phase rotation to stabilize the loop. Thereby, oscillation and overshoot of the step-down circuit can be prevented.

In the above description, all the voltage conversion circuits have been described as current source type step-down circuits for the sake of simplicity. However, the low-potential-side voltage of the BSG (boosted sense ground) method in the DRAM is used. There are also suction-type voltage conversion circuits such as conversion circuits and negative voltage stabilization circuits. In this case, contrary to the above description, the current flows from the load toward the voltage conversion circuit, so that the potential at the load terminal increases. Therefore, in this case, if the output terminal potential of the voltage conversion circuit is controlled to decrease as the load current increases, the increase can be compensated. For this purpose, for example, the pMOS of the embodiment shown in FIGS.
And nMOS are all reversed, and VDD and VS
The configuration may be such that S is reversed.

The functions and effects of the above embodiment are summarized as follows. In a semiconductor device including a step-down circuit that generates a voltage whose absolute value is smaller than an input voltage in a chip and supplies a current to a load circuit, or sinks a current from the load circuit, the step-down circuit includes a load circuit. When supplying current, the output voltage increases in proportion to the load current, and decreases when current from the load circuit is drawn. Thus, even if a voltage drop occurs due to wiring resistance, the voltage at the load terminal can be set to a desired value, and the load can be operated at high speed.

In the above step-down circuit, the step-down circuit includes:
It consists of a differential amplifier and a common source buffer circuit,
One input terminal of the differential amplifier is connected to the output terminal of the common source buffer of the step-down circuit directly or through a voltage divider circuit, and the other terminal of the differential amplifier has a voltage lower than the external power supply voltage. The differential amplifier is connected to the output of a pair of diode-connected first
Drains are connected to first and second conductivity type transistors and third and fourth transistors of second conductivity type respectively connected to their drains, and a common source of the third and fourth transistors. Fifth transistor of second conductivity type, sixth and seventh transistors each having the same conductivity type as the first and second transistors and forming a current mirror circuit, and drain, drain and gate of the sixth transistor An eighth transistor of the second conductivity type to which is connected the drain and the drain of the seventh transistor, a gate of the eighth transistor and a ninth transistor of the second conductivity type to which the gate is connected, Third,
A tenth transistor of the second conductivity type, the drain of which is connected to the common source of the fourth transistor, a drain of the ninth transistor and an eleventh transistor whose drain is connected, The drain is connected to the gate of the driving transistor of the first conductivity type of the buffer circuit, the gates of the tenth and eleventh transistors are connected to the gate of the driving transistor, and the drain is connected to the second. The thirteenth transistor connected to the drain and the gate of the twelfth transistor of the conductivity type is connected to the drain. As a result, when the load current increases, the gate-source voltage of the drive transistor of the first conductivity type of the buffer circuit increases. Therefore, if the buffer circuit is of a current discharge type, its output voltage increases, and In that case, the output voltage drops. Therefore, even if a voltage drop occurs due to wiring resistance, the voltage at the load terminal can be set to a desired value, and the load can be operated at high speed.

In the above step-down circuit, another driving transistor of the first conductivity type, which allows a current to flow in the opposite direction to the driving transistor, is connected to its output terminal, and the gate of the other driving transistor is connected to the differential transistor. There is no transistor corresponding to the twelfth and thirteenth transistors compared to the operational amplifier, and the gates of the transistors corresponding to the tenth and eleventh transistors are connected to the drain of the thirteenth transistor Except for this, the configuration is such that it is driven by the second differential amplifier having the same configuration. Thus, even if the load current rapidly changes from an increase to a decrease, the load current can be returned to the original level at a high speed.

In the above-mentioned step-down circuit, the input level to which the output of the first differential amplifier transitions is lower than the input level to which the output of the second differential amplifier transitions. As a result, it is possible to eliminate a through current flowing between the two drive transistors, thereby eliminating unnecessary current consumption.

In the above step-down circuit, the load is DR
The configuration includes an AM memory array. As a result, the voltage drop due to the wiring resistance can be compensated, so that the sense amplifier can be operated at higher speed.

In a semiconductor integrated circuit including a step-down circuit for supplying a voltage lower than an input voltage to a load circuit in a chip,
The step-down circuit includes a differential amplifier and a common-source buffer circuit, and one input terminal of the differential amplifier is connected to an output terminal of the common-source buffer of the step-down circuit directly or via a voltage dividing circuit. The other terminal of the differential amplifier is connected to an output of a circuit that generates a voltage lower than the external power supply voltage, and the differential amplifier is a pair of diode-connected first conductive type first and second conductive type. Third and fourth transistors of second conductivity type respectively connected to the second transistor and their drains, and second and third transistors of second conductivity type whose drains are connected to a common source of the third and fourth transistors. 5th transistor, 6th and 7th transistors each having the same conductivity type as the first and 2nd transistors and forming a current mirror circuit, and drain and drain of the 6th transistor. And an eighth transistor of the second conductivity type having a gate connected thereto, a drain of the seventh transistor connected to the drain thereof, a ninth transistor of the second conductivity type having the gate connected to the gate of the eighth transistor and the gate thereof , The first and second transistors having their gates and sources connected to the gates and sources thereof, respectively.
Tenth and eleventh transistors of conductivity type;
And the twelfth and thirteenth transistors each having a source connected to each drain of the eleventh transistor. One end is connected to each source of the twelfth and thirteenth transistors and the other end is kept at a constant potential. First and second capacitors,
The sources of the second and thirteenth transistors are connected to the drain of the fourth transistor and the drain of the third transistor, respectively, and the drain of the seventh transistor is connected to the driving transistor of the first conductivity type of the buffer circuit. It is configured to be connected to the gate. As a result, the output impedance of the step-down circuit is reduced, so that the voltage at the load terminal can be further reduced and the load can be operated at high speed.

In the above step-down circuit, the load is DR
The configuration includes an AM memory array. As a result, the output impedance can be reduced, so that the voltage drop at the end of the sense amplifier can be reduced and the sense amplifier can operate at higher speed.

[0025]

The voltage drop due to the output impedance of the step-down circuit and the resistance of the power supply wiring can be compensated.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a comparison of load current dependency between the present invention and the prior art.

FIG. 4 is a diagram showing a step-down circuit according to the related art.

FIG. 5 is a diagram showing a relationship between a step-down circuit and a load in a semiconductor chip.

FIG. 6 is a diagram showing a comparison of load current dependence of a step-down circuit in consideration of power supply wiring resistance.

FIG. 7 is a diagram showing a relationship between a step-down circuit and a memory array in a DRAM.

FIG. 8 is a diagram showing a comparison between sense amplifier operations according to the present invention and the prior art.

FIG. 9 is a diagram showing a third embodiment of the present invention.

FIG. 10 is a diagram showing a comparison of load current dependency between the third embodiment of the present invention and the prior art.

[Explanation of symbols]

VREG, LM1, LM2: step-down circuit, VR: reference voltage, out: output terminal of the step-down circuit, VDD: power supply voltage (high potential side), VSS: power supply voltage (low potential side),
IL: load current, M1 to M27, MA, MB, MC,
MD, MN, MP: MOS transistor, VG: Gate bias voltage, Rp: Wiring resistance, Cc, C1, C
2: Phase compensation capacitance, Rc: Phase compensation resistance, LP, L
N: power supply wiring for sense amplifier, Wi (i = 0 to n) ...
Word line, Bi, / Bi (i = 0 to n) ... bit line,
SAi (i = 0 to n): sense amplifier, PC: bit line precharge signal, FP, FN: sense amplifier activation signal, CP, CN: common source line of sense amplifier, MCA # i (i = 0 to n) ) ... DRAM memory cell array.

Continuing from the front page (71) Applicant 590000879 Texas Instruments Incorporated Rated 13500 North Central Expressway, Dallas, Texas, USA 13500 (72) Inventor Hitoshi Tanaka 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi, Ltd.・ S.I.Systems Co., Ltd. (72) Inventor Takashi Ebihara 5-22-1, Kamizuhoncho, Kodaira-shi, Tokyo Co., Ltd. Hitachi Ultra-Ls.I.Systems Co., Ltd. 2350 Kihara, Miura-mura, Inashiki-gun, Japan F-term (reference) in Nippon Texas Instruments Co., Ltd.

Claims (5)

[Claims] 1. A semiconductor device comprising: a voltage conversion circuit receiving a first voltage and outputting a second voltage smaller than the first voltage; and a load circuit to which the second voltage is supplied, wherein the voltage conversion circuit supplies the second voltage. The conversion circuit is characterized in that, when supplying current to the load circuit, its output voltage increases in proportion to the load current, and when sinking current from the load circuit, its output voltage drops. Semiconductor device. 2. The voltage conversion circuit according to claim 1, wherein the voltage conversion circuit includes a buffer circuit having an output node for outputting the second voltage, a first input node coupled to the output node, and a predetermined reference voltage. And a differential amplifier having a second input node, wherein the differential amplifier has respective gates of the first and second gates.
A first conductivity type pair of a first conductivity type having an input node serving as an input node and having a source connected in common;
Third and fourth transistors of the second conductivity type respectively coupled to the drains of the first and second transistors, and fifth and fifth transistors of the second conductivity type forming current mirror circuits for the third and fourth transistors, respectively. A sixth transistor, a seventh transistor of the first conductivity type having a drain and a gate connected to the drain of the fifth transistor, and a drain connected to the drain of the sixth transistor and a gate connected to the seventh transistor. An eighth transistor of the first conductivity type connected to the gate of the first transistor, a current source connected to the first and second common sources, and a drain connected to a common source of the first and second transistors. And a ninth transistor of the first conductivity type, the drain of which is connected to the drain of the eighth transistor. 1 includes a tenth transistor conductivity type, the drain of the sixth transistor, wherein a is connected to the gate of the driving transistor of the first conductivity type contained in said buffer circuit. 3. The voltage conversion circuit according to claim 2,
A second conductivity-type second drive transistor for causing a current to flow through the output node in a direction opposite to the drive transistor;
A second input node having a third input node coupled to the output node and a fourth input node coupled to the predetermined reference voltage;
A semiconductor device comprising a differential amplifier. 4. The semiconductor device according to claim 1, wherein the load circuit is a memory array including a plurality of dynamic memory cells including one transistor and one capacitor. 5. The semiconductor device according to claim 3, wherein an input level at which the output of the differential amplifier transitions is lower than an input level at which the output of the second differential amplifier transitions.