JP2011071436A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Method of manufacturing semiconductor device, and semiconductor device Download PDF

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JP2011071436A
JP2011071436A JP2009223230A JP2009223230A JP2011071436A JP 2011071436 A JP2011071436 A JP 2011071436A JP 2009223230 A JP2009223230 A JP 2009223230A JP 2009223230 A JP2009223230 A JP 2009223230A JP 2011071436 A JP2011071436 A JP 2011071436A
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underfill material
wiring board
solder
circuit wiring
solder ball
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Japanese (ja)
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Shinji Takei
信二 武井
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Fuji Electric Co Ltd
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Fuji Electric Systems Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To prevent stress concentration from generating at a junction of a solder ball and a semiconductor package, and a circuit wiring board side. <P>SOLUTION: A semiconductor package in which a solder ball 15 is arranged on the same plane is laid on a circuit wiring board 17, and the solder bonding of both is carried out by reflow heating. An underfill member 19, having thermal expansion nature, is filled between the semiconductor package and the circuit wiring board 17. The underfill member 19 is expanded, melting the solder ball 15 by setting the heating temperature at the time of curing of the underfill member 19 to be higher than the melting temperature of the solder ball 15. Consequently, the semiconductor package is hoisted and the solder ball 15 is extended and transformed into a column shape. The shape where stresses do not concentrate at a junction to the solder ball 15 is obtained by the transformation; and crack resistance is improved and the reliability of the junction is improved. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は半導体装置の製造方法および半導体装置に関し、特に半導体チップの同一平面上に配列した接続用電極と回路配線基板上の接続用電極とを接続するはんだバンプの信頼性を向上させる半導体装置の製造方法および半導体装置に関する。   The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly, to a semiconductor device that improves the reliability of solder bumps that connect connection electrodes arranged on the same plane of a semiconductor chip and connection electrodes on a circuit wiring board. The present invention relates to a manufacturing method and a semiconductor device.

携帯端末機などで小型・軽量化を実現させている要素技術の一つとして表面実装技術がある。この表面実装技術は、接続用の電極パッドが同一平面上に配列されていてそこにそれぞれはんだボールが取り付けられている半導体チップを回路配線基板上の接続用電極に対向配置し、はんだを溶融させることで電気的接続を行うフリップチップ実装技術である。この表面実装技術によれば、半導体チップは、電極パッドが同一平面上に配列されていて、周囲に電極のリードが張り出していない構成であるので、回路配線基板への実装面積を縮小することができ、高密度実装を可能にしている。   Surface mounting technology is one of the elemental technologies that have realized miniaturization and weight reduction in portable terminals and the like. In this surface mounting technology, a semiconductor chip on which electrode pads for connection are arranged on the same plane and solder balls are respectively attached is arranged opposite to the connection electrodes on the circuit wiring board, and the solder is melted. This is a flip-chip mounting technology for electrical connection. According to this surface mounting technology, the semiconductor chip has a configuration in which the electrode pads are arranged on the same plane and the lead of the electrode does not protrude around, so that the mounting area on the circuit wiring board can be reduced. High density mounting is possible.

このような表面実装に用いられる半導体パッケージとして、ＣＳＰ（Chip Scale Package, Chip Size Package）またはＢＧＡ（Ball Grid Array）パッケージが開発されている。ＣＳＰは、半導体チップとほぼ変わらない大きさのパッケージであり、ＢＧＡパッケージは、半導体チップを搭載したインターポーザの裏面にボールバンプを格子状に並べたパッケージである。   As a semiconductor package used for such surface mounting, a CSP (Chip Scale Package, Chip Size Package) or a BGA (Ball Grid Array) package has been developed. The CSP is a package that is almost the same size as a semiconductor chip, and the BGA package is a package in which ball bumps are arranged in a grid on the back surface of an interposer on which a semiconductor chip is mounted.

図９はＣＳＰを示す図であって、（Ａ）はＣＳＰの断面構造を示す図（Ｂ）はＣＳＰの底面図、図１０はＢＧＡパッケージを示す図であって、（Ａ）はＢＧＡパッケージの断面構造を示す図、（Ｂ）はＢＧＡパッケージの底面図である。   FIG. 9 is a view showing a CSP, (A) is a view showing a cross-sectional structure of the CSP, (B) is a bottom view of the CSP, FIG. 10 is a view showing a BGA package, and (A) is a view of the BGA package. The figure which shows a cross-section, (B) is a bottom view of a BGA package.

ＣＳＰは、図９に示したように、半導体チップ１０１のアルミ電極１０２を除く部分に応力緩和層１０３を形成し、その応力緩和層１０３の表面にアルミ電極１０２と接続される金属再配線１０４を形成して電極パッドを形成し、そこにはんだボール１０５を取り付けて構成される。金属再配線１０４が形成された応力緩和層１０３は、有機保護膜１０６によって表面処理される。   As shown in FIG. 9, the CSP forms a stress relaxation layer 103 on a portion of the semiconductor chip 101 excluding the aluminum electrode 102, and forms a metal rewiring 104 connected to the aluminum electrode 102 on the surface of the stress relaxation layer 103. An electrode pad is formed, and a solder ball 105 is attached thereto. The stress relaxation layer 103 on which the metal rewiring 104 is formed is surface-treated with the organic protective film 106.

ＢＧＡパッケージは、図１０に示したように、半導体チップ１１１が中間基板であるインターポーザ１１２の上面に接着剤によって固定され、半導体チップ１１１の電極とインターポーザ１１２の上面の配線とを金属ワイヤ１１３によって接続し、インターポーザ１１２の下面にはんだボール１１４を取り付けて構成される。インターポーザ１１２のはんだボール１１４が取り付けられる領域を除いた表面は、ソルダーレジスト１１５によって被覆される。インターポーザ１１２の金属ワイヤ１１３のある側は、モールド樹脂１１６によって封止されている。ＢＧＡパッケージは、はんだボール１１４に代えてはんだペーストでバンプを形成することもある。   In the BGA package, as shown in FIG. 10, the semiconductor chip 111 is fixed to the upper surface of the interposer 112 as an intermediate substrate by an adhesive, and the electrodes of the semiconductor chip 111 and the wiring on the upper surface of the interposer 112 are connected by a metal wire 113 The solder ball 114 is attached to the lower surface of the interposer 112. The surface of the interposer 112 excluding the region where the solder balls 114 are attached is covered with a solder resist 115. The side of the interposer 112 where the metal wire 113 is present is sealed with a mold resin 116. In the BGA package, bumps may be formed with solder paste instead of the solder balls 114.

ＣＳＰおよびＢＧＡパッケージは、何れも、同一平面上にはんだバンプを格子状に配列した構成を有している。回路配線基板へ実装するとき、半導体チップは、はんだバンプのある面を回路配線基板へ対向させた状態で回路配線基板の所定位置に搭載され、その後、リフロー加熱によりはんだボール１０５，１１４を溶融して、回路配線基板上に接合される。   Each of the CSP and BGA packages has a configuration in which solder bumps are arranged in a grid on the same plane. When mounted on the circuit wiring board, the semiconductor chip is mounted at a predetermined position on the circuit wiring board with the surface having the solder bumps facing the circuit wiring board, and then the solder balls 105 and 114 are melted by reflow heating. And bonded onto the circuit wiring board.

このようにして回路配線基板にＣＳＰまたはＢＧＡパッケージが実装される。しかし、実装後に衝撃、折り曲げなどの応力が加わったときに、ＣＳＰまたはＢＧＡパッケージと回路配線基板との接続信頼性が保持できない場合がある。このような場合の対策として、ＣＳＰまたはＢＧＡパッケージと回路配線基板との間にアンダーフィル材と呼ばれる封止樹脂を充填し、加熱硬化させることが行われている。   In this way, the CSP or BGA package is mounted on the circuit wiring board. However, when stress such as impact or bending is applied after mounting, the connection reliability between the CSP or BGA package and the circuit wiring board may not be maintained. As a countermeasure in such a case, a sealing resin called an underfill material is filled between the CSP or BGA package and the circuit wiring board, and is cured by heating.

図１１はＣＳＰを実装した回路配線基板のヒートサイクル試験結果を示す図である。
この図１１では、ＣＳＰタイプの半導体チップがはんだ接合により実装された回路配線基板についてヒートサイクル試験を行った後に、バンプ接合部を観察した結果を示している。すなわち、図１１の上部には、半導体チップ側の金属再配線１０４がはんだボール１０５を介して回路配線基板１０７側の配線のランド１０８に接合されている部分を示し、下部には、金属再配線１０４とはんだボール１０５とのバンプ接合部に発生したクラック１０９を拡大して示している。 FIG. 11 is a diagram showing a heat cycle test result of a circuit wiring board on which CSP is mounted.
FIG. 11 shows the result of observing the bump bonding portion after performing a heat cycle test on the circuit wiring board on which the CSP type semiconductor chip is mounted by solder bonding. That is, the upper part of FIG. 11 shows a portion where the metal rewiring 104 on the semiconductor chip side is joined to the wiring land 108 on the circuit wiring board 107 side via the solder ball 105, and the lower part shows the metal rewiring. The crack 109 generated at the bump joint between 104 and the solder ball 105 is shown enlarged.

このようなクラック１０９は、金属再配線１０４とランド１０８とを接続するはんだバンプの形状に起因することが知られている（たとえば、特許文献１，２参照）。はんだボール１０５は、リフロー工程時に、溶融して回路配線基板１０７側の配線のランド１０８と接合される。そのとき、はんだボール１０５は、半導体パッケージの重さによる沈み込みや反り変形の影響により潰れて、楕円状（太鼓状）に変形してしまい、その後、バンプ高さが低くなった太鼓状の変形状態で硬化される。   It is known that such a crack 109 is caused by the shape of a solder bump that connects the metal rewiring 104 and the land 108 (see, for example, Patent Documents 1 and 2). The solder balls 105 are melted and bonded to the wiring lands 108 on the circuit wiring board 107 side during the reflow process. At that time, the solder ball 105 is crushed due to the sinking or warping deformation due to the weight of the semiconductor package, and deformed into an elliptical shape (drum shape), and then the drum shape deformation with the bump height lowered. Cured in a state.

はんだボール１０５が太鼓状になると、その両端における金属再配線１０４およびランド１０８との接合部が中央部に比べて細くなることから、その細い接合部分に応力集中が生じることになる。その結果、図示の例では、はんだボール１０５と金属再配線１０４との接合部にクラック１０９が入り、温度サイクル寿命を低下させることになる。   When the solder ball 105 has a drum shape, the joint between the metal rewiring 104 and the land 108 at both ends becomes thinner than the center, and stress concentration occurs at the thin joint. As a result, in the illustrated example, a crack 109 enters the joint between the solder ball 105 and the metal rewiring 104, and the temperature cycle life is reduced.

このような接合部におけるクラック発生の原因は、半導体パッケージの沈み込みによるはんだボール１０５の変形にある。このことから、特許文献１では、半導体パッケージと回路配線基板との間にスペーサとして形状記憶合金製の支持柱を設け、はんだボールが溶融している高温雰囲気で、支持柱が半導体パッケージを持ち上げるようにしている。これにより、半導体パッケージの沈み込みが緩和されている。また、特許文献２では、半導体パッケージを機械的に昇降する手段を備え、リフロー時にはんだボールの中央部がくびれた形状になるまで半導体パッケージを引き上げている。これにより、はんだボールは、半導体パッケージおよび回路配線基板側との接合部に応力が集中することはなくなるので、接合部にクラック１０９が発生することがなく、接合の信頼性を高めることができる。   The cause of the occurrence of cracks in such a joint is the deformation of the solder balls 105 due to the sinking of the semiconductor package. For this reason, in Patent Document 1, a support pillar made of shape memory alloy is provided as a spacer between the semiconductor package and the circuit wiring board so that the support pillar lifts the semiconductor package in a high temperature atmosphere in which the solder balls are melted. I have to. This alleviates the sinking of the semiconductor package. Further, in Patent Document 2, a means for moving the semiconductor package up and down mechanically is provided, and the semiconductor package is pulled up until the central portion of the solder ball becomes constricted during reflow. As a result, the solder ball does not concentrate stress at the joint portion between the semiconductor package and the circuit wiring board, so that crack 109 does not occur at the joint portion, and the joint reliability can be improved.

特開２０００−１５０７０９号公報JP 2000-150709 A 特開２００１−２３７２７１号公報JP 2001-237271 A

しかしながら、半導体パッケージを持ち上げるための形状記憶合金または半導体パッケージ昇降手段は高価であるため、半導体パッケージの実装コストが高くなるという問題点があった。   However, since the shape memory alloy or the semiconductor package lifting / lowering means for lifting the semiconductor package is expensive, there is a problem that the mounting cost of the semiconductor package becomes high.

本発明はこのような点に鑑みてなされたものであり、特別な部材または装置を付加することなく、既存設備を利用して、はんだボールと半導体チップおよび回路配線基板との接合部に応力集中が生じないようにした半導体装置の製造方法および半導体装置を提供することを目的とする。   The present invention has been made in view of such a point, and stress concentration is performed at the joint between the solder ball, the semiconductor chip, and the circuit wiring board by using existing equipment without adding a special member or device. An object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device in which the occurrence of the problem is prevented.

本発明では上記の課題を解決するために、同一平面上にはんだバンプを配列した半導体チップを回路配線基板に載置してリフロー加熱により両者を接合し、前記半導体チップと前記回路配線基板との間にアンダーフィル材を充填し、加熱により前記アンダーフィル材を硬化してなる半導体装置の製造方法において、前記アンダーフィル材は、加熱時に体積が膨張する熱膨張性を有するものであり、前記アンダーフィル材を硬化させる温度は、前記はんだバンプのはんだ溶融温度よりも高くしたことを特徴とする半導体装置の製造方法が提供される。   In the present invention, in order to solve the above-described problem, a semiconductor chip having solder bumps arranged on the same plane is placed on a circuit wiring board, and the two are joined by reflow heating, and the semiconductor chip and the circuit wiring board are bonded together. In the method of manufacturing a semiconductor device in which an underfill material is filled in between and the underfill material is cured by heating, the underfill material has a thermal expansion property in which a volume expands when heated, There is provided a method for manufacturing a semiconductor device, characterized in that the temperature at which the fill material is cured is higher than the solder melting temperature of the solder bump.

また、本発明では、同一平面上にはんだバンプを配列した半導体チップを回路配線基板に載置してリフロー加熱により両者を接合し、前記半導体チップと前記回路配線基板との間にアンダーフィル材を充填してなる半導体装置において、前記アンダーフィル材は、加熱時に体積が膨張する添加剤を含んでいることを特徴とする半導体装置が提供される。   In the present invention, a semiconductor chip in which solder bumps are arranged on the same plane is placed on a circuit wiring board, and both are joined by reflow heating, and an underfill material is provided between the semiconductor chip and the circuit wiring board. In the filled semiconductor device, there is provided a semiconductor device characterized in that the underfill material contains an additive that expands in volume when heated.

このような半導体装置の製造方法および半導体装置によれば、アンダーフィル材を加熱して硬化させる際に、アンダーフィル材の体積が膨張する。このアンダーフィル材の膨張により、半導体チップと回路配線基板との間隔が広げられ、それに伴って、加熱により溶融されたはんだバンプが伸長されて、はんだ接合部に応力集中が生じない形状に変形され、その状態で、アンダーフィル材およびはんだバンプが硬化される。   According to such a semiconductor device manufacturing method and semiconductor device, when the underfill material is heated and cured, the volume of the underfill material expands. Due to the expansion of the underfill material, the space between the semiconductor chip and the circuit wiring board is widened, and accordingly, the solder bumps melted by heating are expanded and deformed into a shape that does not cause stress concentration in the solder joints. In this state, the underfill material and the solder bump are cured.

上記構成の半導体装置の製造方法は、アンダーフィル材を熱膨張性を有するものに変更し、アンダーフィル材の硬化温度を変更するだけなので、特別な部材または装置を何ら付加することなく、既存設備を利用して容易に実施することができる。   The manufacturing method of the semiconductor device having the above-described configuration is simply changing the underfill material to one having thermal expansibility and changing the curing temperature of the underfill material, so that existing equipment is not added without adding any special member or device. It can be easily implemented using

はんだボールを搭載したＣＳＰタイプの半導体パッケージを示す断面図である。It is sectional drawing which shows the CSP type semiconductor package carrying a solder ball. 半導体パッケージを回路配線基板に実装した状態を示す断面図である。It is sectional drawing which shows the state which mounted the semiconductor package in the circuit wiring board. 半導体パッケージと回路配線基板との間にアンダーフィル材を充填した状態を示す断面図である。It is sectional drawing which shows the state with which the underfill material was filled between the semiconductor package and the circuit wiring board. アンダーフィル材の膨張によりはんだボールを変形した状態を示す断面図である。It is sectional drawing which shows the state which deform | transformed the solder ball by expansion | swelling of an underfill material. アンダーフィル材の膨張によりはんだボールをさらに変形した状態を示す断面図である。It is sectional drawing which shows the state which deform | transformed the solder ball further by expansion | swelling of an underfill material. アンダーフィル材を構成する膨張性球体の説明図である。It is explanatory drawing of the expansible sphere which comprises an underfill material. 球体が樹脂中に最密充填状態にあるときの説明図である。It is explanatory drawing when a sphere is in the closest packing state in resin. 銅ピラーはんだバンプを搭載した半導体パッケージの実装に適用した例を示す断面図である。It is sectional drawing which shows the example applied to the mounting of the semiconductor package which mounts a copper pillar solder bump. ＣＳＰを示す図であって、（Ａ）はＣＳＰの断面構造を示す図（Ｂ）はＣＳＰの底面図である。It is a figure which shows CSP, Comprising: (A) is a figure which shows the cross-section of CSP, (B) is a bottom view of CSP. ＢＧＡパッケージを示す図であって、（Ａ）はＢＧＡパッケージの断面構造を示す図、（Ｂ）はＢＧＡパッケージの底面図である。It is a figure which shows a BGA package, Comprising: (A) is a figure which shows the cross-section of a BGA package, (B) is a bottom view of a BGA package. ＣＳＰを実装した回路配線基板のヒートサイクル試験結果を示す図である。It is a figure which shows the heat cycle test result of the circuit wiring board which mounted CSP.

以下、本発明の実施の形態について、ＣＳＰタイプの半導体パッケージからなる半導体チップを回路配線基板に実装する場合を例に図面を参照して詳細に説明する。
図１ははんだボールを搭載したＣＳＰタイプの半導体パッケージを示す断面図、図２は半導体パッケージを回路配線基板に実装した状態を示す断面図、図３は半導体パッケージと回路配線基板との間にアンダーフィル材を充填した状態を示す断面図、図４はアンダーフィル材の膨張によりはんだボールを変形した状態を示す断面図、図５はアンダーフィル材の膨張によりはんだボールをさらに変形した状態を示す断面図である。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, taking as an example the case where a semiconductor chip made of a CSP type semiconductor package is mounted on a circuit wiring board.
1 is a cross-sectional view showing a CSP type semiconductor package on which solder balls are mounted, FIG. 2 is a cross-sectional view showing a state in which the semiconductor package is mounted on a circuit wiring board, and FIG. 3 is an underline between the semiconductor package and the circuit wiring board. FIG. 4 is a cross-sectional view showing a state in which the solder ball is deformed by expansion of the underfill material, and FIG. 5 is a cross-sectional view showing a state in which the solder ball is further deformed by expansion of the underfill material. FIG.

ＣＳＰタイプの半導体パッケージは、図１に示したように、半導体チップ１１のアルミ電極１２が形成されている面に応力緩和層１３、銅の金属再配線１４を積層形成して構成される。金属再配線１４には、はんだボール１５が接合され、有機保護膜１６によって表面が保護されている。   As shown in FIG. 1, the CSP type semiconductor package is formed by laminating a stress relaxation layer 13 and a copper metal rewiring 14 on the surface of the semiconductor chip 11 on which the aluminum electrode 12 is formed. Solder balls 15 are joined to the metal rewiring 14, and the surface is protected by an organic protective film 16.

ここで、たとえば、はんだボール１５は、４００マイクロメートル（μｍ）の直径を有し、金属再配線１４のはんだボール１５が接合されるランドの径は、４００マイクロメートルであるとする（以下において、各部の寸法は一例である）。直径４００マイクロメートルのはんだボール１５は、ランド径４００マイクロメートルの金属再配線１４に接合された場合、金属再配線からの高さは、３００マイクロメートルになる。   Here, for example, the solder ball 15 has a diameter of 400 micrometers (μm), and the diameter of the land to which the solder ball 15 of the metal rewiring 14 is joined is 400 micrometers (in the following, The dimensions of each part are examples). When the solder ball 15 having a diameter of 400 micrometers is joined to the metal rewiring 14 having a land diameter of 400 micrometers, the height from the metal rewiring is 300 micrometers.

このような半導体パッケージは、図２に示したように、はんだボール１５を接合した面を回路配線基板１７と対向させてその接続用電極１８が形成された所定位置に載置され、リフロー加熱によって、はんだボール１５は溶融され、回路配線基板１７の接続用電極１８に接合される。このリフロー工程のとき、溶融されるはんだボール１５は、半導体パッケージの重さのために潰されて太鼓状に変形し、たとえば、その高さが２００マイクロメートルまで低くなる。   As shown in FIG. 2, such a semiconductor package is placed at a predetermined position where the connection electrode 18 is formed with the surface to which the solder balls 15 are bonded facing the circuit wiring board 17 and is reflow-heated. The solder balls 15 are melted and joined to the connection electrodes 18 of the circuit wiring board 17. During this reflow process, the solder ball 15 to be melted is crushed due to the weight of the semiconductor package and deformed into a drum shape, for example, its height is reduced to 200 micrometers.

アンダーフィル材充填工程では、図３に示したように、半導体パッケージと回路配線基板１７との間の隙間に熱膨張性のアンダーフィル材１９が充填される。その後、再加熱により、アンダーフィル材１９を膨張させて、はんだボール１５との接合部の信頼性（耐クラック性）を向上させる処理が行われる。   In the underfill material filling step, as shown in FIG. 3, the space between the semiconductor package and the circuit wiring board 17 is filled with the thermally expandable underfill material 19. Thereafter, reheating is performed to expand the underfill material 19 and improve the reliability (crack resistance) of the joint with the solder ball 15.

まず、はんだボール１５が溶融しない温度範囲で加熱した場合、半導体パッケージおよび回路配線基板１７は、固化したはんだボール１５によって拘束されているため、アンダーフィル材１９は、高さ方向には膨張できない。したがって、膨張したアンダーフィル材１９は、回路配線基板１７の面に平行な方向に広がっていくことになる。   First, when the solder ball 15 is heated in a temperature range that does not melt, the semiconductor package and the circuit wiring board 17 are constrained by the solidified solder ball 15, and therefore the underfill material 19 cannot expand in the height direction. Therefore, the expanded underfill material 19 spreads in a direction parallel to the surface of the circuit wiring board 17.

加熱温度を上げていき、加熱温度がはんだボール１５の溶融温度、たとえば２１８℃に達すると、はんだボール１５による高さ方向の拘束が開放される。加熱温度をさらに上昇させることにより、半導体パッケージは、アンダーフィル材１９の膨張によって回路配線基板１７から離れる方向に移動するようになる。この半導体パッケージが上方へ移動するに連れて、太鼓状に変形して固化されていたはんだボール１５は、図４に示したように、引き延ばされて円柱状に変形される。このとき、はんだボール１５の高さｔは、約２４０マイクロメートルになる。   When the heating temperature is increased and the heating temperature reaches the melting temperature of the solder ball 15, for example, 218 ° C., the restraint in the height direction by the solder ball 15 is released. By further increasing the heating temperature, the semiconductor package moves away from the circuit wiring board 17 due to the expansion of the underfill material 19. As the semiconductor package moves upward, the solder ball 15 that has been deformed and solidified in a drum shape is stretched and deformed into a cylindrical shape as shown in FIG. At this time, the height t of the solder ball 15 is about 240 micrometers.

ここで、はんだボール１５が円柱状に達した温度を維持すると、やがてアンダーフィル材１９の硬化が進行していく。これにより、はんだボール１５の形状を維持した状態でアンダーフィル材１９が硬化する。その後、加熱温度をはんだボール１５の融点以下に低下させると、はんだボール１５は、円柱状の形状のまま固化することになる。   Here, when the temperature at which the solder ball 15 reaches the columnar shape is maintained, the underfill material 19 is gradually cured. As a result, the underfill material 19 is cured while the shape of the solder ball 15 is maintained. Thereafter, when the heating temperature is lowered below the melting point of the solder ball 15, the solder ball 15 is solidified in a cylindrical shape.

このように、はんだボール１５が円柱状に変形されることによって、はんだボール１５と半導体パッケージおよび回路配線基板１７との接合部に応力集中がなくなるので、ヒートサイクルによるクラックの発生を防止することができる。   As described above, since the solder ball 15 is deformed into a columnar shape, stress concentration does not occur at the joint between the solder ball 15 and the semiconductor package and the circuit wiring board 17, thereby preventing the occurrence of cracks due to heat cycles. it can.

アンダーフィル材１９が硬化する前に、加熱温度をさらに上げていくと、アンダーフィル材１９は、さらに膨張し、はんだボール１５は、図５に示したように、さらに引き延ばされてつづみ状（砂時計状）に変形される。その後、はんだボール１５のつづみ状（砂時計状）の形状を維持しながらアンダーフィル材１９は硬化し、そして、加熱温度をはんだボール１５の融点以下に低下させることにより、はんだボール１５は、つづみ状（砂時計状）の形状で固化される。これにより、はんだボール１５は、半導体パッケージおよび回路配線基板１７との接合部に応力が集中する形状にはならないので、耐クラック性が向上し、接合部の信頼性が向上した半導体装置にすることができる。   If the heating temperature is further increased before the underfill material 19 is cured, the underfill material 19 further expands, and the solder balls 15 are further stretched as shown in FIG. It is transformed into a shape (hourglass shape). Thereafter, the underfill material 19 is cured while maintaining the shape (hourglass shape) of the solder ball 15, and the heating temperature is lowered below the melting point of the solder ball 15. It is solidified in a mimic (hourglass) shape. As a result, the solder ball 15 does not have a shape in which stress is concentrated at the joint portion between the semiconductor package and the circuit wiring board 17, so that the semiconductor device is improved in crack resistance and reliability in the joint portion. Can do.

次に、はんだボール１５の形状を円柱状またはつづみ状の形状に変形させるアンダーフィル材１９について説明する。
図６はアンダーフィル材を構成する膨張性球体の説明図、図７は球体が樹脂中に最密充填状態にあるときの説明図である。 Next, the underfill material 19 that changes the shape of the solder ball 15 to a columnar shape or a zigzag shape will be described.
FIG. 6 is an explanatory view of the expandable sphere constituting the underfill material, and FIG. 7 is an explanatory view when the sphere is in the closest packed state in the resin.

アンダーフィル材１９は、たとえば、熱硬化性のエポキシ樹脂に膨張性球体２０を添加したもので構成することができる。膨張性球体２０は、図６に示したように、たとえば、中空部２１に液状ガスを内包した熱可塑性プラスチックの殻２２で形成される微小中空球体であり、平均粒子径が１０マイクロメートル前後の大きさを有している。膨張性球体２０は、膨張温度が８０〜２００℃で、殻２２内部のガス圧が増し、熱可塑性プラスチックの殻２２が軟化することで体積が増え、たとえば粒子径が４０マイクロメートルの中空球状粒子にすることができる。これは、最大体積膨張率が５０倍以上にもなることに相当する。なお、膨張性球体２０は、必要に応じて、中空部２１にガスを含まない低膨張率の微小中空球体を使用することもできる。また、アンダーフィル材１９の添加材である膨張性球体２０は、低弾性のため、加熱で膨張した後は、加熱温度が低下しても、その膨張状態を維持している。   The underfill material 19 can be constituted by, for example, a material obtained by adding an expandable sphere 20 to a thermosetting epoxy resin. As shown in FIG. 6, the expandable sphere 20 is a micro hollow sphere formed of, for example, a thermoplastic shell 22 in which a liquid gas is contained in a hollow portion 21, and has an average particle diameter of about 10 micrometers. It has a size. The expandable sphere 20 has an expansion temperature of 80 to 200 ° C., the gas pressure inside the shell 22 is increased, and the volume of the expandable sphere 20 is increased by softening the thermoplastic shell 22, for example, hollow spherical particles having a particle diameter of 40 μm. Can be. This corresponds to the maximum volume expansion coefficient being 50 times or more. In addition, the expansible sphere 20 can also use the micro hollow sphere of the low expansion coefficient which does not contain gas in the hollow part 21 as needed. Further, the expandable sphere 20 that is an additive to the underfill material 19 has low elasticity, and therefore, after expanding due to heating, the expanded state is maintained even if the heating temperature is lowered.

ここで、膨張性球体２０が互いに接触してエポキシ樹脂中に均一に整列していると仮定して、はんだボール１５が円柱状またはつづみ状（砂時計状）の形状に変形される条件について説明する。   Here, assuming that the expandable spheres 20 are in contact with each other and are uniformly aligned in the epoxy resin, the conditions under which the solder balls 15 are deformed into a columnar shape or a zigzag shape (hourglass shape) will be described. To do.

半径ｒの膨張性球体２０が、図７に示したようにエポキシ樹脂中に最密充填されている場合、エポキシ樹脂中における膨張性球体２０の占有率は、
４πｒ3／３÷（２ｒ）3≒０．５２
となり、膨張性球体２０は、アンダーフィル材１９の５２％を占めていることになる。 When the expandable spheres 20 having the radius r are closely packed in the epoxy resin as shown in FIG. 7, the occupation ratio of the expandable spheres 20 in the epoxy resin is
4πr 3/3 ÷ (2r) 3 ≒ 0.52
Thus, the expandable sphere 20 occupies 52% of the underfill material 19.

次に、このようなアンダーフィル材１９を充填し、はんだ溶融温度以上の温度で膨張性球体２０が膨張して、はんだボール１５が図３に示すような円柱状となるのに必要な膨張性球体２０の膨張率を計算してみる。   Next, the underfill material 19 is filled, and the expandable sphere 20 expands at a temperature equal to or higher than the solder melting temperature, and the expandability necessary for the solder ball 15 to have a cylindrical shape as shown in FIG. Let's calculate the expansion coefficient of the sphere 20.

回路配線基板１７の接続用電極１８のランド径が４２０マイクロメートルなら、ランド面積は、π（０．４２÷２）2≒０．１４ｍｍ2になる。一方、粒径が４００マイクロメートルのはんだボール１５の体積は、４π（０．４÷２）3÷３≒０．０３４ｍｍ3であるから、この体積の円柱の高さｔは、０．０３４÷０．１４≒０．２４０ｍｍ（約２４０マイクロメートル）になる。したがって、アンダーフィル材１９の厚さが円柱の高さｔに等しくなるまで膨張すれば、はんだボール１５によるはんだバンプの形状は、円柱状に変形されることになる。 If the land diameter of the connection electrode 18 of the circuit wiring board 17 is 420 micrometers, the land area is π (0.42 / 2) 2 ≈0.14 mm 2 . On the other hand, the volume of the solder ball 15 having a particle diameter of 400 micrometers is 4π (0.4 ÷ 2) 3 ÷ 3≈0.034 mm 3 , and therefore the height t of the cylinder of this volume is 0.034 ÷. 0.14≈0.240 mm (about 240 micrometers). Therefore, if the thickness of the underfill material 19 expands until it becomes equal to the height t of the cylinder, the shape of the solder bump by the solder ball 15 is deformed into a cylinder.

膨張性球体２０が図７に示したようにエポキシ樹脂中に互いに接触して整列している場合、膨張性球体２０の膨張率とアンダーフィル材１９の厚さの増加率は一致している。アンダーフィル材１９の厚さは、２００マイクロメートルから２４０マイクロメートルに膨張すればよいので、膨張性球体２０が１．２倍に膨張すれば、はんだパンプは円柱状となる。   When the expandable spheres 20 are arranged in contact with each other in the epoxy resin as shown in FIG. 7, the expansion rate of the expandable spheres 20 and the increase rate of the thickness of the underfill material 19 are the same. Since the thickness of the underfill material 19 may be expanded from 200 micrometers to 240 micrometers, if the expandable sphere 20 expands 1.2 times, the solder bump becomes a cylindrical shape.

したがって、アンダーフィル材１９として膨張性球体２０がエポキシ樹脂中に最密充填されたものを使用する場合、たとえば、はんだ溶融温度の２１８℃において、１．２倍に膨張するように熱膨張率が調整された膨張性球体２０を使用すればよいことになる。   Therefore, when using the underfill material 19 in which the expandable spheres 20 are closely packed in an epoxy resin, for example, the coefficient of thermal expansion is 1.2 times that of the solder melting temperature of 218 ° C. The adjusted expandable sphere 20 may be used.

しかし、実際のアンダーフィル材１９中の膨張性球体２０の分散状態は、図７のように密に整列していることはなく、膨張性球体２０の間にエポキシ樹脂が存在している。しかも、アンダーフィル材１９の充填性・流動性調整のため、添加量、粒径など調整されるため、体積含有率は、５２％よりも低くなる。このため、エポキシ樹脂内での膨張性球体２０の移動度が増加し、また、膨張時に膨張性球体２０が弾性変形するので、膨張性球体２０の膨張率とアンダーフィル材１９の厚さの膨張率は一致しない。   However, the dispersion state of the expandable spheres 20 in the actual underfill material 19 is not closely aligned as in FIG. 7, and an epoxy resin exists between the expandable spheres 20. Moreover, since the addition amount, particle size, and the like are adjusted to adjust the filling property and fluidity of the underfill material 19, the volume content is lower than 52%. For this reason, the mobility of the expandable sphere 20 in the epoxy resin is increased, and the expandable sphere 20 is elastically deformed during expansion. Therefore, the expansion rate of the expandable sphere 20 and the expansion of the thickness of the underfill material 19 are increased. The rates do not match.

したがって、実際には、上記の計算よりは大きい膨張率が必要となるが、膨張性球体２０の膨張率は、約５０倍まで任意に調整が可能である。加えて、膨張性球体２０の添加量／粒径／粒度分布／膨張率を最適に調整することによって、アンダーフィル材１９としての適切な流動性、充填性と接合信頼性の高い形状のはんだバンプとなるような膨張特性を得ることができる。   Therefore, in practice, a larger expansion coefficient than the above calculation is required, but the expansion coefficient of the expandable sphere 20 can be arbitrarily adjusted up to about 50 times. In addition, by adjusting the addition amount / particle size / particle size distribution / expansion rate of the expandable sphere 20 optimally, the solder bumps having a shape suitable for the underfill material 19 with high fluidity, filling properties and high bonding reliability An expansion characteristic such as

図８は銅ピラーはんだバンプを搭載した半導体パッケージの実装に適用した例を示す断面図である。なお、この図８において、図１〜図５に示した構成要素と同じまたは均等の構成要素については同じ符号を付してその詳細な説明は省略する。   FIG. 8 is a cross-sectional view showing an example applied to mounting of a semiconductor package on which copper pillar solder bumps are mounted. In FIG. 8, the same or equivalent components as those shown in FIGS. 1 to 5 are denoted by the same reference numerals, and detailed description thereof is omitted.

この例は、上述のはんだボールバンプ構造の半導体パッケージよりも信頼性が高く、高集積配線が可能な銅ピラーはんだバンプ構造を有する半導体パッケージの実装の場合を示している。すなわち、この半導体パッケージは、半導体チップ１１の下面の所定位置に銅ピラー２５が形成され、その銅ピラー２５の先端にはんだ１５ａが接合されてバンプを形成している。この銅ピラーはんだバンプは、配線の大部分がリフロー中に形状が変化しない銅であるため、全部はんだでできているバンプよりも、ピッチを小さくでき、バンプ形成に必要なはんだの量を大幅に削減でき、熱伝導性を大幅に高くできるといった特性を有している。   This example shows a case of mounting a semiconductor package having a copper pillar solder bump structure that is more reliable than the above-described semiconductor package having a solder ball bump structure and enables highly integrated wiring. That is, in this semiconductor package, a copper pillar 25 is formed at a predetermined position on the lower surface of the semiconductor chip 11, and a solder 15 a is joined to the tip of the copper pillar 25 to form a bump. This copper pillar solder bump is made of copper whose shape does not change during reflow, so the pitch can be made smaller than the bump made entirely of solder, and the amount of solder required for bump formation is greatly increased. It has the characteristics that it can be reduced and the thermal conductivity can be greatly increased.

このような半導体チップは、回路配線基板１７に搭載され、リフロー加熱によって銅ピラーはんだバンプを回路配線基板１７の接続用電極１８に接合する。このとき、半導体パッケージの大きさによっては、その自重によってはんだ１５ａの部分が太鼓状の形状になる可能性がある。   Such a semiconductor chip is mounted on the circuit wiring board 17, and the copper pillar solder bump is joined to the connection electrode 18 of the circuit wiring board 17 by reflow heating. At this time, depending on the size of the semiconductor package, there is a possibility that the portion of the solder 15a becomes a drum shape due to its own weight.

次に、半導体チップと回路配線基板１７との間の隙間に、熱硬化性のエポキシ樹脂に膨張性球体２０を添加したアンダーフィル材１９が充填される。その後、はんだ１５ａの溶融温度より高い温度でリフロー加熱することにより、はんだ１５ａが軟化し、アンダーフィル材１９の膨張性球体２０が膨張して半導体パッケージを持ち上げ、その状態でアンダーフィル材１９のエポキシ樹脂が熱硬化する。このとき、アンダーフィル材１９の膨張率を最適化しておくことにより、はんだ１５ａは、確実につづみ状のバンプを形成することができるので、さらなる高信頼性を保証することが可能になる。   Next, a gap between the semiconductor chip and the circuit wiring board 17 is filled with an underfill material 19 in which an expandable sphere 20 is added to a thermosetting epoxy resin. Thereafter, reflow heating is performed at a temperature higher than the melting temperature of the solder 15a, so that the solder 15a is softened and the expandable sphere 20 of the underfill material 19 expands to lift the semiconductor package. The resin is thermoset. At this time, by optimizing the expansion coefficient of the underfill material 19, the solder 15 a can surely form a continuous bump, so that further high reliability can be ensured.

１１ 半導体チップ
１２ アルミ電極
１３ 応力緩和層
１４ 金属再配線
１５ はんだボール
１５ａ はんだ
１６ 有機保護膜
１７ 回路配線基板
１８ 接続用電極
１９ アンダーフィル材
２０ 膨張性球体
２１ 中空部
２２ 殻
２５ 銅ピラー DESCRIPTION OF SYMBOLS 11 Semiconductor chip 12 Aluminum electrode 13 Stress relaxation layer 14 Metal rewiring 15 Solder ball 15a Solder 16 Organic protective film 17 Circuit wiring board 18 Connection electrode 19 Underfill material 20 Expandable sphere 21 Hollow part 22 Shell 25 Copper pillar

Claims (6)

同一平面上にはんだバンプを配列した半導体チップを回路配線基板に載置してリフロー加熱により両者を接合し、前記半導体チップと前記回路配線基板との間にアンダーフィル材を充填し、加熱により前記アンダーフィル材を硬化してなる半導体装置の製造方法において、
前記アンダーフィル材は、加熱時に体積が膨張する熱膨張性を有するものであり、前記アンダーフィル材を硬化させる温度は、前記はんだバンプのはんだ溶融温度よりも高くしたことを特徴とする半導体装置の製造方法。 A semiconductor chip in which solder bumps are arranged on the same plane is placed on a circuit wiring board and bonded together by reflow heating, an underfill material is filled between the semiconductor chip and the circuit wiring board, In the manufacturing method of the semiconductor device formed by curing the underfill material,
The underfill material has a thermal expansion property that expands in volume when heated, and a temperature for curing the underfill material is higher than a solder melting temperature of the solder bump. Production method. 前記アンダーフィル材は、熱硬化性のエポキシ樹脂に膨張性球体を添加したもので構成したことを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the underfill material is formed by adding an expandable sphere to a thermosetting epoxy resin. 前記アンダーフィル材は、前記膨張性球体の添加量、粒径および粒度分布を変えることにより最適の膨張率に調整されていることを特徴とする請求項２記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 2, wherein the underfill material is adjusted to an optimum expansion rate by changing an addition amount, a particle size, and a particle size distribution of the expandable sphere. 前記アンダーフィル材は、加熱により硬化されるまでの間、前記はんだバンプが円柱状またはつづみ状の形状に変形されるだけの膨張率を有していることを特徴とする請求項１記載の半導体装置の製造方法。   2. The underfill material has an expansion rate enough to deform the solder bump into a cylindrical shape or a zigzag shape until it is cured by heating. A method for manufacturing a semiconductor device. 同一平面上にはんだバンプを配列した半導体チップを回路配線基板に載置してリフロー加熱により両者を接合し、前記半導体チップと前記回路配線基板との間にアンダーフィル材を充填してなる半導体装置において、
前記アンダーフィル材は、加熱時に体積が膨張する添加剤を含んでいることを特徴とする半導体装置。 A semiconductor device in which a semiconductor chip having solder bumps arranged on the same plane is placed on a circuit wiring board, both are joined by reflow heating, and an underfill material is filled between the semiconductor chip and the circuit wiring board. In
The underfill material includes an additive that expands in volume when heated. 前記はんだバンプは、円柱状またはつづみ状の形状を有していることを特徴とする請求項５記載の半導体装置。   6. The semiconductor device according to claim 5, wherein the solder bump has a columnar shape or a continuous shape.
JP2009223230A 2009-09-28 2009-09-28 Method of manufacturing semiconductor device, and semiconductor device Pending JP2011071436A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013211382A (en) * 2012-03-30 2013-10-10 Fujitsu Ltd Printed circuit board and method of manufacturing the same
JP2014035546A (en) * 2012-08-07 2014-02-24 Luxtera Inc Method and system for hybrid integration of optical communication system
US9041200B2 (en) 2013-06-03 2015-05-26 Samsung Electronics Co., Ltd. Semiconductor devices having solder terminals spaced apart from mold layers and related methods
JP2020004910A (en) * 2018-06-29 2020-01-09 リンテック株式会社 Mounting device and mounting method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007048987A (en) * 2005-08-11 2007-02-22 Matsushita Electric Ind Co Ltd Flip chip packaging method
JP2008311458A (en) * 2007-06-15 2008-12-25 Panasonic Corp Semiconductor device mounting structure, its manufacturing method, and method for peeling semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007048987A (en) * 2005-08-11 2007-02-22 Matsushita Electric Ind Co Ltd Flip chip packaging method
JP2008311458A (en) * 2007-06-15 2008-12-25 Panasonic Corp Semiconductor device mounting structure, its manufacturing method, and method for peeling semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013211382A (en) * 2012-03-30 2013-10-10 Fujitsu Ltd Printed circuit board and method of manufacturing the same
JP2014035546A (en) * 2012-08-07 2014-02-24 Luxtera Inc Method and system for hybrid integration of optical communication system
US9041200B2 (en) 2013-06-03 2015-05-26 Samsung Electronics Co., Ltd. Semiconductor devices having solder terminals spaced apart from mold layers and related methods
JP2020004910A (en) * 2018-06-29 2020-01-09 リンテック株式会社 Mounting device and mounting method
JP7085919B2 (en) 2018-06-29 2022-06-17 リンテック株式会社 Mounting device and mounting method

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