JP2010225598A - Semiconductor component and method of manufacturing semiconductor device - Google Patents

Semiconductor component and method of manufacturing semiconductor device Download PDF

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JP2010225598A
JP2010225598A JP2009067759A JP2009067759A JP2010225598A JP 2010225598 A JP2010225598 A JP 2010225598A JP 2009067759 A JP2009067759 A JP 2009067759A JP 2009067759 A JP2009067759 A JP 2009067759A JP 2010225598 A JP2010225598 A JP 2010225598A
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solder
drum
pad
bump
semiconductor component
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Yasuhiko Ochi
靖彦 越智
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor component which improves the reliability of connection between bumps and pads, and to provide a method of manufacturing a semiconductor device. <P>SOLUTION: The semiconductor component 1, which is not connected to a pad 13 yet, includes a drum-shaped solder bump 6. The drum-shaped solder bump 6 can be connected to the pad 13, and is formed such that a contact surface to the pad 13 and a side face in the vicinity of the contact surface makes an acute angle. This improves the reliability of connection between the drum-shaped solder bump 6 and the pad 13. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は半導体部品及び半導体装置の製造方法に関する。   The present invention relates to a semiconductor component and a method for manufacturing a semiconductor device.

近年の電子機器の小型化、高機能化に伴い、搭載される部品の小型化が進んでいる。小型パッケージは、ボールグリッドアレイ（Ball Grid Array、以下ＢＧＡと称す）やチップサイズパッケージ（Chip Size Package、以下ＣＳＰと称す）など微細なはんだバンプを用いたものが主流となっている。これらのパッケージを回路基板に実装すると、はんだバンプが太鼓状の形状となるため、隣接するはんだバンプ同士が短絡することがある。また、太鼓状の形状は基板との接合部分に応力が集中するため、界面剥離などが生じやすくなる。   With recent downsizing and higher functionality of electronic devices, the components to be mounted are being downsized. Small packages mainly use fine solder bumps such as a ball grid array (hereinafter referred to as BGA) and a chip size package (hereinafter referred to as CSP). When these packages are mounted on a circuit board, the solder bumps have a drum shape, so that adjacent solder bumps may be short-circuited. Further, the drum-shaped shape concentrates stress on the joint portion with the substrate, so that interface peeling or the like is likely to occur.

特許文献１には、隣接するはんだバンプ同士の短絡を防止する技術が開示されている。ここで、特許文献１の発明について、図を用いて説明する。図５（ａ）は、パッケージの構成を示す平面図である。図５（ｂ）は、図５（ａ）のＶＢ−ＶＢ断面図である。図５に示すように、特許文献１のパッケージは、マスクを用いて作製した円柱状はんだバンプ２０、基板支持台２１を有している。基板支持台２１の厚さは、円柱状はんだバンプ２０の高さよりも０．１５ｍｍ程度低く設定されている。   Patent Document 1 discloses a technique for preventing a short circuit between adjacent solder bumps. Here, the invention of Patent Document 1 will be described with reference to the drawings. FIG. 5A is a plan view showing the configuration of the package. FIG. 5B is a VB-VB sectional view of FIG. As shown in FIG. 5, the package of Patent Document 1 includes a columnar solder bump 20 manufactured using a mask and a substrate support base 21. The thickness of the substrate support 21 is set to be about 0.15 mm lower than the height of the columnar solder bump 20.

図６は、パッケージを回路基板に実装・接合するときの状態を示す断面図である。回路基板２２に実装する際は、図６（ａ）に示すように、円柱状はんだバンプ２０を回路基板２２のパッド２２ａに合わせ、リフロー処理を行う。図６（ｂ）に示すように、パッケージの自重は、基板支持台２１によって支えられるため、円柱状はんだバンプ２０の変形もしくは沈み込みも抑制・防止され、隣接する円柱状はんだバンプ２０同士の短絡発生はない。   FIG. 6 is a cross-sectional view showing a state when the package is mounted and bonded to the circuit board. When mounting on the circuit board 22, as shown in FIG. 6A, the columnar solder bumps 20 are aligned with the pads 22a of the circuit board 22, and a reflow process is performed. As shown in FIG. 6B, since the weight of the package is supported by the substrate support 21, deformation or sinking of the columnar solder bumps 20 is also suppressed / prevented, and the adjacent columnar solder bumps 20 are short-circuited. There is no occurrence.

特許文献２には、接続信頼性を向上させる手段が開示されている。ここで、特許文献２の発明について、図を用いて説明する。図７は、パッケージの構成を示す断面図である。特許文献２のパッケージは、図７に示すように、はんだバンプ３０とコア材を含むはんだバンプ３１を有している。コア材を含むはんだバンプ３１は、はんだバンプ３０よりも球径が大きく、パッケージ内の３点以上の支持位置に配置されている。   Patent Document 2 discloses means for improving connection reliability. Here, the invention of Patent Document 2 will be described with reference to the drawings. FIG. 7 is a cross-sectional view showing the structure of the package. As shown in FIG. 7, the package of Patent Document 2 includes solder bumps 30 and solder bumps 31 including a core material. The solder bump 31 including the core material has a sphere diameter larger than that of the solder bump 30 and is arranged at three or more support positions in the package.

図８は、パッケージを回路基板２２に実装・接合するときの状態を示す断面図である。回路基板２２に実装する際は、図８（ａ）に示すように、パッケージを所望の位置に合わせる。はんだバンプ３０よりもコア材を含むはんだバンプ３１の球径が大きいため、コア材を含むはんだバンプ３１のみ回路基板２２上のパッド２２ａに接触している。次にコア材を含むはんだバンプ３１のみを溶融させる条件でリフローを行うと、図８（ｂ）に示すように、はんだバンプ３０がパッド２２ａに点接触する。この状態ではんだバンプ３０を溶融させると、図８（ｃ）に示すように、コア材を含むはんだバンプ３１によってパッケージと回路基板２２の間隔が維持されているため、はんだバンプ３０は球形を保つことができず、鼓状の形となる。はんだ接続部の形を鼓状にすることにより、応力の集中が緩和され、接続信頼性が向上する。   FIG. 8 is a cross-sectional view showing a state when the package is mounted and bonded to the circuit board 22. When mounting on the circuit board 22, as shown in FIG. 8A, the package is adjusted to a desired position. Since the spherical diameter of the solder bump 31 including the core material is larger than that of the solder bump 30, only the solder bump 31 including the core material is in contact with the pad 22 a on the circuit board 22. Next, when reflow is performed under the condition that only the solder bump 31 including the core material is melted, the solder bump 30 makes point contact with the pad 22a as shown in FIG. 8B. When the solder bumps 30 are melted in this state, as shown in FIG. 8C, the distance between the package and the circuit board 22 is maintained by the solder bumps 31 including the core material, so that the solder bumps 30 maintain a spherical shape. Can't do it, it becomes a drum shape. By making the shape of the solder connection portion into a drum shape, the concentration of stress is alleviated and the connection reliability is improved.

また、特許文献３には、はんだ接続部の形を鼓状にする他の手段が開示されている。ここで、特許文献３の発明について、図を用いて説明する。図９は、パッケージを回路基板に実装・接合するときの状態を示す断面図である。特許文献３のパッケージは、図９（ａ）に示すように、半球形状のはんだバンプ４０を有している。すなわち、はんだバンプ４０のはんだ量を減らしている。このパッケージを図９（ｂ）に示すように回路基板２２上に載置し、図９（ｃ）に示すように実装する。   Patent Document 3 discloses another means for making the shape of the solder connection portion a drum shape. Here, the invention of Patent Document 3 will be described with reference to the drawings. FIG. 9 is a cross-sectional view showing a state when the package is mounted and bonded to the circuit board. The package of Patent Document 3 has a hemispherical solder bump 40 as shown in FIG. That is, the solder amount of the solder bump 40 is reduced. This package is placed on the circuit board 22 as shown in FIG. 9B and mounted as shown in FIG. 9C.

このように、はんだ量が少ないはんだバンプ４０を用いることにより、図１０に示すようはんだ接続部（接合部４１）の形が鼓状になる。図１０は、接合部４１の形状を示す断面図である。溶融したはんだバンプ４０はパッケージの重みで押しつぶされる。一方、はんだバンプ４０の表面張力によってパッケージが押し上げられる。そして、パッケージの重量と、表面張力による押し上げ力とがバランスして、接合部４１の形が鼓状となる。   Thus, by using the solder bump 40 with a small amount of solder, the shape of the solder connection portion (joint portion 41) becomes a drum shape as shown in FIG. FIG. 10 is a cross-sectional view showing the shape of the joint portion 41. The molten solder bump 40 is crushed by the weight of the package. On the other hand, the package is pushed up by the surface tension of the solder bumps 40. Then, the weight of the package and the push-up force due to surface tension are balanced, and the shape of the joint portion 41 becomes a drum shape.

特開平１０−１６３３６５号公報Japanese Patent Laid-Open No. 10-163365 特開２００４−１６５５１１号公報JP 2004-165511 A 特開２００１−３３９１５１号公報JP 2001-339151 A

しかし、特許文献１の発明では、回路基板２２に実装した後も、円柱状はんだバンプ２０を柱状に保つためには、パッケージと回路基板２２の間隔を一定に保つ何らかの支持台が必要である。このため、支持台を付ける工程の増加や製造コストが高くなるという問題があった。また、円柱状はんだバンプ２０は、回路基板２２との接合部に応力が集中し界面剥離が生じるなど、はんだ接続の信頼性が低下するという問題があった。   However, in the invention of Patent Document 1, in order to keep the columnar solder bumps 20 in a columnar shape even after being mounted on the circuit board 22, some support base that keeps the distance between the package and the circuit board 22 constant is necessary. For this reason, there existed a problem that the process of attaching a support stand and the manufacturing cost became high. In addition, the columnar solder bump 20 has a problem that reliability of solder connection is lowered, for example, stress concentrates on a joint portion with the circuit board 22 and interface peeling occurs.

また、特許文献２の発明は、球状のはんだバンプ３０を鼓状に変化させるために、コア材を含むはんだバンプ３１を少なくとも３点支持位置に配置する必要がある。さらに、２種類のはんだバンプ３０、３１の融点を違えるなど制約がある。このため、工程が複雑になるという問題があった。   Further, in the invention of Patent Document 2, in order to change the spherical solder bump 30 into a drum shape, it is necessary to arrange the solder bumps 31 including the core material at at least three points. Furthermore, there are restrictions such as different melting points of the two types of solder bumps 30 and 31. For this reason, there existed a problem that a process became complicated.

また、特許文献３では、特許文献２の発明の課題を解決することができる。しかし、パッケージの重量と表面張力による押し上げ力とをバランスさせた場合、図１１のはんだ付け角度αが十分大きくならず、応力緩和の効果が小さくなるという問題があった。また、はんだ量が少なく、はんだバンプ４０の高さが低くなるため、耐応力性の低下や、パッケージ、回路基板２２の平坦性が悪化した時にはんだ接続信頼性が低下するといった問題があった。   Moreover, in patent document 3, the subject of the invention of patent document 2 can be solved. However, when the weight of the package and the push-up force due to the surface tension are balanced, there is a problem that the soldering angle α in FIG. Further, since the amount of solder is small and the height of the solder bump 40 is lowered, there is a problem that the solder connection reliability is lowered when the stress resistance is lowered and the flatness of the package and the circuit board 22 is deteriorated.

以上のように、特許文献２、３の発明では、もともと球状や半球状のはんだバンプを回路基板に実装する際に鼓状に変化させている。このため、工程が複雑になったり、最適な高さ・形状のはんだ接続ができないという問題があった。   As described above, in the inventions of Patent Documents 2 and 3, originally, spherical or hemispherical solder bumps are changed into a drum shape when mounted on a circuit board. For this reason, there existed a problem that a process became complicated and the solder connection of the optimal height and shape could not be performed.

本発明にかかる半導体部品は、パッドと接続する前の半導体部品であって、前記パッドと接続可能であり、前記パッドとの接続面から当該接続面近傍の側面までの角度が鋭角であるバンプを有するものである。これにより、応力集中、バンプの短絡等が抑制されて、バンプとパッドとの接続の信頼性が向上する。   A semiconductor component according to the present invention is a semiconductor component before being connected to a pad, and can be connected to the pad, and a bump having an acute angle from a connection surface with the pad to a side surface in the vicinity of the connection surface. It is what you have. As a result, stress concentration, bump short-circuiting, and the like are suppressed, and the reliability of the connection between the bump and the pad is improved.

本発明にかかる半導体装置の製造方法は、半導体部品のバンプをパッドとの接続面から当該接続面近傍の側面までの角度が鋭角となるように形成し、前記バンプと前記パッドとを接続するものである。これにより、応力集中、バンプの短絡等が抑制されて、バンプとパッドとの接続の信頼性が向上する。   In the method of manufacturing a semiconductor device according to the present invention, a bump of a semiconductor component is formed so that an angle from a connection surface with a pad to a side surface near the connection surface is an acute angle, and the bump and the pad are connected. It is. As a result, stress concentration, bump short-circuiting, and the like are suppressed, and the reliability of the connection between the bump and the pad is improved.

本発明によれば、バンプとパッドとの接続の信頼性が向上する半導体部品及び半導体装置の製造方法を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor component and semiconductor device which the reliability of the connection of a bump and a pad improves can be provided.

実施の形態１にかかる半導体装置の構成を示す断面図である。1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment; 実施の形態１にかかる半導体部品の要部の構成を示す断面図である。FIG. 3 is a cross-sectional view showing a configuration of a main part of the semiconductor component according to the first embodiment. 実施の形態１にかかる鼓状はんだバンプの接続面周辺を拡大した断面図である。FIG. 3 is an enlarged cross-sectional view of the periphery of the connecting surface of the drum-shaped solder bump according to the first embodiment. 実施の形態１にかかる半導体部品を回路基板に実装・接合するときの状態を示す断面図である。FIG. 3 is a cross-sectional view showing a state when the semiconductor component according to the first embodiment is mounted and bonded to a circuit board. 特許文献１におけるパッケージの構成を示す図である。It is a figure which shows the structure of the package in patent document 1. FIG. 特許文献１におけるパッケージを回路基板に実装・接合するときの状態を示す断面図である。It is sectional drawing which shows a state when the package in patent document 1 is mounted and joined to a circuit board. 特許文献２におけるパッケージの構成を示す断面図である。10 is a cross-sectional view illustrating a configuration of a package in Patent Document 2. FIG. 特許文献２におけるパッケージを回路基板に実装・接合するときの状態を示す断面図である。It is sectional drawing which shows a state when the package in patent document 2 is mounted and joined to a circuit board. 特許文献３におけるパッケージを回路基板に実装・接合するときの状態を示す断面図である。It is sectional drawing which shows a state when the package in patent document 3 is mounted and joined to a circuit board. 特許文献３における接続部の形状を示す断面図である。It is sectional drawing which shows the shape of the connection part in patent document 3. FIG. 特許文献３における接続部位の形状を示す説明図である。It is explanatory drawing which shows the shape of the connection site | part in patent document 3. FIG.

実施の形態１
まず、図１を参照して、本実施の形態にかかる半導体装置について説明する。図１は、半導体装置の構成を示す断面図である。 Embodiment 1
First, a semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device.

半導体装置は、半導体部品１と回路基板１２を有する。半導体部品１は、回路基板１２に実装される。半導体部品１とは、例えば、ボールグリッドアレイ（Ball Grid Array、以下ＢＧＡと称す）やチップサイズパッケージ（Chip Size Package、以下ＣＳＰと称す）のパッケージである。半導体部品１は、半導体チップ２を有する。半導体チップ２は、マウント材３によって基板５に接着される。半導体チップ２は、例えば、基板５の中央部に固定される。半導体チップ２は、モールド樹脂４によって封止されている。モールド樹脂４とは、外部環境から半導体チップ２を保護するものである。   The semiconductor device has a semiconductor component 1 and a circuit board 12. The semiconductor component 1 is mounted on the circuit board 12. The semiconductor component 1 is, for example, a ball grid array (hereinafter referred to as BGA) or a chip size package (hereinafter referred to as CSP). The semiconductor component 1 has a semiconductor chip 2. The semiconductor chip 2 is bonded to the substrate 5 by the mount material 3. The semiconductor chip 2 is fixed to the central part of the substrate 5, for example. The semiconductor chip 2 is sealed with a mold resin 4. Mold resin 4 protects semiconductor chip 2 from the external environment.

基板５の下面には、鼓状はんだバンプ６が形成される。鼓状はんだバンプ６とは、鼓状のバンプである。鼓状はんだバンプ６は、ボンディングワイヤ７等を介して半導体チップ２に電気的に接続される。鼓状はんだバンプ６は、回路基板１２のパッド１３と電気的に接続される。パッド１３は、鼓状はんだバンプ６に対応して回路基板１２の上面に形成される。   A drum-like solder bump 6 is formed on the lower surface of the substrate 5. The drum-shaped solder bump 6 is a drum-shaped bump. The drum-like solder bump 6 is electrically connected to the semiconductor chip 2 via a bonding wire 7 or the like. The drum-shaped solder bump 6 is electrically connected to the pad 13 of the circuit board 12. The pad 13 is formed on the upper surface of the circuit board 12 corresponding to the drum-like solder bump 6.

次に、図２を参照して、上記の半導体部品１の構成について詳細に説明する。図２は、半導体部品１の要部の構成を示す断面図である。ここでの半導体部品１は、パッド１３と接続する前の半導体部品である。   Next, the configuration of the semiconductor component 1 will be described in detail with reference to FIG. FIG. 2 is a cross-sectional view showing the configuration of the main part of the semiconductor component 1. The semiconductor component 1 here is a semiconductor component before being connected to the pad 13.

基板５の上面側（半導体チップ２側）には、パッド８が形成される。パッド８は、上面視にて半導体チップ２より外側に形成される。半導体チップ２と基板５のパッド８とは、ボンディングワイヤ７によって電気的に接続されている。また、基板５の下面側にも、パッド９が形成される。パッド９は、例えば格子状に配置される。また、パッド９は、半導体チップ２直下にも形成される。基板５の内部には、電気配線１０及びビア１１が形成される。基板５の上面側のパッド８と基板５の下面側のパッド９とは、電気配線１０やビア１１を介して、電気的に接続される。   Pads 8 are formed on the upper surface side (semiconductor chip 2 side) of the substrate 5. The pad 8 is formed outside the semiconductor chip 2 in a top view. The semiconductor chip 2 and the pad 8 of the substrate 5 are electrically connected by a bonding wire 7. A pad 9 is also formed on the lower surface side of the substrate 5. The pads 9 are arranged in a grid, for example. The pad 9 is also formed immediately below the semiconductor chip 2. An electrical wiring 10 and a via 11 are formed inside the substrate 5. The pad 8 on the upper surface side of the substrate 5 and the pad 9 on the lower surface side of the substrate 5 are electrically connected via the electric wiring 10 and the via 11.

基板５の下面側に形成されたパッド９には、鼓状はんだバンプ６がそれぞれ接続される。鼓状はんだバンプ６は、外部から接続可能になっている。具体的には、鼓状はんだバンプ６は、回路基板１２に形成されたパッド１３と接続可能になっている。鼓状はんだバンプ６は、パッド１３との接続面からこの接続面近傍の側面までの角度が鋭角となるように形成される。すなわち、図３に示された鼓状はんだバンプ６の底面から側面までの角度αは９０度未満である。図３は、鼓状はんだバンプ６の接続面周辺を拡大した断面図である。   The drum-like solder bumps 6 are connected to the pads 9 formed on the lower surface side of the substrate 5, respectively. The drum-like solder bump 6 can be connected from the outside. Specifically, the drum-like solder bumps 6 can be connected to the pads 13 formed on the circuit board 12. The drum-like solder bump 6 is formed so that the angle from the connection surface with the pad 13 to the side surface near the connection surface becomes an acute angle. That is, the angle α from the bottom surface to the side surface of the hourglass solder bump 6 shown in FIG. 3 is less than 90 degrees. FIG. 3 is an enlarged cross-sectional view of the periphery of the connection surface of the drum-like solder bump 6.

換言すると、図１に示されたパッド１３の鼓状はんだバンプ６との接続面から、この接続面近傍の鼓状はんだバンプ６の側面までの角度は鋭角である。また、鼓状はんだバンプ６の基板５側についても同様の形状を有する。すなわち、鼓状はんだバンプ６は、パッド９との接続面からこの接続面近傍の側面までの角度が鋭角となるように形成される。   In other words, the angle from the connection surface of the pad 13 shown in FIG. 1 with the hourglass solder bump 6 to the side surface of the hourglass solder bump 6 near the connection surface is an acute angle. Further, the drum-like solder bump 6 has the same shape on the substrate 5 side. That is, the drum-shaped solder bump 6 is formed so that the angle from the connection surface with the pad 9 to the side surface near the connection surface becomes an acute angle.

鼓状はんだバンプ６は、高さ方向の中央部から上部及び下部に向けて徐々に末広がりになる。換言すると、鼓状はんだバンプ６の高さ方向の中央部における断面積より鼓状はんだバンプ６上部及び下部における断面積のほうが大きい。鼓状はんだバンプ６は、上面視にてパッド９又はパッド１３の内側に形成される。また、鼓状はんだバンプ６の側面は、Ｃ字型に湾曲している。   The drum-like solder bump 6 gradually spreads from the center in the height direction toward the upper and lower parts. In other words, the cross-sectional areas at the top and bottom of the drum-shaped solder bump 6 are larger than the cross-sectional area at the center of the drum-shaped solder bump 6 in the height direction. The drum-shaped solder bump 6 is formed inside the pad 9 or the pad 13 in a top view. The side surface of the drum-like solder bump 6 is curved in a C shape.

このように、本実施の形態にかかる半導体部品１は、鼓状はんだバンプ６を有する。すなわち、図３に示された角度αは鋭角である。これにより、図１に示された半導体装置において、鼓状はんだバンプ６とパッド１３との接合部における応力の集中が緩和され、鼓状はんだバンプ６とパッド１３との接続の信頼性が向上する。すなわち、はんだ接続の信頼性が向上する。また、応力の集中が緩和されるため、接合部の界面剥離等が生じにくくなり、強度が向上する。   Thus, the semiconductor component 1 according to the present embodiment has the drum-like solder bumps 6. That is, the angle α shown in FIG. 3 is an acute angle. Thereby, in the semiconductor device shown in FIG. 1, the concentration of stress at the joint between the hourglass solder bump 6 and the pad 13 is alleviated, and the reliability of the connection between the hourglass solder bump 6 and the pad 13 is improved. . That is, the reliability of solder connection is improved. In addition, since the stress concentration is relaxed, interface peeling or the like at the joint is less likely to occur and the strength is improved.

また、鼓状はんだバンプ６は、上面視にてパッド９又はパッド１３の内側に形成される。このため、狭ピッチでパッド９、１３を形成しても、隣接する鼓状はんだバンプ６同士が短絡しにくくなる。すなわち、半導体部品１としてＢＧＡ、ＣＳＰのパッケージを用いたとしても、鼓状はんだバンプ６とパッド１３との接続の信頼性を維持できる。これにより、半導体部品１や半導体装置の製品としての信頼性が向上する。   The drum-like solder bump 6 is formed inside the pad 9 or the pad 13 when viewed from above. For this reason, even if the pads 9 and 13 are formed at a narrow pitch, the adjacent drum-shaped solder bumps 6 are not easily short-circuited. That is, even when a BGA or CSP package is used as the semiconductor component 1, the reliability of the connection between the drum-shaped solder bump 6 and the pad 13 can be maintained. Thereby, the reliability as a product of the semiconductor component 1 or the semiconductor device is improved.

なお、本実施の形態では、半導体部品１として、例えば、ＢＧＡ、ＣＳＰのパッケージを説明したがこれに限らない。他のタイプのパッケージであってもいいし、パッケージでなくてもよい。すなわち、はんだバンプを用いて回路基板等の基板と接続するタイプであれば、どのような形態の半導体部品を用いてもよい。   In the present embodiment, as the semiconductor component 1, for example, a BGA or CSP package has been described. However, the present invention is not limited to this. Other types of packages may or may not be packages. That is, any type of semiconductor component may be used as long as it is a type that is connected to a substrate such as a circuit board using solder bumps.

また、鼓状はんだバンプ６はパッド１３との接続面からこの接続面近傍の側面までの角度が鋭角となるように形成されていれば、鼓以外の形状のバンプとしてもよい。もちろん、上記のように、パッド１３とは反対側でもパッド９と接続される場合、鼓状はんだバンプ６は、パッド９との接続面からこの接続面近傍の側面までの角度が鋭角となるように形成されることが好ましい。例えば、鼓状とすることが好ましい。   The drum-shaped solder bump 6 may be a bump having a shape other than the drum as long as the angle from the connection surface with the pad 13 to the side surface near the connection surface is an acute angle. Of course, as described above, when the drum-shaped solder bump 6 is connected to the pad 9 on the side opposite to the pad 13, the angle from the connection surface with the pad 9 to the side surface near the connection surface is an acute angle. It is preferable to be formed. For example, a drum shape is preferable.

次に、半導体部品１の製造方法について説明する。まず、電気配線１０及びビア１１が形成された基板５上に、銀ペーストなどのマウント材３によって、半導体チップ２を接着する。そして、金線などのボンディングワイヤ７によって、半導体チップ２と基板５の上面側に形成されたパッド８とを電気的に接続する。半導体チップ２をモールド樹脂４などによって封止し保護する。   Next, a method for manufacturing the semiconductor component 1 will be described. First, the semiconductor chip 2 is bonded to the substrate 5 on which the electrical wiring 10 and the via 11 are formed by the mounting material 3 such as silver paste. Then, the semiconductor chip 2 and the pad 8 formed on the upper surface side of the substrate 5 are electrically connected by a bonding wire 7 such as a gold wire. The semiconductor chip 2 is sealed and protected by a mold resin 4 or the like.

次に、基板５の下面側に形成されたパッド９上にはんだペーストを塗布する。また、パッド９の位置に対応させたカセットに、あらかじめ形成された鼓状はんだバンプ６を並べる。そして、はんだペーストを塗布したパッド９に鼓状はんだバンプ６を転写して接続する。   Next, a solder paste is applied on the pad 9 formed on the lower surface side of the substrate 5. Further, drum-shaped solder bumps 6 formed in advance are arranged in a cassette corresponding to the position of the pad 9. Then, the drum-like solder bumps 6 are transferred and connected to the pads 9 to which the solder paste is applied.

鼓状はんだバンプ６を作製する方法としては、鋳型を用いる方法や球状のはんだボールを加工する方法などがある。鋳型を用いる方法では、まず、鼓状はんだバンプ６の逆型を有する鋳型に溶融させたはんだを流し込む。すなわち、鼓形状の逆型を有する鋳型に溶融させたはんだを流し込む。そして、はんだが冷却して凝固した後、形成された鼓状はんだバンプ６を取り出す。また、球状のはんだボールを加工する方法では、従来用いられている球状のはんだボールに機械的圧力を加えて鼓状に加工する。これにより、鼓状はんだバンプ６が形成される。以上の工程により、図２に示された半導体部品１が完成する。   As a method for producing the drum-like solder bump 6, there are a method using a mold and a method of processing a spherical solder ball. In the method using a mold, first, molten solder is poured into a mold having a reverse mold of the drum-like solder bump 6. That is, the molten solder is poured into a mold having an inverted drum shape. Then, after the solder is cooled and solidified, the formed drum-like solder bump 6 is taken out. Further, in the method of processing a spherical solder ball, mechanical pressure is applied to a conventionally used spherical solder ball to process it into a drum shape. Thereby, the drum-like solder bump 6 is formed. Through the above steps, the semiconductor component 1 shown in FIG. 2 is completed.

次に、図４を参照して、半導体部品１を備える半導体装置の製造方法について説明する。すなわち、半導体部品１の実装方法について説明する。図４は、半導体部品１を回路基板１２に実装・接合するときの状態を示す断面図である。   Next, a method for manufacturing a semiconductor device including the semiconductor component 1 will be described with reference to FIG. That is, a method for mounting the semiconductor component 1 will be described. FIG. 4 is a cross-sectional view showing a state when the semiconductor component 1 is mounted and bonded to the circuit board 12.

半導体部品１を回路基板１２に実装する際、図４（ａ）に示されるように、回路基板１２の上面側に形成されたパッド１３上にあらかじめはんだペースト１４を塗布する。次に、図４（ｂ）に示されるように、はんだペースト１４を介してパッド１３と鼓状はんだバンプ６とを対向配置させる。そして、パッド１３と鼓状はんだバンプ６とを位置合わせする。鼓状はんだバンプ６をパッド１３上のはんだペースト１４に接触させる。次に、リフローを行ってはんだペースト１４を溶融させ、鼓状はんだバンプ６とパッド１３を接続する。以上の工程により、図１に示された半導体装置が完成する。こうして得られたはんだの接続形状は、所望の鼓状となり、接続信頼性を向上させることができる。   When the semiconductor component 1 is mounted on the circuit board 12, as shown in FIG. 4A, a solder paste 14 is applied in advance on the pads 13 formed on the upper surface side of the circuit board 12. Next, as shown in FIG. 4B, the pads 13 and the drum-like solder bumps 6 are arranged to face each other with the solder paste 14 interposed therebetween. Then, the pad 13 and the drum-like solder bump 6 are aligned. The drum-like solder bump 6 is brought into contact with the solder paste 14 on the pad 13. Next, reflow is performed to melt the solder paste 14, and the drum-like solder bump 6 and the pad 13 are connected. Through the above steps, the semiconductor device shown in FIG. 1 is completed. The solder connection shape thus obtained has a desired drum shape, and the connection reliability can be improved.

本実施の形態にかかる半導体装置は、はんだバンプが最初から鼓状の形であることから、余分な部品や工程を追加することなく、鼓状のはんだ接続を行うことができる。すなわち、簡便にはんだの接続形状を鼓状にすることができる。また、鼓状はんだバンプ６の形や高さをあらかじめ調整することにより、回路基板１２に実装した後のはんだの接続形状を容易に制御することができる。   In the semiconductor device according to the present embodiment, since the solder bumps have a drum shape from the beginning, the drum-shaped solder connection can be performed without adding extra parts and processes. That is, the solder connection shape can be simply made into a drum shape. Further, by adjusting the shape and height of the drum-shaped solder bump 6 in advance, the solder connection shape after mounting on the circuit board 12 can be easily controlled.

例えば、応力の集中が十分に緩和する程度まで、図３に示された角度αを小さくすることができる。また、例えば、鼓状はんだバンプ６の高さを高めに設定することにより、半導体部品１や回路基板１２の平坦性が悪い場合でも、そのばらつきを吸収して安定したはんだ接続を行うことができる。さらに、はんだ接続の高さが高くなるので耐応力性が向上し、はんだ接続の信頼性を向上させることができる。また、鼓状はんだバンプ６の短絡を抑制することができるため、実装密度を向上させることができる。   For example, the angle α shown in FIG. 3 can be reduced to the extent that the stress concentration is sufficiently relaxed. Further, for example, by setting the height of the drum-shaped solder bump 6 to be high, even when the flatness of the semiconductor component 1 or the circuit board 12 is poor, the variation can be absorbed and stable solder connection can be performed. . Furthermore, since the height of the solder connection is increased, the stress resistance is improved, and the reliability of the solder connection can be improved. Further, since the short circuit of the drum-like solder bump 6 can be suppressed, the mounting density can be improved.

これに対して、公知技術の半導体装置は、球状あるいは半球状など、もともと鼓状ではないはんだバンプを、回路基板に実装する際に溶融し鼓状に変化させる。このため、鼓の形や高さを希望通りのものに制御することは困難であった。また、はんだバンプを鼓状に変化させるための部品や工程が必要であった。   On the other hand, in the known semiconductor device, solder bumps that are not originally drum-shaped, such as spherical or hemispherical shapes, are melted and changed into a drum shape when mounted on a circuit board. For this reason, it has been difficult to control the shape and height of the drum as desired. Further, parts and processes for changing the solder bumps into a drum shape are necessary.

実施の形態２
本実施の形態では、鼓状はんだバンプ６を融点の高い高温はんだで形成する。具体的には、鼓状はんだバンプ６の融点は、鼓状はんだバンプ６と回路基板１２のパッド１３とを接続するはんだペースト１４の融点より高い。本実施の形態でも半導体装置及び半導体部品１は、図１〜３と同様の構成を有する。また、半導体部品１は、高温はんだを用いて実施の形態１と同様に製造される。なお、実施の形態１と共通する説明は、適宜省略又は簡略化する。ここで、本実施の形態にかかる半導体部品１の実装方法について説明する。 Embodiment 2
In the present embodiment, the drum-shaped solder bump 6 is formed of high-temperature solder having a high melting point. Specifically, the melting point of the drum-like solder bump 6 is higher than the melting point of the solder paste 14 that connects the drum-like solder bump 6 and the pad 13 of the circuit board 12. Also in this embodiment, the semiconductor device and the semiconductor component 1 have the same configuration as that shown in FIGS. The semiconductor component 1 is manufactured in the same manner as in the first embodiment using high temperature solder. Note that the description common to Embodiment 1 is omitted or simplified as appropriate. Here, a mounting method of the semiconductor component 1 according to the present embodiment will be described.

本実施の形態にかかる半導体部品１を回路基板１２に実装する際、回路基板１２の上面側に形成されたパッド１３上にあらかじめはんだペースト１４を塗布する。実施の形態１と同様、パッド１３の上に、鼓状はんだバンプ６を配置し、位置合わせする。そして、鼓状はんだバンプ６とはんだペースト１４を接触させる。次に、リフローを行うが、その温度を鼓状はんだバンプ６が溶融する温度よりも低く、はんだペースト１４が溶融する温度よりも高く設定する。すなわち、温度を鼓状はんだバンプ６の融点よりも低く、はんだペースト１４の融点よりも高く設定する。そして、はんだペースト１４を溶融させて、鼓状はんだバンプ６とパッド１３とを接続させる。これにより、元の形状を保ったまま鼓状はんだバンプ６を回路基板１２に実装することができる。   When the semiconductor component 1 according to the present embodiment is mounted on the circuit board 12, the solder paste 14 is applied in advance on the pads 13 formed on the upper surface side of the circuit board 12. Similar to the first embodiment, the drum-like solder bumps 6 are arranged on the pads 13 and aligned. Then, the drum-like solder bump 6 and the solder paste 14 are brought into contact with each other. Next, reflow is performed, and the temperature is set lower than the temperature at which the drum-shaped solder bumps 6 are melted and higher than the temperature at which the solder paste 14 is melted. That is, the temperature is set lower than the melting point of the drum-like solder bump 6 and higher than the melting point of the solder paste 14. Then, the solder paste 14 is melted to connect the drum-like solder bumps 6 and the pads 13. Thereby, the drum-like solder bump 6 can be mounted on the circuit board 12 while maintaining the original shape.

本実施の形態によっても、実施の形態１と同様の効果を奏することができる。また、実施の形態１では、半導体部品１の重量が重い場合や、搭載された鼓状はんだバンプ６の数が少ない場合、回路基板１２に実装した時に、半導体部品１の自重に耐え切れず、鼓状はんだバンプ６が元の鼓形状を保つことができない可能性がある。本実施の形態では、融点の高い高温はんだを用いることにより、リフロー時に鼓状はんだバンプ６は溶融しない。これにより、回路基板１２に実装した後も元の形状を保つようにしている。なお、本発明は上記実施の形態に限られたものではなく、趣旨を逸脱しない範囲で適宜変更することが可能である。   Also according to the present embodiment, the same effect as in the first embodiment can be obtained. Further, in the first embodiment, when the weight of the semiconductor component 1 is heavy or when the number of mounted drum-like solder bumps 6 is small, the semiconductor component 1 cannot withstand its own weight when mounted on the circuit board 12, There is a possibility that the drum-shaped solder bumps 6 cannot maintain the original drum shape. In this embodiment, by using a high-temperature solder having a high melting point, the drum-like solder bumps 6 are not melted during reflow. Thus, the original shape is maintained after being mounted on the circuit board 12. Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

１ 半導体部品、２ 半導体チップ、３ マウント材、４ モールド樹脂、５ 基板、
６ 鼓状はんだバンプ、７ ボンディングワイヤ、８ パッド、９ パッド、
１０ 電気配線、１１ ビア、１２ 回路基板、１３ パッド、１４ はんだペースト、
２０ 円柱状はんだバンプ、２１ 基板支持台、２２ 回路基板、２２ａ パッド、
３０ はんだバンプ、３１ コア材を含むはんだバンプ、４０ はんだバンプ、
４１ 接合部 1 semiconductor component, 2 semiconductor chip, 3 mounting material, 4 mold resin, 5 substrate,
6 drum-shaped solder bumps, 7 bonding wires, 8 pads, 9 pads,
10 electrical wiring, 11 vias, 12 circuit board, 13 pads, 14 solder paste,
20 cylindrical solder bumps, 21 substrate support, 22 circuit board, 22a pad,
30 solder bumps, 31 solder bumps including core material, 40 solder bumps,
41 joints

Claims (7)

パッドと接続する前の半導体部品であって、
前記パッドと接続可能であり、前記パッドとの接続面から当該接続面近傍の側面までの角度が鋭角であるバンプを有する半導体部品。 A semiconductor component before connecting to the pad,
A semiconductor component having a bump that is connectable to the pad and has an acute angle from a connection surface with the pad to a side surface near the connection surface. 前記バンプは、鼓状であることを特徴とする請求項１に記載の半導体部品。   The semiconductor component according to claim 1, wherein the bump has a drum shape. 半導体部品のバンプをパッドとの接続面から当該接続面近傍の側面までの角度が鋭角となるように形成し、
前記バンプと前記パッドとを接続する半導体装置の製造方法。 Form the bump of the semiconductor component so that the angle from the connection surface with the pad to the side surface in the vicinity of the connection surface becomes an acute angle,
A method of manufacturing a semiconductor device for connecting the bump and the pad. 前記バンプの形成では、鼓状のバンプを形成することを特徴とする請求項３に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 3, wherein in forming the bumps, drum-shaped bumps are formed. 前記バンプの形成では、前記バンプの逆型を有する鋳型に溶融させたはんだを流し込み、前記はんだを凝固させる請求項３又は４に記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 3, wherein in forming the bump, molten solder is poured into a mold having a reverse mold of the bump to solidify the solder. 前記バンプの形成では、球状のはんだボールに機械的圧力を加えて加工する請求項３又は４に記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 3, wherein the bumps are formed by applying mechanical pressure to a spherical solder ball. 前記バンプと前記パッドとの接続では、前記バンプよりも融点が低いはんだペーストを介して、前記バンプと前記パッドとを対向配置させ、
前記バンプの融点よりも低く、前記はんだペーストの融点よりも高い温度で前記はんだペーストを溶融させて、前記バンプと前記パッドとを接続する請求項３乃至６のいずれか１項に記載の半導体装置の製造方法。 In the connection between the bump and the pad, the bump and the pad are arranged to face each other through a solder paste having a melting point lower than that of the bump.
7. The semiconductor device according to claim 3, wherein the solder paste is melted at a temperature lower than the melting point of the bump and higher than the melting point of the solder paste to connect the bump and the pad. Manufacturing method.
JP2009067759A 2009-03-19 2009-03-19 Semiconductor component and method of manufacturing semiconductor device Pending JP2010225598A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019062009A (en) * 2017-09-25 2019-04-18 新光電気工業株式会社 Wiring board device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019062009A (en) * 2017-09-25 2019-04-18 新光電気工業株式会社 Wiring board device
JP7002263B2 (en) 2017-09-25 2022-01-20 新光電気工業株式会社 Wiring board equipment
US11749590B2 (en) 2017-09-25 2023-09-05 Shinko Electric Industries Co., Ltd. Wiring substrate device

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