JP2011066091A - Imaging unit - Google Patents

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JP2011066091A
JP2011066091A JP2009213779A JP2009213779A JP2011066091A JP 2011066091 A JP2011066091 A JP 2011066091A JP 2009213779 A JP2009213779 A JP 2009213779A JP 2009213779 A JP2009213779 A JP 2009213779A JP 2011066091 A JP2011066091 A JP 2011066091A
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solid
circuit board
state imaging
imaging device
holes
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Kiyoshi Tosaka
清 登坂
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Olympus Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To reduce warpage of a solid-state imaging element by suppressing difference in thermal contraction between a circuit board after mounting and the solid-state imaging element. <P>SOLUTION: An imaging unit 1 includes a solid-state imaging element 2, a circuit board 3, and a corrective substrate 7. In the solid-state imaging element 2, a plurality of through-holes 2d are formed outside a light receiving part 2a. On the circuit board 3, an opening part 3a corresponding to the light receiving part 2a and a plurality of substrate through-holes 3b corresponding to the plurality of through-holes 2d are formed, and the solid-state imaging element 2 is mounted with the light receiving part 2a and the opening part 3a being faced to each other. A plurality of engagement pins 7a which penetrate a pair of through-hole 2d and the substrate through-hole 3b are fixed to the corrective substrate 7. The corrective substrate 7 has a high rigidity against thermal contraction force of the circuit board 3, for correcting warpage of the solid-state imaging element 2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、CCDまたはCMOS等の固体撮像素子を備えた撮像ユニットに関し、特に、ベアチップ状態の固体撮像素子の反りを低減可能な撮像ユニットに関するものである。   The present invention relates to an imaging unit including a solid-state imaging device such as a CCD or a CMOS, and more particularly to an imaging unit capable of reducing warpage of a solid-state imaging device in a bare chip state.

従来から、デジタルカメラおよびデジタルビデオカメラを始め、被検体の臓器内部を観察するための内視鏡、撮像機能を備えた携帯電話機など、各種態様の電子撮像装置が登場している。電子撮像装置は、CCDまたはCMOSイメージセンサ等の固体撮像素子を備えた撮像ユニットを内蔵し、レンズ等の光学系によって固体撮像素子の受光部に被写体の光学像を結像し、この固体撮像素子の光電変換処理によって被写体の画像データを撮像する。   2. Description of the Related Art Conventionally, various types of electronic imaging devices such as a digital camera and a digital video camera, an endoscope for observing the inside of an organ of a subject, and a mobile phone having an imaging function have appeared. An electronic imaging device includes an imaging unit including a solid-state imaging device such as a CCD or CMOS image sensor, and forms an optical image of a subject on a light-receiving portion of the solid-state imaging device by an optical system such as a lens. The image data of the subject is picked up by the photoelectric conversion process.

このような撮像ユニットの固体撮像素子は、一般に、受光部側のサブストレートに形成された複数の電極パッド上に金属バンプが各々固定されたベアチップ状態の素子であり、加熱処理等によって回路基板上にフリップチップ実装され、このような各金属バンプ等を介して回路基板の回路配線と電気的に接続される。また、この固体撮像素子を実装後の回路基板には、この固体撮像素子の受光部を覆うようにカバーガラスが接着剤等によって取り付けられる。この結果、回路基板上の固体撮像素子の受光部は、このカバーガラスの内側に封止される。   A solid-state image sensor of such an image pickup unit is generally a bare chip state element in which metal bumps are respectively fixed on a plurality of electrode pads formed on a substrate on the light receiving unit side, and is heated on a circuit board by a heat treatment or the like. Are flip-chip mounted and electrically connected to the circuit wiring of the circuit board through the metal bumps. Further, a cover glass is attached to the circuit board after mounting the solid-state imaging element with an adhesive or the like so as to cover the light receiving portion of the solid-state imaging element. As a result, the light receiving portion of the solid-state image sensor on the circuit board is sealed inside the cover glass.

一方、金属等の導電性を有するダイパッドおよびリードが一体化されたリードフレームが形成され、このダイパッドに半導体チップをダイボンディングし、このダイパッド上の半導体チップとリードフレームのリードとをワイヤボンディングによって電気的に接続し、その後、熱可塑性を有するプラスチックから構成されたベースによって、この半導体チップをパッケージングした態様の半導体装置もある(例えば、特許文献1参照)。   On the other hand, a lead frame in which a die pad having conductivity such as metal and a lead are integrated is formed, a semiconductor chip is die-bonded to the die pad, and the semiconductor chip on the die pad and the lead of the lead frame are electrically connected by wire bonding. There is also a semiconductor device in which this semiconductor chip is packaged by a base that is connected to each other and then formed of a thermoplastic plastic (see, for example, Patent Document 1).

特開2005−93590号公報JP 2005-93590 A

ところで、フリップチップ実装等の実装技術によって回路基板に固体撮像素子を実装した場合、または銀ペースト材等の熱硬化型接着剤を用いて回路基板に固体撮像素子を実装した場合、この実装工程における加熱処理によって、回路基板および固体撮像素子は、共に熱膨張しつつ接合される。その後、このような接合状態の回路基板および固体撮像素子は、常温まで温度低下しつつ、共に熱収縮する。しかしながら、このような回路基板および固体撮像素子の間には熱膨張係数に差があるため、これら両者の熱収縮に差が生じ、これに起因して、実装後の固体撮像素子に反りが発生するという問題点がある。   By the way, when a solid-state image sensor is mounted on a circuit board by a mounting technique such as flip-chip mounting, or when a solid-state image sensor is mounted on a circuit board using a thermosetting adhesive such as a silver paste material, By the heat treatment, the circuit board and the solid-state imaging element are joined together while thermally expanding. Thereafter, the circuit board and the solid-state imaging device in such a bonded state are both thermally contracted while the temperature is lowered to room temperature. However, there is a difference in thermal expansion coefficient between such a circuit board and a solid-state image sensor, resulting in a difference in thermal contraction between the two, resulting in warping of the solid-state image sensor after mounting. There is a problem of doing.

なお、上述した固体撮像素子の反りは、固体撮像素子の受光部の平坦性を損なって被写体に焦点を合わせ難くなる等の固体撮像素子の撮像機能低下を招来する可能性がある。また、このような固体撮像素子の反りに起因する問題は、固体撮像素子の大型化および薄型化に伴って一層顕著になる。   Note that the above-described warpage of the solid-state imaging device may cause a reduction in imaging function of the solid-state imaging device, such as impairing the flatness of the light receiving unit of the solid-state imaging device and making it difficult to focus on the subject. In addition, problems caused by such warpage of the solid-state imaging device become more conspicuous as the solid-state imaging device becomes larger and thinner.

本発明は、上記事情に鑑みてなされたものであって、実装後の回路基板と固体撮像素子との熱収縮差を抑制して固体撮像素子の反りを低減することができる撮像ユニットを提供することを目的とする。   The present invention has been made in view of the above circumstances, and provides an imaging unit capable of reducing the warp of the solid-state imaging device by suppressing the thermal contraction difference between the mounted circuit board and the solid-state imaging device. For the purpose.

上述した課題を解決し、目的を達成するために、本発明にかかる撮像ユニットは、受光部の外側に複数の貫通孔が形成された固体撮像素子と、前記受光部に対応する開口部と複数の前記貫通孔に対応する複数の基板貫通孔とが形成され、前記受光部と前記開口部とを対向させて前記固体撮像素子を実装する回路基板と、一対の前記貫通孔と前記基板貫通孔とを貫通する棒状部材が複数固定され、前記回路基板の熱収縮力に比して強い剛性を有して前記固体撮像素子の反りを補正する補正基板と、を備えたことを特徴とする。   In order to solve the above-described problems and achieve the object, an imaging unit according to the present invention includes a solid-state imaging device in which a plurality of through holes are formed outside a light receiving unit, an opening corresponding to the light receiving unit, and a plurality of openings. A plurality of substrate through-holes corresponding to the through-holes, a circuit board on which the solid-state imaging device is mounted with the light receiving portion and the opening facing each other, a pair of the through-holes and the substrate through-holes A plurality of rod-like members that pass through the substrate, and a correction substrate that has a rigidity higher than the thermal contraction force of the circuit board and corrects the warp of the solid-state imaging device.

また、本発明にかかる撮像ユニットは、上記の発明において、前記棒状部材は、前記回路基板の熱収縮力に抗して一対の前記貫通孔と前記基板貫通孔との相対位置関係を維持することを特徴とする。   In the imaging unit according to the present invention as set forth in the invention described above, the rod-shaped member maintains a relative positional relationship between the pair of through holes and the substrate through holes against the heat shrinkage force of the circuit board. It is characterized by.

また、本発明にかかる撮像ユニットは、上記の発明において、前記補正基板は、複数の前記貫通孔に複数の前記棒状部材を圧入貫通して前記固体撮像素子を相対的に固定することを特徴とする。   Moreover, the imaging unit according to the present invention is characterized in that, in the above invention, the correction substrate press-penetrates the plurality of rod-shaped members into the plurality of through holes and relatively fixes the solid-state imaging device. To do.

また、本発明にかかる撮像ユニットは、上記の発明において、前記補正基板と前記固体撮像素子との熱膨張係数差は、前記固体撮像素子と前記回路基板との熱膨張係数差に比して小さいことを特徴とする。   In the imaging unit according to the present invention, in the above invention, a difference in thermal expansion coefficient between the correction substrate and the solid-state imaging element is smaller than a difference in thermal expansion coefficient between the solid-state imaging element and the circuit board. It is characterized by that.

また、本発明にかかる撮像ユニットは、上記の発明において、前記補正基板の熱膨張係数は、前記固体撮像素子の熱膨張係数と同じであることを特徴とする。   In the imaging unit according to the present invention, the thermal expansion coefficient of the correction substrate is the same as the thermal expansion coefficient of the solid-state imaging device.

また、本発明にかかる撮像ユニットは、上記の発明において、前記補正基板の熱膨張係数は、前記回路基板の熱膨張係数に比して小さいことを特徴とする。   In the imaging unit according to the present invention as set forth in the invention described above, the coefficient of thermal expansion of the correction board is smaller than the coefficient of thermal expansion of the circuit board.

また、本発明にかかる撮像ユニットは、上記の発明において、複数の前記基板貫通孔に対応する複数の嵌合孔が形成され、複数の前記基板貫通孔を貫通して突き出た複数の前記棒状部材を複数の前記嵌合孔に嵌合固定することによって前記補正基板および複数の前記棒状部材を含む立体構造を形成して、前記補正基板による前記固体撮像素子の反りの補正を支援する支援部材をさらに備えたことを特徴とする。   Further, in the imaging unit according to the present invention, in the above invention, the plurality of rod-shaped members that are formed with a plurality of fitting holes corresponding to the plurality of substrate through-holes and project through the plurality of substrate through-holes. A support member that supports the correction of the warp of the solid-state imaging device by the correction substrate by forming a three-dimensional structure including the correction substrate and the plurality of rod-shaped members by fitting and fixing the plurality of fitting holes into the plurality of fitting holes. It is further provided with a feature.

また、本発明にかかる撮像ユニットは、上記の発明において、前記支援部材は、前記回路基板の開口部を閉塞する透光性部材であることを特徴とする。   In the imaging unit according to the present invention as set forth in the invention described above, the support member is a translucent member that closes an opening of the circuit board.

また、本発明にかかる撮像ユニットは、上記の発明において、前記支援部材は、前記回路基板の開口部に連通する開口部が形成された枠体であることを特徴とする。   In the imaging unit according to the present invention as set forth in the invention described above, the support member is a frame having an opening communicating with the opening of the circuit board.

また、本発明にかかる撮像ユニットは、上記の発明において、前記棒状部材は、前記回路基板および前記固体撮像素子がともに熱膨張した際に一対の前記貫通孔と前記基板貫通孔とを貫通することを特徴とする。   In the imaging unit according to the present invention, in the above invention, the rod-shaped member penetrates the pair of through holes and the substrate through holes when both the circuit board and the solid-state imaging element are thermally expanded. It is characterized by.

また、本発明にかかる撮像ユニットは、上記の発明において、前記棒状部材は、前記回路基板および前記固体撮像素子が熱膨張する以前に一対の前記貫通孔と前記基板貫通孔とを貫通することを特徴とする。   In the imaging unit according to the present invention, in the above invention, the rod-shaped member may pass through the pair of through holes and the substrate through holes before the circuit board and the solid-state imaging element are thermally expanded. Features.

また、本発明にかかる撮像ユニットは、上記の発明において、前記固体撮像素子は、前記受光部の外側に、前記回路基板と電気的に接続される複数の突起電極を備え、複数の前記貫通孔は、複数の前記突起電極の外側に形成されることを特徴とする。   In the imaging unit according to the present invention, in the above invention, the solid-state imaging device includes a plurality of protruding electrodes that are electrically connected to the circuit board on the outside of the light receiving unit, and a plurality of the through holes. Is formed outside the plurality of protruding electrodes.

本発明にかかる撮像ユニットでは、受光部の外側に複数の貫通孔が形成された固体撮像素子を、前記受光部に対応する開口部と複数の前記貫通孔に対応する複数の基板貫通孔とが形成された回路基板に前記受光部と前記開口部とを対向させて実装し、一対の前記貫通孔と前記基板貫通孔とを貫通する棒状部材が複数固定され、前記回路基板の熱収縮力に比して強い剛性を有する補正基板によって、前記固体撮像素子の反りを補正している。このため、実装後の回路基板と固体撮像素子との熱収縮差を抑制して固体撮像素子の反りを低減することができるという効果を奏する。   In the imaging unit according to the present invention, the solid-state imaging device in which a plurality of through holes are formed outside the light receiving unit includes an opening corresponding to the light receiving unit and a plurality of substrate through holes corresponding to the plurality of through holes. The light receiving portion and the opening are mounted to face each other on the formed circuit board, and a plurality of rod-shaped members that pass through the pair of through holes and the substrate through holes are fixed. The warpage of the solid-state imaging device is corrected by a correction substrate having a relatively high rigidity. For this reason, the effect that the curvature of a solid-state image sensor can be reduced by suppressing the thermal contraction difference between the circuit board after mounting and the solid-state image sensor is produced.

図1は、本発明の実施の形態1にかかる撮像ユニットの一構成例を示す断面模式図である。FIG. 1 is a schematic cross-sectional view illustrating a configuration example of an imaging unit according to the first embodiment of the present invention. 図2は、本発明の実施の形態1にかかる撮像ユニットの製造方法の一例を示すフローチャートである。FIG. 2 is a flowchart illustrating an example of a manufacturing method of the imaging unit according to the first embodiment of the present invention. 図3は、補正基板に固体撮像素子と回路基板とカバーガラスとを順次取り付ける状態を示す模式図である。FIG. 3 is a schematic diagram illustrating a state in which the solid-state imaging device, the circuit board, and the cover glass are sequentially attached to the correction substrate. 図4は、回路基板に固体撮像素子をフリップチップ実装する状態を示す模式図である。FIG. 4 is a schematic diagram showing a state in which a solid-state imaging device is flip-chip mounted on a circuit board. 図5は、固体撮像素子をフリップチップ実装した回路基板にカバーガラスを取り付ける状態を示す模式図である。FIG. 5 is a schematic diagram showing a state in which a cover glass is attached to a circuit board on which a solid-state imaging device is flip-chip mounted. 図6は、補正基板によって固体撮像素子の反りを低減する状態を示す模式図である。FIG. 6 is a schematic diagram illustrating a state in which the warpage of the solid-state imaging device is reduced by the correction substrate. 図7は、本発明の実施の形態2にかかる撮像ユニットの一構成例を示す断面模式図である。FIG. 7 is a schematic cross-sectional view illustrating a configuration example of an imaging unit according to the second embodiment of the present invention. 図8は、本発明の実施の形態2にかかる撮像ユニットの製造方法の一例を示すフローチャートである。FIG. 8 is a flowchart illustrating an example of a manufacturing method of the imaging unit according to the second embodiment of the present invention. 図9は、熱膨張状態の固体撮像素子に補正基板を取り付ける状態を示す模式図である。FIG. 9 is a schematic diagram illustrating a state in which the correction substrate is attached to the solid-state imaging device in a thermal expansion state. 図10は、本発明の実施の形態3にかかる撮像ユニットの一構成例を示す断面模式図である。FIG. 10 is a schematic cross-sectional view illustrating a configuration example of an imaging unit according to the third embodiment of the present invention. 図11は、本発明の実施の形態3にかかる撮像ユニットの製造方法の一例を示すフローチャートである。FIG. 11 is a flowchart illustrating an example of a manufacturing method of the imaging unit according to the third embodiment of the present invention. 図12は、補正基板に固体撮像素子と回路基板と枠体とを順次取り付ける状態を示す模式図である。FIG. 12 is a schematic diagram showing a state in which the solid-state imaging device, the circuit board, and the frame are sequentially attached to the correction board. 図13は、補正基板および枠体を含む立体構造体によって固体撮像素子の反りを低減する状態を示す模式図である。FIG. 13 is a schematic diagram illustrating a state in which the warpage of the solid-state imaging device is reduced by the three-dimensional structure including the correction substrate and the frame.

以下に、本発明にかかる撮像ユニットの実施の形態を図面に基づいて詳細に説明する。なお、以下では、本発明にかかる撮像ユニットの一例として、回路基板にフリップチップ実装した固体撮像素子を備える撮像ユニットを例示するが、この実施の形態によって本発明が限定されるものではない。   Hereinafter, embodiments of an imaging unit according to the present invention will be described in detail with reference to the drawings. Hereinafter, as an example of the imaging unit according to the present invention, an imaging unit including a solid-state imaging device flip-chip mounted on a circuit board is illustrated, but the present invention is not limited to this embodiment.

(実施の形態1)
図1は、本発明の実施の形態1にかかる撮像ユニットの一構成例を示す断面模式図である。図1に示すように、この実施の形態1にかかる撮像ユニット1は、被写体の画像を撮像する固体撮像素子2と、固体撮像素子2をフリップチップ実装する回路基板3と、固体撮像素子2と回路基板3との実装強度を補強する接着剤4と、回路基板3にフリップチップ実装された固体撮像素子2を封止するカバーガラス5と、回路基板3にカバーガラス5を接着する接着剤6と、固体撮像素子2の反りを補正する補正基板7とを備える。
(Embodiment 1)
FIG. 1 is a schematic cross-sectional view illustrating a configuration example of an imaging unit according to the first embodiment of the present invention. As shown in FIG. 1, the imaging unit 1 according to the first embodiment includes a solid-state imaging device 2 that captures an image of a subject, a circuit board 3 on which the solid-state imaging device 2 is flip-chip mounted, a solid-state imaging device 2, and the like. An adhesive 4 for reinforcing the mounting strength with the circuit board 3, a cover glass 5 for sealing the solid-state imaging device 2 flip-chip mounted on the circuit board 3, and an adhesive 6 for bonding the cover glass 5 to the circuit board 3 And a correction substrate 7 that corrects the warpage of the solid-state imaging device 2.

固体撮像素子2は、CCDまたはCMOSイメージセンサ等に例示されるベアチップ状の半導体素子であり、被写体からの光を受光してこの被写体の画像を撮像する撮像機能を有する。具体的には、固体撮像素子2は、サブストレート等のチップ基板上に、被写体からの光を受光する受光部2aと、撮像動作を実行するための駆動回路が形成された駆動回路部2bと、駆動回路部2bと電気的に接続された複数の突起電極2cとを備える。また、固体撮像素子2は、補正基板7の嵌合ピン7aを圧入する貫通孔2dが複数形成される。   The solid-state imaging device 2 is a bare chip-shaped semiconductor device exemplified by a CCD or CMOS image sensor and has an imaging function of receiving light from a subject and capturing an image of the subject. Specifically, the solid-state imaging device 2 includes a light receiving unit 2a that receives light from a subject on a chip substrate such as a substrate, and a drive circuit unit 2b in which a drive circuit for performing an imaging operation is formed. And a plurality of protruding electrodes 2c electrically connected to the drive circuit portion 2b. Further, the solid-state imaging device 2 is formed with a plurality of through holes 2d into which the fitting pins 7a of the correction substrate 7 are press-fitted.

受光部2aは、格子形状等の所定の形状に配置される画素群およびカラーフィルタ等を用いて実現され、固体撮像素子2のチップ基板上に形成される。駆動回路部2bは、この受光部2aの周辺に形成される。複数の突起電極2cの各々は、固体撮像素子2のチップ基板に形成された配線(図示せず)を介して駆動回路部2bと電気的に接続された複数の電極パッドの各々に形成される。これら複数の突起電極2cを接続する複数の電極パッドは、駆動回路部2bの周辺(例えば対向する2辺または4辺)に形成される。   The light receiving unit 2a is realized using a pixel group and a color filter that are arranged in a predetermined shape such as a lattice shape, and is formed on the chip substrate of the solid-state imaging device 2. The drive circuit unit 2b is formed around the light receiving unit 2a. Each of the plurality of protruding electrodes 2c is formed on each of a plurality of electrode pads that are electrically connected to the drive circuit unit 2b via wiring (not shown) formed on the chip substrate of the solid-state imaging device 2. . A plurality of electrode pads that connect the plurality of protruding electrodes 2c are formed around the drive circuit portion 2b (for example, two or four sides facing each other).

なお、突起電極2cは、ワイヤボンディング方式によって形成された金または銅等のスタッドバンプであってもよいし、めっき方式によって形成された金、銀、銅、インジウムまたは半田等の金属バンプであってもよい。また、突起電極2cは、金属ボールまたは表面に金属めっきを施した樹脂ボールであってもよいし、印刷等によってパターン形成された導電性接着剤であってもよい。   The protruding electrode 2c may be a gold or copper stud bump formed by a wire bonding method, or a metal bump such as gold, silver, copper, indium or solder formed by a plating method. Also good. In addition, the protruding electrode 2c may be a metal ball or a resin ball having a surface plated with metal, or may be a conductive adhesive patterned by printing or the like.

貫通孔2dは、上述したように補正基板7の嵌合ピン7aを圧入するためのものであり、固体撮像素子2の受光部2aの外側に複数形成される。詳細には、複数の貫通孔2dは、受光部2aの外側に配置された複数の突起電極2cの外側に形成される。この場合、これら複数の貫通孔2dは、図1に示すように、突起電極2cと固体撮像素子2の外縁部との間に形成されることが望ましい。何故ならば、このような位置に複数の貫通孔2dが形成されることによって、回路基板3の熱変形(特に熱収縮)の影響を受け易い固体撮像素子2の部位に補正基板7の複数の嵌合ピン7aを圧入することができ、これによって、回路基板3の熱変形による固体撮像素子2の反りを低減し易くなるからである。   As described above, the through holes 2d are for press-fitting the fitting pins 7a of the correction substrate 7, and a plurality of the through holes 2d are formed outside the light receiving portion 2a of the solid-state imaging device 2. Specifically, the plurality of through holes 2d are formed outside the plurality of protruding electrodes 2c disposed outside the light receiving portion 2a. In this case, it is desirable that the plurality of through holes 2d be formed between the protruding electrode 2c and the outer edge portion of the solid-state imaging device 2 as shown in FIG. This is because a plurality of through-holes 2d are formed at such positions, so that a plurality of correction substrates 7 on a portion of the solid-state imaging device 2 that is easily affected by thermal deformation (particularly thermal contraction) of the circuit board 3 are provided. This is because the fitting pin 7a can be press-fitted, and this makes it easy to reduce the warpage of the solid-state imaging device 2 due to thermal deformation of the circuit board 3.

上述したような構成を有する固体撮像素子2は、図1に示すように、回路基板3の開口部3aと受光部2aとを対向させて回路基板3上にフリップチップ実装される。このフリップチップ実装によって、固体撮像素子2の複数の突起電極2cは、回路基板3の回路配線(図示せず)と電気的に接続される。このように回路基板3に実装された固体撮像素子2において、受光部2aは、後述するカバーガラス5等を介して被写体からの光を受光し、この受光した光を光電変換処理する。駆動回路部2bは、受光部2aによって光電変換処理された信号をもとに被写体の画像信号を生成し、この生成した画像信号を複数の突起電極2cを介して回路基板3側に出力する。   As shown in FIG. 1, the solid-state imaging device 2 having the above-described configuration is flip-chip mounted on the circuit board 3 with the opening 3 a and the light receiving part 2 a of the circuit board 3 facing each other. By this flip chip mounting, the plurality of protruding electrodes 2 c of the solid-state imaging device 2 are electrically connected to circuit wiring (not shown) of the circuit board 3. In the solid-state imaging device 2 mounted on the circuit board 3 in this way, the light receiving unit 2a receives light from the subject via a cover glass 5 or the like described later, and performs photoelectric conversion processing on the received light. The drive circuit unit 2b generates an image signal of the subject based on the signal subjected to the photoelectric conversion process by the light receiving unit 2a, and outputs the generated image signal to the circuit board 3 side through the plurality of protruding electrodes 2c.

回路基板3は、上述した固体撮像素子2の撮像機能を実現するための回路がパターン形成された単層構造または多層構造の回路基板である。具体的には、図1に示すように、回路基板3には、上述した固体撮像素子2の受光部2aに対応する開口部3aと複数の貫通孔2dに対応する複数の基板貫通孔3bとが形成される。また、回路基板3は、このようなパターン形成された回路と固体撮像素子2の突起電極2cとを電気的に接続するための複数の電極パッド(図示せず)を有する。   The circuit board 3 is a circuit board having a single layer structure or a multilayer structure in which a circuit for realizing the imaging function of the solid-state imaging device 2 described above is patterned. Specifically, as shown in FIG. 1, the circuit board 3 includes an opening 3 a corresponding to the light receiving portion 2 a of the solid-state imaging element 2 and a plurality of substrate through holes 3 b corresponding to the plurality of through holes 2 d. Is formed. In addition, the circuit board 3 has a plurality of electrode pads (not shown) for electrically connecting such a pattern-formed circuit and the protruding electrode 2 c of the solid-state imaging device 2.

開口部3aは、固体撮像素子2の受光部2aに対応して設計された開口寸法を有し、この受光部2aに対する被写体からの光の入射を可能にする。複数の基板貫通孔3bは、上述した固体撮像素子2に形成された複数の貫通孔2dと対を成して補正基板7の複数の嵌合ピン7aを貫入する貫通孔である。これら複数の基板貫通孔3bの各々は、例えば図1に示すように、開口部3aの外側に形成された電極パッド(図示せず)の外側であって、回路基板3にフリップチップ実装された状態の固体撮像素子2の各貫通孔2dに対向する位置に形成される。この場合、各基板貫通孔3bおよび各貫通孔2dは、互いに対向するもの同士で対を成す。なお、これら複数の基板貫通孔3bは、上述した固体撮像素子2の各貫通孔2dの場合と同様に補正基板7の各嵌合ピン7aを圧入する程度の径に形成されてもよいし、各嵌合ピン7aを摺動自在に挿入可能な程度の径に形成されてもよい。   The opening 3a has an opening dimension designed to correspond to the light receiving part 2a of the solid-state imaging device 2, and allows light from a subject to enter the light receiving part 2a. The plurality of substrate through-holes 3b are through-holes that are paired with the plurality of through-holes 2d formed in the solid-state imaging device 2 and penetrate the plurality of fitting pins 7a of the correction substrate 7. Each of the plurality of substrate through holes 3b is flip-chip mounted on the circuit board 3 on the outside of an electrode pad (not shown) formed outside the opening 3a, for example, as shown in FIG. It is formed at a position facing each through hole 2d of the solid-state imaging device 2 in the state. In this case, each substrate through-hole 3b and each through-hole 2d are paired with each other facing each other. The plurality of substrate through-holes 3b may be formed to have a diameter enough to press-fit each fitting pin 7a of the correction substrate 7 as in the case of each through-hole 2d of the solid-state imaging device 2 described above. Each fitting pin 7a may be formed to have a diameter that can be slidably inserted.

このような回路基板3には、図1に示すように、固体撮像素子2の受光部2aと開口部3aとを対向させた態様で固体撮像素子2がフリップチップ実装される。この固体撮像素子2のフリップチップ実装において、回路基板3の各電極パッド(図示せず)には、熱圧着技術または超音波接続技術等によって固体撮像素子2の各突起電極2cが各々接続される。   As shown in FIG. 1, the solid-state imaging device 2 is flip-chip mounted on the circuit board 3 in such a manner that the light receiving portion 2a and the opening 3a of the solid-state imaging device 2 face each other. In the flip-chip mounting of the solid-state image pickup device 2, each protruding electrode 2c of the solid-state image pickup device 2 is connected to each electrode pad (not shown) of the circuit board 3 by a thermocompression bonding technique or an ultrasonic connection technique. .

なお、上述した回路基板3は、外力の印加によって容易に変形可能である柔軟なフレキシブル回路基板であってもよいし、フレキシブル回路基板に比して変形し難いリジッド回路基板であってもよい。また、図1には、この実施の形態1にかかる撮像ユニット1の一部分、具体的には固体撮像素子2およびその近傍が図示されている。すなわち、上述した回路基板3の外形は、プレート状または帯状等の所望の外形に設計される。   The circuit board 3 described above may be a flexible flexible circuit board that can be easily deformed by application of an external force, or may be a rigid circuit board that is less likely to be deformed than a flexible circuit board. FIG. 1 shows a part of the imaging unit 1 according to the first embodiment, specifically, a solid-state imaging device 2 and the vicinity thereof. That is, the outer shape of the circuit board 3 described above is designed to have a desired outer shape such as a plate shape or a belt shape.

接着剤4は、上述した固体撮像素子2と回路基板3とを確実に固定するためのものである。具体的には、接着剤4は、エポキシ系、フェノール系、シリコン系、ウレタン系またはアクリル系等の絶縁性接着剤である。接着剤4は、図1に示すように、固体撮像素子2の受光部2aと回路基板3の開口部3aとの間の空隙に進入しないように、フリップチップ実装後の固体撮像素子2と回路基板3との間隙に充填される。また、接着剤4は、この回路基板3上の固体撮像素子2の周囲に沿って裾野形状を形成する状態になるまで塗布され、これによって、この固体撮像素子2と回路基板3との間隙を閉塞する。このように充填および塗布された接着剤4は、加熱処理または紫外線照射処理等によって硬化する。この結果、接着剤4は、固体撮像素子2と回路基板3とを接着して固体撮像素子2と回路基板3との実装強度、すなわち固体撮像素子2の各突起電極2cと回路基板3の各電極パッドとの接合強度を補強する。さらに、接着剤4は、このような固体撮像素子2と回路基板3との間隙を介しての受光部2aへの異物混入および不要光の入射を防止する。   The adhesive 4 is for securely fixing the solid-state imaging device 2 and the circuit board 3 described above. Specifically, the adhesive 4 is an insulating adhesive such as epoxy, phenol, silicon, urethane, or acrylic. As shown in FIG. 1, the adhesive 4 does not enter the gap between the light receiving part 2 a of the solid-state image sensor 2 and the opening 3 a of the circuit board 3, and the solid-state image sensor 2 and the circuit after flip-chip mounting. The gap with the substrate 3 is filled. Further, the adhesive 4 is applied until a skirt shape is formed along the periphery of the solid-state image pickup device 2 on the circuit board 3, whereby the gap between the solid-state image pickup device 2 and the circuit board 3 is reduced. Block. The adhesive 4 filled and applied in this way is cured by heat treatment or ultraviolet irradiation treatment. As a result, the adhesive 4 bonds the solid-state image pickup element 2 and the circuit board 3 to each other, so that the mounting strength between the solid-state image pickup element 2 and the circuit board 3, i.e., each protruding electrode 2 c of the solid-state image pickup element 2 and each circuit board 3. Reinforce the bonding strength with the electrode pad. Furthermore, the adhesive 4 prevents foreign matter from entering the light receiving unit 2a and the incidence of unnecessary light through the gap between the solid-state imaging device 2 and the circuit board 3 as described above.

なお、接着剤4は、上述した絶縁性接着剤に限定されず、異方導電性接着剤であってもよい。この場合、接着剤4は、上述した固体撮像素子2のフリップチップ実装において、固体撮像素子2と回路基板3とを接着するとともに、このフリップチップ実装された固体撮像素子2の各突起電極2cと回路基板3の各電極パッドとを各々電気的に接続する。   Note that the adhesive 4 is not limited to the insulating adhesive described above, and may be an anisotropic conductive adhesive. In this case, the adhesive 4 bonds the solid-state imaging device 2 and the circuit board 3 in the above-described flip-chip mounting of the solid-state imaging device 2, and the protruding electrodes 2 c of the flip-chip-mounted solid-state imaging device 2. The electrode pads of the circuit board 3 are electrically connected to each other.

カバーガラス5は、固体撮像素子2の受光部2aへの光透過性を損なうことなく受光部2aを封止する。具体的には、カバーガラス5は、被写体からの光、すなわち固体撮像素子2の受光部2aが受光すべき光に対して透明な板状の透光性部材であり、固体撮像素子2をフリップチップ実装した状態の回路基板3の開口部3aを閉塞する。すなわち、図1に示すように、カバーガラス5は、回路基板3の開口部3aを閉じるように接着剤6によって回路基板3に固定される。このように回路基板3上に固定されたカバーガラス5は、フリップチップ実装後の固体撮像素子2の受光部2aを内部に気密封止し、この結果、この受光部2aへの光透過性を損なうことなく、この回路基板3の開口部3a側からの異物混入を防止する。   The cover glass 5 seals the light receiving part 2a without impairing light transmittance to the light receiving part 2a of the solid-state imaging device 2. Specifically, the cover glass 5 is a plate-like translucent member that is transparent to the light from the subject, that is, the light that should be received by the light receiving portion 2a of the solid-state image sensor 2, and flips the solid-state image sensor 2 The opening 3a of the circuit board 3 in a chip-mounted state is closed. That is, as shown in FIG. 1, the cover glass 5 is fixed to the circuit board 3 by the adhesive 6 so as to close the opening 3 a of the circuit board 3. Thus, the cover glass 5 fixed on the circuit board 3 hermetically seals the light receiving portion 2a of the solid-state imaging device 2 after flip chip mounting, and as a result, the light transmission to the light receiving portion 2a is improved. Without impairing, foreign matter from the opening 3a side of the circuit board 3 is prevented.

また、カバーガラス5には、上述したように回路基板3に形成された複数の基板貫通孔3bに対応する複数の嵌合孔5aが形成される。複数の嵌合孔5aは、上述した複数の基板貫通孔3bと対を成して補正基板7の複数の嵌合ピン7aを圧入する貫通孔である。これら複数の嵌合孔5aの各々は、例えば図1に示すように、固体撮像素子2をフリップチップ実装した状態の回路基板3の各基板貫通孔3bに対向する位置に形成される。この場合、各嵌合孔5aおよび各基板貫通孔3bは、互いに対向するもの同士で対を成す。これら複数の嵌合孔5aが形成されたカバーガラス5は、上述した複数の基板貫通孔3bを貫通して突き出た複数の嵌合ピン7aを複数の嵌合孔5aに圧入して嵌合固定することによって、補正基板7および複数の嵌合ピン7aを含む立体構造を形成する。   The cover glass 5 is formed with a plurality of fitting holes 5a corresponding to the plurality of substrate through holes 3b formed in the circuit board 3 as described above. The plurality of fitting holes 5a are through holes that press-fit the plurality of fitting pins 7a of the correction board 7 in pairs with the plurality of board through holes 3b described above. Each of the plurality of fitting holes 5a is formed at a position facing each substrate through hole 3b of the circuit board 3 in a state where the solid-state imaging device 2 is flip-chip mounted, for example, as shown in FIG. In this case, each fitting hole 5a and each substrate through-hole 3b make a pair with each other facing each other. The cover glass 5 in which the plurality of fitting holes 5a are formed is fitted and fixed by press-fitting the plurality of fitting pins 7a protruding through the plurality of substrate through holes 3b described above into the plurality of fitting holes 5a. By doing so, a three-dimensional structure including the correction substrate 7 and the plurality of fitting pins 7a is formed.

なお、これら複数の嵌合孔5aは、上述した固体撮像素子2の各貫通孔2dの場合と同様に補正基板7の各嵌合ピン7aを圧入する程度の径に形成されてもよいが、接着剤6によって回路基板3とカバーガラス5とが接着される場合、上述した回路基板3の各基板貫通孔3bの場合と同様に各嵌合ピン7aを摺動自在に挿入可能な程度の径に形成されてもよい。また、これら複数の嵌合孔5aに複数の嵌合ピン7aを嵌合固定することによって回路基板3とカバーガラス5との固定が達成される場合、回路基板3とカバーガラス5との間隙には、接着剤6の代わりに、この間隙を閉塞するための封止材(シール材)を充填してもよい。一方、カバーガラス5と回路基板3とを接着する接着剤6は、エポキシ系、フェノール系、シリコン系、ウレタン系またはアクリル系等の熱硬化型接着剤であってもよいし、紫外線硬化型接着剤であってもよい。   The plurality of fitting holes 5a may be formed with a diameter enough to press-fit each fitting pin 7a of the correction substrate 7 as in the case of each through-hole 2d of the solid-state imaging device 2 described above. When the circuit board 3 and the cover glass 5 are bonded to each other by the adhesive 6, the diameter is such that each fitting pin 7a can be slidably inserted as in the case of each board through hole 3b of the circuit board 3 described above. May be formed. Further, when the circuit board 3 and the cover glass 5 are fixed by fitting and fixing the plurality of fitting pins 7a in the plurality of fitting holes 5a, the gap between the circuit board 3 and the cover glass 5 is set. May be filled with a sealing material (sealing material) for closing the gap instead of the adhesive 6. On the other hand, the adhesive 6 for bonding the cover glass 5 and the circuit board 3 may be a thermosetting adhesive such as epoxy, phenol, silicon, urethane or acrylic, or UV curable adhesive. An agent may be used.

補正基板7は、回路基板3の実装される固体撮像素子2の反りを低減するためのものである。具体的には、補正基板7は、上述した固体撮像素子2における複数の貫通孔2dと回路基板3における基板貫通孔3bとカバーガラス5における複数の嵌合孔5aとを貫通する複数の嵌合ピン7aを備える。補正基板7は、回路基板3の熱変形力(特に熱収縮力)に比して強い剛性を有する平板部材であり、図1に示すように複数の嵌合ピン7aを固体撮像素子2の複数の貫通孔2dに圧入貫通することによって、固体撮像素子2に面接触した状態で固体撮像素子2を相対的に固定する。このような補正基板7は、回路基板3の複数の基板貫通孔3bを貫通した複数の嵌合ピン7aを介して受ける回路基板3の熱収縮力に抗して平板状態を維持し、これによって、この面接触状態の固体撮像素子2の反りを補正する。   The correction board 7 is for reducing the warp of the solid-state imaging device 2 on which the circuit board 3 is mounted. Specifically, the correction substrate 7 has a plurality of fittings penetrating through the plurality of through holes 2d in the solid-state imaging device 2 described above, the substrate through holes 3b in the circuit board 3, and the plurality of fitting holes 5a in the cover glass 5. A pin 7a is provided. The correction board 7 is a flat plate member having a rigidity higher than the thermal deformation force (particularly the heat shrinkage force) of the circuit board 3, and a plurality of fitting pins 7 a are provided in the solid-state image sensor 2 as shown in FIG. 1. The solid-state image sensor 2 is relatively fixed in a state of being in surface contact with the solid-state image sensor 2 by being press-fitted into the through-hole 2d. Such a correction board 7 maintains a flat state against the thermal contraction force of the circuit board 3 received through the plurality of fitting pins 7a penetrating the plurality of board through holes 3b of the circuit board 3, thereby Then, the warpage of the solid-state imaging device 2 in the surface contact state is corrected.

嵌合ピン7aは、上述したように互いに対向するもの同士で対を成す一対の少なくとも貫通孔2dと基板貫通孔3bとを貫通する棒状部材であり、補正基板7の平板部に複数固定される。具体的には、複数の嵌合ピン7aの各々は、例えば図1に示すように、回路基板3にフリップチップ実装された状態の固体撮像素子2の各貫通孔2dに対向する位置に形成される。これら複数の嵌合ピン7aの各々は、回路基板3の熱変形力(特に熱収縮力)に比して強い剛性を有し、固体撮像素子2の各貫通孔2dと回路基板3の各基板貫通孔3bとを貫通した状態において、この回路基板3の熱収縮力に抗して一対の貫通孔2dと基板貫通孔3bとの相対位置関係を維持する。一方、基板貫通孔3bを貫通して突き出た各嵌合ピン7aは、図1に示すように、カバーガラス5の各嵌合孔5aに嵌め込まれる。このように貫通孔2dおよび基板貫通孔3bを貫通して嵌合孔5aに嵌合した複数の嵌合ピン7aは、上述したカバーガラス5および補正基板7を含む立体構造の支柱として機能する。   As described above, the fitting pins 7a are rod-like members that penetrate at least a pair of the through holes 2d and the substrate through holes 3b that are paired with each other, and are fixed to the flat plate portion of the correction substrate 7. . Specifically, each of the plurality of fitting pins 7a is formed at a position facing each through-hole 2d of the solid-state imaging device 2 in a state of being flip-chip mounted on the circuit board 3 as shown in FIG. The Each of the plurality of fitting pins 7a has a rigidity higher than the thermal deformation force (especially thermal contraction force) of the circuit board 3, and each through-hole 2d of the solid-state imaging device 2 and each board of the circuit board 3 In a state of penetrating through the through hole 3b, the relative positional relationship between the pair of through holes 2d and the substrate through hole 3b is maintained against the thermal contraction force of the circuit board 3. On the other hand, each fitting pin 7a protruding through the substrate through hole 3b is fitted into each fitting hole 5a of the cover glass 5 as shown in FIG. Thus, the plurality of fitting pins 7 a that have passed through the through-hole 2 d and the board through-hole 3 b and fitted into the fitting hole 5 a function as a three-dimensional structure column including the cover glass 5 and the correction board 7 described above.

ここで、上述した補正基板7の平板部の熱膨張係数と固体撮像素子2の熱膨張係数との差は、この固体撮像素子2と回路基板3との熱膨張係数差に比して小さく、さらには、補正基板7と固体撮像素子2との熱膨張係数差は略零値であること、すなわち、補正基板7の熱膨張係数は固体撮像素子2の熱膨張係数と同じであることが望ましい。これによって、補正基板7は、回路基板3の熱収縮に起因する固体撮像素子2の反りを許容範囲内の反りに容易に低減することができる。また、補正基板7の熱膨張係数は、回路基板3の熱膨張係数に比して小さいことが望ましい。これによって、補正基板7は、回路基板3の熱収縮に起因する固体撮像素子2の反りを許容範囲内の反りに一層容易に低減できるようになる。   Here, the difference between the thermal expansion coefficient of the flat plate portion of the correction substrate 7 and the thermal expansion coefficient of the solid-state imaging device 2 is smaller than the thermal expansion coefficient difference between the solid-state imaging device 2 and the circuit board 3. Furthermore, it is desirable that the difference in thermal expansion coefficient between the correction substrate 7 and the solid-state imaging device 2 is substantially zero, that is, the thermal expansion coefficient of the correction substrate 7 is the same as the thermal expansion coefficient of the solid-state imaging device 2. . Thereby, the correction substrate 7 can easily reduce the warpage of the solid-state imaging device 2 due to the thermal contraction of the circuit board 3 to the warpage within the allowable range. Further, it is desirable that the thermal expansion coefficient of the correction substrate 7 is smaller than the thermal expansion coefficient of the circuit board 3. As a result, the correction substrate 7 can more easily reduce the warpage of the solid-state imaging device 2 due to the thermal contraction of the circuit board 3 to the warpage within the allowable range.

なお、上述したような熱膨張係数差になる固体撮像素子2および補正基板7の材質の組み合わせとして、例えば、シリコンおよびセラミック(アルミナ等)の組み合わせ、シリコンおよびシリコンまたはセラミックおよびセラミック等の同一材質同士の組み合わせ等が挙げられる。   In addition, as a combination of the materials of the solid-state imaging device 2 and the correction substrate 7 having the difference in thermal expansion coefficient as described above, for example, a combination of silicon and ceramic (alumina or the like), or the same material such as silicon and silicon or ceramic and ceramic are used. And the like.

つぎに、本発明の実施の形態1にかかる撮像ユニット1の製造方法について説明する。図2は、本発明の実施の形態1にかかる撮像ユニットの製造方法の一例を示すフローチャートである。図3は、補正基板に固体撮像素子と回路基板とカバーガラスとを順次取り付ける状態を示す模式図である。図4は、回路基板に固体撮像素子をフリップチップ実装する状態を示す模式図である。図5は、固体撮像素子をフリップチップ実装した回路基板にカバーガラスを取り付ける状態を示す模式図である。   Next, a method for manufacturing the imaging unit 1 according to the first embodiment of the present invention will be described. FIG. 2 is a flowchart illustrating an example of a manufacturing method of the imaging unit according to the first embodiment of the present invention. FIG. 3 is a schematic diagram illustrating a state in which the solid-state imaging device, the circuit board, and the cover glass are sequentially attached to the correction substrate. FIG. 4 is a schematic diagram showing a state in which a solid-state imaging device is flip-chip mounted on a circuit board. FIG. 5 is a schematic diagram showing a state in which a cover glass is attached to a circuit board on which a solid-state imaging device is flip-chip mounted.

本発明の実施の形態1にかかる撮像ユニット1は、上述した固体撮像素子2と回路基板3とカバーガラス5と補正基板7とを撮像ユニット1の構成部品として予め準備し、接着剤4,6等を用いてこれらの各構成部品を組み合わせることによって製造される。   In the imaging unit 1 according to the first embodiment of the present invention, the solid-state imaging device 2, the circuit board 3, the cover glass 5, and the correction board 7 described above are prepared in advance as components of the imaging unit 1, and the adhesives 4, 6 Etc. are used to combine these components.

すなわち、図2に示すように、まず、補正基板7に固体撮像素子2を取り付ける(ステップS101)。このステップS101において、補正基板7は、図3に示すように、回路基板3にフリップチップ実装前であるベアチップ状態の固体撮像素子2に形成された複数の貫通孔2dに複数の嵌合ピン7aを圧入して最終的に固体撮像素子2に面接触し、この結果、固体撮像素子2を相対的に固定する。   That is, as shown in FIG. 2, first, the solid-state imaging device 2 is attached to the correction substrate 7 (step S101). In this step S101, as shown in FIG. 3, the correction board 7 has a plurality of fitting pins 7a in a plurality of through holes 2d formed in the solid-state image pickup device 2 in a bare chip state before flip chip mounting on the circuit board 3. Are finally brought into surface contact with the solid-state image sensor 2, and as a result, the solid-state image sensor 2 is relatively fixed.

つぎに、この補正基板7上の固体撮像素子2と回路基板3とを仮実装する(ステップS102)。このステップS102において、回路基板3は、図3,4に示すように、補正基板7を取り付けた後の固体撮像素子2の受光部2aと回路基板3の開口部3aとを対向させて、この固体撮像素子2の各貫通孔2dと対を成す回路基板3の各基板貫通孔3bに補正基板7の各嵌合ピン7aを貫通させる。このような各基板貫通孔3bへの各嵌合ピン7aの貫通によって、この固体撮像素子2の各突起電極2cと回路基板3の各電極パッドとの位置決めが達成され、このように位置決めされた各突起電極2cと回路基板3の各電極パッドとが接触するまで各基板貫通孔3bに各嵌合ピン7aを貫通させて、この固体撮像素子2に回路基板3を仮付けする。   Next, the solid-state imaging device 2 and the circuit board 3 on the correction substrate 7 are temporarily mounted (step S102). In this step S102, as shown in FIGS. 3 and 4, the circuit board 3 makes the light receiving portion 2a of the solid-state imaging device 2 after the correction substrate 7 is attached and the opening 3a of the circuit board 3 face each other. Each fitting pin 7a of the correction board 7 is passed through each board through hole 3b of the circuit board 3 paired with each through hole 2d of the solid-state imaging device 2. Positioning of each protruding electrode 2c of this solid-state image pickup device 2 and each electrode pad of the circuit board 3 is achieved by passing through the respective fitting pins 7a into the respective board through holes 3b. The circuit board 3 is temporarily attached to the solid-state imaging device 2 by passing the fitting pins 7a through the substrate through holes 3b until the protruding electrodes 2c come into contact with the electrode pads of the circuit board 3.

なお、このステップS102において、固体撮像素子2および回路基板3に対して押圧処理または超音波処理等をさらに行って、この回路基板3の各電極パッドに固体撮像素子2の各突起電極2cを仮接合してもよい。   In step S102, the solid-state imaging device 2 and the circuit board 3 are further subjected to a pressing process or an ultrasonic process, and the protruding electrodes 2c of the solid-state imaging element 2 are temporarily attached to the electrode pads of the circuit board 3. You may join.

その後、固体撮像素子2と回路基板3とを本実装する(ステップS103)。このステップS103において、図4に示したように補正基板7上の固体撮像素子2と回路基板3とを仮実装した仮実装体10は、リフロー炉等の所定の加熱装置に投入され、この加熱装置によって加熱処理される。この加熱処理によって、固体撮像素子2の各突起電極2cは、回路基板3の各電極パッドに溶着接合される。この結果、固体撮像素子2と回路基板3とのフリップチップ実装が真に達成され、固体撮像素子2は、回路基板3の開口部3aと受光部2aとを対向させた状態で回路基板3と電気的に接続される。   Thereafter, the solid-state imaging device 2 and the circuit board 3 are mounted on the main body (step S103). In step S103, the temporary mounting body 10 on which the solid-state imaging device 2 and the circuit board 3 on the correction substrate 7 are temporarily mounted as shown in FIG. 4 is put into a predetermined heating device such as a reflow furnace, and this heating is performed. Heat treatment is performed by the apparatus. By this heat treatment, each protruding electrode 2 c of the solid-state imaging device 2 is welded and bonded to each electrode pad of the circuit board 3. As a result, the flip-chip mounting of the solid-state imaging device 2 and the circuit board 3 is truly achieved, and the solid-state imaging device 2 is connected to the circuit board 3 with the opening 3a and the light receiving portion 2a of the circuit board 3 facing each other. Electrically connected.

ここで、この本実装後(すなわち真のフリップチップ実装後)の状態において、補正基板7の各嵌合ピン7aは、この回路基板3の熱収縮力に抗して各一対の貫通孔2dと基板貫通孔3bとの相対的位置関係を維持している。これとともに、補正基板7は、この回路基板3の熱収縮力に比して強い剛性によって固体撮像素子2の反りを補正し、この結果、この固体撮像素子2を平坦な状態に維持している。   Here, in the state after the main mounting (that is, after the true flip chip mounting), each fitting pin 7a of the correction substrate 7 is opposed to the pair of through holes 2d against the thermal contraction force of the circuit substrate 3. The relative positional relationship with the substrate through-hole 3b is maintained. At the same time, the correction substrate 7 corrects the warpage of the solid-state image sensor 2 with a rigidity higher than the thermal contraction force of the circuit board 3, and as a result, maintains the solid-state image sensor 2 in a flat state. .

つぎに、ステップS103による本実装工程後の固体撮像素子2と回路基板3との間に接着剤4を充填する(ステップS104)。このステップS104において、接着剤4は、固体撮像素子2の受光部2aと回路基板3の開口部3aとの間の空隙に進入しないように固体撮像素子2と回路基板3との間隙に充填され、その後、この固体撮像素子2と回路基板3との間隙を閉塞するまで、この回路基板3上の固体撮像素子2の周囲に沿って裾野形状に塗布される(図5参照)。この結果、固体撮像素子2の各突起電極2cと回路基板3の各電極パッドとの接合強度は、接着剤4によって補強される。なお、接着剤4は、UV照射等によって常温硬化してもよいし、加熱処理によって熱硬化してもよい。   Next, the adhesive 4 is filled between the solid-state imaging device 2 and the circuit board 3 after the main mounting process in step S103 (step S104). In this step S104, the adhesive 4 is filled in the gap between the solid-state imaging device 2 and the circuit board 3 so as not to enter the gap between the light receiving portion 2a of the solid-state imaging device 2 and the opening 3a of the circuit board 3. Then, it is applied in a skirt shape along the periphery of the solid-state image pickup device 2 on the circuit board 3 until the gap between the solid-state image pickup device 2 and the circuit board 3 is closed (see FIG. 5). As a result, the bonding strength between the protruding electrodes 2 c of the solid-state imaging device 2 and the electrode pads of the circuit board 3 is reinforced by the adhesive 4. The adhesive 4 may be cured at room temperature by UV irradiation or the like, or may be cured by heat treatment.

その後、回路基板3に本実装済みの固体撮像素子2を封止する(ステップS105)。このステップS105において、カバーガラス5は、図3,5に示すように、本実装後の回路基板3の各基板貫通孔3bを貫通して突き出た各嵌合ピン7aを各嵌合孔5aに嵌め込みつつ、この回路基板3の開口部3aを覆うように回路基板3に面接触する。この際、回路基板3とカバーガラス5との間に接着剤6を介在させ(図1参照)、この接着剤6によって回路基板3とカバーガラス5とを接着するとともに回路基板3とカバーガラス5との間隙を閉塞する。このように回路基板3に取り付けられたカバーガラス5は、固体撮像素子2の受光部2aへの光入射を可能にしつつ、内部に受光部2aを封止する。なお、回路基板3とカバーガラス5とを接着する接着剤6は、UV照射等によって常温硬化してもよいし、加熱処理によって熱硬化してもよい。   Thereafter, the solid-state imaging device 2 that has been mounted on the circuit board 3 is sealed (step S105). In this step S105, as shown in FIGS. 3 and 5, in the cover glass 5, the fitting pins 7a protruding through the board through holes 3b of the circuit board 3 after the main mounting are projected to the fitting holes 5a. While fitting, the circuit board 3 is brought into surface contact so as to cover the opening 3a of the circuit board 3. At this time, an adhesive 6 is interposed between the circuit board 3 and the cover glass 5 (see FIG. 1), and the circuit board 3 and the cover glass 5 are bonded by the adhesive 6 and the circuit board 3 and the cover glass 5 are bonded. To close the gap. The cover glass 5 attached to the circuit board 3 in this way seals the light receiving portion 2a inside while allowing light to enter the light receiving portion 2a of the solid-state imaging device 2. The adhesive 6 that bonds the circuit board 3 and the cover glass 5 may be cured at room temperature by UV irradiation or the like, or may be thermally cured by heat treatment.

上述したステップS101〜S105の各製造工程を順次行うことによって、図1に示した構成を有する撮像ユニット1を製造することができる。このように製造された撮像ユニット1は、デジタルカメラおよびデジタルビデオカメラを始め、被検体の臓器内部を観察するための内視鏡、撮像機能を備えた携帯電話機等、各種態様の電子撮像装置に内蔵することができる。   The imaging unit 1 having the configuration shown in FIG. 1 can be manufactured by sequentially performing the manufacturing steps of steps S101 to S105 described above. The imaging unit 1 manufactured in this manner is used in various types of electronic imaging devices such as a digital camera and a digital video camera, an endoscope for observing the inside of an organ of a subject, and a mobile phone having an imaging function. Can be built in.

つぎに、上述した補正基板7による固体撮像素子2の反り低減作用について説明する。図6は、補正基板によって固体撮像素子の反りを低減する状態を示す模式図である。この実施の形態1にかかる撮像ユニット1の補正基板7は、上述したように、一対の貫通孔2dと基板貫通孔3bとを貫通する嵌合ピン7aを複数備え、回路基板3の熱収縮力に比して強い剛性を有する。このような補正基板7の各嵌合ピン7aは、上述したステップS101,S102において、回路基板3および固体撮像素子2が熱膨張する以前に各一対の貫通孔2dと基板貫通孔3bとを貫通し、補正基板7は、この固体撮像素子2と面接触した状態でこの固体撮像素子2を相対的に固定する。この結果、図4に示した仮実装体10が組み立てられる。   Next, the warp reducing action of the solid-state imaging device 2 by the correction substrate 7 described above will be described. FIG. 6 is a schematic diagram illustrating a state in which the warpage of the solid-state imaging device is reduced by the correction substrate. As described above, the correction board 7 of the imaging unit 1 according to the first embodiment includes a plurality of fitting pins 7a penetrating the pair of through holes 2d and the board through holes 3b. Strong rigidity compared to Each of the fitting pins 7a of the correction board 7 passes through the pair of through holes 2d and the board through holes 3b before the circuit board 3 and the solid-state imaging device 2 are thermally expanded in the above-described steps S101 and S102. Then, the correction substrate 7 relatively fixes the solid-state image sensor 2 in a state of being in surface contact with the solid-state image sensor 2. As a result, the temporary mounting body 10 shown in FIG. 4 is assembled.

ここで、仮実装体10内の回路基板3は、上述したステップS103における加熱処理によって熱膨張し、その後、常温まで温度低下しつつ熱収縮する。この状態において、仮実装体10内の補正基板7は、図6に示すように、各嵌合ピン7aを介して回路基板3の熱膨張力F1を受け、その後、各嵌合ピン7aを介して回路基板3の熱収縮力F2を受ける。このような補正基板7は、上述したように回路基板3の熱変形力に比して強い剛性を有し、このように熱変形する回路基板3および固体撮像素子2に対して、この自身の剛性に基づいた反作用力F11,F12を作用させる。   Here, the circuit board 3 in the temporary mounting body 10 is thermally expanded by the heat treatment in step S103 described above, and then thermally contracted while the temperature is lowered to room temperature. In this state, as shown in FIG. 6, the correction board 7 in the temporary mounting body 10 receives the thermal expansion force F1 of the circuit board 3 through the fitting pins 7a, and then passes through the fitting pins 7a. The thermal contraction force F2 of the circuit board 3 is received. Such a correction board 7 has a rigidity higher than the thermal deformation force of the circuit board 3 as described above, and this correction board 7 has its own resistance to the circuit board 3 and the solid-state imaging device 2 that are thermally deformed in this way. Reaction forces F11 and F12 based on rigidity are applied.

なお、この補正基板7に発生する一方の反作用力F11は、回路基板3および固体撮像素子2の熱膨張力F1に対抗する力であり、他方の反作用力F12は、回路基板3および固体撮像素子2の熱収縮力F2に対抗する力である。   One reaction force F11 generated on the correction substrate 7 is a force that opposes the thermal expansion force F1 of the circuit board 3 and the solid-state imaging device 2, and the other reaction force F12 is the circuit substrate 3 and the solid-state imaging device. 2 is a force that opposes the thermal contraction force F2.

補正基板7は、上述した回路基板3の熱膨張力F1に対抗する反作用力F11によって、加熱処理時の回路基板3の熱膨張変形に伴う固体撮像素子2の熱膨張変形を抑制し、これによって、この固体撮像素子2の熱膨張に起因する応力を十分に吸収する。この結果、補正基板7は、このような応力によって招来される固体撮像素子2の反りを低減する。さらに、補正基板7は、上述した回路基板3の熱収縮力F2に対抗する反作用力F12によって、温度低下時の回路基板3の熱収縮変形に伴う固体撮像素子2の熱収縮変形を抑制し、これによって、この固体撮像素子2の熱収縮に起因する応力を十分に吸収する。この結果、補正基板7は、このような応力によって招来される固体撮像素子2の反りを低減する。以上のようにして、補正基板7は、加熱処理後、具体的には回路基板3へのフリップチップ実装後の固体撮像素子2の反りを補正する。このような補正基板7の作用によって、回路基板3上の固体撮像素子2は、受光部2aを平坦な状態に維持することができる。なお、このような補正基板7において、複数の嵌合ピン7aは、この回路基板3の熱膨張力F1または熱収縮力F2に抗して複数の貫通孔2dと複数の基板貫通孔3bとの各相対位置関係を対毎に維持する。   The correction substrate 7 suppresses the thermal expansion deformation of the solid-state imaging device 2 due to the thermal expansion deformation of the circuit board 3 during the heat treatment by the reaction force F11 that opposes the thermal expansion force F1 of the circuit board 3 described above. The stress resulting from the thermal expansion of the solid-state imaging device 2 is sufficiently absorbed. As a result, the correction substrate 7 reduces the warpage of the solid-state imaging device 2 caused by such stress. Furthermore, the correction substrate 7 suppresses the heat shrink deformation of the solid-state imaging device 2 due to the heat shrink deformation of the circuit board 3 when the temperature is lowered by the reaction force F12 that opposes the heat shrink force F2 of the circuit board 3 described above. As a result, the stress caused by the thermal contraction of the solid-state imaging device 2 is sufficiently absorbed. As a result, the correction substrate 7 reduces the warpage of the solid-state imaging device 2 caused by such stress. As described above, the correction substrate 7 corrects the warp of the solid-state imaging element 2 after the heat treatment, specifically, after the flip chip mounting on the circuit board 3. By such an action of the correction substrate 7, the solid-state imaging device 2 on the circuit substrate 3 can maintain the light receiving portion 2 a in a flat state. In such a correction substrate 7, the plurality of fitting pins 7 a are formed between the plurality of through holes 2 d and the plurality of substrate through holes 3 b against the thermal expansion force F 1 or the thermal contraction force F 2 of the circuit board 3. Each relative positional relationship is maintained for each pair.

なお、補正基板7は、上述した固体撮像素子2のフリップチップ実装工程後における加熱処理(例えば、接着剤4,6の熱硬化処理等)の前後においても、同様に、回路基板3の熱変形を抑制でき、この結果、この回路基板3の熱収縮に起因する固体撮像素子2の反りを低減することができる。   The correction substrate 7 is similarly subjected to thermal deformation of the circuit board 3 before and after the heat treatment (for example, thermosetting treatment of the adhesives 4 and 6) after the flip-chip mounting process of the solid-state imaging device 2 described above. As a result, the warpage of the solid-state imaging device 2 due to the thermal contraction of the circuit board 3 can be reduced.

以上、説明したように、本発明の実施の形態1では、加熱処理によって固体撮像素子を実装する回路基板の熱収縮力に比して強い剛性を有する補正基板に固定された複数の嵌合ピンをこの固体撮像素子の各貫通孔とこの回路基板の各基板貫通孔とに貫通させて、この固体撮像素子と補正基板とを相対的に固定し、この回路基板の熱収縮変形に伴う固体撮像素子の反りをこの補正基板によって補正するように構成した。このため、このような回路基板の熱収縮力に対抗する補正基板の剛性に基づく反作用力によって、回路基板の熱収縮変形に伴う固体撮像素子の熱収縮変形を抑制でき、これによって、この固体撮像素子の熱収縮に起因する応力を十分に吸収できる。この結果、加熱処理による実装後の回路基板と固体撮像素子との熱収縮差を抑制して固体撮像素子の反りを低減することができる。   As described above, in the first embodiment of the present invention, a plurality of fitting pins fixed to a correction board having rigidity higher than that of a circuit board on which a solid-state imaging device is mounted by heat treatment. Is passed through each through-hole of the solid-state imaging device and each substrate through-hole of the circuit board, the solid-state imaging device and the correction board are relatively fixed, and the solid-state imaging accompanying the thermal contraction deformation of the circuit board The warp of the element is configured to be corrected by the correction substrate. For this reason, the thermal contraction deformation of the solid-state imaging device due to the thermal contraction deformation of the circuit board can be suppressed by the reaction force based on the rigidity of the correction board, which counters the thermal contraction force of the circuit board, and thereby this solid-state imaging The stress resulting from the thermal contraction of the element can be sufficiently absorbed. As a result, the warp of the solid-state image sensor can be reduced by suppressing the thermal contraction difference between the circuit board after mounting by the heat treatment and the solid-state image sensor.

また、上述した実施の形態1では、このような補正基板の熱膨張係数と固体撮像素子の熱膨張係数との差をこの固体撮像素子と回路基板との熱膨張係数差に比して小さくし、さらに望ましくは、このような補正基板の熱膨張係数と固体撮像素子の熱膨張係数とを同等に調整している。このため、補正基板は、回路基板の熱収縮に起因する固体撮像素子の反りを許容範囲内の反りに容易に低減することができる。さらに、このような補正基板の熱膨張係数を回路基板の熱膨張係数に比して小さくすることによって、回路基板の熱収縮に起因する固体撮像素子の反りを許容範囲内の反りに一層容易に低減することができる。   In the first embodiment described above, the difference between the thermal expansion coefficient of the correction substrate and the thermal expansion coefficient of the solid-state image sensor is made smaller than the difference in thermal expansion coefficient between the solid-state image sensor and the circuit board. More preferably, the thermal expansion coefficient of the correction substrate and the thermal expansion coefficient of the solid-state imaging device are adjusted to be equal. For this reason, the correction board can easily reduce the warpage of the solid-state imaging device due to the thermal contraction of the circuit board to the warpage within the allowable range. Furthermore, by making the coefficient of thermal expansion of the correction substrate smaller than the coefficient of thermal expansion of the circuit board, the warpage of the solid-state imaging device due to the thermal contraction of the circuit board can be made easier to the warp within the allowable range. Can be reduced.

(実施の形態2)
つぎに、本発明の実施の形態2について説明する。上述した実施の形態1では、加熱処理前(すなわち熱膨張前)の回路基板3および固体撮像素子2に補正基板7の各嵌合ピン7aを貫通させていたが、この実施の形態2では、加熱処理によって熱膨張した状態の回路基板3および固体撮像素子2に補正基板7の各嵌合ピン7aを貫通させるようにしている。
(Embodiment 2)
Next, a second embodiment of the present invention will be described. In the first embodiment described above, each fitting pin 7a of the correction substrate 7 is made to penetrate the circuit board 3 and the solid-state imaging device 2 before the heat treatment (that is, before thermal expansion), but in this second embodiment, Each fitting pin 7a of the correction board 7 is made to penetrate the circuit board 3 and the solid-state imaging device 2 in a state of being thermally expanded by the heat treatment.

図7は、本発明の実施の形態2にかかる撮像ユニットの一構成例を示す断面模式図である。図7に示すように、この実施の形態2にかかる撮像ユニット21は、上述した実施の形態1にかかる撮像ユニット1の補正基板7に代えて補正基板27を備える。この補正基板27は、加熱処理によって熱膨張状態の固体撮像素子2および回路基板3に複数の嵌合ピン7aを貫通させてこの固体撮像素子2に相対的に固定される。その他の構成は実施の形態1と同じであり、同一構成部分には同一符号を付している。   FIG. 7 is a schematic cross-sectional view illustrating a configuration example of an imaging unit according to the second embodiment of the present invention. As shown in FIG. 7, the imaging unit 21 according to the second embodiment includes a correction board 27 instead of the correction board 7 of the imaging unit 1 according to the first embodiment described above. The correction substrate 27 is relatively fixed to the solid-state image pickup device 2 by passing a plurality of fitting pins 7a through the solid-state image pickup device 2 and the circuit board 3 in a thermally expanded state by heat treatment. Other configurations are the same as those of the first embodiment, and the same reference numerals are given to the same components.

補正基板27は、加熱処理によって熱膨張した状態の回路基板3上の固体撮像素子2に取り付けられ、この熱膨張状態の回路基板3の温度低下に伴う熱収縮変形に起因して発生する固体撮像素子2の反りを補正するものである。具体的には、補正基板27は、加熱処理等によって回路基板3にフリップチップ実装された際に熱膨張した状態の固体撮像素子2に合わせて構造設計される。すなわち、補正基板7の平板部の外形および寸法は、回路基板3へのフリップチップ実装のための加熱処理によって熱膨張した状態の固体撮像素子2の外形および寸法に合わせて設定される。また、複数の嵌合ピン7aは、このような加熱処理によって固体撮像素子2が熱膨張した際に変位する複数の貫通孔2dの各変位後位置に対応して補正基板27の平板部に固定配置される。なお、これら複数の嵌合ピン7aは、加熱処理によって回路基板3が熱膨張した際に変位する複数の基板貫通孔3bの各変位後位置に対応して補正基板27の平板部に固定配置されてもよい。   The correction board 27 is attached to the solid-state imaging device 2 on the circuit board 3 in a state of being thermally expanded by the heat treatment, and the solid-state imaging generated due to thermal contraction deformation accompanying the temperature drop of the circuit board 3 in the state of thermal expansion. The warping of the element 2 is corrected. Specifically, the correction substrate 27 is structurally designed in accordance with the solid-state imaging device 2 that has been thermally expanded when it is flip-chip mounted on the circuit board 3 by heat treatment or the like. That is, the outer shape and dimensions of the flat plate portion of the correction substrate 7 are set in accordance with the outer shape and dimensions of the solid-state imaging device 2 in a state of being thermally expanded by heat treatment for flip chip mounting on the circuit board 3. Further, the plurality of fitting pins 7a are fixed to the flat plate portion of the correction substrate 27 corresponding to the positions after displacement of the plurality of through holes 2d that are displaced when the solid-state imaging device 2 is thermally expanded by such heat treatment. Be placed. The plurality of fitting pins 7a are fixedly arranged on the flat plate portion of the correction board 27 corresponding to the respective positions after displacement of the plurality of board through holes 3b that are displaced when the circuit board 3 is thermally expanded by heat treatment. May be.

このような補正基板27は、熱膨張状態の固体撮像素子2の複数の貫通孔2dに複数の嵌合ピン7aを圧入することによって、固体撮像素子2に面接触した状態で固体撮像素子2を相対的に固定する。また、このような基板貫通孔3bを貫通して突き出た各嵌合ピン7aは、この固体撮像素子2をフリップチップ実装した熱膨張状態の回路基板3の複数の基板貫通孔3bを貫通する。補正基板27は、熱膨張状態の回路基板3の複数の基板貫通孔3bを貫通した複数の嵌合ピン7aを介して受ける回路基板3の熱収縮力に抗して平板状態を維持し、これによって、この面接触状態の固体撮像素子2の反りを補正する。なお、これら複数の嵌合ピン7aを含む補正基板27は、熱膨張状態の固体撮像素子2に対応して設計された構造以外、上述した実施の形態1にかかる補正基板7と同様の剛性等の機能および構造を有する。   Such a correction substrate 27 presses the solid-state image pickup device 2 in surface contact with the solid-state image pickup device 2 by press-fitting a plurality of fitting pins 7a into the plurality of through holes 2d of the solid-state image pickup device 2 in a thermally expanded state. Fix relatively. Further, each fitting pin 7a protruding through the board through hole 3b penetrates the plurality of board through holes 3b of the circuit board 3 in a thermally expanded state on which the solid-state imaging device 2 is flip-chip mounted. The correction board 27 maintains a flat state against the thermal contraction force of the circuit board 3 received through the plurality of fitting pins 7a penetrating the plurality of board through holes 3b of the circuit board 3 in the thermally expanded state. Thus, the warpage of the solid-state imaging device 2 in the surface contact state is corrected. The correction board 27 including the plurality of fitting pins 7a has the same rigidity as the correction board 7 according to the first embodiment described above, except for the structure designed for the solid-state imaging device 2 in the thermally expanded state. It has the function and structure.

つぎに、本発明の実施の形態2にかかる撮像ユニット21の製造方法について説明する。図8は、本発明の実施の形態2にかかる撮像ユニットの製造方法の一例を示すフローチャートである。図9は、熱膨張状態の固体撮像素子に補正基板を取り付ける状態を示す模式図である。本発明の実施の形態2にかかる撮像ユニット21は、上述した固体撮像素子2と回路基板3とカバーガラス5と補正基板27とを撮像ユニット21の構成部品として予め準備し、接着剤4,6等を用いてこれらの各構成部品を組み合わせることによって製造される。   Next, a method for manufacturing the imaging unit 21 according to the second embodiment of the present invention will be described. FIG. 8 is a flowchart illustrating an example of a manufacturing method of the imaging unit according to the second embodiment of the present invention. FIG. 9 is a schematic diagram illustrating a state in which the correction substrate is attached to the solid-state imaging device in a thermal expansion state. The imaging unit 21 according to the second embodiment of the present invention prepares the solid-state imaging device 2, the circuit board 3, the cover glass 5, and the correction substrate 27 in advance as components of the imaging unit 21, and adhesives 4 and 6. Etc. are used to combine these components.

すなわち、図8に示すように、まず、回路基板3に固体撮像素子2を実装する(ステップS201)。このステップS201において、回路基板3は、固体撮像素子2の受光部2aと回路基板3の開口部3aとを対向させるとともに、この固体撮像素子2の各貫通孔2dに対する各基板貫通孔3bの位置決めを対毎に行う。続いて、このような各一対の貫通孔2dと基板貫通孔3bとの位置決めが成された回路基板3と固体撮像素子2とを仮付けし、この仮付けした回路基板3と固体撮像素子2との本実装を行う。すなわち、このように互いに仮付けされた回路基板3および固体撮像素子2である仮実装体をリフロー炉等の所定の加熱装置に投入し、この加熱装置によってこの仮実装体を加熱処理する。この加熱処理によって、固体撮像素子2の各突起電極2cは、回路基板3の各電極パッドに溶着接合され、この結果、固体撮像素子2と回路基板3とのフリップチップ実装が達成される。この場合、固体撮像素子2は、回路基板3の開口部3aと受光部2aとを対向させた状態で回路基板3と電気的に接続される。   That is, as shown in FIG. 8, first, the solid-state imaging device 2 is mounted on the circuit board 3 (step S201). In this step S201, the circuit board 3 makes the light receiving portion 2a of the solid-state imaging device 2 and the opening 3a of the circuit substrate 3 face each other, and positioning each substrate through-hole 3b with respect to each through-hole 2d of the solid-state imaging device 2. For each pair. Subsequently, the circuit board 3 and the solid-state imaging device 2 in which the positioning of each pair of the through-holes 2d and the substrate through-holes 3b is temporarily attached, and the temporarily attached circuit board 3 and the solid-state imaging device 2 are temporarily attached. And this implementation. That is, the temporary mounting body which is the circuit board 3 and the solid-state imaging device 2 temporarily attached to each other in this manner is put into a predetermined heating device such as a reflow furnace, and the temporary mounting body is heated by the heating device. By this heat treatment, each protruding electrode 2c of the solid-state imaging device 2 is welded and bonded to each electrode pad of the circuit board 3, and as a result, flip-chip mounting between the solid-state imaging device 2 and the circuit board 3 is achieved. In this case, the solid-state imaging device 2 is electrically connected to the circuit board 3 with the opening 3a of the circuit board 3 and the light receiving unit 2a facing each other.

なお、このステップS201における仮実装において、上述したような位置決め処理後の固体撮像素子2および回路基板3に対して押圧処理または超音波処理等をさらに行って、この回路基板3の各電極パッドに固体撮像素子2の各突起電極2cを仮接合してもよい。   In the temporary mounting in step S201, the solid-state imaging device 2 and the circuit board 3 after the positioning process as described above are further subjected to a pressing process, an ultrasonic process, or the like, and applied to each electrode pad of the circuit board 3. Each protruding electrode 2c of the solid-state imaging device 2 may be temporarily joined.

つぎに、上述したステップS201のフリップチップ実装における加熱処理によって熱膨張状態の固体撮像素子2および回路基板3に補正基板27を取り付ける(ステップS202)。このステップS202において、補正基板27は、図9に示すように、ステップS201の加熱処理によって熱膨張状態である固体撮像素子2と回路基板3とのフリップチップ実装体(以下、単に、実装体という)15内の固体撮像素子2における複数の貫通孔2dに複数の嵌合ピン7aを圧入して最終的に固体撮像素子2に面接触する。これによって、補正基板27は、この熱膨張状態の固体撮像素子2を相対的に固定する。さらに図9に示すように、補正基板27は、この実装体15内の回路基板3における複数の基板貫通孔3bに、これら複数の貫通孔2dを貫通して突き出た複数の嵌合ピン7aを熱膨張状態の回路基板3における複数の基板貫通孔3bに貫通させる。この結果、補正基板27は、この熱膨張状態の固体撮像素子2および回路基板3を含む実装体15を相対的に固定する。   Next, the correction substrate 27 is attached to the solid-state imaging device 2 and the circuit board 3 in the thermally expanded state by the heat treatment in the flip-chip mounting in step S201 described above (step S202). In this step S202, as shown in FIG. 9, the correction substrate 27 is a flip-chip mounting body (hereinafter simply referred to as a mounting body) of the solid-state imaging device 2 and the circuit board 3 that are in a thermally expanded state by the heat treatment in step S201. ) A plurality of fitting pins 7a are press-fitted into the plurality of through holes 2d in the solid-state image pickup device 2 in 15, and finally come into surface contact with the solid-state image pickup device 2. Thereby, the correction substrate 27 relatively fixes the solid-state imaging device 2 in the thermal expansion state. Further, as shown in FIG. 9, the correction board 27 includes a plurality of fitting pins 7 a protruding through the plurality of through holes 2 d in the plurality of board through holes 3 b in the circuit board 3 in the mounting body 15. It penetrates through the plurality of substrate through holes 3b in the circuit board 3 in a thermally expanded state. As a result, the correction board 27 relatively fixes the mounting body 15 including the solid-state imaging element 2 and the circuit board 3 in the thermally expanded state.

ここで、このフリップチップ実装後の状態において、補正基板27の各嵌合ピン7aは、この実装体15内の回路基板3の熱収縮力に抗して各一対の貫通孔2dと基板貫通孔3bとの相対的位置関係を維持している。これとともに、補正基板27は、この実装体15内の回路基板3の熱収縮力に比して強い剛性によって固体撮像素子2の反りを補正し、この結果、この固体撮像素子2を平坦な状態に維持している。   Here, in the state after the flip-chip mounting, each fitting pin 7a of the correction board 27 resists the thermal contraction force of the circuit board 3 in the mounting body 15 and each pair of the through holes 2d and the board through holes. The relative positional relationship with 3b is maintained. At the same time, the correction substrate 27 corrects the warp of the solid-state image sensor 2 with a rigidity higher than the thermal contraction force of the circuit board 3 in the mounting body 15, and as a result, the solid-state image sensor 2 is in a flat state. To maintain.

つぎに、ステップS202による補正基板27の取り付け工程後の固体撮像素子2と回路基板3との間に接着剤4を充填する(ステップS203)。このステップS203において、接着剤4は、上述した実施の形態1の場合と同様に固体撮像素子2と回路基板3との間隙に充填され、さらに、この固体撮像素子2と回路基板3との間隙を閉塞するまで、この回路基板3上の固体撮像素子2の周囲に沿って裾野形状に塗布される。なお、このような接着剤4の充填作業は、熱膨張状態の実装体15に対して行ってもよいし、例えば常温程度まで温度低下して熱収縮した状態の実装体15に対して行ってもよい。   Next, the adhesive 4 is filled between the solid-state imaging device 2 and the circuit board 3 after the correction substrate 27 is attached in step S202 (step S203). In this step S203, the adhesive 4 is filled in the gap between the solid-state imaging device 2 and the circuit board 3 as in the case of the first embodiment, and further, the gap between the solid-state imaging element 2 and the circuit board 3 is filled. Is applied in the shape of a skirt along the periphery of the solid-state imaging device 2 on the circuit board 3 until it is closed. Note that such a filling operation of the adhesive 4 may be performed on the mounting body 15 in a thermally expanded state, for example, on the mounting body 15 in a state in which the temperature is reduced to about room temperature and thermally contracted. Also good.

その後、上述した実施の形態1のステップS105の場合と同様に、回路基板3にフリップチップ実装済みの固体撮像素子2を封止する(ステップS204)。このステップS204によって、上述した実装体15にカバーガラス5が取り付けられ、この結果、図7に示した構成を有する撮像ユニット21が製造される。このように製造された撮像ユニット21は、デジタルカメラおよびデジタルビデオカメラを始め、被検体の臓器内部を観察するための内視鏡、撮像機能を備えた携帯電話機等、各種態様の電子撮像装置に内蔵することができる。   Thereafter, as in the case of step S105 of the first embodiment described above, the solid-state imaging device 2 that has been flip-chip mounted on the circuit board 3 is sealed (step S204). By this step S204, the cover glass 5 is attached to the mounting body 15 described above, and as a result, the imaging unit 21 having the configuration shown in FIG. 7 is manufactured. The imaging unit 21 manufactured in this way is used in various types of electronic imaging devices such as a digital camera and a digital video camera, an endoscope for observing the inside of an organ of a subject, and a mobile phone having an imaging function. Can be built in.

ここで、上述した補正基板27は、上述したようにステップS202において、加熱処理による熱膨張状態の実装体15に対して取り付けられる。この熱膨張状態の実装体15内の回路基板3は、補正基板27の複数の嵌合ピン7aを複数の基板貫通孔3bに貫通した状態を維持しつつ常温まで温度低下し、この温度低下に伴って熱収縮する。この状態において、補正基板27は、各嵌合ピン7aを介して回路基板3の熱収縮力F2(図6参照)を受ける。このような補正基板27は、上述したように回路基板3の熱変形力に比して強い剛性を有し、このように熱変形する回路基板3および固体撮像素子2に対して、この自身の剛性に基づいた反作用力F12(図6参照)を作用させる。   Here, as described above, the correction board 27 described above is attached to the mounting body 15 in the thermally expanded state by the heat treatment in step S202. The circuit board 3 in the mounting body 15 in the thermally expanded state is lowered to room temperature while maintaining a state in which the plurality of fitting pins 7a of the correction board 27 are passed through the plurality of board through holes 3b. Accompanied by heat shrinkage. In this state, the correction board 27 receives the thermal contraction force F2 (see FIG. 6) of the circuit board 3 through each fitting pin 7a. Such a correction board 27 has a rigidity higher than the thermal deformation force of the circuit board 3 as described above, and this correction board 27 has its own resistance to the circuit board 3 and the solid-state imaging device 2 that are thermally deformed in this way. A reaction force F12 (see FIG. 6) based on rigidity is applied.

補正基板27は、上述したような回路基板3の熱収縮力F2に対抗する反作用力F12によって、温度低下時の回路基板3の熱収縮変形に伴う固体撮像素子2の熱収縮変形を抑制し、これによって、この固体撮像素子2の熱収縮に起因する応力を十分に吸収する。この結果、補正基板27は、このような応力によって招来される固体撮像素子2の反りを低減する。このようにして、補正基板27は、加熱処理後、具体的には回路基板3へのフリップチップ実装後の固体撮像素子2の反りを補正する。このような補正基板27の作用によって、回路基板3上の固体撮像素子2は、実施の形態1の場合と同様に受光部2aを平坦な状態に維持することができる。なお、このような補正基板27において、複数の嵌合ピン7aは、この回路基板3の熱収縮力F2に抗して複数の貫通孔2dと複数の基板貫通孔3bとの各相対位置関係を対毎に維持する。   The correction substrate 27 suppresses the thermal contraction deformation of the solid-state imaging device 2 due to the thermal contraction deformation of the circuit board 3 at the time of the temperature decrease by the reaction force F12 that opposes the thermal contraction force F2 of the circuit board 3 as described above. As a result, the stress caused by the thermal contraction of the solid-state imaging device 2 is sufficiently absorbed. As a result, the correction substrate 27 reduces the warpage of the solid-state imaging device 2 caused by such stress. In this way, the correction substrate 27 corrects the warp of the solid-state imaging device 2 after the heat treatment, specifically, after flip chip mounting on the circuit board 3. By such an action of the correction substrate 27, the solid-state imaging device 2 on the circuit board 3 can maintain the light receiving unit 2a in a flat state as in the case of the first embodiment. In such a correction board 27, the plurality of fitting pins 7 a have the relative positional relationship between the plurality of through holes 2 d and the plurality of board through holes 3 b against the thermal contraction force F 2 of the circuit board 3. Keep pairwise.

なお、補正基板27は、上述した固体撮像素子2のフリップチップ実装工程後における加熱処理(例えば、接着剤4,6の熱硬化処理等)の前後においても、同様に、回路基板3の熱変形を抑制でき、この結果、この回路基板3の熱収縮に起因する固体撮像素子2の反りを低減することができる。   The correction substrate 27 is similarly subjected to thermal deformation of the circuit board 3 before and after the heat treatment (for example, thermosetting treatment of the adhesives 4 and 6) after the flip-chip mounting process of the solid-state imaging device 2 described above. As a result, the warpage of the solid-state imaging device 2 due to the thermal contraction of the circuit board 3 can be reduced.

以上、説明したように、本発明の実施の形態2では、熱膨張状態であるフリップチップ実装後の実装体、すなわち、熱膨張状態の固体撮像素子および回路基板に補正基板を取り付け、この補正基板によってこの回路基板の熱収縮変形に伴う固体撮像素子の反りを補正するようにし、その他を実施の形態1と同様に構成した。このため、たとえフリップチップ実装後の熱膨張した状態の回路基板が温度低下とともに熱収縮しても、この補正基板によって強制的に回路基板およびこの回路基板の熱収縮に伴う固体撮像素子の熱収縮を強制的に抑制でき、この結果、より少ない作業工程によって上述した実施の形態1の場合と同様の作用効果を享受する撮像ユニットを実現することができる。   As described above, in the second embodiment of the present invention, a correction board is attached to a mounted body after flip chip mounting in a thermally expanded state, that is, a solid-state imaging device and a circuit board in a thermally expanded state. Thus, the warp of the solid-state imaging device due to the thermal contraction deformation of the circuit board is corrected, and the others are configured in the same manner as in the first embodiment. For this reason, even if the circuit board in a thermally expanded state after flip-chip mounting is thermally shrunk as the temperature drops, the correction board forcibly causes the circuit board and the thermal contraction of the solid-state imaging device accompanying the heat shrinking of the circuit board. As a result, it is possible to realize an imaging unit that enjoys the same effects as those of the first embodiment described above with fewer work steps.

(実施の形態3)
つぎに、本発明の実施の形態3について説明する。上述した実施の形態1では、複数の嵌合ピン7aを介した補正基板7とカバーガラス5との立体構造によって固体撮像素子2および回路基板3を挟んでいたが、この実施の形態3では、回路基板3の開口部3aに連通する開口部が形成された枠体と上述した補正基板7とを用いて、固体撮像素子2の反りを低減する立体構造を形成している。
(Embodiment 3)
Next, a third embodiment of the present invention will be described. In the first embodiment described above, the solid-state imaging device 2 and the circuit board 3 are sandwiched by the three-dimensional structure of the correction substrate 7 and the cover glass 5 via the plurality of fitting pins 7a. In this third embodiment, A three-dimensional structure that reduces warpage of the solid-state imaging device 2 is formed by using the frame body in which the opening communicating with the opening 3 a of the circuit board 3 is formed and the correction substrate 7 described above.

図10は、本発明の実施の形態3にかかる撮像ユニットの一構成例を示す断面模式図である。図10に示すように、この実施の形態3にかかる撮像ユニット31は、上述した実施の形態1にかかる撮像ユニット1のカバーガラス5に代えてカバーガラス35を備え、このカバーガラス35と回路基板3との間に枠体38を備える。この実施の形態3において、補正基板7および枠体38は、複数の嵌合ピン7aを支柱にして固体撮像素子2および回路基板3を挟む立体構造を成している。その他の構成は実施の形態1と同じであり、同一構成部分には同一符号を付している。   FIG. 10 is a schematic cross-sectional view illustrating a configuration example of an imaging unit according to the third embodiment of the present invention. As shown in FIG. 10, the imaging unit 31 according to the third embodiment includes a cover glass 35 instead of the cover glass 5 of the imaging unit 1 according to the first embodiment described above, and the cover glass 35 and the circuit board. 3 is provided with a frame 38. In the third embodiment, the correction board 7 and the frame body 38 have a three-dimensional structure that sandwiches the solid-state imaging device 2 and the circuit board 3 with a plurality of fitting pins 7a as columns. Other configurations are the same as those of the first embodiment, and the same reference numerals are given to the same components.

カバーガラス35は、固体撮像素子2の受光部2aへの光透過性を損なうことなく受光部2aを封止する。具体的には、カバーガラス35は、被写体からの光、すなわち固体撮像素子2の受光部2aが受光すべき光に対して透明な板状の透光性部材である。なお、このカバーガラス35には、上述した実施の形態1において例示した複数の嵌合孔5aが形成されていない。このようなカバーガラス35は、図10に示すように、回路基板3の開口部3aに連通する枠体38の開口部38aを閉塞するように、接着剤6によって枠体38に固定される。このように枠体38上に固定されたカバーガラス35は、フリップチップ実装後の固体撮像素子2の受光部2aを内部に気密封止し、この結果、この受光部2aへの光透過性を損なうことなく、この枠体38の開口部38a側からの異物混入を防止する。   The cover glass 35 seals the light receiving part 2a without impairing the light transmittance to the light receiving part 2a of the solid-state imaging device 2. Specifically, the cover glass 35 is a plate-like translucent member that is transparent to light from a subject, that is, light that should be received by the light receiving unit 2a of the solid-state imaging device 2. The cover glass 35 is not formed with the plurality of fitting holes 5a illustrated in the first embodiment. As shown in FIG. 10, such a cover glass 35 is fixed to the frame 38 by the adhesive 6 so as to close the opening 38 a of the frame 38 communicating with the opening 3 a of the circuit board 3. The cover glass 35 fixed on the frame 38 in this manner hermetically seals the light receiving portion 2a of the solid-state imaging device 2 after flip chip mounting. As a result, the light transmission to the light receiving portion 2a is improved. Without impairing, foreign matter contamination from the opening 38a side of the frame 38 is prevented.

枠体38は、固体撮像素子2の反り低減を実現する立体構造の一部をなす枠状部材であり、上述した補正基板7による固体撮像素子2の反りの補正を支援する支援部材として機能する。具体的には、図10に示すように、枠体38には、回路基板3の開口部3aに対応する開口部38aと、回路基板3の複数の基板貫通孔3bに対応する複数の嵌合孔38bとが形成される。   The frame 38 is a frame-like member that forms a part of a three-dimensional structure that realizes a reduction in warpage of the solid-state imaging device 2, and functions as a support member that supports correction of warpage of the solid-state imaging device 2 by the correction substrate 7 described above. . Specifically, as shown in FIG. 10, the frame body 38 has an opening 38 a corresponding to the opening 3 a of the circuit board 3 and a plurality of fittings corresponding to the plurality of substrate through holes 3 b of the circuit board 3. A hole 38b is formed.

枠体38の開口部38aは、上述した回路基板3の開口部3aと同様に、固体撮像素子2の受光部2aに対応して設計された開口寸法を有し、この受光部2aに対する被写体からの光の入射を可能にする。このような枠体38は、図10に示すように、回路基板3の開口部3aと自身の開口部38aとを連通させるように回路基板3に面的に取り付けられる。この場合、この枠体38に形成された複数の嵌合孔38bには、この回路基板3を貫通して突き出た複数の嵌合ピン7aが嵌合固定される。   The opening 38a of the frame 38 has an opening dimension designed corresponding to the light receiving part 2a of the solid-state imaging device 2 in the same manner as the opening 3a of the circuit board 3 described above. Enables the incidence of light. As shown in FIG. 10, such a frame 38 is attached to the circuit board 3 so that the opening 3a of the circuit board 3 and the opening 38a of the circuit board 3 communicate with each other. In this case, a plurality of fitting pins 7 a protruding through the circuit board 3 are fitted and fixed in the plurality of fitting holes 38 b formed in the frame 38.

複数の嵌合孔38bは、上述した複数の基板貫通孔3bと対を成して補正基板7の複数の嵌合ピン7aを圧入する貫通孔である。これら複数の嵌合孔38bの各々は、例えば図10に示すように、各嵌合ピン7aを貫通させる回路基板3の各基板貫通孔3bに対向する位置に形成される。この場合、各嵌合孔38bおよび各基板貫通孔3bは、互いに対向するもの同士で対を成す。これら複数の嵌合孔38bが形成された枠体38は、上述した複数の基板貫通孔3bを貫通して突き出た複数の嵌合ピン7aを複数の嵌合孔38bに圧入して嵌合固定することによって、補正基板7および複数の嵌合ピン7aを含む立体構造を形成する。この場合、図10に示したように固体撮像素子2と回路基板3とを貫通し枠体38に嵌め込まれた複数の嵌合ピン7aは、このような補正基板7および枠体38による立体構造体の支柱として機能する。このような立体構造体は、図10に示すように固体撮像素子2および回路基板3を面接触状態で内部に挟み込み、この結果、この固体撮像素子2の反りを強固に低減する。なお、枠体38は、この立体構造体のベースをなす剛性基板である補正基板7による固体撮像素子2の反り補正作用を支援する。   The plurality of fitting holes 38b are through holes that press-fit the plurality of fitting pins 7a of the correction board 7 in pairs with the plurality of board through holes 3b described above. Each of the plurality of fitting holes 38b is formed at a position facing each board through hole 3b of the circuit board 3 through which each fitting pin 7a passes, for example, as shown in FIG. In this case, each fitting hole 38b and each substrate through-hole 3b make a pair with each other facing each other. The frame 38 formed with the plurality of fitting holes 38b is press-fitted into the plurality of fitting holes 38b with the plurality of fitting pins 7a protruding through the plurality of substrate through-holes 3b described above. By doing so, a three-dimensional structure including the correction substrate 7 and the plurality of fitting pins 7a is formed. In this case, as shown in FIG. 10, the plurality of fitting pins 7 a that pass through the solid-state imaging device 2 and the circuit board 3 and are fitted into the frame body 38 have a three-dimensional structure formed by the correction board 7 and the frame body 38. Functions as a body support. Such a three-dimensional structure sandwiches the solid-state imaging device 2 and the circuit board 3 in a surface contact state as shown in FIG. 10, and as a result, the warpage of the solid-state imaging device 2 is strongly reduced. The frame body 38 supports the warp correction action of the solid-state imaging device 2 by the correction board 7 which is a rigid board that forms the base of the three-dimensional structure.

なお、これら複数の嵌合孔38bは、上述した固体撮像素子2の各貫通孔2dの場合と同様に補正基板7の各嵌合ピン7aを圧入する程度の径に形成されてもよいが、回路基板3の各基板貫通孔3bの場合と同様に各嵌合ピン7aを摺動自在に挿入可能な程度の径に形成されてもよい。このような各嵌合孔38bに各嵌合ピン7aを摺動自在に挿入する場合、枠体38は、接着剤によって回路基板3に接着すればよい。また、これら複数の嵌合孔38bに複数の嵌合ピン7aを嵌合固定することによって回路基板3と枠体38との固定が達成される場合、回路基板3と枠体38との間隙に、この間隙を閉塞するための封止材(シール材)を充填してもよい。   The plurality of fitting holes 38b may be formed to have a diameter enough to press-fit each fitting pin 7a of the correction substrate 7 as in the case of each through-hole 2d of the solid-state imaging device 2 described above. Similarly to the case of each board through hole 3b of the circuit board 3, each fitting pin 7a may be formed with a diameter that can be slidably inserted. When the respective fitting pins 7a are slidably inserted into the respective fitting holes 38b, the frame body 38 may be bonded to the circuit board 3 with an adhesive. Further, when the circuit board 3 and the frame body 38 are fixed by fitting and fixing the plurality of fitting pins 7a into the plurality of fitting holes 38b, the gap between the circuit board 3 and the frame body 38 is set. A sealing material (sealing material) for closing the gap may be filled.

つぎに、本発明の実施の形態3にかかる撮像ユニット31の製造方法について説明する。図11は、本発明の実施の形態3にかかる撮像ユニットの製造方法の一例を示すフローチャートである。図12は、補正基板に固体撮像素子と回路基板と枠体とを順次取り付ける状態を示す模式図である。本発明の実施の形態3にかかる撮像ユニット31は、上述した固体撮像素子2、回路基板3、カバーガラス35、補正基板7および枠体38を撮像ユニット31の構成部品として予め準備し、接着剤4,6等を用いてこれらの各構成部品を組み合わせることによって製造される。   Next, a method for manufacturing the imaging unit 31 according to the third embodiment of the present invention will be described. FIG. 11 is a flowchart illustrating an example of a manufacturing method of the imaging unit according to the third embodiment of the present invention. FIG. 12 is a schematic diagram showing a state in which the solid-state imaging device, the circuit board, and the frame are sequentially attached to the correction board. The imaging unit 31 according to the third embodiment of the present invention prepares the solid-state imaging device 2, the circuit board 3, the cover glass 35, the correction substrate 7, and the frame body 38 as constituent parts of the imaging unit 31 in advance, and an adhesive. It is manufactured by combining these components using 4, 6, etc.

すなわち、図11に示すように、まず、実施の形態1におけるステップS101の場合と同様に補正基板7に固体撮像素子2を取り付け(ステップS301)、つぎに、実施の形態1におけるステップS102の場合と同様に、この補正基板7上の固体撮像素子2と回路基板3とを仮実装する(ステップS302)。   That is, as shown in FIG. 11, first, the solid-state imaging device 2 is attached to the correction substrate 7 in the same manner as in step S101 in the first embodiment (step S301), and then in the case of step S102 in the first embodiment. Similarly, the solid-state imaging device 2 and the circuit board 3 on the correction substrate 7 are temporarily mounted (step S302).

つぎに、ステップS302によって仮実装した固体撮像素子2および回路基板3を補正基板7と枠体38との間に挟み込む(ステップS303)。このステップS303において、枠体38は、固体撮像素子2を仮実装後の回路基板3の開口部3aと自身の開口部38aとを連通させるように、この回路基板3に面的に取り付けられる。この場合、枠体38の複数の嵌合孔38bには、図12に示すように、仮実装後の固体撮像素子2の各貫通孔2dと回路基板3の各基板貫通孔3bとを順次貫通して回路基板3から突き出た複数の嵌合ピン7aが圧入される。この結果、枠体38は、各開口部3a,38aを対向させた状態で回路基板3に面接触して固定され、この枠体38および補正基板7は、複数の嵌合ピン7aを支柱とする立体構造体の内部に仮実装後の固体撮像素子2および回路基板3を挟み込む。   Next, the solid-state imaging device 2 and the circuit board 3 temporarily mounted in step S302 are sandwiched between the correction board 7 and the frame body 38 (step S303). In step S303, the frame 38 is attached to the circuit board 3 so as to communicate the opening 3a of the circuit board 3 after the temporary mounting of the solid-state imaging device 2 and the opening 38a of the frame body 38 itself. In this case, the plurality of fitting holes 38b of the frame body 38 sequentially pass through the through holes 2d of the solid-state imaging device 2 after provisional mounting and the board through holes 3b of the circuit board 3 as shown in FIG. Then, a plurality of fitting pins 7a protruding from the circuit board 3 are press-fitted. As a result, the frame body 38 is fixed in surface contact with the circuit board 3 with the openings 3a and 38a facing each other. The frame body 38 and the correction board 7 have a plurality of fitting pins 7a as support columns. The solid-state imaging device 2 and the circuit board 3 after temporary mounting are sandwiched inside the three-dimensional structure to be performed.

その後、この立体構造体の内部に挟み込まれた固体撮像素子2と回路基板3とを本実装する(ステップS304)。このステップS304において、上述した立体構造体内部の仮実装体、すなわち、ステップS302の仮実装工程において仮実装した固体撮像素子2および回路基板3は、上述した補正基板7および枠体38による立体構造体に挟み込まれた状態を維持しつつ、リフロー炉等の所定の加熱装置に投入され、この加熱装置によって加熱処理される。この加熱処理によって、固体撮像素子2の各突起電極2cは、回路基板3の各電極パッドに溶着接合される。この結果、固体撮像素子2と回路基板3とのフリップチップ実装が真に達成され、固体撮像素子2は、回路基板3の開口部3aを介して枠体38の開口部38aと受光部2aとを対向させた状態で回路基板3と電気的に接続される。   Thereafter, the solid-state imaging device 2 and the circuit board 3 sandwiched between the three-dimensional structures are fully mounted (step S304). In step S304, the temporary mounting body inside the above-described three-dimensional structure, that is, the solid-state imaging device 2 and the circuit board 3 temporarily mounted in the temporary mounting process in step S302 are the three-dimensional structure formed by the correction substrate 7 and the frame body 38 described above. While maintaining the state of being sandwiched between the body, it is put into a predetermined heating device such as a reflow furnace and heat-treated by this heating device. By this heat treatment, each protruding electrode 2 c of the solid-state imaging device 2 is welded and bonded to each electrode pad of the circuit board 3. As a result, the flip-chip mounting of the solid-state imaging device 2 and the circuit board 3 is truly achieved, and the solid-state imaging device 2 is connected to the opening 38 a and the light receiving unit 2 a of the frame 38 through the opening 3 a of the circuit board 3. Are electrically connected to the circuit board 3 in a state of facing each other.

ここで、この本実装後(すなわち真のフリップチップ実装後)の状態において、補正基板7の各嵌合ピン7aは、枠体38と協同して、この回路基板3の熱収縮力に抗して各一対の貫通孔2dと基板貫通孔3bとの相対的位置関係を維持している。これとともに、補正基板7は、この回路基板3の熱収縮力に比して強い剛性および枠体38の支援的な剛性によって固体撮像素子2の反りを補正し、この結果、この固体撮像素子2を平坦な状態に維持している。   Here, in the state after the main mounting (that is, after the true flip chip mounting), each fitting pin 7a of the correction substrate 7 cooperates with the frame body 38 to resist the thermal contraction force of the circuit substrate 3. Thus, the relative positional relationship between each pair of through holes 2d and the substrate through holes 3b is maintained. At the same time, the correction board 7 corrects the warp of the solid-state image pickup device 2 by the rigidity that is stronger than the thermal contraction force of the circuit board 3 and the support rigidity of the frame body 38, and as a result, the solid-state image pickup element 2. Is kept flat.

つぎに、ステップS304による本実装工程後の固体撮像素子2と回路基板3との間に接着剤4を充填する(ステップS305)。このステップS305において、接着剤4は、実施の形態1におけるステップS104の場合と同様に、固体撮像素子2と回路基板3との間隙に充填され、さらに、この回路基板3上の固体撮像素子2の周囲に沿って裾野形状に塗布される(図10参照)。   Next, the adhesive 4 is filled between the solid-state imaging device 2 and the circuit board 3 after the main mounting process in step S304 (step S305). In this step S305, the adhesive 4 is filled in the gap between the solid-state image sensor 2 and the circuit board 3 as in the case of step S104 in the first embodiment, and further, the solid-state image sensor 2 on the circuit board 3 is filled. It is applied in the shape of a skirt along the periphery (see FIG. 10).

その後、回路基板3に本実装済みの固体撮像素子2を封止する(ステップS306)。このステップS306において、カバーガラス35は、図10に示したように、本実装後の回路基板3の開口部3aに連通する枠体38の開口部38aを覆うように枠体38に固定される。この際、枠体38とカバーガラス35との間に接着剤6を介在させ、この接着剤6によって枠体38とカバーガラス35とを接着するとともに枠体38とカバーガラス35との間隙を閉塞する。このように枠体38に取り付けられたカバーガラス35は、実施の形態1の場合と同様に、固体撮像素子2の受光部2aへの光入射を可能にしつつ、内部に受光部2aを封止する。   Thereafter, the solid-state imaging device 2 that has been mounted on the circuit board 3 is sealed (step S306). In this step S306, as shown in FIG. 10, the cover glass 35 is fixed to the frame 38 so as to cover the opening 38a of the frame 38 communicating with the opening 3a of the circuit board 3 after the main mounting. . At this time, the adhesive 6 is interposed between the frame body 38 and the cover glass 35, and the frame body 38 and the cover glass 35 are bonded by the adhesive 6 and the gap between the frame body 38 and the cover glass 35 is closed. To do. The cover glass 35 attached to the frame body 38 in this manner seals the light receiving portion 2a inside while allowing light to enter the light receiving portion 2a of the solid-state imaging device 2 as in the case of the first embodiment. To do.

上述したステップS301〜S306の各製造工程を順次行うことによって、図10に示した構成を有する撮像ユニット31を製造することができる。このように製造された撮像ユニット31は、実施の形態1にかかる撮像ユニット1の場合と同様に、デジタルカメラおよびデジタルビデオカメラを始め、被検体の臓器内部を観察するための内視鏡、撮像機能を備えた携帯電話機等、各種態様の電子撮像装置に内蔵することができる。   The imaging unit 31 having the configuration shown in FIG. 10 can be manufactured by sequentially performing the manufacturing steps of steps S301 to S306 described above. As with the imaging unit 1 according to the first embodiment, the imaging unit 31 manufactured in this way includes a digital camera and a digital video camera, an endoscope for observing the inside of the organ of the subject, and imaging. It can be incorporated in various types of electronic imaging devices such as a mobile phone having a function.

つぎに、上述した補正基板7および枠体38を含む立体構造体による固体撮像素子2の反り低減作用について説明する。図13は、補正基板および枠体を含む立体構造体によって固体撮像素子の反りを低減する状態を示す模式図である。   Next, the warp reducing action of the solid-state imaging device 2 by the three-dimensional structure including the correction substrate 7 and the frame body 38 described above will be described. FIG. 13 is a schematic diagram illustrating a state in which the warpage of the solid-state imaging device is reduced by the three-dimensional structure including the correction substrate and the frame.

この実施の形態3にかかる撮像ユニット31の補正基板7は、図13に示すように、枠体38と協同して複数の嵌合ピン7aを支柱として含む立体構造体18を形成する。この立体構造体18は、仮実装後の固体撮像素子2および回路基板3(すなわち仮実装体)を内部に挟み込んだ状態を維持する。このような仮実装体を挟み込んだ立体構造体18は、上述したステップS304の本実装工程において加熱処理される。   As shown in FIG. 13, the correction substrate 7 of the imaging unit 31 according to the third embodiment forms a three-dimensional structure 18 including a plurality of fitting pins 7a as columns in cooperation with the frame body 38. The three-dimensional structure 18 maintains a state in which the solid-state imaging device 2 and the circuit board 3 (that is, the temporary mounting body) after temporary mounting are sandwiched inside. The three-dimensional structure 18 sandwiching such a temporary mounting body is subjected to heat treatment in the main mounting process of step S304 described above.

ここで、立体構造体18内の回路基板3は、ステップS304における加熱処理によって熱膨張し、その後、常温まで温度低下しつつ熱収縮する。この状態において、立体構造体18は、図13に示すように、回路基板3の熱膨張力を受け、その後、回路基板3の熱収縮力を受ける。このような立体構造体18は、このように熱変形する回路基板3および固体撮像素子2に対して反作用力F11,F12を作用させる。具体的には、この立体構造体18内の補正基板7および枠体38は、各嵌合ピン7aを介して回路基板3の熱膨張力を受け、その後、各嵌合ピン7aを介して回路基板3の熱収縮力を受ける。このような補正基板7は、上述したように回路基板3の熱変形力に比して強い剛性を有し、このように熱変形する回路基板3および固体撮像素子2に対して、枠体38の剛性と自身の剛性とに基づいた反作用力F11,F12を作用させる。   Here, the circuit board 3 in the three-dimensional structure 18 is thermally expanded by the heat treatment in step S304, and then thermally contracted while the temperature is lowered to room temperature. In this state, the three-dimensional structure 18 receives the thermal expansion force of the circuit board 3 and then receives the thermal contraction force of the circuit board 3 as shown in FIG. Such a three-dimensional structure 18 causes reaction forces F11 and F12 to act on the circuit board 3 and the solid-state imaging device 2 that are thermally deformed in this manner. Specifically, the correction board 7 and the frame body 38 in the three-dimensional structure 18 receive the thermal expansion force of the circuit board 3 through the fitting pins 7a, and then the circuit through the fitting pins 7a. The thermal contraction force of the substrate 3 is received. As described above, the correction board 7 has a rigidity higher than the thermal deformation force of the circuit board 3, and the frame body 38 against the circuit board 3 and the solid-state imaging device 2 that are thermally deformed in this way. Reaction forces F11 and F12 are applied based on the rigidity and the own rigidity.

なお、この立体構造体18に発生する一方の反作用力F11は、回路基板3および固体撮像素子2の熱膨張力に対抗する力であり、他方の反作用力F12は、回路基板3および固体撮像素子2の熱収縮力に対抗する力である。   One reaction force F11 generated in the three-dimensional structure 18 is a force that opposes the thermal expansion force of the circuit board 3 and the solid-state imaging device 2, and the other reaction force F12 is the circuit board 3 and the solid-state imaging device. This is a force that opposes the heat shrinkage force of 2.

立体構造体18は、上述した回路基板3の熱膨張力に対抗する反作用力F11によって、加熱処理時の回路基板3の熱膨張変形に伴う固体撮像素子2の熱膨張変形を抑制し、これによって、この固体撮像素子2の熱膨張に起因する応力を十分に吸収する。この結果、立体構造体18は、このような応力によって招来される固体撮像素子2の反りを低減する。この場合、立体構造体18内の補正基板7は、枠体38と協同してこの固体撮像素子2の反りを低減する。   The three-dimensional structure 18 suppresses the thermal expansion deformation of the solid-state imaging device 2 due to the thermal expansion deformation of the circuit board 3 during the heat treatment by the reaction force F11 that opposes the thermal expansion force of the circuit board 3 described above. The stress resulting from the thermal expansion of the solid-state imaging device 2 is sufficiently absorbed. As a result, the three-dimensional structure 18 reduces the warpage of the solid-state imaging device 2 caused by such stress. In this case, the correction substrate 7 in the three-dimensional structure 18 reduces the warpage of the solid-state imaging device 2 in cooperation with the frame body 38.

一方、立体構造体18は、上述した回路基板3の熱収縮力に対抗する反作用力F12によって、温度低下時の回路基板3の熱収縮変形に伴う固体撮像素子2の熱収縮変形を抑制し、これによって、この固体撮像素子2の熱収縮に起因する応力を十分に吸収する。この結果、立体構造体18は、このような応力によって招来される固体撮像素子2の反りを低減する。この場合、立体構造体18内の補正基板7は、枠体38と協同してこの固体撮像素子2の反りを低減する。   On the other hand, the three-dimensional structure 18 suppresses the thermal contraction deformation of the solid-state imaging device 2 due to the thermal contraction deformation of the circuit board 3 when the temperature is lowered by the reaction force F12 that opposes the thermal contraction force of the circuit board 3 described above. As a result, the stress caused by the thermal contraction of the solid-state imaging device 2 is sufficiently absorbed. As a result, the three-dimensional structure 18 reduces the warpage of the solid-state imaging device 2 caused by such stress. In this case, the correction substrate 7 in the three-dimensional structure 18 reduces the warpage of the solid-state imaging device 2 in cooperation with the frame body 38.

以上のようにして、補正基板7は、枠体38の支援を受けつつ、加熱処理後、具体的には回路基板3へのフリップチップ実装後の固体撮像素子2の反りを補正する。このような補正基板7および枠体38の作用によって、回路基板3上の固体撮像素子2は、受光部2aの平坦な状態を一層強固に維持することができる。なお、上述した立体構造体18において、複数の嵌合ピン7aは、この回路基板3の熱膨張力または熱収縮力に抗して複数の貫通孔2dと複数の基板貫通孔3bとの各相対位置関係を対毎に維持する。   As described above, the correction substrate 7 corrects the warpage of the solid-state imaging device 2 after the heat treatment, specifically, after flip-chip mounting on the circuit substrate 3, with the support of the frame body 38. By such an action of the correction substrate 7 and the frame 38, the solid-state imaging device 2 on the circuit substrate 3 can maintain the flat state of the light receiving portion 2a more firmly. In the above-described three-dimensional structure 18, the plurality of fitting pins 7 a are respectively opposed to the plurality of through holes 2 d and the plurality of substrate through holes 3 b against the thermal expansion force or thermal contraction force of the circuit board 3. Maintain positional relationships for each pair.

なお、立体構造体18は、上述した固体撮像素子2のフリップチップ実装工程後における加熱処理(例えば、接着剤4,6の熱硬化処理等)の前後においても、同様に、回路基板3の熱変形を抑制でき、この結果、この回路基板3の熱収縮に起因する固体撮像素子2の反りを低減することができる。   Note that the three-dimensional structure 18 is similarly heated before and after the heat treatment (for example, thermosetting treatment of the adhesives 4 and 6) after the flip chip mounting process of the solid-state imaging device 2 described above. Deformation can be suppressed, and as a result, warpage of the solid-state imaging device 2 due to thermal contraction of the circuit board 3 can be reduced.

以上、説明したように、本発明の実施の形態3では、固体撮像素子を仮実装した回路基板を貫通して突き出た複数の嵌合ピンを枠体に形成した複数の嵌合孔に嵌め込んでこの回路基板と枠体とを相対的に固定し、これら複数の嵌合ピンを支柱としてこの枠体と補正基板とによって形成される立体構造体によって、この回路基板の熱収縮変形に伴う固体撮像素子の反りを補正するようにし、その他を実施の形態1と同様に構成した。このため、上述した実施の形態1と同様の作用効果を享受するとともに、このような補正基板と枠体とが相互に協同して回路基板の熱収縮変形に伴う固体撮像素子の熱収縮変形を抑制でき、この結果、加熱処理による実装後の回路基板と固体撮像素子との熱収縮差を一層強固に抑制して固体撮像素子の反りを確実に低減することができる。   As described above, in the third embodiment of the present invention, the plurality of fitting pins protruding through the circuit board on which the solid-state imaging device is temporarily mounted are fitted into the plurality of fitting holes formed in the frame. The circuit board and the frame are relatively fixed to each other, and a solid structure accompanying the thermal contraction deformation of the circuit board is formed by a three-dimensional structure formed by the frame and the correction board using the plurality of fitting pins as support columns. The warp of the image sensor is corrected, and the rest is configured in the same manner as in the first embodiment. For this reason, while enjoying the same operation effect as Embodiment 1 mentioned above, such a correction board and a frame cooperate with each other, and heat contraction deformation of a solid-state image sensing device accompanying heat contraction deformation of a circuit board is carried out. As a result, the thermal contraction difference between the circuit board after mounting by the heat treatment and the solid-state image sensor can be more firmly suppressed, and the warpage of the solid-state image sensor can be surely reduced.

なお、上述した実施の形態1〜3では、回路基板に固体撮像素子を実装完了後にカバーガラスを取り付けていたが、これに限らず、回路基板に固体撮像素子を実装完了する前にカバーガラスを取り付け、このカバーガラスを取り付けた状態で回路基板と固体撮像素子との実装工程を行ってもよい。   In Embodiments 1 to 3 described above, the cover glass is attached after the mounting of the solid-state imaging device on the circuit board. However, the present invention is not limited thereto, and the cover glass is attached before the mounting of the solid-state imaging device on the circuit board is completed. The mounting step of mounting the circuit board and the solid-state imaging device may be performed with the cover glass attached.

具体的には、上述した実施の形態1においては、ステップS103の本実装工程以前の工程、例えばステップS102の仮実装工程後の仮実装体10にカバーガラス5を取り付け、このカバーガラス5を取り付けた仮実装体10を用いてステップS103の本実装工程を行ってもよい。一方、上述した実施の形態2においては、ステップS201における固体撮像素子2の本実装以前、すなわち、このステップS102における固体撮像素子2の仮実装工程後に、固体撮像素子2と回路基板3との仮実装体にカバーガラス5を取り付け、このカバーガラス5を取り付けた仮実装体を用いて固体撮像素子2と回路基板3との本実装(加熱処理)を行ってもよい。   Specifically, in Embodiment 1 described above, the cover glass 5 is attached to the temporary mounting body 10 after the temporary mounting process of Step S102, for example, the process before the main mounting process of Step S103, and the cover glass 5 is attached. The temporary mounting body 10 may be used to perform the main mounting process of step S103. On the other hand, in the above-described second embodiment, before the solid-state imaging device 2 is actually mounted in step S201, that is, after the temporary mounting step of the solid-state imaging device 2 in step S102, the provisional connection between the solid-state imaging device 2 and the circuit board 3 is performed. The cover glass 5 may be attached to the mounting body, and the mounting (heat treatment) of the solid-state imaging device 2 and the circuit board 3 may be performed using the temporary mounting body to which the cover glass 5 is attached.

ここで、この実施の形態1,2において、カバーガラス5は、複数の嵌合孔5aに複数の嵌合ピン7aを嵌め込んだ状態で回路基板3に固定され、この結果、これら複数の嵌合ピン7aを支柱として補正基板7,27とカバーガラス5とを含む立体構造体が形成される。この立体構造体は、上述した実施の形態3における立体構造体18と同様に固体撮像素子2の反りを低減することができる。ここで、カバーガラス5は、上述したように複数の基板貫通孔3bに対応する複数の嵌合孔5aが形成され、実施の形態3における枠体38の場合と同様に、複数の基板貫通孔3bを貫通して突き出た複数の嵌合ピン7aを複数の嵌合孔5aに嵌合固定することによって補正基板7,27および複数の嵌合ピン7aを含む立体構造を形成する。このような立体構造内のカバーガラス5は、補正基板7,27による固体撮像素子2の反りの補正を支援する支援部材として機能する。   Here, in the first and second embodiments, the cover glass 5 is fixed to the circuit board 3 with the plurality of fitting pins 7a fitted in the plurality of fitting holes 5a. A three-dimensional structure including the correction substrates 7 and 27 and the cover glass 5 is formed using the combination pin 7a as a support. This three-dimensional structure can reduce the warpage of the solid-state imaging device 2 in the same manner as the three-dimensional structure 18 in the third embodiment described above. Here, the cover glass 5 is formed with a plurality of fitting holes 5a corresponding to the plurality of substrate through-holes 3b as described above, and a plurality of substrate through-holes as in the case of the frame 38 in the third embodiment. A plurality of fitting pins 7a protruding through 3b are fitted and fixed in the plurality of fitting holes 5a to form a three-dimensional structure including the correction substrates 7 and 27 and the plurality of fitting pins 7a. The cover glass 5 in such a three-dimensional structure functions as a support member that supports correction of the warp of the solid-state imaging device 2 by the correction substrates 7 and 27.

一方、上述した実施の形態3においては、ステップS304の本実装工程以前の工程、例えばステップS303の工程後の立体構造体18にカバーガラス35を取り付け、このカバーガラス35を取り付けた立体構造体18を用いてステップS304の本実装工程を行ってもよい。   On the other hand, in the above-described third embodiment, the cover glass 35 is attached to the three-dimensional structure 18 after the main mounting process of step S304, for example, the process of step S303, and the three-dimensional structure 18 to which the cover glass 35 is attached. May be used to perform the main mounting process of step S304.

なお、上述した実施の形態1〜3では、固体撮像素子2を封止するためにカバーガラスを取り付けていたが、固体撮像素子2を封止するために用いる透光性部材は、上述したカバーガラスに限らず、アクリル等の樹脂、ローパスフィルタ、IRカットフィルタ、レンズまたはプリズム等の板状光学部材であってもよい。   In Embodiments 1 to 3 described above, the cover glass is attached to seal the solid-state image sensor 2, but the translucent member used to seal the solid-state image sensor 2 is the cover described above. It is not limited to glass, but may be a resin such as acrylic, a low-pass filter, an IR cut filter, a plate-like optical member such as a lens or a prism.

また、上述した実施の形態1〜3では、回路基板3に固体撮像素子2をフリップチップ実装した場合を例示したが、これに限らず、回路基板3に固体撮像素子2を銀ペ−スト材等の接着剤等によってダイボンディング実装し、この回路基板3と固体撮像素子2とを金属ワイヤボンディング技術によって電気的に接続してもよい。   In the first to third embodiments described above, the case where the solid-state imaging device 2 is flip-chip mounted on the circuit board 3 is exemplified. However, the present invention is not limited thereto, and the solid-state imaging device 2 is attached to the circuit board 3 with a silver paste material. The circuit board 3 and the solid-state imaging device 2 may be electrically connected by a metal wire bonding technique.

さらに、上述した実施の形態1〜3では、固体撮像素子2の各貫通孔2dと回路基板3の各基板貫通孔3bとが対毎に対向配置されていたが、これに限らず、このような各一対の貫通孔2dおよび基板貫通孔3bは、互いに対向していなくてもよい。この場合、各一対の貫通孔2dおよび基板貫通孔3bを貫通する各嵌合ピン7aは、この非対向配置に合わせて屈曲または湾曲させればよい。   Further, in the first to third embodiments described above, each through hole 2d of the solid-state imaging device 2 and each substrate through hole 3b of the circuit board 3 are disposed to face each other. Each pair of through-holes 2d and substrate through-holes 3b may not face each other. In this case, each fitting pin 7a penetrating each pair of through-holes 2d and substrate through-holes 3b may be bent or curved according to this non-opposing arrangement.

また、上述した実施の形態1〜3では、固体撮像素子2の各貫通孔2dは、複数の突起電極2cの外側に形成されていたが、これに限らず、受光部2aの外側であれば、突起電極2cと同列または同行の位置に形成されてもよいし、受光部2aと突起電極2cとの間に形成されてもよい。   In the first to third embodiments described above, each through-hole 2d of the solid-state imaging device 2 is formed outside the plurality of protruding electrodes 2c. Further, it may be formed at the same column or in the same row as the protruding electrode 2c, or may be formed between the light receiving portion 2a and the protruding electrode 2c.

以上のように、本発明にかかる撮像ユニットは、CCDまたはCMOS等の固体撮像素子を備えた撮像ユニットに有用であり、特に、回路基板の熱収縮に起因する固体撮像素子の反りを低減することができる撮像ユニットに適している。   As described above, the imaging unit according to the present invention is useful for an imaging unit including a solid-state imaging device such as a CCD or a CMOS, and particularly reduces the warpage of the solid-state imaging device due to thermal contraction of the circuit board. Suitable for imaging units that can

1,21,31 撮像ユニット
2 固体撮像素子
2a 受光部
2b 駆動回路部
2c 突起電極
2d 貫通孔
3 回路基板
3a 開口部
3b 基板貫通孔
4,6 接着剤
5,35 カバーガラス
5a 嵌合孔
7,27 補正基板
7a 嵌合ピン
10 仮実装体
15 実装体
18 立体構造体
38 枠体
38a 開口部
38b 嵌合孔
1, 2, 31 Image pickup unit 2 Solid-state image pickup device 2a Light receiving portion 2b Drive circuit portion 2c Projection electrode 2d Through hole 3 Circuit board 3a Opening portion 3b Substrate through hole 4, 6 Adhesive 5,35 Cover glass 5a Fitting hole 7, 27 Correction board 7a Fitting pin 10 Temporary mounting body 15 Mounting body 18 Three-dimensional structure 38 Frame body 38a Opening portion 38b Fitting hole

Claims (12)

受光部の外側に複数の貫通孔が形成された固体撮像素子と、
前記受光部に対応する開口部と複数の前記貫通孔に対応する複数の基板貫通孔とが形成され、前記受光部と前記開口部とを対向させて前記固体撮像素子を実装する回路基板と、
一対の前記貫通孔と前記基板貫通孔とを貫通する棒状部材が複数固定され、前記回路基板の熱収縮力に比して強い剛性を有して前記固体撮像素子の反りを補正する補正基板と、
を備えたことを特徴とする撮像ユニット。
A solid-state imaging device in which a plurality of through holes are formed outside the light receiving unit;
An opening corresponding to the light receiving portion and a plurality of substrate through holes corresponding to the plurality of through holes; a circuit board on which the solid-state imaging device is mounted with the light receiving portion and the opening facing each other;
A plurality of rod-shaped members that pass through the pair of through-holes and the substrate through-holes, and a correction substrate that has a rigidity higher than the thermal contraction force of the circuit board and corrects the warp of the solid-state imaging device; ,
An imaging unit comprising:
前記棒状部材は、前記回路基板の熱収縮力に抗して一対の前記貫通孔と前記基板貫通孔との相対位置関係を維持することを特徴とする請求項1に記載の撮像ユニット。   2. The imaging unit according to claim 1, wherein the rod-shaped member maintains a relative positional relationship between the pair of through holes and the substrate through holes against a thermal contraction force of the circuit board. 前記補正基板は、複数の前記貫通孔に複数の前記棒状部材を圧入貫通して前記固体撮像素子を相対的に固定することを特徴とする請求項1または2に記載の撮像ユニット。   3. The imaging unit according to claim 1, wherein the correction substrate press-fits the plurality of rod-shaped members into the plurality of through holes and relatively fixes the solid-state imaging device. 前記補正基板と前記固体撮像素子との熱膨張係数差は、前記固体撮像素子と前記回路基板との熱膨張係数差に比して小さいことを特徴とする請求項1〜3のいずれか一つに記載の撮像ユニット。   The thermal expansion coefficient difference between the correction substrate and the solid-state imaging device is smaller than the thermal expansion coefficient difference between the solid-state imaging device and the circuit board. The imaging unit described in 1. 前記補正基板の熱膨張係数は、前記固体撮像素子の熱膨張係数と同じであることを特徴とする請求項4に記載の撮像ユニット。   The imaging unit according to claim 4, wherein a thermal expansion coefficient of the correction substrate is the same as a thermal expansion coefficient of the solid-state imaging device. 前記補正基板の熱膨張係数は、前記回路基板の熱膨張係数に比して小さいことを特徴とする請求項4または5に記載の撮像ユニット。   The imaging unit according to claim 4, wherein a thermal expansion coefficient of the correction board is smaller than a thermal expansion coefficient of the circuit board. 複数の前記基板貫通孔に対応する複数の嵌合孔が形成され、複数の前記基板貫通孔を貫通して突き出た複数の前記棒状部材を複数の前記嵌合孔に嵌合固定することによって前記補正基板および複数の前記棒状部材を含む立体構造を形成して、前記補正基板による前記固体撮像素子の反りの補正を支援する支援部材をさらに備えたことを特徴とする請求項1〜6のいずれか一つに記載の撮像ユニット。   A plurality of fitting holes corresponding to the plurality of substrate through holes are formed, and the plurality of rod-shaped members protruding through the plurality of substrate through holes are fitted and fixed to the plurality of fitting holes. 7. A support member for forming a three-dimensional structure including a correction substrate and a plurality of the rod-shaped members, and further assisting correction of warpage of the solid-state imaging device by the correction substrate. The imaging unit according to any one of the above. 前記支援部材は、前記回路基板の開口部を閉塞する透光性部材であることを特徴とする請求項7に記載の撮像ユニット。   The imaging unit according to claim 7, wherein the support member is a translucent member that closes an opening of the circuit board. 前記支援部材は、前記回路基板の開口部に連通する開口部が形成された枠体であることを特徴とする請求項7に記載の撮像ユニット。   The imaging unit according to claim 7, wherein the support member is a frame having an opening communicating with the opening of the circuit board. 前記棒状部材は、前記回路基板および前記固体撮像素子がともに熱膨張した際に一対の前記貫通孔と前記基板貫通孔とを貫通することを特徴とする請求項1〜9のいずれか一つに記載の撮像ユニット。   The rod-shaped member penetrates the pair of through-holes and the substrate through-holes when both the circuit board and the solid-state imaging element are thermally expanded. The imaging unit described. 前記棒状部材は、前記回路基板および前記固体撮像素子が熱膨張する以前に一対の前記貫通孔と前記基板貫通孔とを貫通することを特徴とする請求項1〜9のいずれか一つに記載の撮像ユニット。   The said rod-shaped member penetrates a pair of said through-hole and the said board | substrate through-hole before the said circuit board and the said solid-state image sensor thermally expand, The any one of Claims 1-9 characterized by the above-mentioned. Imaging unit. 前記固体撮像素子は、前記受光部の外側に、前記回路基板と電気的に接続される複数の突起電極を備え、
複数の前記貫通孔は、複数の前記突起電極の外側に形成されることを特徴とする請求項1〜11のいずれか一つに記載の撮像ユニット。
The solid-state imaging device includes a plurality of protruding electrodes that are electrically connected to the circuit board on the outside of the light receiving unit,
The imaging unit according to claim 1, wherein the plurality of through holes are formed outside the plurality of protruding electrodes.
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