JP2011063688A - Semiconductor device - Google Patents

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JP2011063688A
JP2011063688A JP2009214556A JP2009214556A JP2011063688A JP 2011063688 A JP2011063688 A JP 2011063688A JP 2009214556 A JP2009214556 A JP 2009214556A JP 2009214556 A JP2009214556 A JP 2009214556A JP 2011063688 A JP2011063688 A JP 2011063688A
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silicon
covering portion
component
curable composition
semiconductor device
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JP5393373B2 (en
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Toru Izumi
徹 泉
Katsunori Asano
勝則 浅野
Yoshitaka Sugawara
良孝 菅原
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Adeka Corp
Kansai Electric Power Co Inc
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Kansai Electric Power Co Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which high heat resistance and high voltage endurance can be attained and adhesiveness between a covering section of a semiconductor device and a support of a semiconductor device can be improved, thus allowing the use thereof in high temperatures. <P>SOLUTION: The semiconductor device includes a first covering section 15 and a second covering section. The first covering section 15, which covers SiC pn diode elements 1 and 2, is formed from a first silicon-containing curable composition which contains a silicon-containing polymer having a cyclic siloxane structure and a linear siloxane structure and a molecular weight of 3,000-1,000,000 and a platinum-based catalyst which is a curing reaction catalyst. The second covering section 16 is produced from a silicon-containing curable composition which covers the whole surface 15A of the first covering section 15 and is not in contact with a support 3. The second covering section 16 is formed from a second silicon-containing curable composition in which alumina particles having a particle size of 20 μm are blended with the first silicon-containing curable composition as insulating ceramics and have a volume filling factor of 50%. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

この発明は、半導体装置に関し、例えば耐熱性が高い高耐電圧パワー半導体装置に関する。   The present invention relates to a semiconductor device, for example, a high withstand voltage power semiconductor device having high heat resistance.

炭化珪素(以下、SiCと記す)等のワイドギャップ半導体材料は、シリコン(以下、Siと記す)に比べて、エネルギーギャップが大きく絶縁破壊電界強度も約1桁大きい等の優れた物理特性を有しているため、高耐熱かつ高耐電圧のパワー半導体装置に用いるのに好適である。   Wide-gap semiconductor materials such as silicon carbide (hereinafter referred to as SiC) have superior physical properties such as a larger energy gap and a breakdown electric field strength that is about one order of magnitude larger than silicon (hereinafter referred to as Si). Therefore, it is suitable for use in a power semiconductor device with high heat resistance and high withstand voltage.

従来、SiCを用いた高耐電圧半導体装置では、例えば高逆耐電圧を有するSiC半導体素子を金属製のパッケージ内に収納し、このパッケージ内に六弗化硫黄ガス等の絶縁用ガスを充填している。これにより、上記SiC半導体素子の高電圧が印加される電極間の周囲の空間における絶縁性を高めている。   Conventionally, in a high withstand voltage semiconductor device using SiC, for example, a SiC semiconductor element having a high reverse withstand voltage is accommodated in a metal package, and an insulating gas such as sulfur hexafluoride gas is filled in the package. ing. Thereby, the insulation in the surrounding space between the electrodes to which the high voltage of the SiC semiconductor element is applied is enhanced.

ここで、上記六弗化硫黄ガスは絶縁用ガスとしては優れた絶縁性を持つが、地球温暖化防止の観点からは使用を避ける必要がある。また、特に、高い絶縁性を得るためには、半導体装置内に充填する六弗化硫黄ガスの圧力を常温で2気圧程度にする必要がある。よって、上記半導体装置の使用中に温度が上昇すると、この圧力は2気圧以上に高くなるので、上記半導体装置のパッケージを相当堅牢にしないと爆発やガス漏れの危険性がある。   Here, the sulfur hexafluoride gas has an excellent insulating property as an insulating gas, but it must be avoided from the viewpoint of preventing global warming. In particular, in order to obtain high insulation, it is necessary to set the pressure of sulfur hexafluoride gas filled in the semiconductor device to about 2 atm. Therefore, when the temperature rises during use of the semiconductor device, this pressure becomes 2 atmospheres or more. Therefore, there is a risk of explosion or gas leakage unless the package of the semiconductor device is made quite robust.

一方、特許文献1(特開2006−206721号公報)では、上記六弗化硫黄ガス以外の物質で半導体装置の高絶縁性を保つために使用される優れた絶縁性を有する材料が提案されている。この材料は、シロキサン(Si−O−Si結合体)による橋かけ構造を有する有機珪素ポリマーとシロキサンによる線状連結構造を有する有機珪素ポリマーとをシロキサン結合により連結させた有機珪素ポリマー同士を、付加反応により生成される共有結合で連結させて三次元の立体構造に形成した合成高分子化合物である。この合成高分子化合物で半導体素子(半導体チップ)全体を覆うように塗布し、常温から200℃程度の温度に加熱して硬化させることで、上記半導体素子の高い絶縁性を保ち耐電圧を高くすることができる。   On the other hand, Patent Document 1 (Japanese Patent Laid-Open No. 2006-206721) proposes a material having an excellent insulating property that is used to maintain a high insulating property of a semiconductor device with a substance other than the above-described sulfur hexafluoride gas. Yes. This material is an addition of an organosilicon polymer having a crosslinked structure of siloxane (Si-O-Si conjugate) and an organosilicon polymer having a linear linkage structure of siloxane linked by a siloxane bond. It is a synthetic polymer compound formed into a three-dimensional structure by linking with covalent bonds generated by the reaction. This synthetic polymer compound is applied so as to cover the entire semiconductor element (semiconductor chip) and is cured by heating from room temperature to about 200 ° C., thereby maintaining the high insulation of the semiconductor element and increasing the withstand voltage. be able to.

また、特許文献1では、図6に示す半導体装置が開示されている。この半導体装置は、半導体素子101に合成高分子化合物を塗布して被覆しさらに熱硬化させた熱硬化被覆102を有する。そして、この半導体装置は、この熱硬化被覆102の表面酸化を防止するため、窒素雰囲気中で金属キャップ103を支持体104に取り付けて溶接し、内部空間105に窒素ガスを充たしたものである。なお、図6において、106,110は端子、107,111は端子106,110と支持体104とを絶縁する絶縁体、108,112は半導体素子101を端子106,110に接続するリード線である。   Patent Document 1 discloses a semiconductor device shown in FIG. This semiconductor device has a thermosetting coating 102 in which a synthetic polymer compound is applied to a semiconductor element 101 and then coated and further thermally cured. In this semiconductor device, in order to prevent surface oxidation of the thermosetting coating 102, the metal cap 103 is attached to the support 104 and welded in a nitrogen atmosphere, and the internal space 105 is filled with nitrogen gas. In FIG. 6, 106 and 110 are terminals, 107 and 111 are insulators that insulate the terminals 106 and 110 and the support 104, and 108 and 112 are lead wires that connect the semiconductor element 101 to the terminals 106 and 110. .

ところで、上記半導体装置では、金属キャップ103と支持体104とを溶接する際、溶接部109に上記被覆102をなす合成高分子化合物がわずかでも付着していると、溶接が不完全となる。すると、窒素ガスを充たしている内部空間105に空気が流入する。この状態で半導体装置を長時間使用すると、装置内部の熱硬化物である被覆102が酸化劣化してしまい、被覆102の絶縁性が低下する。また、金属キャップ103と支持体104は窒素雰囲気中にて溶接する際、特殊な治具を必要とするので、溶接作業には多くの時間とコストを要する。   By the way, in the semiconductor device, when the metal cap 103 and the support 104 are welded, welding is incomplete if a slight amount of the synthetic polymer compound forming the coating 102 adheres to the welded portion 109. Then, air flows into the internal space 105 filled with nitrogen gas. When the semiconductor device is used for a long time in this state, the coating 102 which is a thermosetting material inside the device is oxidized and deteriorated, and the insulating property of the coating 102 is lowered. Further, since the metal cap 103 and the support 104 require a special jig when welding in a nitrogen atmosphere, the welding work requires a lot of time and cost.

一方、トランジスタやIC等に使用されている一般的なエポキシ樹脂を用いて半導体装置をモールドすれば金属キャップは不要になるが、エポキシ樹脂は高温での柔軟性が乏しく、200℃以上になるとガラス化して硬くなってしまう。このため、半導体素子の温度が通電時の高温状態からオフ時の室温状態に戻ると、エポキシ樹脂の内部に多数のクラックが発生し、高電界には耐えることができず、耐電圧性はよくない。   On the other hand, if a semiconductor device is molded using a general epoxy resin used in transistors, ICs, etc., a metal cap is not necessary, but epoxy resin is not flexible at high temperatures, and when it exceeds 200 ° C., glass Will become harder. For this reason, when the temperature of the semiconductor element returns from the high temperature state at the time of energization to the room temperature state at the time of off, a large number of cracks are generated inside the epoxy resin, it cannot withstand a high electric field, and the withstand voltage is good. Absent.

これに対して、上述の合成高分子化合物は高温でも柔軟性を保持するが、この合成高分子化合物を硬化して半導体装置をモールドした場合、この合成高分子化合物と支持体との線膨張係数の違いにより、温度の上昇と降下を繰り返すとモールドが剥がれてしまうという問題がある。   In contrast, the synthetic polymer compound described above retains flexibility even at high temperatures, but when this synthetic polymer compound is cured and a semiconductor device is molded, the linear expansion coefficient between the synthetic polymer compound and the support is determined. Due to this difference, there is a problem that the mold peels off when the temperature rises and falls repeatedly.

そこで、未公開であり従来例ではないが、本出願人による出願(特願2008‐054630)では、図7に示すようなGTOサイリスタ装置が記載されている。このGTOサイリスタ装置は、GTOサイリスタ素子201を覆う被覆部215が、シロキサン(Si−O−Si結合体)による橋かけ構造を一箇所以上有する珪素含有重合体を含有し、かつ硬化反応触媒である白金系触媒、および鉄族含有錆体を含有する珪素含有硬化性組成物で形成されている。また、このGTOサイリスタ装置は、上記被覆部215および支持体211上のアノード端子205,ゲート端子208を覆う被覆部216を有する。この被覆部216は、上記被覆部215を形成する上記珪素含有硬化性組成物に絶縁性セラミックスとして粒径20μmのアルミナ微粒子を50%の体積充填率で配合した珪素含有硬化性組成物で形成されている。なお、図7において、202,206,210はアノード電極,ゲート電極,カソード電極、203,207はリード線、212,213は絶縁材である。   Therefore, although not disclosed and not a conventional example, an application (Japanese Patent Application No. 2008-054630) by the present applicant describes a GTO thyristor device as shown in FIG. In this GTO thyristor device, the covering portion 215 covering the GTO thyristor element 201 contains a silicon-containing polymer having one or more cross-linked structures of siloxane (Si—O—Si conjugate), and is a curing reaction catalyst. It is formed with a silicon-containing curable composition containing a platinum-based catalyst and an iron group-containing rust. Further, this GTO thyristor device has a covering portion 216 that covers the covering portion 215 and the anode terminal 205 and the gate terminal 208 on the support 211. The covering portion 216 is formed of a silicon-containing curable composition in which alumina fine particles having a particle diameter of 20 μm are blended as insulating ceramics with the silicon-containing curable composition forming the covering portion 215 at a volume filling rate of 50%. ing. In FIG. 7, 202, 206 and 210 are anode electrodes, gate electrodes and cathode electrodes, 203 and 207 are lead wires, and 212 and 213 are insulating materials.

上記GTOサイリスタ装置によれば、高い耐熱性と高い耐電圧性を有すると共に高い柔軟性を有する被覆部215でもって、GTOサイリスタ素子201を絶縁できる。また、上記被覆部216は、高温(例えば200℃以上)で使用してもクラック等が発生せず、高絶縁耐力を達成できる。また、上記被覆部216は上記セラミックスが配合されたことで線膨張係数が小さくなり、例えば銅等の金属で作製されてGTOサイリスタ素子201を支持する支持体211との線膨張係数の差を低減させることで、被覆部216と支持体211との密着性の向上を図っている。   According to the GTO thyristor device, the GTO thyristor element 201 can be insulated by the covering portion 215 having high heat resistance, high voltage resistance and high flexibility. In addition, the covering portion 216 does not generate cracks even when used at a high temperature (for example, 200 ° C. or higher), and can achieve high dielectric strength. In addition, the coating portion 216 has a smaller linear expansion coefficient due to the blending of the ceramics, and reduces the difference in linear expansion coefficient from the support 211 made of a metal such as copper and supporting the GTO thyristor element 201. By doing so, the adhesion between the covering portion 216 and the support 211 is improved.

しかし、上記GTOサイリスタ装置でも、被覆部216の線膨張係数150ppmと、銅製とした支持体211の線膨張係数17ppmとの差はかなりあるので、高温(200℃以上)で使用すると、支持体211と被覆部216との間に応力が発生して被覆部216が支持体211から剥離する可能性がある。この被覆部216の剥離が生じた場合、被覆部216による封止機能が損なわれ、GTOサイリスタ装置の信頼性が低下する。   However, even in the GTO thyristor device, since there is a considerable difference between the linear expansion coefficient of 150 ppm of the covering portion 216 and the linear expansion coefficient of 17 ppm of the support 211 made of copper, when used at a high temperature (200 ° C. or more), the support 211 There is a possibility that a stress is generated between the covering portion 216 and the covering portion 216 is peeled off from the support 211. When peeling of this coating | coated part 216 arises, the sealing function by the coating | coated part 216 will be impaired, and the reliability of a GTO thyristor apparatus will fall.

特開2006−206721号公報JP 2006-206721 A 特開2005−325174号公報JP 2005-325174 A 特開2008−266484号公報JP 2008-266484 A

そこで、この発明の課題は、高耐熱性と高耐電圧性を達成できると共に半導体素子の被覆部と半導体素子の支持体との密着性を向上でき、高温での使用を可能にできる半導体装置を提供することにある。   Accordingly, an object of the present invention is to provide a semiconductor device that can achieve high heat resistance and high voltage resistance, improve adhesion between the covering portion of the semiconductor element and the support of the semiconductor element, and can be used at a high temperature. It is to provide.

上記課題を解決するため、この発明の半導体装置は、半導体素子と、
上記半導体素子が載置される支持体と、
上記半導体素子を外部機器に電気的に接続するための電気接続部と、
上記半導体素子および上記半導体素子が載置される上記支持体の上面を被覆すると共に上記電気接続部の少なくとも一部を被覆する珪素含有硬化性組成物で作製された第1の被覆部と、
上記第1の被覆部の表面を被覆すると共に上記支持体に接しない珪素含有硬化性組成物で作製された第2の被覆部とを備え、
上記第1の被覆部を作製する珪素含有硬化性組成物は、
下記の(A)成分、(B)成分および(D)成分を含有する珪素含有硬化性組成物であり、
上記第2の被覆部を作製する珪素含有硬化性組成物は、
下記の(A)成分、(B)成分、(D)成分および (F)成分を含有する珪素含有硬化性組成物であり、
上記第2の被覆部は、上記珪素含有硬化性組成物を熱硬化させた硬化物であり、上記硬化物の線膨張係数が50〜200ppm/℃であることを特徴としている。
(A)成分:下記一般式(1)で表される珪素含有化合物。

Figure 2011063688
(式中、R〜Rは、同一でも異なっていてもよく、炭素原子数1〜12の飽和脂肪族炭化水素基、又は、飽和脂肪族炭化水素基で置換されていてもよい炭素原子数6〜12の芳香族炭化水素基であり(但し、R及びRは同時に炭素原子数1〜12の飽和脂肪族炭化水素基となることはない)、Rは炭素原子数2〜4のアルキレン基であり、Zは炭素原子数2〜4のアルケニル基若しくはアルキニル基であり、aは2〜7の数であり、bは1〜7の数であり、bを繰り返し数とする重合部分と、a−bを繰り返し数とする重合部分とは、ブロック状であってもランダム状であってもよい。eは0〜3の数である。c及びdは、d:c=1:1〜1:100且つ全てのcと全てのdとの合計が15以上となる数であって、且つ一般式(1)で表される珪素含有化合物の質量平均分子量を3000〜100万とする数である。また、cを繰り返し数とする重合部分と、dを繰り返し数とする重合部分とは、ブロック状であってもランダム状であってもよい。)
(B)成分:下記一般式(2)で表される珪素含有化合物。
Figure 2011063688
(式中、R〜R15は、同一でも異なっていてもよく、炭素原子数1〜12の飽和脂肪族炭化水素基、又は、飽和脂肪族炭化水素基で置換されていてもよい炭素原子数6〜12の芳香族炭化水素基であり(但し、R13及びR14は同時に炭素原子数1〜12の飽和脂肪族炭化水素基となることはない)、R16は炭素原子数2〜4のアルキレン基であり、fは2〜7の数であり、gは1〜7の数であり、gを繰り返し数とする重合部分と、f−gを繰り返し数とする重合部分とは、ブロック状であってもランダム状であってもよい。jは0〜3の数である。h及びiは、i:h=1:1〜1:100且つ全てのhと全てのiとの合計が15以上となる数であって、且つ一般式(2)で表される珪素含有化合物の質量平均分子量を3000〜100万とする数である。また、hを繰り返し数とする重合部分と、iを繰り返し数とする重合部分とは、ブロック状であってもランダム状であってもよい。)
(D)成分:白金系触媒である硬化反応触媒
(F)成分:セラミックス粒子 In order to solve the above problems, a semiconductor device of the present invention includes a semiconductor element,
A support on which the semiconductor element is mounted;
An electrical connection for electrically connecting the semiconductor element to an external device;
A first covering portion made of a silicon-containing curable composition that covers the upper surface of the semiconductor element and the support on which the semiconductor element is placed and covers at least a part of the electrical connection portion;
And a second covering portion made of a silicon-containing curable composition that covers the surface of the first covering portion and does not contact the support,
The silicon-containing curable composition for producing the first covering portion is:
A silicon-containing curable composition containing the following component (A), component (B) and component (D):
The silicon-containing curable composition for producing the second covering portion is:
A silicon-containing curable composition containing the following component (A), component (B), component (D) and component (F):
The said 2nd coating | coated part is the hardened | cured material which heat-cured the said silicon-containing curable composition, The linear expansion coefficient of the said hardened | cured material is 50-200 ppm / degreeC, It is characterized by the above-mentioned.
Component (A): A silicon-containing compound represented by the following general formula (1).
Figure 2011063688
(In the formula, R 1 to R 7 may be the same or different and may be substituted with a saturated aliphatic hydrocarbon group having 1 to 12 carbon atoms or a saturated aliphatic hydrocarbon group. An aromatic hydrocarbon group of 6 to 12 (provided that R 5 and R 6 cannot simultaneously become a saturated aliphatic hydrocarbon group of 1 to 12 carbon atoms), and R 8 has 2 to 2 carbon atoms. 4 is an alkylene group, Z is an alkenyl group or alkynyl group having 2 to 4 carbon atoms, a is a number from 2 to 7, b is a number from 1 to 7, and b is a repeating number. The polymerization portion and the polymerization portion having ab as the number of repetitions may be in the form of blocks or random, e is a number from 0 to 3. c and d are d: c = 1: 1 to 1: 100 and the sum of all c and all d is 15 or more, and in general The silicon-containing compound represented by (1) is a number having a mass average molecular weight of 3000 to 1,000,000, and a polymerization part having c as the number of repetitions and a polymerization part having d as the number of repetitions are block-like. Or random.)
Component (B): A silicon-containing compound represented by the following general formula (2).
Figure 2011063688
(In formula, R < 9 > -R < 15 > may be same or different, The carbon atom which may be substituted by the C1-C12 saturated aliphatic hydrocarbon group or a saturated aliphatic hydrocarbon group. An aromatic hydrocarbon group having 6 to 12 carbon atoms (provided that R 13 and R 14 do not simultaneously become a saturated aliphatic hydrocarbon group having 1 to 12 carbon atoms), and R16 has 2 to 4 carbon atoms. F is a number from 2 to 7, g is a number from 1 to 7, and a polymerization portion having g as a repeating number and a polymerization portion having f-g as a repeating number are blocks. J may be a number from 0 to 3. h and i are i: h = 1: 1 to 1: 100 and the sum of all h and all i The number average molecular weight of the silicon-containing compound represented by the general formula (2) is 30 and the number is 15 or more. It is a number 0 to 100 to 250,000. Also, the overlapping portion of the number of repeated h, and the overlapping portion of the number of repeated i, be a block form or a random form.)
Component (D): a curing reaction catalyst that is a platinum-based catalyst
Component (F): Ceramic particles

この発明の半導体装置では、上記半導体素子および上記半導体素子が載置される上記支持体の上面を被覆すると共に電気接続部の少なくとも一部を被覆する第1の被覆部を、珪素含有硬化性組成物で作製した。そして、この珪素含有硬化性組成物は、上記の(A)成分および(B)成分を含有し、かつ硬化反応触媒である白金系触媒を配合している。したがって、この高い耐熱性と高い耐電圧性を有すると共に高い柔軟性を有する第1の被覆部でもって、半導体素子を絶縁できる。   In the semiconductor device of the present invention, the first covering portion that covers the upper surface of the semiconductor element and the support on which the semiconductor element is placed and covers at least a part of the electrical connection portion is provided with a silicon-containing curable composition. It was made with a thing. And this silicon-containing curable composition contains the platinum-type catalyst which contains said (A) component and (B) component, and is a hardening reaction catalyst. Therefore, it is possible to insulate the semiconductor element with the first covering portion having high heat resistance and high voltage resistance and high flexibility.

また、上記第2の被覆部は、上記第1の被覆部の表面を被覆すると共に上記支持体に接しない珪素含有硬化性組成物で作製されている。この第2の被覆部を作製する珪素含有硬化性組成物は、上記の(A)成分および(B)成分を含有し、かつ硬化反応触媒である白金系触媒を含有する珪素含有硬化性組成物に充填剤としてセラミックス粒子を配合している。上記第2の被覆部は高温(例えば200℃以上)で使用してもクラック等が発生せず、高絶縁耐力を達成できる。また、上記第2の被覆部は、上記第1の被覆部の表面を被覆するが上記支持体に接しないので、銅等の金属製あるいはセラミック製の支持体との線膨張係数の差がかなりある第2の被覆部が高温時(例えば200℃以上)に支持体から剥がれることがない。また、第1の被覆部が支持体と第2の被覆部との間で緩衝材として働き、高温時の応力を低減できる。   The second covering portion is made of a silicon-containing curable composition that covers the surface of the first covering portion and does not contact the support. The silicon-containing curable composition for producing the second covering portion contains the above-described component (A) and component (B) and a platinum-based catalyst that is a curing reaction catalyst. Ceramic particles as a filler. Even if the second covering portion is used at a high temperature (for example, 200 ° C. or higher), cracks and the like are not generated, and a high dielectric strength can be achieved. Further, since the second covering portion covers the surface of the first covering portion but does not contact the support, there is a considerable difference in linear expansion coefficient from a metal or ceramic support such as copper. A certain 2nd coating | coated part does not peel from a support body at the time of high temperature (for example, 200 degreeC or more). Moreover, the 1st coating | coated part works as a buffer material between a support body and a 2nd coating | coated part, and can reduce the stress at the time of high temperature.

これにより、この発明の半導体装置によれば、高耐熱性と高耐電圧性を達成できると共に半導体素子の被覆部と半導体素子の支持体との密着性を向上でき、高温での使用を可能にできる。なお、上記第2の被覆部は、上記第1の被覆部の表面全体を被覆することが望ましい。   Thus, according to the semiconductor device of the present invention, high heat resistance and high voltage resistance can be achieved, and the adhesion between the covering portion of the semiconductor element and the support of the semiconductor element can be improved, enabling use at a high temperature. it can. The second covering portion desirably covers the entire surface of the first covering portion.

また、上記セラミックス粒子の粒径は1〜50μmが好ましく、5〜25μmがより好ましい。また、上記第2の被覆部をなす上記珪素含有硬化性組成物に占めるセラミックスの体積充填率は40〜70%であるのが好ましく、50〜60%がより好ましい。これにより、上記珪素含有硬化性組成物を硬化させてなる硬化物の線膨張係数を50〜200ppm/℃、より好ましくは100〜150ppm/℃にすることができる。なお、上記第2の被覆部をなす珪素含有硬化性組成物を硬化させてなる硬化物の線膨張係数を50ppm/℃より小さくすると、第1の被覆部との密着性が悪くなり、絶縁材として作用しなくなる。一方、上記第2の被覆部をなす珪素含有硬化性組成物を硬化させてなる硬化物の線膨張係数を200ppm/℃より大きくすると、半導体装置を保護できる程度の硬度が得られない。   The ceramic particles preferably have a particle size of 1 to 50 μm, more preferably 5 to 25 μm. Moreover, it is preferable that the volume filling rate of the ceramics which occupies for the said silicon-containing curable composition which comprises the said 2nd coating part is 40 to 70%, and 50 to 60% is more preferable. Thereby, the linear expansion coefficient of the hardened | cured material formed by hardening | curing the said silicon-containing curable composition can be 50-200 ppm / degreeC, More preferably, it can be 100-150 ppm / degreeC. In addition, if the linear expansion coefficient of the cured product obtained by curing the silicon-containing curable composition forming the second covering portion is less than 50 ppm / ° C., the adhesion with the first covering portion is deteriorated, and the insulating material No longer works. On the other hand, if the linear expansion coefficient of a cured product obtained by curing the silicon-containing curable composition forming the second covering portion is greater than 200 ppm / ° C., a hardness that can protect the semiconductor device cannot be obtained.

なお、上記(D)成分の白金系触媒は、白金、パラジウム及びロジウムの一種以上の金属を含有し、ヒドロシリル化反応を促進する触媒であり、公知のものを用いることができる。ヒドロシリル化反応用の触媒として用いられる該白金系触媒としては、白金−カルボニルビニルメチル錯体、白金−ジビニルテトラメチルジシロキサン錯体、白金−シクロビニルメチルシロキサン錯体、白金−オクチルアルデヒド錯体等が挙げられるほか、これらの触媒における白金を、同じく白金系金属であるパラジウムまたはロジウムに代えた化合物が挙げられ、これらは一種で用いてもよく又は二種以上を併用してもよい。硬化性の点から、白金を含有するものが好ましく、具体的には、白金−カルボニルビニルメチル錯体が特に好ましい。また、クロロトリストリフェニルホスフィンロジウム(I)等の、上記白金系金属を含有するいわゆるWilkinson触媒も、(D)成分の白金系触媒に含まれる。   The platinum catalyst of the component (D) is a catalyst that contains one or more metals of platinum, palladium, and rhodium and promotes the hydrosilylation reaction, and known ones can be used. Examples of the platinum-based catalyst used as a catalyst for hydrosilylation reaction include platinum-carbonylvinylmethyl complex, platinum-divinyltetramethyldisiloxane complex, platinum-cyclovinylmethylsiloxane complex, platinum-octylaldehyde complex and the like. The compounds in which platinum in these catalysts is replaced with palladium or rhodium, which are also platinum-based metals, may be used, and these may be used alone or in combination of two or more. From the viewpoint of curability, those containing platinum are preferred, and specifically, platinum-carbonylvinylmethyl complexes are particularly preferred. In addition, so-called Wilkinson catalysts containing the above platinum-based metals, such as chlorotristriphenylphosphine rhodium (I), are also included in the platinum catalyst of component (D).

また、上記(F)成分のセラミックス粒子の例としては、コロイダルシリカ、シリカフィラー、シリカゲル、マイカやモンモリロナイト等の鉱物、酸化アルミニウムや酸化亜鉛、二酸化珪素等の金属酸化物、窒化珪素、窒化アルミニウム、窒化ホウ素、炭化珪素等のセラミックス等が挙げられる。耐熱性の点から、酸化アルミニウムが好ましい。   Examples of the ceramic particles of the component (F) include colloidal silica, silica filler, silica gel, minerals such as mica and montmorillonite, metal oxides such as aluminum oxide, zinc oxide, and silicon dioxide, silicon nitride, aluminum nitride, Examples thereof include ceramics such as boron nitride and silicon carbide. Aluminum oxide is preferable from the viewpoint of heat resistance.

また、この発明によれば、上記第2の被覆部をなす硬化物の線膨張係数が50ppm/℃以上なので、第1の被覆部との密着性が良く、かつ、上記硬化物の線膨張係数が200ppm/℃以下なので、半導体装置を保護できる程度の硬度が得られる。   Moreover, according to this invention, since the linear expansion coefficient of the hardened | cured material which comprises the said 2nd coating | coated part is 50 ppm / degrees C or more, adhesiveness with a 1st coating | coated part is good and the linear expansion coefficient of the said hardened | cured material is good. Is 200 ppm / ° C. or less, a hardness sufficient to protect the semiconductor device can be obtained.

また、一実施形態の半導体装置では、上記第1の被覆部は、上記(F)成分を含有し、
さらに、上記第1の被覆部に表面が被覆されていると共に上記半導体素子を直接被覆する第3の被覆部と、
上記第2の被覆部に表面が被覆されていると共に上記第1の被覆部を直接被覆する第4の被覆部とを備え、
上記第3の被覆部および第4の被覆部を作製する珪素含有硬化性組成物は、
上記の(A)成分、(B)成分、(D)成分および(F)成分を含有する珪素含有硬化性組成物であり、
上記第3および第4の被覆部を作製する珪素含有硬化性組成物の成分の内の上記(F)成分の含有重量%が上記第2の被覆部を作製する珪素含有硬化性組成物の成分の内の上記(F)成分の含有重量%よりも低い。
In the semiconductor device of one embodiment, the first covering portion contains the component (F),
Further, a third covering portion whose surface is coated on the first covering portion and directly covering the semiconductor element;
A surface of the second covering portion is coated and a fourth covering portion that directly covers the first covering portion;
The silicon-containing curable composition for producing the third covering portion and the fourth covering portion is:
A silicon-containing curable composition containing the above component (A), component (B), component (D) and component (F),
Of the components of the silicon-containing curable composition for producing the third and fourth coating parts, the content (%) of the component (F) is a component of the silicon-containing curable composition for producing the second coating part. The content is lower than the content (%) of the component (F).

この実施形態の半導体装置によれば、上記半導体素子を直接被覆する第3の被覆部および上記第1の被覆部を直接被覆する第4の被覆部の成分の内の上記(F)成分の含有重量%を第1,第2の被覆部の成分の内の上記(F)成分の含有重量%よりも低くした。これにより、上記第3,第4の被覆部の粘度と接着力を、上記第1,第2の被覆部の粘度と接着力に比べて高くすることができる。なお、上記第3,第4の被覆部の(F)成分の含有重量%を、5%以下にすることが望ましい。また、上記第3,第4の被覆部の(F)成分の含有重量%を略零%とすることがより好ましい。   According to the semiconductor device of this embodiment, inclusion of the component (F) among the components of the third covering portion that directly covers the semiconductor element and the fourth covering portion that directly covers the first covering portion. % By weight was lower than the content% by weight of the component (F) in the components of the first and second coating parts. Thereby, the viscosity and adhesive force of the said 3rd, 4th coating | coated part can be made high compared with the viscosity and adhesive force of the said 1st, 2nd coating | coated part. In addition, it is desirable that the content weight% of the component (F) in the third and fourth covering portions is 5% or less. Further, it is more preferable that the content% by weight of the component (F) in the third and fourth covering portions is substantially zero%.

また、一実施形態の半導体装置では、上記半導体素子と上記支持体との間に配置されたセラミック絶縁基板を備える。   In one embodiment, the semiconductor device includes a ceramic insulating substrate disposed between the semiconductor element and the support.

この実施形態の半導体装置によれば、上記半導体素子を上記セラミック絶縁基板で上記支持体から絶縁できる。なお、上記セラミック絶縁基板は、一例として酸化アルミニウム,窒化アルミニウム,窒化ケイ素等で作製される。   According to the semiconductor device of this embodiment, the semiconductor element can be insulated from the support by the ceramic insulating substrate. The ceramic insulating substrate is made of aluminum oxide, aluminum nitride, silicon nitride or the like as an example.

また、一実施形態の半導体装置では、上記支持体は、銅,アルミニウムのような金属、または、Al‐SiCのような金属と半導体の複合材料、または、銅とモリブデン等の異種金属の積層構造材料で作製されている。   In one embodiment of the semiconductor device, the support is made of a metal such as copper or aluminum, a composite material of a metal and a semiconductor such as Al-SiC, or a stacked structure of different metals such as copper and molybdenum. Made of material.

また、一実施形態の半導体装置では、上記支持体の表面が金またはニッケル等でメッキされている。   In one embodiment, the surface of the support is plated with gold or nickel.

また、一実施形態の半導体装置では、上記支持体上に配置されていると共に上記第1および第2の被覆部の側面を覆う枠を備える。   In one embodiment, the semiconductor device includes a frame that is disposed on the support and covers the side surfaces of the first and second cover portions.

この実施形態の半導体装置によれば、第1,第2の被覆部の側面付近の強度を向上できる。   According to the semiconductor device of this embodiment, the strength in the vicinity of the side surfaces of the first and second covering portions can be improved.

また、一実施形態の半導体装置では、上記半導体素子が、ワイドギヤップ半導体で作製されたワイドギヤップ半導体素子である。   In one embodiment, the semiconductor element is a wide gear semiconductor element made of a wide gear semiconductor.

この実施形態の半導体装置によれば、高い耐熱性と高い耐電圧性を有すると共に高い柔軟性を有する第1の被覆部でもって、SiCもしくはGaNあるいはその他のワイドギャップ半導体で作製されたワイドギヤップ半導体素子を絶縁でき、上記第1の被覆部の表面全体を被覆するが上記支持体に接しない上記第2の被覆部は高温(例えば200℃以上)で使用してもクラック等が発生せず、高絶縁耐力を達成できる。   According to the semiconductor device of this embodiment, a wide gearup semiconductor made of SiC, GaN, or other wide gap semiconductor with the first covering portion having high heat resistance and high voltage resistance and high flexibility. The element can be insulated, and the second covering portion that covers the entire surface of the first covering portion but is not in contact with the support does not generate cracks even when used at a high temperature (eg, 200 ° C. or higher). High dielectric strength can be achieved.

また、一実施形態の半導体装置では、上記第2の被覆部の珪素含有硬化性組成物が、硬化性およびハンドリング性の点から、体積充填率が40〜70%のセラミックス粒子を含有することが望ましい。   In one embodiment, the silicon-containing curable composition of the second covering portion may contain ceramic particles having a volume filling rate of 40 to 70% from the viewpoint of curability and handling properties. desirable.

この発明の半導体装置によれば、環状シロキサン構造と鎖状シロキサン構造とを有し、分子量が3000〜100万である珪素含有重合体を含有し、かつ硬化反応触媒である白金系触媒を配合している珪素含有硬化性組成物で作製した高い耐熱性と高い耐電圧性を有すると共に高い柔軟性を有する第1の被覆部でもって、半導体素子を被覆して半導体素子を絶縁できる。   According to the semiconductor device of the present invention, a platinum-based catalyst that has a cyclic siloxane structure and a chain siloxane structure, contains a silicon-containing polymer having a molecular weight of 3000 to 1,000,000, and is a curing reaction catalyst is blended. The semiconductor element can be covered and insulated with the first covering portion having high heat resistance and high voltage resistance and high flexibility, which is manufactured from the silicon-containing curable composition.

また、上記第1の被覆部の表面を被覆する第2の被覆部を、環状シロキサン構造と鎖状シロキサン構造とを有し、分子量が3000〜100万である珪素含有重合体を含有し、かつ硬化反応触媒である白金系触媒を含有する珪素含有硬化性組成物に充填剤としてセラミックス粒子を配合している珪素含有硬化性組成物で作製したから、高温(例えば200℃以上)で使用してもクラック等が発生せず、高絶縁耐力を達成できる上に、上記第2の被覆部は上記支持体に接しないので、高温時(例えば200℃以上)に支持体との線膨張係数の差で剥がれることがなく、また、第1の被覆部が支持体と第2の被覆部との間で緩衝材として働き、高温時の応力を低減できる。   The second covering portion covering the surface of the first covering portion contains a silicon-containing polymer having a cyclic siloxane structure and a chain siloxane structure and having a molecular weight of 3000 to 1,000,000, and Since a silicon-containing curable composition containing ceramic particles as a filler in a silicon-containing curable composition containing a platinum-based catalyst that is a curing reaction catalyst was used, it was used at a high temperature (eg, 200 ° C. or higher). In addition, cracks and the like are not generated, and a high dielectric strength can be achieved. Further, since the second covering portion does not contact the support, the difference in linear expansion coefficient from the support at a high temperature (for example, 200 ° C. or higher). And the first covering portion acts as a cushioning material between the support and the second covering portion, and stress at high temperatures can be reduced.

これにより、この発明の半導体装置によれば、高耐熱性と高耐電圧性を達成できると共に半導体素子の被覆部と半導体素子の支持体との密着性を向上でき、高温での使用を可能にできる。   Thus, according to the semiconductor device of the present invention, high heat resistance and high voltage resistance can be achieved, and the adhesion between the covering portion of the semiconductor element and the support of the semiconductor element can be improved, enabling use at a high temperature. it can.

この発明の半導体装置の第1実施形態であるSiC GTOサイリスタを備えた半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device provided with the SiC GTO thyristor which is 1st Embodiment of the semiconductor device of this invention. この発明の半導体装置の第3実施形態であるSiC GTOサイリスタを備えた半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device provided with the SiC GTO thyristor which is 3rd Embodiment of the semiconductor device of this invention. この発明の半導体装置の第4実施形態であるSiC GTOサイリスタを備えた半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device provided with the SiC GTO thyristor which is 4th Embodiment of the semiconductor device of this invention. この発明の半導体装置の第5実施形態であるSiC GTOサイリスタを備えた半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device provided with the SiC GTO thyristor which is 5th Embodiment of the semiconductor device of this invention. 上記第3実施形態の変形例を示す断面図である。It is sectional drawing which shows the modification of the said 3rd Embodiment. 従来の半導体装置を示す断面図である。It is sectional drawing which shows the conventional semiconductor device. 参考例のGTOサイリスタ装置の断面図である。It is sectional drawing of the GTO thyristor apparatus of a reference example.

以下、この発明を図示の実施の形態により詳細に説明する。なお、この発明はこれらの実施形態により限定されるものではない。   Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. Note that the present invention is not limited to these embodiments.

(第1の実施の形態)
図1は、この発明の半導体装置の第1実施形態の断面図である。この第1実施形態の半導体装置は、耐圧5kVのSiC GTOサイリスタ素子1を有し、このSiC サイリスタ素子1を銅製の支持体3の上面3Aに載置している。
(First embodiment)
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. The semiconductor device according to the first embodiment includes a SiC GTO thyristor element 1 having a withstand voltage of 5 kV, and this SiC thyristor element 1 is mounted on an upper surface 3A of a support 3 made of copper.

このSiC GTOサイリスタ素子1のアノード電極2はアルミニウム,金,銅等で作製されるリード線7によりアノード端子10の上端に接続されている。また、GTOサイリスタ素子1のゲート電極6は、アルミニウム,金,銅等で作製されるリード線8によりゲート端子11の上端に接続されている。このリード線7,8と、アノード端子10およびゲート端子11は電気接続部である。   The anode electrode 2 of the SiC GTO thyristor element 1 is connected to the upper end of the anode terminal 10 by a lead wire 7 made of aluminum, gold, copper or the like. The gate electrode 6 of the GTO thyristor element 1 is connected to the upper end of the gate terminal 11 by a lead wire 8 made of aluminum, gold, copper or the like. The lead wires 7, 8 and the anode terminal 10 and the gate terminal 11 are electrical connection portions.

また、上記SiC GTOサイリスタ素子1のカソード電極4はカソード端子であるパッケージの銅製の支持体3に金シリコン,金スズ,金ゲルマニウムのような金系半田やその他の高温用半田を用いて電気的接続を保って取り付けられている。アノード端子10およびゲート端子11はそれぞれ絶縁材14,19で支持体3との間の絶縁を保ちつつ支持体3を貫通して固定されている。   Further, the cathode electrode 4 of the SiC GTO thyristor element 1 is electrically connected to the copper support 3 of the package as a cathode terminal by using a gold-based solder such as gold silicon, gold tin, gold germanium or other high-temperature solder. It is attached to keep the connection. The anode terminal 10 and the gate terminal 11 are fixed through the support 3 while maintaining insulation between the anode terminal 10 and the gate terminal 11 with the insulating materials 14 and 19, respectively.

上記SiC GTOサイリスタ素子1の全表面、およびリード線7,8とSiC GTOサイリスタ素子1との接続部近傍、および支持体3の上面3Aの大部分と、支持体3の上面3Aから突出したアノード端子10,ゲート端子11を覆うように、第1の被覆部である被覆部15となる第1の珪素含有硬化性組成物が塗布されている。   The entire surface of the SiC GTO thyristor element 1, the vicinity of the connecting portion between the lead wires 7 and 8 and the SiC GTO thyristor element 1, most of the upper surface 3 A of the support 3, and the anode protruding from the upper surface 3 A of the support 3 A first silicon-containing curable composition is applied so as to cover the terminal 10 and the gate terminal 11 and serve as the covering portion 15 as the first covering portion.

この第1の被覆部15として使用される第1の珪素含有硬化性組成物は、次に説明する合成工程1から合成工程5によって合成した。なお、この合成工程1〜5において「部」とは重量部を表す。上記第1の珪素含有硬化性組成物を250℃にて3時間硬化反応させることにより第1の被覆部15が得られる。   The first silicon-containing curable composition used as the first covering portion 15 was synthesized by the synthesis step 1 to the synthesis step 5 described below. In the synthesis steps 1 to 5, “part” represents part by weight. The 1st coating | coated part 15 is obtained by carrying out hardening reaction of the said 1st silicon containing curable composition at 250 degreeC for 3 hours.

さらに、この実施形態では、上記第1の被覆部15の全表面15Aを覆うが第1の被覆部15から露出した支持体3の部分3Bは覆わず支持体3に接しないように、第2の被覆部16となる第2の珪素含有硬化性組成物が塗布されている。この第2の被覆部16として使用される第2の珪素含有硬化性組成物は上記第1の珪素含有硬化性組成物に絶縁性セラミックスとして粒径20μmのアルミナ微粒子を50%の体積充填率で配合している。この第2の珪素含有硬化性組成物を200℃にて6時間硬化反応させることにより第1の被覆部16が得られる。また、上記硬化後の第2の珪素含有硬化性組成物の線膨張係数は150ppm/℃である。   Further, in this embodiment, the second surface is covered so that the entire surface 15A of the first covering portion 15 is covered but the portion 3B of the supporting body 3 exposed from the first covering portion 15 is not covered and does not contact the supporting body 3. The 2nd silicon-containing curable composition used as the coating | coated part 16 is apply | coated. The second silicon-containing curable composition used as the second covering portion 16 is composed of alumina fine particles having a particle diameter of 20 μm as insulating ceramics in the first silicon-containing curable composition at a volume filling rate of 50%. It is blended. The 1st coating | coated part 16 is obtained by making this 2nd silicon-containing curable composition make hardening reaction at 200 degreeC for 6 hours. The linear expansion coefficient of the second silicon-containing curable composition after curing is 150 ppm / ° C.

〔合成工程1〕 ジクロロジメチルシラン90部とジクロロジフェニルシラン9部とを混合し、100部のイオン交換水、50部のトルエン及び450部の48%水酸化ナトリウム水溶液の混合物中に滴下し、105℃で5時間重合させた。得られた反応溶液を500部のイオン交換水で水洗した後、このトルエン溶液を脱水し、ピリジンを20部加え、これにさらにジメチルクロロシラン20部を加えて70℃で30分間攪拌した。その後、100部のイオン交換水で水洗した後、150℃で溶媒を減圧留去した。次に100部のアセトニトリルで洗浄し、その後、70℃で溶媒を減圧留去し、鎖状ポリシロキサン化合物(HSi−1)を得た。鎖状ポリシロキサン化合物(HSi−1)のGPCによる分子量はMw=20,000であった。   [Synthesis step 1] 90 parts of dichlorodimethylsilane and 9 parts of dichlorodiphenylsilane were mixed and dropped into a mixture of 100 parts of ion-exchanged water, 50 parts of toluene and 450 parts of 48% aqueous sodium hydroxide, Polymerization was carried out at 5 ° C. for 5 hours. The obtained reaction solution was washed with 500 parts of ion exchange water, and then this toluene solution was dehydrated, 20 parts of pyridine was added, 20 parts of dimethylchlorosilane was further added thereto, and the mixture was stirred at 70 ° C. for 30 minutes. Then, after washing with 100 parts of ion exchange water, the solvent was distilled off under reduced pressure at 150 ° C. Next, it was washed with 100 parts of acetonitrile, and then the solvent was distilled off under reduced pressure at 70 ° C. to obtain a chain polysiloxane compound (HSi-1). The molecular weight by GPC of the chain polysiloxane compound (HSi-1) was Mw = 20,000.

〔合成工程2〕上記合成工程1で得られた非環状ポリシロキサン化合物(HSi−1)100部をトルエン200部に溶かし、白金系触媒として白金−カルボニルビニルメチル錯体0.003部、及び不飽和結合を有する環状ポリシロキサン化合物である1,3,5,7−テトラメチル−1,3,5,7−テトラビニルシクロテトラシロキサン10部を加え、105℃で2時間反応させた。70℃で溶媒を減圧留去した後にアセトニトリル100部で洗浄した。その後、70℃で溶媒を減圧留去し、珪素含有化合物(VSi−1)を得た。珪素含有化合物(VSi−1)は、前記一般式(1)に該当する化合物であり、GPCによる分析の結果、Mw=22,000であった。   [Synthesis Step 2] 100 parts of the acyclic polysiloxane compound (HSi-1) obtained in Synthesis Step 1 above is dissolved in 200 parts of toluene, 0.003 part of platinum-carbonylvinylmethyl complex as a platinum-based catalyst, and unsaturated 10 parts of 1,3,5,7-tetramethyl-1,3,5,7-tetravinylcyclotetrasiloxane, which is a cyclic polysiloxane compound having a bond, was added and reacted at 105 ° C. for 2 hours. The solvent was distilled off under reduced pressure at 70 ° C. and then washed with 100 parts of acetonitrile. Thereafter, the solvent was distilled off under reduced pressure at 70 ° C. to obtain a silicon-containing compound (VSi-1). The silicon-containing compound (VSi-1) is a compound corresponding to the general formula (1), and as a result of analysis by GPC, Mw = 22,000.

〔合成工程3〕 ジクロロジメチルシラン90部とジクロロジフェニルシラン9部とを混合し、100部のイオン交換水、50部のトルエン及び450部の48%水酸化ナトリウム水溶液の混合物中に滴下し、105℃で5時間重合させた。得られた反応溶液を500部のイオン交換水で水洗した後に、このトルエン溶液を脱水し、ピリジンを20部加え、これにさらにジメチルビニルクロロシラン20部を加えて70℃で30分間攪拌した。その後、100部のイオン交換水で水洗した後、150℃で溶媒を減圧留去した。次に100部のアセトニトリルで洗浄し、その後、70℃で溶媒を減圧留去し、不飽和結合を有する鎖状ポリシロキサン化合物(VSi−2)を得た。不飽和結合を有する鎖状ポリシロキサン化合物(VSi−2)のGPCによる分子量はMw=20,000であった。   [Synthesis Step 3] 90 parts of dichlorodimethylsilane and 9 parts of dichlorodiphenylsilane were mixed and dropped into a mixture of 100 parts of ion exchange water, 50 parts of toluene and 450 parts of 48% aqueous sodium hydroxide, Polymerization was carried out at 5 ° C. for 5 hours. The obtained reaction solution was washed with 500 parts of ion exchange water, and then this toluene solution was dehydrated, 20 parts of pyridine was added, 20 parts of dimethylvinylchlorosilane was further added, and the mixture was stirred at 70 ° C. for 30 minutes. Then, after washing with 100 parts of ion exchange water, the solvent was distilled off under reduced pressure at 150 ° C. Next, it was washed with 100 parts of acetonitrile, and then the solvent was distilled off under reduced pressure at 70 ° C. to obtain a chain polysiloxane compound (VSi-2) having an unsaturated bond. The molecular weight by GPC of the chain polysiloxane compound (VSi-2) having an unsaturated bond was Mw = 20,000.

〔合成工程4〕上記合成工程1で得られた不飽和結合を有する非環状ポリシロキサン化合物(VSi−2)100部をトルエン200部に溶かし、白金系触媒として白金−カルボニルビニルメチル錯体0.003部、及び環状ポリシロキサン化合物である1,3,5,7−テトラメチルシクロテトラシロキサン10部を加え、105℃で2時間反応させた。70℃で溶媒を減圧留去した後にアセトニトリル100部で洗浄した。その後、70℃で溶媒を減圧留去し、珪素含有化合物(HSi−2)を得た。珪素含有化合物(HSi−2)は、前記一般式(2)に相当する化合物であり、GPCによる分子量は、Mw=22,000であった。   [Synthesis Step 4] 100 parts of an acyclic polysiloxane compound (VSi-2) having an unsaturated bond obtained in Synthesis Step 1 above is dissolved in 200 parts of toluene, and a platinum-carbonylvinylmethyl complex 0.003 as a platinum catalyst. And 10 parts of 1,3,5,7-tetramethylcyclotetrasiloxane, which is a cyclic polysiloxane compound, were added and reacted at 105 ° C. for 2 hours. The solvent was distilled off under reduced pressure at 70 ° C. and then washed with 100 parts of acetonitrile. Thereafter, the solvent was distilled off under reduced pressure at 70 ° C. to obtain a silicon-containing compound (HSi-2). The silicon-containing compound (HSi-2) is a compound corresponding to the general formula (2), and the molecular weight by GPC was Mw = 22,000.

〔合成工程5〕(A)成分として上記合成工程2で得られた珪素含有化合物(VSi−1)50部と(B)成分として上記合成工程4で得られた珪素含有化合物(HSi−2)50部とを混合したものに、(D)成分として白金系触媒である白金−カルボニルビニルメチル錯体0.005部を混合して、上記第一の珪素含有硬化性組成物を得た。   [Synthesis step 5] 50 parts of the silicon-containing compound (VSi-1) obtained in the synthesis step 2 as the component (A) and the silicon-containing compound (HSi-2) obtained in the synthesis step 4 as the component (B) To the mixture of 50 parts, 0.005 part of a platinum-carbonylvinylmethyl complex, which is a platinum-based catalyst, was mixed as component (D) to obtain the first silicon-containing curable composition.

この実施形態によれば、第2の被覆部16となる第2の珪素含有硬化性組成物は上記第1の珪素含有硬化性組成物にセラミックスとしての粒径20μmのアルミナ微粒子を50%の体積充填率で配合している。そして、この第2の珪素含有硬化性組成物を200℃にて6時間硬化反応させることにより第2の被覆部16とした。上記硬化後の第2の珪素含有硬化性組成物の線膨張係数は150ppm/℃である。この実施形態によれば、上記第2の被覆部16は高温(例えば200℃以上)で使用してもクラック等が発生せず、高絶縁耐力を達成できる。また、この第2の被覆部16は支持体3に接しないので、高温時(例えば200℃以上)に支持体3との線膨張係数の差で剥がれることがなく、また、第1の被覆部15が支持体3と第2の被覆部16との間で緩衝材として働き、高温時の応力を低減できる。   According to this embodiment, the second silicon-containing curable composition to be the second covering portion 16 is composed of 50% volume of alumina fine particles having a particle diameter of 20 μm as ceramics in the first silicon-containing curable composition. It is blended at the filling rate. The second silicon-containing curable composition was subjected to a curing reaction at 200 ° C. for 6 hours to obtain the second covering portion 16. The linear expansion coefficient of the second silicon-containing curable composition after curing is 150 ppm / ° C. According to this embodiment, even if the second covering portion 16 is used at a high temperature (for example, 200 ° C. or higher), cracks and the like do not occur, and a high dielectric strength can be achieved. Further, since the second covering portion 16 does not come into contact with the support 3, the second covering portion 16 does not peel off due to a difference in linear expansion coefficient from the support 3 at a high temperature (for example, 200 ° C. or more), and the first covering portion 16 15 acts as a cushioning material between the support 3 and the second covering portion 16, and can reduce stress at high temperatures.

なお、上記第1,第2の珪素含有硬化性組成物が含有する上記珪素含有重合体(A),(B)としては、次に示す組成のものを採用できる。   The silicon-containing polymers (A) and (B) contained in the first and second silicon-containing curable compositions may be those having the following compositions.

珪素含有重合体(A)成分:下記(A)成分:下記一般式(1)で表される珪素含有化合物。

Figure 2011063688
(式中、R〜Rは、同一でも異なっていてもよく、炭素原子数1〜12の飽和脂肪族炭化水素基、又は、飽和脂肪族炭化水素基で置換されていてもよい炭素原子数6〜12の芳香族炭化水素基であり(但し、R及びRは同時に炭素原子数1〜12の飽和脂肪族炭化水素基となることはない)、Rは炭素原子数2〜4のアルキレン基であり、Zは炭素原子数2〜4のアルケニル基若しくはアルキニル基であり、aは2〜7の数であり、bは1〜7の数であり、bを繰り返し数とする重合部分と、a−bを繰り返し数とする重合部分とは、ブロック状であってもランダム状であってもよい。eは0〜3の数である。c及びdは、d:c=1:1〜1:100且つ全てのcと全てのdとの合計が15以上となる数であって、且つ一般式(1)で表される珪素含有化合物の質量平均分子量を3000〜100万とする数である。また、cを繰り返し数とする重合部分と、dを繰り返し数とする重合部分とは、ブロック状であってもランダム状であってもよい。) Silicon-containing polymer (A) component: The following (A) component: A silicon-containing compound represented by the following general formula (1).
Figure 2011063688
(In the formula, R 1 to R 7 may be the same or different and may be substituted with a saturated aliphatic hydrocarbon group having 1 to 12 carbon atoms or a saturated aliphatic hydrocarbon group. An aromatic hydrocarbon group of 6 to 12 (provided that R 5 and R 6 cannot simultaneously become a saturated aliphatic hydrocarbon group of 1 to 12 carbon atoms), and R 8 has 2 to 2 carbon atoms. 4 is an alkylene group, Z is an alkenyl group or alkynyl group having 2 to 4 carbon atoms, a is a number from 2 to 7, b is a number from 1 to 7, and b is a repeating number. The polymerization portion and the polymerization portion having ab as the number of repetitions may be in the form of blocks or random, e is a number from 0 to 3. c and d are d: c = 1: 1 to 1: 100 and the sum of all c and all d is 15 or more, and in general The silicon-containing compound represented by (1) is a number having a mass average molecular weight of 3000 to 1,000,000, and a polymerization part having c as the number of repetitions and a polymerization part having d as the number of repetitions are block-like. Or random.)

珪素含有重合体(B)成分:下記一般式(2)で表される珪素含有化合物。

Figure 2011063688
(式中、R〜R15は、同一でも異なっていてもよく、炭素原子数1〜12の飽和脂肪族炭化水素基、又は、飽和脂肪族炭化水素基で置換されていてもよい炭素原子数6〜12の芳香族炭化水素基であり(但し、R13及びR14は同時に炭素原子数1〜12の飽和脂肪族炭化水素基となることはない)、R16は炭素原子数2〜4のアルキレン基であり、
fは2〜7の数であり、gは1〜7の数であり、gを繰り返し数とする重合部分と、f−gを繰り返し数とする重合部分とは、ブロック状であってもランダム状であってもよい。jは0〜3の数である。h及びiは、i:h=1:1〜1:100且つ全てのhと全てのiとの合計が15以上となる数であって、且つ一般式(2)で表される珪素含有化合物の質量平均分子量を3000〜100万とする数である。また、hを繰り返し数とする重合部分と、iを繰り返し数とする重合部分とは、ブロック状であってもランダム状であってもよい。) Silicon-containing polymer (B) component: A silicon-containing compound represented by the following general formula (2).
Figure 2011063688
(In formula, R < 9 > -R < 15 > may be same or different, The carbon atom which may be substituted by the C1-C12 saturated aliphatic hydrocarbon group or a saturated aliphatic hydrocarbon group. An aromatic hydrocarbon group having a number of 6 to 12 (provided that R 13 and R 14 do not simultaneously become a saturated aliphatic hydrocarbon group having 1 to 12 carbon atoms), and R 16 has 2 to 2 carbon atoms. 4 alkylene groups,
f is a number from 2 to 7, g is a number from 1 to 7, and the polymerization part having g as the number of repetitions and the polymerization part having f-g as the number of repetitions are random even in a block form. It may be a shape. j is a number from 0 to 3. h and i are numbers in which i: h = 1: 1 to 1: 100, and the sum of all h and all i is 15 or more, and is a silicon-containing compound represented by the general formula (2) The number average molecular weight is 3000 to 1,000,000. Moreover, the polymer part having h as the number of repetitions and the polymer part having i as the number of repetitions may be in a block form or in a random form. )

また、上記第2の被覆部16をなす第2の珪素含有硬化性組成物が含有するセラミックス粒子の粒径は1〜50μmが好ましく、5〜25μmがより好ましい。また、上記第2の珪素含有硬化性組成物に占めるセラミックス粒子の体積充填率は40〜70%であるのが好ましく、50〜60%がより好ましい。これにより、上記第2の珪素含有硬化性組成物を硬化させてなる硬化物の線膨張係数を50〜200ppm/℃、より好ましくは100〜150ppm/℃にすることができる。なお、上記第2の被覆部16をなす第2の珪素含有硬化性組成物を硬化させてなる硬化物の線膨張係数を50ppm/℃より小さくすると、第1の被覆部15との密着性が悪くなり、絶縁材として作用しなくなる。一方、上記第2の被覆部16をなす第2の珪素含有硬化性組成物を硬化させてなる硬化物の線膨張係数を200ppm/℃より大きくすると、半導体装置を保護できる程度の硬度が得られない。   Moreover, 1-50 micrometers is preferable and, as for the particle size of the ceramic particle which the 2nd silicon-containing curable composition which comprises the said 2nd coating part 16 contains, 5-25 micrometers is more preferable. Moreover, it is preferable that the volume filling rate of the ceramic particle which occupies for said 2nd silicon containing curable composition is 40 to 70%, and 50 to 60% is more preferable. Thereby, the linear expansion coefficient of the hardened | cured material formed by hardening | curing the said 2nd silicon containing curable composition can be 50-200 ppm / degreeC, More preferably, it can be 100-150 ppm / degreeC. In addition, when the linear expansion coefficient of the hardened | cured material which hardens the 2nd silicon-containing curable composition which comprises the said 2nd coating part 16 is made smaller than 50 ppm / degrees C, the adhesiveness with the 1st coating part 15 will be sufficient. It becomes worse and does not act as an insulating material. On the other hand, when the linear expansion coefficient of the cured product obtained by curing the second silicon-containing curable composition forming the second covering portion 16 is greater than 200 ppm / ° C., a hardness that can protect the semiconductor device is obtained. Absent.

また、上記第2の被覆部16をなす第2の珪素含有硬化性組成物は絶縁性セラミックス微粒子を含有することで、上記第2の珪素含有硬化性組成物のガスバリア性が向上する。すなわち、上記第2の珪素含有硬化性組成物は酸化劣化しにくくなる。   In addition, the second silicon-containing curable composition forming the second covering portion 16 contains insulating ceramic fine particles, whereby the gas barrier property of the second silicon-containing curable composition is improved. That is, the second silicon-containing curable composition is less susceptible to oxidative degradation.

(第2の実施の形態)
次に、この発明の半導体装置の第2実施形態を説明する。この第2実施形態は、前述の第1実施形態における第1の被覆部15および第2の被覆部16を形成する珪素含有硬化性組成物の組成が、前述の第1実施形態と異なる。よって、この第2実施形態では、前述の第1実施形態と異なる点を説明する。
(Second Embodiment)
Next, a second embodiment of the semiconductor device of the present invention will be described. This 2nd Embodiment differs in the composition of the silicon-containing curable composition which forms the 1st coating | coated part 15 and the 2nd coating | coated part 16 in above-mentioned 1st Embodiment from the above-mentioned 1st Embodiment. Therefore, in the second embodiment, points different from the first embodiment will be described.

この第2実施形態では、第1の被覆部15を前述の第1の珪素含有硬化性組成物に替えて第3の珪素含有硬化性組成物で形成した。この第3の有硬化性祖成物は次に説明する合成工程6によって合成した。なお、この合成工程6において「部」とは重量部を表す。上記第3の珪素含有硬化性組成物を250℃にて3時間硬化反応させることにより第1の被覆部15が得られる。   In the second embodiment, the first covering portion 15 is formed of the third silicon-containing curable composition instead of the first silicon-containing curable composition. This third curable genus was synthesized by the synthesis step 6 described below. In this synthesis step 6, “parts” represents parts by weight. The 1st coating | coated part 15 is obtained by making the said 3rd silicon-containing curable composition carry out hardening reaction at 250 degreeC for 3 hours.

さらに、この第2実施形態では、第1の被覆部15の全表面15Aを覆うが第1の被覆部15から露出した支持体3の部分3Bは覆わず接しないように、第2の被覆部16となる第4の珪素含有硬化性組成物を塗布する。この第2の被覆部16として使用される第4の珪素含有硬化性組成物は上記第3の珪素含有硬化性組成物にセラミックス粒子として粒径20μmのアルミナ微粒子を40%の体積充填率で配合している。この第4の珪素含有硬化性組成物を200℃にて6時間硬化反応させることにより第2の被覆部16が得られる。また、上記第4の珪素含有硬化性組成物の線膨張係数は180ppm/℃である。   Further, in the second embodiment, the second covering portion is covered so that the entire surface 15A of the first covering portion 15 is covered but the portion 3B of the support 3 exposed from the first covering portion 15 is not covered and is not touched. A fourth silicon-containing curable composition to be 16 is applied. The fourth silicon-containing curable composition used as the second covering portion 16 is compounded with the third silicon-containing curable composition with alumina fine particles having a particle diameter of 20 μm as ceramic particles at a volume filling rate of 40%. is doing. The second covering portion 16 is obtained by allowing the fourth silicon-containing curable composition to undergo a curing reaction at 200 ° C. for 6 hours. The linear expansion coefficient of the fourth silicon-containing curable composition is 180 ppm / ° C.

〔合成工程6〕 (A)成分として上記合成工程2で得られた珪素含有化合物(VSi−1)50部と(B)成分として上記合成工程4で得られた珪素含有化合物(HSi−2)50部とを混合したものに、(D)成分として白金系触媒である白金−カルボニルビニルメチル錯体0.01部、および鉄(III)アセチルアセトネート0.01部を混合して、上記第3の珪素含有硬化性組成物を得た。   [Synthesis Step 6] 50 parts of silicon-containing compound (VSi-1) obtained in Synthesis Step 2 as component (A) and silicon-containing compound (HSi-2) obtained in Synthesis Step 4 as component (B) 50 parts is mixed with 0.01 parts of platinum-carbonylvinylmethyl complex which is a platinum-based catalyst as component (D) and 0.01 parts of iron (III) acetylacetonate. A silicon-containing curable composition was obtained.

この第2実施形態によれば、第2の被覆部16となる第4の珪素含有硬化性組成物は上記第3の珪素含有硬化性組成物にセラミックスとしての粒径20μmのアルミナ微粒子を40%の体積充填率で配合している。そして、この第4の珪素含有硬化性組成物を200℃にて6時間硬化反応させることにより第2の被覆部16とした。上記硬化後の第4の珪素含有硬化性組成物の線膨張係数は180ppm/℃である。この第2実施形態によれば、上記第2の被覆部16は高温(例えば200℃以上)で使用してもクラック等が発生せず、高絶縁耐力を達成できる。また、この第2の被覆部16は支持体3に接しないので、高温時(例えば200℃以上)に支持体3との線膨張係数の差で剥がれることがなく、また、第1の被覆部15が支持体3と第2の被覆部16との間で緩衝材として働き、高温時の応力を低減できる。   According to the second embodiment, the fourth silicon-containing curable composition serving as the second covering portion 16 is composed of 40% alumina fine particles having a particle diameter of 20 μm as ceramics in the third silicon-containing curable composition. It is blended at a volume filling rate of. Then, the fourth silicon-containing curable composition was subjected to a curing reaction at 200 ° C. for 6 hours to obtain the second covering portion 16. The fourth silicon-containing curable composition after curing has a linear expansion coefficient of 180 ppm / ° C. According to the second embodiment, the second covering portion 16 does not generate cracks even when used at a high temperature (for example, 200 ° C. or higher), and can achieve high dielectric strength. Further, since the second covering portion 16 does not come into contact with the support 3, the second covering portion 16 does not peel off due to a difference in linear expansion coefficient from the support 3 at a high temperature (for example, 200 ° C. or more), and the first covering portion 16 15 acts as a cushioning material between the support 3 and the second covering portion 16, and can reduce stress at high temperatures.

尚、上記第1,第2実施形態において、上記第1の被覆部15に表面が被覆されていると共に上記GTOサイリスタ素子1を直接被覆する下塗り部となる第3の被覆部(図示せず)と、上記第2の被覆部16に表面が被覆されていると共に上記第1の被覆部15を直接被覆する下塗り部となる第4の被覆部(図示せず)とを備えてもよい。ここで、上記第3の被覆部(図示せず)および第4の被覆部(図示せず)を作製する珪素含有硬化性組成物は、上記の(A)成分、(B)成分、(D)成分および(F)成分を含有する珪素含有硬化性組成物である。そして、上記第3および第4の被覆部を作製する珪素含有硬化性組成物の成分の内の上記(F)成分の含有重量%が上記第1および第2の被覆部15,16を作製する珪素含有硬化性組成物の成分の内の上記(F)成分の含有重量%よりも低い。つまり、上記第3,第4の被覆部を作製する珪素含有硬化性組成物の成分は、上記(F)成分以外は、上記第1の被覆部15を作製する珪素含有硬化性組成物の成分と同様である。これにより、下塗り部となる上記第3,第4の被覆部(図示せず)の粘度と接着力を、上記第1,第2の被覆部15,16の粘度と接着力に比べて高くすることができる。なお、上記第3,第4の被覆部の(F)成分の含有重量%を、5%以下にすることが望ましい。また、上記第3,第4の被覆部の(F)成分の含有重量%を略零%とすることがより好ましい。   In the first and second embodiments, a third covering portion (not shown) which is the surface of the first covering portion 15 and serves as an undercoat portion which directly covers the GTO thyristor element 1. And a fourth covering portion (not shown) serving as an undercoat portion that covers the surface of the second covering portion 16 and directly covers the first covering portion 15. Here, the silicon-containing curable composition for producing the third covering portion (not shown) and the fourth covering portion (not shown) is composed of the components (A), (B), (D ) Component and (F) component containing a silicon-containing curable composition. And the content weight% of the said (F) component of the components of the silicon containing curable composition which produces the said 3rd and 4th coating part produces the said 1st and 2nd coating parts 15 and 16. It is lower than the content by weight of the component (F) in the components of the silicon-containing curable composition. That is, the components of the silicon-containing curable composition for producing the third and fourth coating portions are the components of the silicon-containing curable composition for producing the first coating portion 15 except for the component (F). It is the same. As a result, the viscosity and adhesive strength of the third and fourth covering portions (not shown), which are the undercoat portions, are made higher than the viscosity and adhesive strength of the first and second covering portions 15 and 16. be able to. In addition, it is desirable that the content weight% of the component (F) in the third and fourth covering portions is 5% or less. Further, it is more preferable that the content% by weight of the component (F) in the third and fourth covering portions is substantially zero%.

また、上記第1の被覆部15の厚さを0.1mm以上かつ10mm以下とし、上記第2の被覆部16の厚さを5mm以上かつ30mm以下とし、上記第3および第4の被覆部の厚さを0.01mm以上かつ5mm以下とすることが好ましい。また、上記実施形態では、支持体3を銅製としたが、銅の他にアルミニウムのような金属、または、Al‐SiCのような金属と半導体の複合材料、または、銅とモリブデン等の異種金属の積層構造材料で作製してもよい。また、上記支持体の表面を金またはニッケル等でメッキしてもよい。   Further, the thickness of the first covering portion 15 is set to 0.1 mm or more and 10 mm or less, the thickness of the second covering portion 16 is set to 5 mm or more and 30 mm or less, and the third and fourth covering portions are formed. The thickness is preferably 0.01 mm or more and 5 mm or less. In the above embodiment, the support 3 is made of copper. However, in addition to copper, a metal such as aluminum, a metal-semiconductor composite material such as Al-SiC, or a dissimilar metal such as copper and molybdenum. You may produce with the laminated structure material of. The surface of the support may be plated with gold or nickel.

(第3の実施の形態)
次に、図2に、この発明の半導体装置の第3実施形態を示す。この第3実施形態は、図1のSiC GTOサイリスタ素子1に替えてSiC GTOサイリスタ素子21を有する点と、支持体3に替えて、銅,アルミニウムのような金属材料もしくはAl‐SiCのような複合材料もしくは銅とモリブデン等の異種金属の積層構造材料で作製された支持体23および上記支持体23上に設置されてSiC GTOサイリスタ素子21が載置されたセラミック絶縁基板25を有する点が、前述の第1実施形態と異なる。よって、この第3実施形態では、前述の第1実施形態と異なる部分を主に説明する。
(Third embodiment)
Next, FIG. 2 shows a third embodiment of the semiconductor device of the present invention. This third embodiment has a SiC GTO thyristor element 21 instead of the SiC GTO thyristor element 1 of FIG. 1, and a metal material such as copper or aluminum or Al-SiC instead of the support 3. A support 23 made of a composite material or a laminated structure material of dissimilar metals such as copper and molybdenum, and a ceramic insulating substrate 25 placed on the support 23 and on which the SiC GTO thyristor element 21 is placed, Different from the first embodiment described above. Therefore, in the third embodiment, parts different from the first embodiment will be mainly described.

この第3実施形態が有するGTOサイリスタ素子21は、アノード電極22がアルミニウム,金,銅等で作製されるリード線7によりアノード端子10の上端に接続され、カソード電極27がセラミック絶縁基板25上に配置されている。また、GTOサイリスタ素子21のゲート電極26は、アルミニウム,金,銅等で作製されるリード線8によりゲート端子11の上端に接続されている。すなわち、この第3実施形態は、GTOサイリスタ素子21がカソード電極27を有し、支持体3に替えてセラミック絶縁基板25と支持体23を備え、SiC GTOサイリスタ素子21の下にセラミック絶縁基板25を敷いてGTOサイリスタ素子21のカソード電極27を支持体23と絶縁した構造とした点が、先述の第1実施形態と異なっている。また、この第3実施形態では、第1の被覆部15が支持体23の表面23Aの端部23Bまで覆っている。   In the GTO thyristor element 21 of the third embodiment, the anode electrode 22 is connected to the upper end of the anode terminal 10 by a lead wire 7 made of aluminum, gold, copper or the like, and the cathode electrode 27 is placed on the ceramic insulating substrate 25. Has been placed. The gate electrode 26 of the GTO thyristor element 21 is connected to the upper end of the gate terminal 11 by a lead wire 8 made of aluminum, gold, copper or the like. That is, in this third embodiment, the GTO thyristor element 21 has a cathode electrode 27, and is provided with a ceramic insulating substrate 25 and a supporting body 23 instead of the supporting body 3, and the ceramic insulating substrate 25 is provided under the SiC GTO thyristor element 21. Is different from the first embodiment described above in that the cathode electrode 27 of the GTO thyristor element 21 is insulated from the support 23. In the third embodiment, the first cover 15 covers up to the end 23B of the surface 23A of the support 23.

尚、この第3実施形態において、図5に示すように、上記第1の被覆部15に表面31Aが被覆されていると共に上記GTOサイリスタ素子21を直接被覆する第3の被覆部31と、上記第2の被覆部16に表面32Aが被覆されていると共に上記第1の被覆部15を直接被覆する第4の被覆部32とを備えてもよい。上記第3の被覆部31は、素子被覆(第1の被覆部15)の下塗りとなり、上記第4の被覆部32は、モールド(第2の被覆部16)の下塗りとなる。   In the third embodiment, as shown in FIG. 5, the first covering portion 15 is covered with a surface 31A and directly covers the GTO thyristor element 21. The second covering portion 16 may be provided with a surface 32A and a fourth covering portion 32 that directly covers the first covering portion 15. The third covering portion 31 is an undercoat of the element covering (first covering portion 15), and the fourth covering portion 32 is an undercoat of the mold (second covering portion 16).

ここで、上記第3の被覆部31および第4の被覆部32を作製する珪素含有硬化性組成物は、上記の(A)成分、(B)成分、(D)成分および(F)成分を含有する珪素含有硬化性組成物である。そして、上記第3および第4の被覆部31,32を作製する珪素含有硬化性組成物の成分の内の上記(F)成分の含有重量%が上記第1および第2の被覆部15,16を作製する珪素含有硬化性組成物の成分の内の上記(F)成分の含有重量%よりも低い。つまり、上記第3,第4の被覆部31,32を作製する珪素含有硬化性組成物の成分は、上記(F)成分以外は、上記第1の被覆部15を作製する珪素含有硬化性組成物の成分と同様である。これにより、上記第3,第4の被覆部31,32の粘度と接着力を、上記第1,第2の被覆部15,16の粘度と接着力に比べて高くすることができる。また、上記第3,第4の被覆部31,32の(F)成分の含有重量%を、5%以下にすることが望ましい。また、上記第3,第4の被覆部31,32の(F)成分の含有重量%を約0%とすることがより好ましい。   Here, the silicon-containing curable composition for producing the third covering portion 31 and the fourth covering portion 32 has the above-mentioned components (A), (B), (D) and (F). It is a silicon-containing curable composition to contain. The content weight percentage of the component (F) in the components of the silicon-containing curable composition for producing the third and fourth covering portions 31 and 32 is the first and second covering portions 15 and 16. The content is lower than the content% by weight of the component (F) among the components of the silicon-containing curable composition. That is, the components of the silicon-containing curable composition for producing the third and fourth coating portions 31 and 32 are the silicon-containing curable composition for producing the first coating portion 15 except for the component (F). It is the same as the component of a thing. Thereby, the viscosity and adhesive force of the third and fourth covering portions 31 and 32 can be made higher than the viscosity and adhesive force of the first and second covering portions 15 and 16. Moreover, it is desirable that the content weight percentage of the component (F) in the third and fourth covering portions 31 and 32 is 5% or less. Further, it is more preferable that the content weight% of the component (F) in the third and fourth covering portions 31 and 32 is about 0%.

また、上記第1の被覆部15の厚さを0.1mm以上かつ10mm以下とし、上記第2の被覆部16の厚さを5mm以上かつ30mm以下とし、上記第3,第4の被覆部31,32の厚さを0.01mm以上かつ5mm以下とすることが好ましい。また、図5では、第3の被覆部31は、GTOサイリスタ素子21とその周辺部だけを覆っているが、第3の被覆部31を支持体23の端まで広く塗って第1の被覆部15の端まで延在させてもよい。尚、上記セラミック絶縁基板25は、一例として酸化アルミニウム,窒化アルミニウム,窒化ケイ素等で作製される。また、支持体23の表面に金またはニッケル等によるメッキを施してもよい。   Further, the thickness of the first covering portion 15 is set to 0.1 mm to 10 mm, the thickness of the second covering portion 16 is set to 5 mm to 30 mm, and the third and fourth covering portions 31 are used. 32 is preferably 0.01 mm or more and 5 mm or less. Further, in FIG. 5, the third covering portion 31 covers only the GTO thyristor element 21 and its peripheral portion. However, the third covering portion 31 is applied to the end of the support 23 so as to cover the first covering portion. You may extend to 15 ends. The ceramic insulating substrate 25 is made of aluminum oxide, aluminum nitride, silicon nitride or the like as an example. Further, the surface of the support 23 may be plated with gold or nickel.

(第4の実施の形態)
次に、図3に、この発明の半導体装置の第4実施形態を示す。この第4実施形態は、耐圧5kVのSiC GTOサイリスタ素子41を有し、このSiC サイリスタ素子41は、カソード電極49がセラミック絶縁基板42の上面42Aに配置されるように載置されている。このセラミック絶縁基板42は支持体43上に配置されている。このセラミック絶縁基板42は、一例として酸化アルミニウム,窒化アルミニウム,窒化ケイ素等で作製される。また、上記支持体43は、銅,アルミニウムのような金属材料もしくはAl‐SiCのような複合材料もしくは銅とモリブデン等の異種金属の積層構造材料で作製されている。また、支持体43の表面に金またはニッケル等によるメッキを施してもよい。
(Fourth embodiment)
Next, FIG. 3 shows a fourth embodiment of the semiconductor device of the present invention. The fourth embodiment has a SiC GTO thyristor element 41 having a withstand voltage of 5 kV, and the SiC thyristor element 41 is placed so that the cathode electrode 49 is disposed on the upper surface 42A of the ceramic insulating substrate 42. The ceramic insulating substrate 42 is disposed on the support 43. As an example, the ceramic insulating substrate 42 is made of aluminum oxide, aluminum nitride, silicon nitride, or the like. The support 43 is made of a metal material such as copper or aluminum, a composite material such as Al-SiC, or a laminated structure material of different metals such as copper and molybdenum. Further, the surface of the support 43 may be plated with gold or nickel.

このSiC GTOサイリスタ素子41のアノード電極45はアルミニウム,金,銅等で作製されるリード線46により電極47に接続されている。また、GTOサイリスタ素子41のゲート電極44は、アルミニウム,金,銅等で作製されるリード線48により電極50に接続されている。また、上記電極50には電極50上に延在するゲート端子51が接続され、上記電極47には電極47上に延在するアノード端子52が接続されている。   The anode electrode 45 of the SiC GTO thyristor element 41 is connected to the electrode 47 by a lead wire 46 made of aluminum, gold, copper or the like. The gate electrode 44 of the GTO thyristor element 41 is connected to the electrode 50 by a lead wire 48 made of aluminum, gold, copper or the like. A gate terminal 51 extending on the electrode 50 is connected to the electrode 50, and an anode terminal 52 extending on the electrode 47 is connected to the electrode 47.

そして、上記SiC GTOサイリスタ素子41の全表面、およびリード線46,48と電極47,50、および電極47,50上の端子51,52の一部分を覆うように、第1の被覆部である被覆部53となる第1の珪素含有硬化性組成物が塗布されている。ここで、この第1の被覆部53として使用される第1の珪素含有硬化性組成物は、先述の第1実施形態の第1の被覆部15として使用される第1の珪素含有硬化性組成物と同様であるので、詳細な説明を省略する。   Then, the covering which is the first covering portion is formed so as to cover the entire surface of the SiC GTO thyristor element 41, the lead wires 46 and 48, the electrodes 47 and 50, and a part of the terminals 51 and 52 on the electrodes 47 and 50. A first silicon-containing curable composition that becomes part 53 is applied. Here, the first silicon-containing curable composition used as the first covering portion 53 is the first silicon-containing curable composition used as the first covering portion 15 of the first embodiment described above. Since it is the same as a thing, detailed description is abbreviate | omitted.

また、この実施形態では、上記第1の被覆部53の全表面53Aを覆うと共に上記セラミック絶縁基板42,支持体43に接しない第2の被覆部54となる第2の珪素含有硬化性組成物が塗布されている。この第2の被覆部54として使用される第2の珪素含有硬化性組成物は、先述の第1実施形態の第2の被覆部16として使用される第2の珪素含有硬化性組成物と同様であるので、詳細な説明を省略する。   In this embodiment, the second silicon-containing curable composition that covers the entire surface 53A of the first covering portion 53 and becomes the second covering portion 54 that does not contact the ceramic insulating substrate 42 and the support 43. Is applied. The second silicon-containing curable composition used as the second covering portion 54 is the same as the second silicon-containing curable composition used as the second covering portion 16 of the first embodiment described above. Therefore, detailed description is omitted.

この実施形態によれば、高い耐熱性と高い耐電圧性を有すると共に高い柔軟性を有する第1の被覆部53でもって、GTOサイリスタ素子41を絶縁できる。また、上記第2の被覆部54は、上記第1の被覆部53の表面を被覆するが上記セラミック絶縁基板42,支持体43に接しないので、セラミック製の絶縁基板42との線膨張係数の差がかなりある第2の被覆部54が高温時(例えば200℃以上)に絶縁基板42から剥がれることがない。また、第1の被覆部53がセラミック製の絶縁基板42と第2の被覆部54との間で緩衝材として働き、高温時の応力を低減できる。これにより、この実施形態によれば、高耐熱性と高耐電圧性を達成できると共にGTOサイリスタ素子41の被覆部53とGTOサイリスタ素子41の支持体をなすセラミック製の絶縁基板42との密着性を向上でき、高温での使用を可能にできる。   According to this embodiment, the GTO thyristor element 41 can be insulated by the first covering portion 53 having high heat resistance, high voltage resistance and high flexibility. In addition, the second covering portion 54 covers the surface of the first covering portion 53 but does not contact the ceramic insulating substrate 42 and the support 43, and therefore has a linear expansion coefficient with the ceramic insulating substrate 42. The second covering portion 54 having a considerable difference is not peeled off from the insulating substrate 42 at a high temperature (for example, 200 ° C. or more). Moreover, the 1st coating | coated part 53 works as a buffering material between the ceramic insulating substrates 42 and the 2nd coating | coated part 54, and can reduce the stress at the time of high temperature. Thereby, according to this embodiment, high heat resistance and high withstand voltage can be achieved, and adhesion between the covering portion 53 of the GTO thyristor element 41 and the ceramic insulating substrate 42 forming the support of the GTO thyristor element 41 is achieved. And can be used at high temperatures.

(第5の実施の形態)
次に、図4に、この発明の半導体装置の第5実施形態を示す。この第5実施形態は、次の(1)、(2)の点だけが、前述の第4実施形態と異なる。よって、この第5実施形態では、前述の第4実施形態と同じ部分には同じ符号を付して、前述の第4実施形態と異なる部分を主に説明する。
(Fifth embodiment)
Next, FIG. 4 shows a fifth embodiment of the semiconductor device of the present invention. The fifth embodiment is different from the above-described fourth embodiment only in the following points (1) and (2). Therefore, in the fifth embodiment, the same parts as those in the above-described fourth embodiment are denoted by the same reference numerals, and different parts from the above-described fourth embodiment will be mainly described.

(1) セラミック絶縁基板42の縁部42Aから上方へ延在するセラミック製、金属製もしくは樹脂製等の機械的強度を有する枠61を備えた点。
(2) 第1の被覆部53と第2の被覆部54に替えて、第1の被覆部63と第2の被覆部64を備えた点。
(1) A frame 61 having mechanical strength such as ceramic, metal, or resin extending upward from the edge 42A of the ceramic insulating substrate 42 is provided.
(2) A point that a first covering portion 63 and a second covering portion 64 are provided instead of the first covering portion 53 and the second covering portion 54.

この第5実施形態では、第1の被覆部63は、上記SiC GTOサイリスタ素子41の全表面、およびリード線46,48と電極47,50、および電極47,50上の端子51,52の一部分を覆う点は、前述の第1の被覆部53と同様である。一方、この第5実施形態の第1の被覆部63は、その側面63Bがセラミック絶縁基板42の上面から略真上に延在していて、枠61の内壁61Aに密接している点で、前述の第1の被覆部53と相違している。この枠61は、セラミック絶縁基板42の縁部42Aから上方へ延在している。   In the fifth embodiment, the first covering portion 63 is formed on the entire surface of the SiC GTO thyristor element 41, the lead wires 46 and 48, the electrodes 47 and 50, and a part of the terminals 51 and 52 on the electrodes 47 and 50. The point of covering is the same as the first covering portion 53 described above. On the other hand, the first covering portion 63 of the fifth embodiment has a side surface 63B that extends substantially directly above the upper surface of the ceramic insulating substrate 42 and is in close contact with the inner wall 61A of the frame 61. This is different from the first covering portion 53 described above. The frame 61 extends upward from the edge portion 42 </ b> A of the ceramic insulating substrate 42.

また、この第5実施形態では、上記第2の被覆部64は、上記第1の被覆部63の上面63Cの全体を覆うが上記側面63Bを覆わないと共に上記セラミック絶縁基板42,支持体43に接していない。また、この第2の被覆部64の側面64Bは、上記枠61の内壁61Aに密接している。なお、上記第1,第2の被覆部63,64を作製する第1,第2の珪素含有硬化性組成物は、先述の第1,第2の被覆部53,54と同様であるので、詳細な説明を省略する。   Further, in the fifth embodiment, the second covering portion 64 covers the entire upper surface 63C of the first covering portion 63 but does not cover the side surface 63B, and the ceramic insulating substrate 42 and the support body 43 are covered. Not touching. Further, the side surface 64 </ b> B of the second covering portion 64 is in close contact with the inner wall 61 </ b> A of the frame 61. Since the first and second silicon-containing curable compositions for producing the first and second covering portions 63 and 64 are the same as the first and second covering portions 53 and 54 described above, Detailed description is omitted.

この第5実施形態によれば、上記第1,第2の被覆部63,64の厚さを中央部から端部まで均一化できると共に端部が枠61で保護されているので、特に端部での機械的強度を向上できる。   According to the fifth embodiment, since the thicknesses of the first and second covering portions 63 and 64 can be made uniform from the center portion to the end portion and the end portion is protected by the frame 61, the end portion is particularly preferable. The mechanical strength at can be improved.

尚、上記第4,第5実施形態において、上記第1の被覆部53,63に表面が被覆されていると共に上記GTOサイリスタ素子41を直接被覆する下塗り部となる第3の被覆部(図示せず)と、上記第2の被覆部54,64に表面が被覆されていると共に上記第1の被覆部53,63を直接被覆する下塗り部となる第4の被覆部(図示せず)とを備えてもよい。ここで、上記第3の被覆部(図示せず)および第4の被覆部(図示せず)を作製する珪素含有硬化性組成物は、上記の(A)成分、(B)成分、(D)成分および(F)成分を含有する珪素含有硬化性組成物である。そして、上記第3および第4の被覆部を作製する珪素含有硬化性組成物の成分の内の上記(F)成分の含有重量%が上記第1および第2の被覆部53,54を作製する珪素含有硬化性組成物の成分の内の上記(F)成分の含有重量%よりも低い。つまり、上記第3,第4の被覆部を作製する珪素含有硬化性組成物の成分は、上記(F)成分以外は、上記第1の被覆部53を作製する珪素含有硬化性組成物の成分と同様である。これにより、下塗り部となる上記第3,第4の被覆部(図示せず)の粘度と接着力を、上記第1,第2の被覆部53,54の粘度と接着力に比べて高くすることができる。なお、上記第3,第4の被覆部の(F)成分の含有重量%を、5%以下にすることが望ましい。また、上記第3,第4の被覆部の(F)成分の含有重量%を略零%とすることがより好ましい。   In the fourth and fifth embodiments, the first covering portions 53 and 63 are coated on the surface, and a third covering portion (not shown) that serves as an undercoat portion that directly covers the GTO thyristor element 41. And a fourth covering portion (not shown) serving as an undercoat portion that directly covers the first covering portions 53 and 63 while the surface of the second covering portions 54 and 64 is covered. You may prepare. Here, the silicon-containing curable composition for producing the third covering portion (not shown) and the fourth covering portion (not shown) is composed of the components (A), (B), (D ) Component and (F) component containing a silicon-containing curable composition. And the content weight% of the said (F) component of the components of the silicon containing curable composition which produces the said 3rd and 4th coating part produces the said 1st and 2nd coating parts 53 and 54. It is lower than the content by weight of the component (F) in the components of the silicon-containing curable composition. That is, the components of the silicon-containing curable composition for producing the third and fourth covering portions are the components of the silicon-containing curable composition for producing the first covering portion 53 except for the component (F). It is the same. As a result, the viscosity and adhesive strength of the third and fourth covering portions (not shown) serving as the undercoat portions are made higher than the viscosity and adhesive strength of the first and second covering portions 53 and 54. be able to. In addition, it is desirable that the content weight% of the component (F) in the third and fourth covering portions is 5% or less. Further, it is more preferable that the content% by weight of the component (F) in the third and fourth covering portions is substantially zero%.

また、上記第1の被覆部53,63の厚さを0.1mm以上かつ80mm以下とし、上記第2の被覆部54,64の厚さを0.1mm以上かつ80mm以下とし、上記第3,第4の被覆部の厚さを0.01mm以上かつ5mm以下とすることが好ましい。   Further, the thickness of the first covering portions 53 and 63 is set to 0.1 mm or more and 80 mm or less, the thickness of the second covering portions 54 and 64 is set to 0.1 mm or more and 80 mm or less, and the third, It is preferable that the thickness of the fourth covering portion is 0.01 mm or more and 5 mm or less.

尚、上記第1〜第5実施形態では、半導体素子としてSiCによるGTOサイリスタを備えたが、pnダイオード素子等、SiCで作製された他の半導体素子を備えてもよく、GaNもしくは他のワイドギャップ半導体で作製された半導体素子を備えてもよく、ワイドギャップ半導体以外の半導体で作製された半導体素子を備えてもよい。また、上記第1,第2実施形態では、支持体3に1つの半導体素子を載置したが、2つの半導体素子もしくは3つ以上の半導体素子を載置してもよい。また、上記第1,第2実施形態では、第2の被覆部16が第1の被覆部15の表面15Aの全体を被覆したが、第1の被覆部15の表面15Aの外縁部が上記第2の被覆部16から露出していてもよい。また、上記第1,第2実施形態では、支持体3を銅製としたが、アルミニウム等の他の金属製としてもよく、Al‐SiCのような複合放熱材料としてもよい。   In the first to fifth embodiments, the GTO thyristor made of SiC is provided as the semiconductor element. However, other semiconductor elements made of SiC such as a pn diode element may be provided, and GaN or other wide gaps may be provided. A semiconductor element made of a semiconductor may be provided, or a semiconductor element made of a semiconductor other than a wide gap semiconductor may be provided. In the first and second embodiments, one semiconductor element is placed on the support 3. However, two semiconductor elements or three or more semiconductor elements may be placed. In the first and second embodiments, the second covering portion 16 covers the entire surface 15A of the first covering portion 15. However, the outer edge portion of the surface 15A of the first covering portion 15 is the above-described first portion. The two covering portions 16 may be exposed. In the first and second embodiments, the support 3 is made of copper. However, the support 3 may be made of other metal such as aluminum, or a composite heat dissipation material such as Al-SiC.

この発明は、高耐電圧かつ高耐熱のワイドギャップ半導体装置に利用可能であり、一例として耐熱性が高い高耐電圧パワー半導体装置として有用である。   The present invention can be used for a wide gap semiconductor device having high withstand voltage and high heat resistance, and is useful as a high withstand voltage power semiconductor device having high heat resistance as an example.

1,21,41 GTOサイリスタ素子
3 支持体
3A 上面
3B 部分
7,8,46,48 リード線
10,11,52 アノード端子
14,19 絶縁材
15,53,63 第1の被覆部
16,54,64 第2の被覆部
23,43 支持体
25,42 セラミック絶縁基板
31 第3の被覆部
32 第4の被覆部
47,50 電極
51 ゲート端子
61 枠
1,21,41 GTO thyristor element 3 support 3A upper surface 3B part 7,8,46,48 lead wire 10,11,52 anode terminal 14,19 insulating material 15,53,63 first covering portion 16,54, 64 2nd coating | cover part 23,43 Support body 25,42 Ceramic insulating substrate 31 3rd coating | coated part 32 4th coating | coated part 47,50 Electrode 51 Gate terminal 61 Frame

Claims (7)

半導体素子と、
上記半導体素子が載置される支持体と、
上記半導体素子を外部機器に電気的に接続するための電気接続部と、
上記半導体素子および上記半導体素子が載置される上記支持体の上面を被覆すると共に上記電気接続部の少なくとも一部を被覆する珪素含有硬化性組成物で作製された第1の被覆部と、
上記第1の被覆部の表面を被覆すると共に上記支持体に接しない珪素含有硬化性組成物で作製された第2の被覆部とを備え、
上記第1の被覆部を作製する珪素含有硬化性組成物は、
下記の(A)成分、(B)成分および(D)成分を含有する珪素含有硬化性組成物であり、
上記第2の被覆部を作製する珪素含有硬化性組成物は、
下記の(A)成分、(B)成分、(D)成分および (F)成分を含有する珪素含有硬化性組成物であり、
上記第2の被覆部は、上記珪素含有硬化性組成物を熱硬化させた硬化物であり、上記硬化物の線膨張係数が50〜200ppm/℃であることを特徴としている。
(A)成分:下記一般式(1)で表される珪素含有化合物。
Figure 2011063688
(上式(1)中、R〜Rは、同一でも異なっていてもよく、炭素原子数1〜12の飽和脂肪族炭化水素基、又は、飽和脂肪族炭化水素基で置換されていてもよい炭素原子数6〜12の芳香族炭化水素基であり(但し、R及びRは同時に炭素原子数1〜12の飽和脂肪族炭化水素基となることはない)、Rは炭素原子数2〜4のアルキレン基であり、Zは炭素原子数2〜4のアルケニル基若しくはアルキニル基であり、aは2〜7の数であり、bは1〜7の数であり、bを繰り返し数とする重合部分と、a−bを繰り返し数とする重合部分とは、ブロック状であってもランダム状であってもよい。eは0〜3の数である。c及びdは、d:c=1:1〜1:100且つ全てのcと全てのdとの合計が15以上となる数であって、且つ一般式(1)で表される珪素含有化合物の質量平均分子量を3000〜100万とする数である。また、cを繰り返し数とする重合部分と、dを繰り返し数とする重合部分とは、ブロック状であってもランダム状であってもよい。)
(B)成分:下記一般式(2)で表される珪素含有化合物。
Figure 2011063688
(上式(2)中、R〜R15は、同一でも異なっていてもよく、炭素原子数1〜12の飽和脂肪族炭化水素基、又は、飽和脂肪族炭化水素基で置換されていてもよい炭素原子数6〜12の芳香族炭化水素基であり(但し、R13及びR14は同時に炭素原子数1〜12の飽和脂肪族炭化水素基となることはない)、R16は炭素原子数2〜4のアルキレン基であり、fは2〜7の数であり、gは1〜7の数であり、gを繰り返し数とする重合部分と、f−gを繰り返し数とする重合部分とは、ブロック状であってもランダム状であってもよい。jは0〜3の数である。h及びiは、i:h=1:1〜1:100且つ全てのhと全てのiとの合計が15以上となる数であって、且つ一般式(2)で表される珪素含有化合物の質量平均分子量を3000〜100万とする数である。また、hを繰り返し数とする重合部分と、iを繰り返し数とする重合部分とは、ブロック状であってもランダム状であってもよい。)
(D)成分:白金系触媒である硬化反応触媒
(F)成分:セラミックス粒子
A semiconductor element;
A support on which the semiconductor element is mounted;
An electrical connection for electrically connecting the semiconductor element to an external device;
A first covering portion made of a silicon-containing curable composition that covers the upper surface of the semiconductor element and the support on which the semiconductor element is placed and covers at least a part of the electrical connection portion;
And a second covering portion made of a silicon-containing curable composition that covers the surface of the first covering portion and does not contact the support,
The silicon-containing curable composition for producing the first covering portion is:
A silicon-containing curable composition containing the following component (A), component (B) and component (D):
The silicon-containing curable composition for producing the second covering portion is:
A silicon-containing curable composition containing the following component (A), component (B), component (D) and component (F):
The said 2nd coating | coated part is the hardened | cured material which heat-cured the said silicon-containing curable composition, The linear expansion coefficient of the said hardened | cured material is 50-200 ppm / degreeC, It is characterized by the above-mentioned.
Component (A): A silicon-containing compound represented by the following general formula (1).
Figure 2011063688
(In the above formula (1), R 1 to R 7 may be the same or different and are substituted with a saturated aliphatic hydrocarbon group having 1 to 12 carbon atoms or a saturated aliphatic hydrocarbon group. Or an aromatic hydrocarbon group having 6 to 12 carbon atoms (provided that R 5 and R 6 do not simultaneously become a saturated aliphatic hydrocarbon group having 1 to 12 carbon atoms), and R 8 is carbon. An alkylene group having 2 to 4 atoms, Z is an alkenyl group or alkynyl group having 2 to 4 carbon atoms, a is a number from 2 to 7, b is a number from 1 to 7, and b is The polymer moiety having the repeating number and the polymer moiety having the repeating number ab may be block-like or random, e is a number from 0 to 3. c and d are d: c = 1: 1 to 1: 100, and the sum of all c and all d is 15 or more, and The number average molecular weight of the silicon-containing compound represented by the general formula (1) is a number between 3000 and 1,000,000, and the polymerization portion where c is the number of repetitions and the polymerization portion where d is the number of repetitions are: It may be block or random.)
Component (B): A silicon-containing compound represented by the following general formula (2).
Figure 2011063688
(In the above formula (2), R 9 to R 15 may be the same or different and are substituted with a saturated aliphatic hydrocarbon group having 1 to 12 carbon atoms or a saturated aliphatic hydrocarbon group. An aromatic hydrocarbon group having 6 to 12 carbon atoms (provided that R 13 and R 14 do not simultaneously become a saturated aliphatic hydrocarbon group having 1 to 12 carbon atoms), and R 16 is a carbon atom. An alkylene group having a number of 2 to 4, f is a number of 2 to 7, g is a number of 1 to 7, and a polymer part having g as a repeat number and a polymer part having f-g as a repeat number May be block or random, j is a number from 0 to 3. h and i are i: h = 1: 1 to 1: 100 and all h and all The number average molecular weight of the silicon-containing compound represented by the general formula (2) is a number that is a sum of i and 15 or more. (The number is set to 3000 to 1,000,000. Moreover, the polymerization portion having h as the number of repetitions and the polymerization portion having i as the number of repetitions may be block-shaped or random).
Component (D): a curing reaction catalyst that is a platinum-based catalyst
Component (F): Ceramic particles
請求項1に記載の半導体装置において、
上記第1の被覆部は、上記(F)成分を含有し、
さらに、上記第1の被覆部に表面が被覆されていると共に上記半導体素子を直接被覆する第3の被覆部と、
上記第2の被覆部に表面が被覆されていると共に上記第1の被覆部を直接被覆する第4の被覆部とを備え、
上記第3の被覆部および第4の被覆部を作製する珪素含有硬化性組成物は、
上記の(A)成分、(B)成分、(D)成分および(F)成分を含有する珪素含有硬化性組成物であり、
上記第3および第4の被覆部を作製する珪素含有硬化性組成物の成分の内の上記(F)成分の含有重量%が上記第2の被覆部を作製する珪素含有硬化性組成物の成分の内の上記(F)成分の含有重量%よりも低いことを特徴とする半導体装置。
The semiconductor device according to claim 1,
The first covering portion contains the component (F),
Further, a third covering portion whose surface is coated on the first covering portion and directly covering the semiconductor element;
A surface of the second covering portion is coated and a fourth covering portion that directly covers the first covering portion;
The silicon-containing curable composition for producing the third covering portion and the fourth covering portion is:
A silicon-containing curable composition containing the above component (A), component (B), component (D) and component (F),
Of the components of the silicon-containing curable composition for producing the third and fourth coating parts, the content (%) of the component (F) is a component of the silicon-containing curable composition for producing the second coating part. A semiconductor device characterized by being lower than the content% by weight of the component (F).
請求項1または2に記載の半導体装置において、
上記半導体素子と上記支持体との間に配置されたセラミック絶縁基板を備えることを特徴とする半導体装置。
The semiconductor device according to claim 1 or 2,
A semiconductor device comprising a ceramic insulating substrate disposed between the semiconductor element and the support.
請求項1から3のいずれか1つに記載の半導体装置において、
上記支持体は、金属、または、金属と半導体の複合材料、または、異種金属の積層構造材料で作製されていることを特徴とする半導体装置。
The semiconductor device according to any one of claims 1 to 3,
The semiconductor device is characterized in that the support is made of a metal, a composite material of a metal and a semiconductor, or a stacked structure material of different metals.
請求項4に記載の半導体装置において、
上記支持体の表面がメッキされていることを特徴とする半導体装置。
The semiconductor device according to claim 4,
A semiconductor device, wherein the surface of the support is plated.
請求項1から5のいずれか1つに記載の半導体装置において、
上記支持体上に配置されていると共に上記第1および第2の被覆部の側面を覆う枠を備えることを特徴とする半導体装置。
The semiconductor device according to any one of claims 1 to 5,
A semiconductor device, comprising: a frame disposed on the support and covering a side surface of the first and second covering portions.
請求項1から6のいずれか1つに記載の半導体装置において、
上記半導体素子が、ワイドギヤップ半導体で作製されたワイドギヤップ半導体素子であることを特徴とする半導体装置。
The semiconductor device according to any one of claims 1 to 6,
A semiconductor device, wherein the semiconductor element is a wide gear semiconductor element made of a wide gear semiconductor.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011222869A (en) * 2010-04-13 2011-11-04 Kansai Electric Power Co Inc:The Semiconductor device
WO2012014560A1 (en) * 2010-07-27 2012-02-02 株式会社Adeka Curable composition for semiconductor encapsulation
JP2014120619A (en) * 2012-12-17 2014-06-30 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same
JPWO2014097798A1 (en) * 2012-12-18 2017-01-12 富士電機株式会社 Semiconductor device
JPWO2019038906A1 (en) * 2017-08-25 2019-11-07 三菱電機株式会社 Power semiconductor device and method for manufacturing power semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005325174A (en) * 2004-05-12 2005-11-24 Asahi Denka Kogyo Kk Silicon-containing curable composition and its thermally cured material
JP2006073950A (en) * 2004-09-06 2006-03-16 Kansai Electric Power Co Inc:The High heat resistive semiconductor device
JP2006206721A (en) * 2005-01-27 2006-08-10 Kansai Electric Power Co Inc:The Highly heat-resistant synthetic polymer compound and semiconductor device of high dielectric strength coated with the same
JP2006283012A (en) * 2005-03-08 2006-10-19 Adeka Corp Silicon-containing curable composition and thermally cured material therefrom
JP2008266484A (en) * 2007-04-23 2008-11-06 Adeka Corp Silicon-containing compound, curable composition, and cured material
JP2009212342A (en) * 2008-03-05 2009-09-17 Kansai Electric Power Co Inc:The Semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005325174A (en) * 2004-05-12 2005-11-24 Asahi Denka Kogyo Kk Silicon-containing curable composition and its thermally cured material
JP2006073950A (en) * 2004-09-06 2006-03-16 Kansai Electric Power Co Inc:The High heat resistive semiconductor device
JP2006206721A (en) * 2005-01-27 2006-08-10 Kansai Electric Power Co Inc:The Highly heat-resistant synthetic polymer compound and semiconductor device of high dielectric strength coated with the same
JP2006283012A (en) * 2005-03-08 2006-10-19 Adeka Corp Silicon-containing curable composition and thermally cured material therefrom
JP2008266484A (en) * 2007-04-23 2008-11-06 Adeka Corp Silicon-containing compound, curable composition, and cured material
JP2009212342A (en) * 2008-03-05 2009-09-17 Kansai Electric Power Co Inc:The Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011222869A (en) * 2010-04-13 2011-11-04 Kansai Electric Power Co Inc:The Semiconductor device
WO2012014560A1 (en) * 2010-07-27 2012-02-02 株式会社Adeka Curable composition for semiconductor encapsulation
US8470937B2 (en) 2010-07-27 2013-06-25 Adeka Corporation Curable composition for semiconductor encapsulation
JP2014120619A (en) * 2012-12-17 2014-06-30 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same
JPWO2014097798A1 (en) * 2012-12-18 2017-01-12 富士電機株式会社 Semiconductor device
JPWO2019038906A1 (en) * 2017-08-25 2019-11-07 三菱電機株式会社 Power semiconductor device and method for manufacturing power semiconductor device

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