JP2016139692A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having improved reliability in a power semiconductor device using a semiconductor element which operates at high temperature by inhibiting generation of air bubbles at boundaries between an encapsulation member and various components which contact the encapsulation member.SOLUTION: A semiconductor device comprises a substrate 3, a semiconductor element 5 and an encapsulation member 9. The substrate 3 is arranged in a case 1. The semiconductor element 5 is placed on one principal surface of the substrate 3. The encapsulation member 9 is a member to fill the inside of the case 1. The encapsulation member 9 has a first region 9aa and a second region 9bb having a thickness thinner than that of the first region 9aa.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a power semiconductor device in which a power semiconductor element is sealed in a resin case.

  2. Description of the Related Art Conventionally, for example, a resin-sealed power semiconductor device in which a semiconductor element is housed in a case and filled with a gel-like synthetic resin and sealed as shown in, for example, Japanese Patent Laid-Open No. 2010-130015 (Patent Document 1). Are known. This type of power semiconductor device is suitably used for an inverter device that performs power conversion, such as a train, a hybrid car, or an electric vehicle. By including the number of power semiconductor devices corresponding to the number of phases of the motor, an inverter device is configured.

  Also, for example, in Japanese Patent Application Laid-Open No. 2008-98584 (Patent Document 2), a liquid insulating oil having sufficient heat resistance at a temperature higher than a heat generation temperature at the time of driving a semiconductor chip is placed in a plastic case housing a semiconductor chip. A power semiconductor device formed by filling and sealing is disclosed. Furthermore, here, as the insulating oil, a mixture of a hygroscopic agent and heat transfer particles having higher thermal conductivity than the insulating oil is used. With this configuration, the power semiconductor device is resistant to thermal shock, good heat dissipation characteristics are obtained, and reliability is improved.

JP 2010-130015 A JP 2008-98584 A

  For example, in the semiconductor devices disclosed in Japanese Patent Application Laid-Open Nos. 2010-130015 and 2008-98584, moisture at the interface between various members such as an insulating substrate and an electrode and a sealing member that touches the member due to heat generation during use is removed. It becomes easy to generate gas. This gas may reduce the creeping withstand voltage of an insulating substrate or the like and may reduce the reliability of the semiconductor device.

  From the viewpoint of suppressing such inconveniences, in Japanese Patent Application Laid-Open No. 2008-98584, the semiconductor element is filled with an insulating oil containing a hygroscopic agent and heat transfer particles, but the heat transfer particles settle in the insulating oil. The heat dissipation effect may be weakened. In the configuration shown in Japanese Patent Application Laid-Open No. 2010-130015, no measures are taken regarding suppression of gas due to internal heat generation during use.

  The present invention has been made in view of the above problems, and an object thereof is generated at an interface between a sealing member and various members that touch the sealing member in a power semiconductor device using a semiconductor element that operates at a high temperature. It is an object of the present invention to provide a semiconductor device whose reliability is improved by suppressing the generation of bubbles.

  The semiconductor device of the present invention includes a substrate, a semiconductor element, and a sealing member. The substrate is disposed in the case. The semiconductor element is mounted on one main surface of the substrate. The sealing member fills the case. The sealing member has a first region and a second region that is thinner than the first region.

  According to the present invention, the thickness of the sealing member in the region where heat generated during the operation of the semiconductor element is difficult to be transmitted is made thinner than the other regions, and the volume thereof is reduced. If the sealing member is warmed, the effect of exhausting the gas in the sealing member to the outside of the sealing member is enhanced, so that the entire sealing member can be easily warmed in this way. It is possible to suppress a decrease in reliability due to bubbles generated at the interface with various members to be touched.

Schematic plan view (A) showing the configuration of the power semiconductor device of the first embodiment, a perspective view (B) seen from a dotted line L1 in FIG. 1 (A), and a perspective seen from a dotted line L2 in FIG. 1 (A) It is a figure (C). Schematic (A) showing a first step in the first example of the method for manufacturing the power semiconductor device of the first embodiment and an outline showing the first step in the second example of the method for manufacturing the power semiconductor device of the first embodiment. FIG. 5B is a schematic diagram illustrating a second step in the second example of the method for manufacturing the power semiconductor device of the first embodiment. Schematic diagram (A) showing the process following FIG. 2 (A) or (C) and schematic diagram (B) showing the process following FIG. 3 (A) in the method for manufacturing the power semiconductor device of the first embodiment. FIG. 4C is a schematic diagram (C) illustrating a process subsequent to FIG. It is the schematic plan view (A) which shows the structure of the power semiconductor device of a comparative example, and the perspective view (B) seen from the dotted line L1 of FIG. 4 (A). The gas movement mode (A) shown on the perspective view seen from the dotted line L2 in FIG. 4A showing the power semiconductor device of the comparative example, and the dotted line L2 in FIG. 4A showing the power semiconductor device of the comparative example It is the generation | occurrence | production aspect (B) of the bubble represented on the perspective view seen from. FIG. 6 is a perspective view (A) viewed from a dotted line L2 in FIG. 1 (A) showing the power semiconductor device of the first embodiment, and a gas movement mode (B) shown on the perspective view in FIG. 6 (A). . 7A is a schematic plan view showing the configuration of the power semiconductor device according to the second embodiment, FIG. 7B is a perspective view seen from the dotted line L1 in FIG. 7A, and FIG. 7A is a perspective seen from the dotted line L2. It is a figure (C). Schematic diagram (A) showing the first step of the method for manufacturing the power semiconductor device of the second embodiment, schematic diagram (B) showing the second step of the method for manufacturing the power semiconductor device of the second embodiment, It is the schematic (C) which shows the 3rd process of the manufacturing method of the power semiconductor device of Embodiment 2, and the schematic (D) which shows the 4th process of the manufacturing method of the power semiconductor device of Embodiment 2. 9A is a schematic plan view showing the configuration of the power semiconductor device of Embodiment 3, FIG. 9B is a perspective view seen from the dotted line L3 in FIG. 9A, and FIG. 9A is seen perspective from the dotted line L4. FIG. 10C is a perspective view viewed from a dotted line L5 in FIG. 9A. Schematic plan view showing the configuration of the power semiconductor device of sample 1 of the first embodiment, schematic perspective view (A) of the power semiconductor device viewed from the Y direction, and power semiconductor devices of samples 2, 3, and 4 of the first embodiment And a schematic perspective view (B) of the power semiconductor device seen from the Y direction, a schematic plan view showing the configuration of the power semiconductor device of Sample 5 of Example 1, and the power semiconductor device Y It is the schematic perspective view (C) seen from the direction, and the schematic plan view (D) which shows the point which measured the temperature of the uppermost surface of a sealing member, and the dimension of each part. A schematic plan view (A) showing the configuration of the power semiconductor device of Sample 6 of Example 2, a perspective view (B) seen from the dotted line L3 in FIG. 11 (A), and a dotted line L4 in FIG. 11 (A) They are a perspective view (C) and a perspective view (D) viewed from a dotted line L5 in FIG. 11 (A). A schematic plan view (A) showing the configuration of the power semiconductor device of sample 7 of Example 2, a perspective view (B) seen from the dotted line L3 in FIG. 12 (A), and a perspective view from the dotted line L4 in FIG. 12 (A) They are a perspective view (C) and a perspective view (D) viewed from a dotted line L5 in FIG. 12 (A).

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
First, a configuration of a power semiconductor device will be described with reference to FIG. 1 as a configuration of the semiconductor device of the present embodiment. For convenience of explanation, an X direction, a Y direction, and a Z direction are introduced. The X direction and the Y direction mean the horizontal direction and the vertical direction in a plan view, respectively, and the Z direction means a thickness (height) direction that intersects the X direction and the Y direction.

  FIG. 1A is a plan view showing the internal configuration of the power semiconductor device of the present embodiment that does not include a lid 13 described later, and FIG. 1B shows the power of the present embodiment including the lid 13. It is the perspective view (side view) which looked at the internal structure of the semiconductor device from the dotted line L1 in FIG. FIG. 1C is a perspective view (side view) of the internal configuration of the power semiconductor device of the present embodiment including the lid 13 as viewed from the dotted line L2 in FIG. It is. In each perspective view, a part of the visible member may be omitted and only a main member (main part) may be extracted, and a plan view may be partly shown for easy understanding of the drawing. There are cases where there is a location that does not match (the same applies to the following figures).

  1A, 1B, 1C, the power semiconductor device of the present embodiment includes a case 1, a substrate 3, a semiconductor element 5, an electrode member 7, and a sealing member 9. And a guide member 11.

  The case 1 is, for example, a rectangular parallelepiped member having a shape capable of accommodating various members such as the substrate 3 constituting the power semiconductor device. Case 1 is formed of a resin material such as poly-phenylene sulfide, for example.

  The substrate 3 is a constituent member that is a base of the power semiconductor device, and is disposed in the case 1. Referring particularly to FIGS. 1B and 1C, the substrate 3 includes an insulating substrate 3a, a back electrode 3b, and a front electrode 3c.

The insulating substrate 3a is a flat plate member made of an insulating material such as ceramics, and has a rectangular shape in plan view, for example, and has a constant thickness in the Z direction. More specifically, as the ceramic material constituting the insulating substrate 3a, for example, aluminum nitride (AlN), silicon nitride (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ), beryllium oxide (BeO), silicon oxide ( Any one selected from the group consisting of SiO ₂ ) and glass ceramics is preferably used. However, the insulating substrate 3a can be made of any material and Z-direction thickness satisfying characteristics such as insulation characteristics, heat dissipation, and linear expansion coefficient required by a power semiconductor device including the same.

  The back electrode 3b is formed so as to be bonded to at least a part of the main surface on the lower side in the Z direction of the insulating substrate 3a, for example, by brazing, and has, for example, a rectangular shape in a plan view and constant in the Z direction. It is the pattern of the thin film which has the thickness of. Similarly, the surface electrode 3c is formed on at least a part of the upper main surface in the Z direction of the insulating substrate 3a so as to be bonded by, for example, brazing (so as to directly cover the upper main surface of the insulating substrate 3a). For example, it is a thin film pattern having a rectangular shape in a plan view and a constant thickness in the Z direction. The back electrode 3b and the front electrode 3c are formed of generally known aluminum, copper, or a metal material combining these. In addition, the metal material which comprises the back surface electrode 3b and the surface electrode 3c may be processed by nickel plating etc. on the surface for oxidation prevention.

  The material constituting the semiconductor element 5 is any one selected from the group consisting of silicon, silicon carbide (SiC), gallium nitride (GaN), and diamond, or a combination of silicon carbide, gallium nitride, and diamond. It may be a composite material. Thereby, the semiconductor element 5 can be used as a power semiconductor element to which a high voltage is applied.

  The semiconductor element 5 has a chip shape (thin plate shape) made of the above-described material, and a plurality of semiconductor elements 5 (see FIG. 1) are spaced apart from each other on one main surface (main surface on the upper side in the Z direction) of the substrate 3, for example. In (A), two rows in each of the X direction and the Y direction, a total of four) are placed. That is, the semiconductor element 5 is bonded by a bonding material such as solder (not shown) such that the main surface on the lower side in the Z direction is in contact with the main surface on the upper side in the Z direction (the surface of the surface electrode 3c). It is installed.

  The semiconductor element 5 is a member constituting an integrated circuit by forming a plurality of fine elements on the surface (upper Z direction in FIG. 1) of a semiconductor chip made of silicon or silicon carbide (SiC). As the fine elements here, for example, power control semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), or so-called power semiconductor elements such as freewheeling diodes are used. However, the present invention is not limited to this, and as a fine element, at least one or more of a number of semiconductor elements whose operating temperature exceeds 125 ° C. may be used.

  The electrode member 7 is disposed in order to electrically connect (conduct) the power semiconductor device (semiconductor element 5) and the external wiring thereof. The electrode member 7 includes a source electrode 7a, a drain electrode 7b, and a gate electrode 7c.

  The source electrode 7 a is electrically connected to the source electrode that constitutes a fine element included in the semiconductor element 5 and is electrically connected to the outside of the semiconductor element 5 including the substrate 3. This corresponds to one large source electrode for the entire power semiconductor device. Similarly, the drain electrode 7 b (gate electrode 7 c) is electrically connected to the drain electrode (gate electrode) constituting a fine element included in the semiconductor element 5, and the semiconductor element 5 including the substrate 3 is connected to the drain electrode 7 b (gate electrode 7 c). This is for electrical connection to the outside, and corresponds to one large drain electrode (gate electrode) for the entire power semiconductor device.

  In FIG. 1, a plurality (three) of surface electrodes 3 c of the substrate 3 are arranged at intervals with respect to the X direction. The source electrode 7a is connected to the leftmost surface electrode 3c, the drain electrode 7b is connected to the central surface electrode 3c, and the gate electrode 7c is connected to the rightmost surface electrode 3c. Therefore, each of the three surface electrodes 3 c has the same potential as each of the electrode members 7. However, here, each of the three surface electrodes 3c constitutes the substrate 3, and the electrode member 7 means each electrode 7a, 7b, 7c connected to the substrate 3 (each of the three surface electrodes 3c). And

  As shown in FIG. 1, each of the source electrode 7a, the drain electrode 7b, and the gate electrode 7c is located above the substrate 3 (surface electrode 3c) from the upper side in the Z direction in the region connected to the surface electrode 3c (lowermost portion in the Z direction). It may have a shape bent at a substantially right angle so as to extend. Thereby, each of the source electrode 7a, the drain electrode 7b, and the gate electrode 7c has a configuration in which most of the regions extend upward in the Z direction.

  The source electrode 7a, the drain electrode 7b, and the gate electrode 7c have a structure in which, for example, nickel plating or the like is performed on the surface of a copper base, and are connected to the surface electrode 3c of the substrate 3 by, for example, ultrasonic bonding. The However, the source electrode 7a, the drain electrode 7b, and the gate electrode 7c can be formed of any material having high electrical conductivity, and are connected to the surface electrode 3c of the substrate 3 by soldering or caulking bonding in addition to ultrasonic bonding. May be.

  Further, the size and position of each electrode 7a, 7b, 7c are not particularly limited, and it is sufficient that the electrodes 7a, 7b, and 7c have a size that allows a desired current to flow. Note that the names of the electrodes 7a to 7c in FIG. 1 are named for convenience of description of the device configuration. For example, the positions and functions of the source electrode and the drain electrode may be replaced with those in FIG. A common electrode may be arranged so as to have both functions of the drain electrode and the drain electrode.

  As shown in FIGS. 1B and 1C, the sealing member 9 is disposed so as to fill the inside of the case 1, and is, for example, a generally known sealing resin material cured. It is not always necessary to use a resin material. Accordingly, the sealing member 9 is disposed so as to cover at least a part of the surface of each member such as the substrate 3, the semiconductor element 5, and the electrode member 7 disposed in the case 1 while being in contact with each other. .

  The resin material as the sealing member 9 is preferably a material having excellent moldability, curability, storage stability, particularly long-term heat resistance, and good crack resistance. Specifically, as the sealing member 9, for example, a silicone-based resin (a two-component mixed reaction material such as silicone gel) mainly including a thermosetting organopolysiloxane is generally used. Further, as the sealing member 9, an epoxy-based or fluorine-based resin material may be used, and a curing accelerator, an antifoaming agent, an inorganic filler, or the like is added as long as the above-described properties such as moldability are not impaired. It can also be used.

  A plurality of types (two liquids) of which a predetermined amount is weighed are mixed, and the sealing member 9 is first defoamed for 10 minutes under a vacuum of about 13.3 Pa, and then cast into the case 1. Is formed (supplied in the case 1). Thereafter, the sealing member 9 is subjected to secondary degassing for 10 minutes under a vacuum state of 13.3 Pa, and is cured by heating at 70 ° C. for 1 hour.

  The uppermost surface in the Z direction of the sealing member 9 has a first sealing member uppermost surface 9a and a second sealing member uppermost surface 9b having different heights (coordinates in the Z direction). Specifically, the first sealing member uppermost surface 9a is disposed above the second sealing member uppermost surface 9b in the Z direction. And the sealing member 9 has 1st area | region 9aa which has the 1st sealing member uppermost surface 9a, and 2nd area | region 9bb which has the 2nd sealing member uppermost surface 9b. In both the first region 9aa and the second region 9bb, the height of the bottom surface in the Z direction (coordinates in the Z direction) is the same, and the bottom surfaces are substantially pitched.

  Accordingly, the second region 9bb is thinner in the Z direction than the first region 9aa. Specifically, the second region 9bb is thinner than the first region 9aa by at least 1 mm or more in the Z direction. However, as will be described later, it is more preferable that the second region 9bb is thinner than the first region 9aa by 3 mm or more (in the Z direction).

  Basically, the second region 9bb is preferably arranged near the edge of the region in the case 1 in a plan view, and is lower in the Y direction in FIG. 1A (leftward in the Y direction in FIG. 1C). ). The second region 9bb is provided in a region other than the region overlapping the semiconductor element 5 and the electrode member 7 in plan view. In FIG. 1A, there is a region where the semiconductor element 5 and the electrode member 7 are arranged relatively upward (as the first region 9aa) in the Y direction, and the guide member 11 is spaced below the Y direction. The second region 9bb exists.

  A moisture permeable membrane 10 is disposed on the surface so as to be in contact with the second sealing member uppermost surface 9b. In other words, the second sealing member uppermost surface 9b (the surface on the same side as one main surface of the substrate 3), which is the upper surface of the second region 9bb, is covered with the moisture permeable film 10. In other words, the uppermost surface of the sealing member 9 when the moisture permeable film 10 is removed in the second region 9bb corresponds to the uppermost surface 9b of the second sealing member. Therefore, the moisture permeable film 10 is disposed so as to overlap the second region 9bb in plan view, and has a rectangular shape extending in the X direction, for example, in plan view.

  The moisture permeable film 10 is not particularly limited as long as it has heat resistance and does not allow the sealing resin to pass through. For the moisture permeable film 10, for example, a film having moisture permeability can be used. Specifically, for example, a film made by stretching polytetrafluoroethylene to give moisture permeability, or a film made by mixing an organic filler with polypropylene to form a sheet, and then dissolving and removing the organic filler to give moisture permeability. Etc. are used. In addition, it is preferable that the thickness regarding the Z direction of the moisture permeable film 10 shall be 10 micrometers or more and 3 mm or less, for example.

  A guide member 11 is arranged at the boundary between the first region 9aa and the second region 9bb of the sealing member 9 in the case 1 so as to partition the first region 9aa and the second region 9bb in the Y direction. Yes. The guide member 11 has a rectangular shape extending in the X direction on a plane formed by the Z direction and the X direction, and has a flat plate shape having a thickness in the Y direction and a width (height) in the Z direction. The guide member 11 is formed of a resin material such as poly-phenylene sulfide, for example.

  Further, the guide member 11 and the moisture permeable membrane 10 may be the same member. For example, when the thickness of the moisture permeable film 10 is 10 μm, the moisture permeable film 10 itself does not have a shape maintaining characteristic, and therefore the second region 9bb needs to be formed using a resin material such as poly-phenylene sulfide, for example. . However, when the thickness of the moisture permeable membrane 10 is 1 mm, the moisture permeable membrane 10 itself has a shape maintaining characteristic. Therefore, even if only the moisture permeable membrane 10 itself is disposed, it can also function as the guide member 11. In this case, since the moisture can be permeated also in the portion of the sealing member 9 in contact with the guide member 11, further improvement in reliability can be expected.

  The guide member 11 is a member used for installing the moisture permeable film 10 in a region where the relatively thin second region 9bb of the sealing member 9 is to be formed. It is arranged at the boundary with the part that does not. The guide member 11 may be formed so as to be integrated with the case 1 when the case 1 is formed, or may be formed after the case 1 is formed.

  The power semiconductor device of the present embodiment includes, for example, a lid 13, a base plate 15, and a wire 17 in addition to the above-described members.

  The lid 13 is installed so as to block the uppermost opening in the Z direction of the case 1 so that the region filled with the sealing member 9 inside the case 1 is not exposed to the outside of the case 1. . The lid 13 is preferably a flat plate member basically formed of the same resin material as the case 1.

  Here, in particular, as shown in FIGS. 1B and 1C, the sealing member 9 does not fill the entire case 1 and is slightly below the uppermost portion in the case 1 in the Z direction. It is supplied so as to have an uppermost surface 9a. That is, in the case 1, a gap 14 (gap due to air or the like) exists between the sealing member uppermost surfaces 9 a and 9 b and the lid 13. The gap 14 is in the Z direction above the second region 9bb (second sealing member uppermost surface 9b) rather than directly above the first region 9aa (first sealing member uppermost surface 9a) of the sealing member 9. The thickness of is increased.

  Sealing in the case 1 by the lid 13 is attached after the sealing member 9 is heated and cured, thereby completing a power semiconductor device.

  The base plate 15 is a member that constitutes the bottom of the case 1 by being disposed so as to close the outer frame constituting the case 1 and the lower side in the Z direction inside the case. That is, the base plate 15 is disposed so as to be connected to the other main surface (the main surface on the lower side in the Z direction) of the substrate 3 opposite to the one main surface. More specifically, the base plate 15 is bonded with a bonding material such as solder (not shown) such that the main surface on the upper side in the Z direction contacts the main surface on the lower side in the Z direction of the substrate 3 (the surface of the back electrode 3b). It is mounted to be. The base plate 15 is a flat plate-like member having a rectangular shape in plan view, for example, and is attached to the bottom of the case 1 with an adhesive or the like (not shown).

  The base plate 15 has a function of radiating heat generated when the semiconductor element 5 is driven from the lower side in the Z direction to the outside of the power semiconductor device. The base plate 15 can have any Z-direction thickness and material satisfying characteristics such as electrical characteristics, heat dissipation, and linear expansion coefficient required by a power semiconductor device including the base plate 15.

  For example, the base plate 15 is generally formed of copper, but may be formed of, for example, molybdenum or tungsten, or an alloy of copper and tungsten, or an alloy of copper and molybdenum (copper molybdenum: CuMo). May be. Alternatively, the base plate 15 may be formed of a ceramic metal material such as a synthetic material of aluminum and silicon carbide (SiC) (aluminum silicon carbide: AlSiC), a synthetic material of silicon and silicon carbide (SiC), Further, it may be formed of synthetic diamond or a composite material of diamond and copper. Further, the base plate 15 may be electrically connected to the semiconductor element 5 or the like by being electrically connected to the back electrode 3b. The base plate 15 formed of such a material can sufficiently satisfy characteristics such as heat dissipation.

  As described above, the sealing member 9 filling the case 1 in the power semiconductor device fills a part of the space surrounded by the side surface of the case 1, the lid 13, and the base plate 15. . Thereby, the sealing member 9 ensures the confidentiality which protects the semiconductor element 5 etc. which are arrange | positioned in the said space from external contamination, etc., or improves the shape precision by the shaping | molding of the whole power semiconductor device. In particular, the heat generated by the semiconductor element 5 and the like is radiated to the outside with high efficiency by the base plate 15.

  For example, the wire 17 electrically connects the semiconductor elements 5 to each other, or the surface electrode 3c other than the semiconductor element 5 and the surface electrode 3c on which the semiconductor element 5 is placed (for example, adjacent to the surface electrode 3c). Are thin wirings connected to the surface of the semiconductor element 5 and the like.

  The wire 17 can be formed of any material that can electrically connect the two regions to be connected. Specifically, the wire 17 is usually formed of a thin wire made of a metal material such as aluminum, copper, or gold. For example, a wire 17 made of copper whose surface is covered with aluminum may be used.

  Although the material used for connecting the wire 17 to the surface electrode 3c or the like is not shown, it is preferably a heat melting member such as solder or silver. The connection method of the wire 17 to the surface electrode 3c and the like is performed by an arbitrary method that enables electrical connection between the wire 17 and the surface electrode 3c and the like. For example, the surface electrode 3c and the wire 17 may be connected to each other by ultrasonic bonding.

  The power semiconductor device of the present embodiment having the above configuration may be used by being attached to a cooling device or the like. In that case, for example, the mounting screw hole 19 may be machined in the case 1 for installation in the cooling device or the like. In FIG. 1A, one mounting screw hole 19 is formed at one end and the other end in the X direction, but there is no particular limitation on the shape and number, and the required mounting strength and product The shape and number can be appropriately determined in consideration of standards and the like.

  More specifically, the power semiconductor device is placed on a cooling fin (not shown) and fixed on the cooling fin by a screw or the like inserted into the mounting screw hole 19. At this time, it is preferable that a heat radiating member such as a heat radiating grease (not shown) is interposed between the power semiconductor device and the cooling fin.

  Next, a method for manufacturing the power semiconductor device of the present embodiment will be described with reference to FIGS.

  Referring to FIGS. 2 (A) I and II, as a first example of the manufacturing method, a region to be a region between the guide member 11 and the case 1 (a region where the moisture permeable membrane 10 is to be installed) is previously permeable. A wet film 10 is disposed. In this state, the case 1 and the guide member 11 are simultaneously formed by casting the resin material. The guide member 11 is formed at a position where it can be fixed together with the edge of the case 1 while sandwiching the moisture permeable membrane 10.

  Referring to FIGS. 2B, I, II, III, and IV, as a second example of the manufacturing method, case 1 and guide member 11 having the same material, position, and shape as in the first example are cast first. After being formed, only the moisture permeable film 10 may be formed by a separate process. In this case, the moisture permeable membrane 10 is formed around the moisture permeable membrane 10 in a plan view so that the moisture permeable membrane 10 can be easily formed in the case 1 (region between the guide member 11) by retrofitting. It is preferable that the moisture permeable membrane outer frame 10a is formed of the same resin material as that constituting the material.

  Referring to FIG. 2C, a groove portion 1a for installing the moisture permeable film 10 is formed in a part of the wall surface of the inner region of the case 1 that accommodates the semiconductor element 5 and the like, and is fitted into the groove portion 1a. As described above, the moisture permeable membrane 10 (including the moisture permeable membrane outer frame 10a) formed in FIG.

  Each of the steps in FIGS. 3A to 3C is a step common to both the first example and the second example. Referring to FIG. 3 (A), the case 1 in which the moisture permeable membrane 10 is set, which is formed by the first example of FIG. 2 (A) or the second example of FIGS. 2 (B) and 2 (C). The base plate 15 is bonded to the bottom, and the members such as the substrate 3, the semiconductor element 5, and the electrode member 7 are placed on the upper surface of the base plate 15 (in the case 1).

  Referring to FIG. 3B, the sealing member 9 is formed. Specifically, a gel 20 in which a plurality of types (two liquids) measured in a predetermined amount are mixed as described above, and the gel 20 is primarily defoamed for 10 minutes in a vacuum state of about 13.3 Pa is obtained. 3, each member such as the semiconductor element 5 and the electrode member 7 is injected into the case 1 on which the members are placed. However, the gel 20 may be injected without being in a vacuum state.

  At this time, the supply of the gel 20 stops when it reaches the height of the moisture permeable membrane 10 in the Z direction in the region to be the second region 9bb. On the other hand, since the moisture permeable film 10 is not disposed in the area to be the first area 9aa, the moisture permeable film 10 is supplied higher than the moisture permeable film 10 so as to reach the upper side in the Z direction. For this reason, if the moisture permeable film 10 is formed in a desired region, the region where the moisture permeable film 10 is not disposed (the first region 9aa and the region where the moisture permeable film 10 is disposed (the region to be the second region 9bb)). The gel 20 is supplied so that the uppermost surface thereof is lower than the region to be formed (so that there is a step). Thereafter, the gel 20 is secondly degassed for 10 minutes under a vacuum state of 13.3 Pa, and is cured by heating at 70 ° C. for 1 hour.

  Referring to FIG. 3C, by the heat curing described above, the second sealing member uppermost surface 9b of the second region 9bb is in contact with the moisture permeable membrane 10, and it is the first sealing member uppermost surface of the first region 9aa. The sealing member 9 is formed so as to be disposed 1 mm or more below the upper surface 9 a in the Z direction.

  Thereafter, as shown in the figure, the lid 13 is attached, whereby the sealing member 9 is sealed in the case 1 to complete the power semiconductor device. A gap 14 (wider on the uppermost surface 9b than on the uppermost surface 9a) is preferably formed between the uppermost surfaces 9a, 9b of the sealing member 9 and the lid 13.

  As described above, in the present embodiment, either the first example shown in FIG. 2A or the second example shown in FIGS. 2B and 2C may be adopted. The point is that the moisture permeable membrane 10 can be disposed at a position where the second region 9bb can be formed 1 mm or more thinner than the first region 9aa while maintaining the moisture permeability of the sealing member 9. It may be formed by such a method.

  Next, while explaining the configuration, operation, problem, and the like of the comparative example of FIGS. 4 to 6, the operation effect and more preferable configuration of the present embodiment will be described.

  FIG. 4A is a plan view showing an internal configuration of a power semiconductor device of a comparative example that does not include the lid 13, and FIG. 4B is an internal view of the power semiconductor device of the present embodiment including the lid 13. 5 is a perspective view (side view) of the structure of FIG. 4A viewed from the dotted line L1 in FIG.

  4A and 4B, the power semiconductor device of the comparative example has basically the same configuration as the power semiconductor device of the present embodiment of FIG. 4 is different from FIG. 1 in that the sealing member 9 does not have two regions 9aa and 9bb having different thicknesses. Since the configuration of the other comparative example (FIG. 4) is almost the same as that of Embodiment 1 (FIG. 1), the same elements are denoted by the same reference numerals, and the description thereof will not be repeated.

  During the operation of the power semiconductor device, a high voltage is applied to the circuit pattern formed by the semiconductor element 5 and the substrate 3 (surface electrode 3c). In the power semiconductor device of the comparative example of FIG. 4, since the sealing member 9 is formed of silicone gel, a high creeping withstand voltage such as the substrate 3 is ensured with a short creepage length even when such a high voltage is applied. can do. In addition, the sealing member 9 can electrically insulate the semiconductor element 5, the electrode member 7, and the wire 17 from each other, for example.

  When a high voltage is applied to the semiconductor element 5 or the like of the power semiconductor device of the comparative example shown in FIG. 4 and the semiconductor element 5 reaches a high temperature, the substrate 3 and the electrode member 7 and the sealing member 9 that covers and contacts the substrate 3 and the electrode member 7 As a result, bubbles may be generated at the interface, and as a result, the creeping withstand voltage of the substrate 3 or the like may be reduced, causing a problem that the reliability of the power semiconductor device is reduced. This is because moisture present inside the sealing member 9 and at the interface between the sealing member 9 and each member such as the substrate 3 in contact with the sealing member 9 is vaporized by heat during operation of the semiconductor element 5. This is considered to occur when the amount of gas generated is greater than the gas diffusion rate inside. Such a phenomenon occurs remarkably when a semiconductor element 5 (chip) made of silicon carbide is used and an operation in which the maximum junction temperature (Tjmax) of the semiconductor element 5 exceeds 150 ° C. is performed.

  In order to suppress such a phenomenon, for example, it is conceivable to fill a liquid insulating oil having high heat resistance into the case 1 in which the semiconductor element 5 is housed. There is a possibility that it is difficult to seal and the yield of the product cannot be improved.

  Therefore, in order to suppress such a phenomenon, the inventors of the present invention have conducted extensive research. As a result, the generation of the bubbles due to the temperature rise is caused by the moisture permeability of the silicone gel constituting the sealing member 9 being the temperature of the silicone gel. We paid attention to change depending on.

  5A and 5B are perspective views (side views) seen from the dotted line L2 in FIG. 4A toward the left side of the figure. Referring to FIG. 5A, for example, the region on the relatively right side of the drawing corresponds to a position directly above the semiconductor element 5 that is at a high temperature, and therefore the sealing member 9 is at a relatively high temperature (this is illustrated in the drawing). "H"). On the other hand, for example, since the semiconductor element 5 is not arranged in the region on the left side of the drawing, the sealing member 9 becomes relatively low temperature (this is indicated by “L” in the drawing).

  In the region H in which the sealing member 9 is sufficiently warmed, the gas diffusion rate of the sealing member 9 is large, so that the gas Gs (water vapor) actively flows from above the semiconductor element 5 into the sealing member 9 as indicated by arrows. Is moved upward in the Z direction. That is, the gas Gs generated by the vaporization of moisture due to the high-temperature operation of the semiconductor element 5 actively moves above the sealing member 9 and is discharged to the outside of the sealing member 9.

  On the other hand, in the region L where the sealing member 9 is cooled, the gas diffusion rate of the sealing member 9 is small, and the gas Gs generated by the vaporization of moisture due to the high temperature operation of the semiconductor element 5 moves in the sealing member 9. It is hard to be discharged outside. Therefore, as shown in FIG. 5B, bubbles 25 are likely to be generated particularly at the interface between the sealing member 9 and the substrate 3 in the low temperature region 21 of the sealing member 9.

  Therefore, as in FIGS. 5A and 5B, refer to FIGS. 6A and 6B which are perspective views (side views) seen from the dotted line L2 in FIG. Then, as shown in the present embodiment (FIG. 1), the sealing member 9 in the case 1 has other regions (specifically, the low temperature region 21: the second region 9bb) in the other region ( It is formed so that the thickness in the Z direction is 1 mm or more thinner than the first region 9aa).

  Thereby, in the low temperature region 21 where the temperature rise due to the heat generated during the operation of the semiconductor element 5 in the case 1 is unlikely to occur, the sealing member 9 is thinner than the other regions, so that the bubbles 25 are smaller than the other regions. The distance to move in the direction is shortened. For this reason, as shown by a thick arrow in FIG. 6B, the bubbles 25 due to heating are quickly discharged out of the sealing member 9 even in the low temperature region 21. Accordingly, it is possible to suppress a decrease in creeping withstand voltage of the substrate 3 or the like due to the bubbles 25 staying in the vicinity of the interface even in the low temperature region 21 and to improve the reliability of the power semiconductor device.

  On the other hand, in the first region 9aa, the sealing member 9 that is 1 mm or more thicker than the second region 9bb is formed, so that the function of protecting the semiconductor device from the outside can be further ensured, and the semiconductor element 5 And insulation between the electrode member 7 and the wire 17 can be ensured.

  As the step between the first region 9aa and the second region 9bb is larger, the second region 9bb is basically thinner, and thus the above-described effect is increased.

  In the present embodiment, since the sealing member 9 is heated using the heat generated by driving the semiconductor element 5, it is not necessary to supply, for example, power for heating the sealing member 9 from the outside. For this reason, it is possible to warm the sealing member 9 at a low cost and with high efficiency, and to suppress the occurrence of problems due to the retention of the bubbles 25.

  In the present embodiment, the second region 9bb where the sealing member 9 is thin is provided in a region other than the region overlapping the semiconductor element 5 and the electrode member 7 in plan view. In the region overlapping with the semiconductor element 5 and the electrode member 7, the sealing member 9 is likely to be warmed by these heat generations, but heat generated from the semiconductor element 5 or the like is difficult to be transmitted in other regions. For this reason, the effect of discharging the bubbles 25 as described above can be enhanced by thinning the sealing member 9 in the region where the heat is not easily transmitted.

  If the second region 9bb is made thinner, the amount of heat necessary to warm the region is reduced, and the region is likely to be warmed. For this reason, the gas Gs (water vapor) can be more efficiently discharged to the outside by forming the second region 9bb.

  In the present embodiment, the sealing member 9 is formed by the moisture permeable film 10 so as to be divided into two regions 9aa and 9bb having different thicknesses. Thereby, for example, the sealing process by the sealing member 9 is simplified as compared to the case where two regions having different thicknesses are formed on the sealing member 9 using the auxiliary member 27 as in the second embodiment described later. . This is because the auxiliary member 27 does not need to be removed after completion of the sealing process and can remain in the final product.

  In the power semiconductor device according to the present embodiment, the height of the surface of the surface electrode 3c (related to the Z direction) and the surface (second sealing upper side) on the same side as the one main surface of the substrate 3 in the second region 9bb (upper Z direction). The difference between the height of the stopper member uppermost surface 9b (corresponding to the position where the moisture permeable membrane 10 is placed) and the height (with respect to the Z direction) is preferably 25 mm or less. Thereby, since the thickness of the sealing member 9 in the second region 9bb in the Z direction is sufficiently thin to enhance the gas Gs discharge effect, the gas Gs discharge effect is further enhanced. At this time, the difference between the height (in the Z direction) of the surface of the surface electrode 3c and the height in the Z direction between the first sealing member uppermost surface 9a is more than 25 mm, and is usually 28 mm or more. is there.

  Furthermore, in the power semiconductor device according to the present embodiment, the temperature of the surface (upper side in the Z direction) during the operation of the semiconductor element 5 (chip) and one main surface of the substrate 3 in the sealing member 9 are driven. It is preferable that the difference from the minimum value of the temperature on the same side as the surface (upper Z direction) (that is, the first sealing member uppermost surface 9a or the second sealing member uppermost surface 9b) is 120 ° C. or less. That is, referring again to FIG. 1B, the temperature T1 of the upper surface in the Z direction (on which many fine elements are mounted) of the semiconductor element 5 and the minimum value T2 of the temperatures of the sealing member uppermost surfaces 9a and 9b. The difference from (T1> T2) is 120 ° C. or less. In this way, since it can be said that the whole sealing member 9 is relatively warm, the bubbles 25 are easily discharged, and the reliability of the power semiconductor device can be improved. These features will be described later in detail as examples.

  The power semiconductor device described above is a so-called case type power semiconductor device formed by the base plate 15 and the substrate 3 including the insulating substrate 3a thereon. However, the present invention is not limited to this. For example, a so-called case-type power module structure in which a metallic substrate is placed on the base plate 15 with an organic insulating film interposed therebetween also achieves the same effect as the above-described embodiment. be able to.

(Embodiment 2)
7A, 7B, and 7C show the power semiconductor device of the second embodiment in the same manner as in FIGS. 1A, 1B, and 1C of the first embodiment (the same as in FIG. It shows an aspect as seen from the location and from the same direction. Referring to FIGS. 7A, 7B, and 7C, the power semiconductor device of the present embodiment has basically the same configuration as the power semiconductor device of the first embodiment of FIG. However, the first region 9aa and the second region 9bb having different thicknesses of 1 mm or more are formed without the moisture permeable membrane 10 and the guide member 11 being installed. In this respect, FIG. 7 differs from FIG. 1, but the configuration of the present embodiment (FIG. 7) other than this is substantially the same as the configuration of the first embodiment (FIG. 1). The same reference numerals are given and description thereof will not be repeated.

Next, a method for manufacturing the power semiconductor device of the present embodiment will be described with reference to FIG.
Referring to FIG. 8A, for example, as in FIG. 3A, case 1 having a base plate 15 bonded to the bottom is prepared, and substrate 3 is placed on the upper surface of base plate 15 (in case 1). Each member such as the semiconductor element 5 and the electrode member 7 is placed.

  Next, the auxiliary member 27 is installed in a region where the thin second region 9bb of the sealing member 9 is to be formed, for example, near the edge in the case 1 in the Y direction. The auxiliary member 27 is preferably a rectangular parallelepiped member made of, for example, Teflon, and a release agent may be applied to the surface thereof. The auxiliary member 27 is installed in a region where the space 14 is formed in the region where the second region 9bb is to be formed. In that state, the gel 20 for forming the sealing member 9 is supplied similarly to FIG. 3 (B).

  At this time, the supply of the gel 20 is stopped when it reaches the height of the lowermost part of the auxiliary member 27 in the Z direction in the region to be the second region 9bb. On the other hand, since the auxiliary member 27 is not disposed in the region to be the first region 9aa, the auxiliary member 27 is supplied to be higher than the lowermost portion of the auxiliary member 27 in the Z direction. For this reason, in the area | region (area | region which should become 2nd area | region 9bb) where the auxiliary member 27 is arrange | positioned, the uppermost surface becomes lower compared with the area | region (area | region which should become 1st area | region 9aa) where the auxiliary member 27 is not arrange | positioned. Gel 20 is supplied (so that there is a step).

  With reference to FIG. 8 (B), the gel 20 is secondarily degassed for 10 minutes under a vacuum of 13.3 Pa and heated at 70 ° C. for 1 hour with the auxiliary member 27 still installed. By being cured, the sealing member 9 is obtained. Referring to FIG. 8C, auxiliary member 27 is removed after curing. Referring to FIG. 8D, the lid 13 is attached in the same manner as in FIG. 3C, whereby the sealing member 9 is sealed in the case 1 and the power semiconductor device is completed.

  7 and 8, the sealing member uppermost surfaces 9a and 9b are formed in a planar shape. However, the present invention is not limited to this. For example, the sealing member uppermost surfaces 9a and 9b are curved. May be. 7 and FIG. 8, two sealing member uppermost surfaces 9a and 9b having different heights in the Z direction are formed. However, the present invention is not limited to this, and for example, three or more heights in the Z direction are formed. The top surfaces of the sealing members having different thicknesses (that is, three or more regions of the sealing members 9 having different thicknesses) may be formed. In short, when the power semiconductor device can be reduced by thinly forming a region where the sealing member 9 is difficult to warm, the top surface of the sealing member 9 is not limited.

  Even when the first and second regions 9aa and 9bb are formed by using the auxiliary member 27 to be removed in the final product without using the moisture permeable membrane 10 and the guide member 11 as in the present embodiment. As in the case of the first embodiment, the bubbles 25 can be quickly discharged to the outside of the sealing member 9 in the second region 9bb. Accordingly, it is possible to suppress a decrease in creeping withstand voltage of the substrate 3 or the like due to the bubbles 25 staying in the vicinity of the interface even in the low temperature region 21 and to improve the reliability of the power semiconductor device. Other functions and effects of the present embodiment are basically the same as those of the first embodiment.

(Embodiment 3)
9A is a plan view similar to FIG. 7A, and FIG. 9B is a perspective view seen from the dotted line L3 in FIG. 9A upward. 9C is a perspective view seen from the dotted line L4 in FIG. 9A toward the left side of the figure, and FIG. 9D is a perspective view seen from the dotted line L5 in FIG. 9A toward the right side of the figure. .

  Referring to FIGS. 9A, 9B, 9C, and 9D, the basic configuration of the power semiconductor device of the present embodiment is the same as that of the power semiconductor device of the second embodiment in FIG. However, in the present embodiment, the case 1 is large, and the number of substrates 3 and semiconductor elements 5 housed in the case 1 is increased compared to the first embodiment.

  Specifically, in FIG. 9, a plurality of (for example, a total of eight in this case) substrates 3 are arranged in a storage space inside one large case 1 at intervals. That is, four rows 3 in the X direction and two rows in the Y direction are arranged in a matrix, and the four substrates 3 in the upper Y direction in FIG. 9A are the substrate 31, the substrate 32, the substrate 33, The four substrates 3 on the lower stage in the Y direction in FIG. 9A are a substrate 35, a substrate 36, a substrate 37, and a substrate 38 in order from the left side.

  As shown in FIGS. 9B, 9 </ b> C, and 9 </ b> D, similarly to the substrate 3, the substrates 31 to 38 include insulating substrates 31 a to 38 a and a back electrode 31 b on the main surface on the lower side in the Z direction. To 38b and surface electrodes 31c to 38c on the main surface on the upper side in the Z direction of the insulating substrates 31a to 38a.

  Each of the substrates 31 to 38 is mounted with, for example, four semiconductor elements 5 and electrically connected using the wires 17 in the same manner as the substrate 3 in the first embodiment. A single large base plate 15 is bonded so as to be in contact with all the back electrodes 31b to 38b of these substrates 31 to 38, whereby a power semiconductor device including the large case 1 is configured.

  As shown in FIG. 9A and the like, a plurality (six in this case) of guide members 11 are arranged at a distance from each other in a part of a relatively outer region of the region in the case 1. As a result, in a plurality of (six here) regions surrounded by the wall surface of the case 1 and the guide member 11, the uppermost surface 9b of the sealing member 9 is lower (for example, 1 mm or more) than the other regions 9aa. This is the second area 9bb.

  Although such a configuration has the guide member 11, it is formed by a process similar to the process shown in FIG. 8 of the second embodiment. That is, the gel 20 for forming the sealing member 9 in a state where the auxiliary member 27 to be finally removed is addressed to the region surrounded by the guide member 11 and the case 1 as in FIG. Is supplied, a second region 9bb having a thickness in the Z direction thinner than the other regions is formed in the region surrounded by the guide member 11 and the case 1.

  Thus, if the guide member 11 and the auxiliary member 27 (see FIG. 8A) are used in combination, the position where the guide member 11 should be formed can be adjusted with high accuracy using the auxiliary member 27. Manufacturing variations in the range of the second region 9bb of the member 9 can be suppressed. However, also in the present embodiment, for example, as in the first embodiment, the gel 20 is supplied in a state where the moisture permeable membrane 10 finally remaining in the product is installed in the region surrounded by the guide member 11 and the case 1. Alternatively, for example, similarly to the second embodiment, the two regions 9aa and 9bb may be formed without using the guide member 11 and the moisture permeable membrane 10.

  In FIG. 9, a single source electrode 7a and drain electrode 7b are connected to each substrate 31-38 (surface electrode 3c thereof). The source electrode 7a can be electrically connected to the outside of the power semiconductor device by, for example, three source terminals 7a1, 7a2 and 7a3 connected thereto. Similarly, the drain electrode 7b can be electrically connected to the outside of the power semiconductor device by, for example, three drain terminals 7b1, 7b2, and 7b3 connected thereto. The source terminals 7a1, 7a2, 7a3 and the drain terminals 7b1, 7b2, 7b3 are arranged so as to be exposed to the outside of the case 1. On the other hand, one gate electrode 7c is connected to each of the substrates 31 to 38 so as to extend upward in the Z direction so as to be exposed outside the case 1.

  FIG. 9 is different from FIG. 7 in the above points, but the configuration of the present embodiment (FIG. 9) other than this is substantially the same as the configuration of the second embodiment (FIG. 7). Are denoted by the same reference numerals, and the description thereof will not be repeated.

Next, the effect of this Embodiment is demonstrated.
In a power module for trains, for example, for driving an inverter through which a large current flows, a large power semiconductor device (package having a large case 1) may be used as in this embodiment. In this case, the variation in the temperature distribution in the sealing member 9 is further larger than that in the first embodiment, and a region where gas diffusion is difficult such as the low temperature region 21 in FIGS. 4 and 5 may be expanded. There is. For this reason, if the sealing member 9 having the two regions 9aa and 9bb having different thicknesses is formed for the large-sized power semiconductor device as in the present embodiment, the two regions 9aa and 9bb having different thicknesses do not exist. Great effects can be obtained compared to the case.

  Also in the present embodiment, as in the other embodiments, the difference between the height of the surface electrode 3c (with respect to the Z direction) and the height of the second sealing member uppermost surface 9b may be 25 mm or less. preferable. Also in the present embodiment, it is preferable that the difference between the temperature T1 of the upper surface of the semiconductor element 5 and the minimum temperature T2 of the sealing member uppermost surfaces 9a and 9b is 120 ° C. or less.

  In FIG. 9B, the thickness of the sealing member 9 in the second region 9bb on the left side and the second region 9bb on the right side are different from each other, and the second region 9bb on the right side is thicker. (The uppermost surface 9b of the second region 9bb on the right side is disposed above the uppermost surface 9b of the second region 9bb on the left side in the Z direction). Thus, the sealing member 9 may have a plurality of second regions 9bb having different thicknesses. For example, by forming the second region 9bb that is particularly thinner than the other second region 9bb in a region where the temperature of the sealing member 9 is difficult to increase, the operational effects of the present embodiment can be further enhanced.

  In this example, the power semiconductor device is a small power semiconductor device particularly as shown in the second embodiment, and the auxiliary member 27 is used (without using the moisture permeable membrane 10 and the guide member 11). Two regions 9aa and 9bb are formed. The thermal diffusion in the sealing member 9 and the creeping insulation resistance (reliability of the power semiconductor device) when the power semiconductor device is driven are examined. First, a sample used for the investigation of this example will be described with reference to FIGS.

  Referring to FIGS. 10A to 10C, these correspond to samples 1, 2 to 4 and 5 of the power semiconductor device for investigation, respectively. Specifically, the sample 1 corresponds to the power semiconductor device of the comparative example of FIG. 4A shown in FIG. 10A, and the sealing member 9 does not have two regions 9aa and 9bb having different thicknesses. The whole has a substantially uniform thickness. The height difference X in the Z direction between the surface on the upper side in the Z direction of the surface electrode 3c of the sample 1 and the uppermost surface 9a in the Z direction of the sealing member 9 is 28 mm.

  Sample 2 corresponds to the power semiconductor device of the first embodiment shown in FIGS. 1A and 1C shown in FIG. 10B, and has a moisture permeable film 10 and a guide member 11 to thereby form a sealing member 9. Two regions having different thicknesses are formed. The moisture permeable membrane 10 is installed later after the case 1 is formed, and its thickness in the Z direction is 1.7 mm. The height difference X in the Z direction between the surface on the upper side in the Z direction of the surface electrode 3c and the uppermost surface 9b of the thin second region 9bb is 27 mm.

  Sample 3 corresponds to the power semiconductor device of the first embodiment shown in FIGS. 1A and 1C shown in FIG. 10B as in sample 2, but the height difference X is 25 mm. ing. Sample 4 corresponds to the power semiconductor device of the first embodiment shown in FIG. 1 (A) shown in FIG. 10 (B) like sample 2, but the height difference X is 20 mm.

  The sample 5 corresponds to the power semiconductor device of the second embodiment shown in FIGS. 7A and 7C shown in FIG. 10C, and does not have the moisture permeable film 10 and the guide member 11 but the sealing member 9. Two regions having different thicknesses are formed. The height difference X in the Z direction between the surface on the upper side in the Z direction of the surface electrode 3c and the uppermost surface 9b of the thin second region 9bb is 25 mm.

In the substrates 3 of the samples 1 to 5, the insulating substrate 3a was formed of silicon nitride (Si ₃ N ₄ ), and the back surface and the surface electrodes 3b and 3c were formed as a copper pattern. The semiconductor element 5 (chip) bonded so as to be in contact with the surface electrode 3c is formed of silicon carbide (SiC), and a number of MOSFETs and Schottky barrier diodes are mounted on the surface thereof. Base plate 15 joined so as to be in contact with back electrode 3b was formed of aluminum silicon carbide. The electrode member 7 was connected on the surface electrode 3c by ultrasonic bonding. The wire 17 was connected to the surface electrode 3c and the semiconductor element 5 by ultrasonic bonding.

  A case in which the case 1 made of polyphenylene sulfide formed so as to surround the periphery of the base plate 15 in plan view is bonded to the base plate 15 so that the substrate 3 and the semiconductor element 5 are arranged in the case 1 became. The base plate 15 and the case 1 were bonded with a silicone adhesive. Here, the sealing member 9 is supplied by the method shown in FIG. 3 or FIG. 8 so that two regions having different thicknesses are formed particularly for the samples 2 to 5, thereby the substrate 3 and the semiconductor element 5. Etc. were sealed in the case 1.

  In this embodiment, a base polymer (weight average molecular weight 38700) is used as the sealing resin as the sealing member 9, and a complex of platinum and divinyltetramethyldisiloxane (the platinum metal in the composition is expressed in weight units). A silicone gel composition was prepared by uniformly mixing (amount of 5 ppm). After the silicone gel composition was vacuum degassed, the silicone gel composition was poured into an intermediate power semiconductor device in which the base plate 15 and the case 1 were bonded, and heated at 70 ° C. for 60 minutes.

  This silicone gel had a penetration of 40 and tan δ (0.1 Hz) of 0.30. Here, tan δ is called a loss factor and is a value that can be measured by a rheometer. The smaller this value, the better the shock absorption. The height of the sealing member uppermost surface 9a in the thicker region of the two regions having different thicknesses of the sealing member 9 with respect to the uppermost surface of the surface electrode 3c was 28 mm.

  By attaching the lid 13 to the power semiconductor device in the above intermediate stage, samples 1 to 5 of the power semiconductor device were formed, and a reliability test was performed on the samples 1 to 5. Next, the reliability test method will be described.

  The reliability test of the power semiconductor device was performed by putting the samples 1 to 5 into a constant temperature and humidity chamber, and then performing a power cycle test and evaluating the insulation resistance of the samples 1 to 5 thereafter. In the constant temperature and humidity chamber, the power semiconductor device is loaded for 16 hours under a temperature and humidity condition of 85 ° C. and 85%, and then the condensed water is dried and removed at 85 ° C. for 60 minutes. After removing condensed water, the power semiconductor device was cooled to room temperature and a power cycle test was performed. A high voltage of 8000 V was applied between the substrate 3 and the base plate 15 every specified number of times during the power cycle test, and the insulation resistance was measured. The power cycle test was conducted up to 300 k cycles, and the reliability of Samples 1 to 5 was confirmed by confirming the presence or absence of creeping breakdown due to the deterioration of the insulation resistance when the high voltage was applied.

  Referring to FIG. 10 (D), the temperature of the sealing member 9 is any one of four points where the X coordinate shown in FIG. 10 (D) is 1 to 4, and the Y coordinate is 1 to 3 The temperature of the sealing member uppermost surface 9a or the sealing member uppermost surface 9b at a total of 12 points (12 locations) was measured using a thermocouple. The distance between adjacent X coordinates 1, 2, 3, 4 and the distance between adjacent Y coordinates 1, 2, 3 are 25 mm. In the following, among the points at which the temperature of the uppermost surface of the sealing member 9 is measured, for example, a point having an X coordinate of 1 and a Y coordinate of 2 will be expressed as (1, 2).

The temperature during continuous operation (Tj (op)) was measured using a MOSFET temperature sensor. The module was operated at the rated 6500 V, the surface temperature (chip temperature) of the semiconductor element 5 at this time was measured, and the operation was controlled so that the chip temperature (T _OPmax ) at the rated operation did not exceed 175 ° C. Further, the temperature of each point of the sealing member 9 when the module was operated at a high voltage of 6500 V was examined. Therefore, basically, the temperature of the surface of the semiconductor element 5 at the time of measuring the temperature of the sealing member uppermost surfaces 9a and 9b is 175 ° C., and this temperature and the sealing member uppermost surface 9a or the sealing member uppermost surface 9b The difference between each point (12 points) and the temperature was examined. The results are shown in Table 1 below.

  “Thermocouple temperature” in Table 1 indicates a value obtained by measuring the temperature at each point (12 points) of the sealing member uppermost surface 9a (or the sealing member uppermost surface 9b) with a thermocouple. “Difference” indicates the temperature difference between the temperatures (12 points) of the sealing member uppermost surfaces 9a and 9b and the surface of the semiconductor element 5 (175 ° C.). The underline in the table indicates the minimum temperature measured for each sample.

  Referring to Table 1, in sample 1, which is equivalent to the comparative example (FIG. 4) and has a uniform thickness without providing two regions having different thicknesses in the sealing member 9, the temperature at (4, 3) is 47 ° C. Thus, the temperature difference from the chip was 128 ° C. When the power cycle test was performed for 120 k cycles, generation of bubbles and traces of dielectric breakdown were confirmed in the portion of the substrate 3 just below the Z direction at the position (4, 3).

  In the power semiconductor device of sample 1, the surrounding moisture is vaporized by heating of the semiconductor element 5, but the surrounding silicone gel exceeds the vaporization rate at the position (4, 3) where the temperature of the sealing member 9 is not increased. It is considered that bubbles are generated due to the low diffusion rate of. As a result, it is considered that dielectric breakdown occurred at the site where bubbles were generated during the subsequent evaluation of insulation resistance. Moreover, since the surface temperature of the silicone gel is low at the site where the bubbles are generated, it is considered that the moisture permeability of the silicone gel in this region is particularly lower than that in other areas, which is also a factor in generating bubbles in this portion.

  Sample 2 is an example in which the second region 9bb is formed by the moisture permeable membrane 10, but the height X of the second sealing member uppermost surface 9 from the surface electrode 3c is 27 mm, and the first sealing member uppermost surface is 9 mm. Since the height of the upper surface 9a from the surface electrode 3c is 28 mm, these steps are 1 mm. In this case, the number of power cycles until dielectric breakdown increases to 240 k and the temperature difference from the chip decreases to 124 ° C. It can be said that it has the effect of. However, even in this case, since the value of X is large (because the distance from the surface electrode 3c of the second sealing member uppermost surface 9b is large), the second sealing member uppermost surface 9b at the position (4, 3) The temperature did not rise sufficiently (51 ° C.), and generation of bubbles 25 and dielectric breakdown traces were confirmed in the portion of the insulating substrate 3a at the position.

  On the other hand, for samples 3 and 4, regions 9aa and 9bb are formed as in sample 2, but the height X of the second sealing member uppermost surface 9b from the surface electrode 3c is higher than that of sample 2 (27 mm). It is short (25 mm or less). In this way, dielectric breakdown does not occur after a predetermined number of power cycles, and the reliability is further improved as compared with sample 2. In addition, the temperature difference from the chip at this time is 120 ° C. or less, and the temperature of the second sealing member uppermost surface 9b is further increased from that of the sample 2. Therefore, also in the low temperature region 21 (see FIG. 4). It is thought that the diffusion of bubbles in the sealing member 9 further progressed and the dielectric breakdown was suppressed.

  Thus, it is clear that by setting X to 25 mm or less and the level difference of the sealing member 9 between the two regions 9aa and 9bb to 3 mm or more, the reliability can be ensured even when the power semiconductor device is heated. It became. It has also been clarified that the reliability of the power semiconductor device can be ensured if the difference between the surface temperature of the silicone gel constituting the sealing member 9 and the chip temperature is 120 ° C. or less.

  Although not shown in Table 1, if at least X is 25 mm or less, if the level difference of the sealing member 9 between the two regions 9aa and 9bb is 1 mm or more, the region 9bb is defined as a region where the sealing member 9 is thin. The reliability of the power semiconductor device can be increased by increasing the temperature and promoting bubble diffusion.

  For sample 5, moisture permeable membrane 10 and guide member 11 are not provided, but in this case as well as sample 3, by setting X to 25 mm (step difference of sealing member 9 to 3 mm), It became clear that the reliability could be ensured similarly to Sample 3. Also in this case, it has also been clarified that the reliability of the power semiconductor device can be ensured if the difference between the surface temperature of the silicone gel constituting the sealing member 9 and the chip temperature is 120 ° C. or less.

  Note that it is considered that the difference between the chip temperature and the sample 4 in Sample 4 is the smallest because X is the smallest and the surface of the sealing member 9 was easily warmed.

  In the present embodiment, in particular, in the sealing member 9 when a large-sized power semiconductor device having a plurality of (for example, eight) substrates 3 is driven in one case 1 as shown in the third embodiment. Investigating thermal diffusion and creeping insulation resistance. First, the sample used for the investigation of this example will be described with reference to FIGS.

  Referring to FIGS. 11A to 11D, this corresponds to the sample 6 of the power semiconductor device for investigation. 11A to 11D have basically the same configuration as the power semiconductor device of the third embodiment shown in FIGS. 9A to 9D, but the sealing member 9 has a thickness. FIG. 11 is different from FIG. 9 in that it does not have two different regions 9aa and 9bb. In this sense, the sample 6 in FIG. 11 is a sample for comparison with the third embodiment. Other than this, the configuration of the sample 6 (comparative example) in FIGS. 11A to 11D is almost the same as the configuration of the third embodiment in FIGS. The same reference numerals are given and description thereof will not be repeated.

  With reference to FIGS. 12A to 12D, this corresponds to the sample 7 of the power semiconductor device for investigation. 12A to 12D have basically the same configuration as the power semiconductor device of the third embodiment shown in FIGS. 9A to 9D, and the guide member 11 is similar to FIG. And a plurality of (here, six) second regions 9bb that do not have the moisture permeable membrane 10 are disposed.

  11A and 12A again, in FIGS. 11A and 12A, from any of the source electrode 7a, the drain electrode 7b, and the gate electrode 7c of the electrode member 7. An area where the shortest distance of the distance exceeds 25 mm is indicated as an area 51.

  In FIG. 12A, the second region 9bb surrounded by the guide member 11 and the case 1 is formed in a region substantially overlapping the region 51, and at least the second region 9bb overlaps a part of the region 51. Is formed. In FIG. 12A, the second region 9bb partially overlaps the semiconductor element 5 in plan view (unlike Embodiment Mode 1), but may have such a configuration. .

  Since the materials of the various members constituting these samples, the method of manufacturing each sample, and the method of reliability testing are the same as those in Example 1, the description thereof will not be repeated. Referring to FIG. 11A again, the temperature of the sealing member 9 is the top surface of the sealing member at three points A, B, and C shown in FIG. The temperature of 9a, 9b was measured using a thermocouple.

  Table 2 below shows the results of the same investigation as Samples 1 to 5 on Samples 6 and 7.

  Referring to Table 2, in the power semiconductor device of Sample 6 corresponding to the comparative example (FIG. 11), the temperature at point B was 45 ° C., and the temperature difference from the chip was 130 ° C. Also, dielectric breakdown marks were confirmed when the power cycle test was performed for 60 k cycles.

  On the other hand, by providing two regions 9aa and 9bb having different thicknesses in the sealing member 9 as in the sample 7, the temperature difference from the chip is reduced, and the dielectric breakdown is continued after a predetermined number of power cycles. Did not happen. Also in this example, the reliability of the power semiconductor device could be improved by forming the two regions 9aa and 9bb having different thicknesses in the sealing member 9 based on the same theory as in the first example.

  The region 51 is a region away from any of the electrode members 7 and is a region that tends to become the low temperature region 21 (see FIGS. 4 and 5) of the sealing member 9. Therefore, by providing the second region 9bb where the thickness of the sealing member 9 is thin in this region, it is possible to shorten the distance to which the bubbles move in the region 51, and there are effects such as suppression of the retention of bubbles. it can.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Case, 1a Groove part, 3 board | substrate, 3a insulation board, 3b back surface electrode, 3c surface electrode, 5 semiconductor element, 7 electrode member, 9 sealing member, 9a 1st sealing member top surface, 9aa 1st area | region, 9b 1st 2 sealing member top surface, 9bb 2nd region, 10 moisture permeable membrane, 10a moisture permeable membrane outer frame, 11 guide member, 13 lid, 14 gap, 15 base plate, 17 wire, 19 mounting screw hole, 20 gel, 21 Low temperature region, 25 bubbles, 27 auxiliary members, Gs gas.

Claims (11)

A substrate placed in the case;
A semiconductor element mounted on one main surface of the substrate;
A sealing member filling the case,
The said sealing member is a semiconductor device which has a 1st area | region and a 2nd area | region where thickness is thinner than the said 1st area | region.   2. The semiconductor device according to claim 1, wherein the second region of the sealing member is thinner than the first region by 1 mm or more.   The semiconductor device according to claim 1, wherein a base plate is connected to the other main surface of the substrate opposite to the one main surface.   The semiconductor device according to claim 3, wherein a material constituting the base plate is any one selected from the group consisting of copper, aluminum silicon carbide, and copper molybdenum.   5. The semiconductor device according to claim 1, wherein the second region has a plurality of regions in which the thickness of the sealing member is different from each other.   The semiconductor device according to claim 1, wherein the sealing member is a silicone resin. A surface electrode formed so as to cover at least a part of the one main surface of the substrate;
The difference between the height of the surface of the surface electrode and the height of the surface on the same side as the one main surface of the sealing member in the second region is 25 mm or less. A semiconductor device according to 1.   The difference between the temperature of the surface during driving of the semiconductor element and the minimum value of the temperature of the surface on the same side as the one main surface of the sealing member is 120 ° C. or less. 2. A semiconductor device according to item 1.   The material constituting the semiconductor element is any one selected from the group consisting of silicon carbide, gallium nitride, diamond, and a composite material of silicon carbide, gallium nitride, and diamond. 2. The semiconductor device according to claim 1. An electrode member connected to the substrate and electrically conductive with the outside of the semiconductor element;
10. The semiconductor device according to claim 1, wherein the second region is provided in a region other than a region overlapping the semiconductor element and the electrode member in plan view.   11. The semiconductor device according to claim 1, wherein a surface of the second region on the same side as the one main surface is covered with a moisture permeable film.

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