JP2011061030A - Crystal silicon-based solar cell - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photovoltaic device having improved photoelectric conversion efficiency, in a photovoltaic device that uses a single-crystal silicon substrate. <P>SOLUTION: A crystal silicon solar cell uses a one conductivity-type single-crystal silicon substrate and includes: a p-type silicon-based thin-film layer on one surface of the substrate; a substantially intrinsic silicon-based thin-film layer between the substrate and the p-type silicon-based thin-film layer; an n-type silicon-based thin-film layer on the other surface of the substrate; and a substantially intrinsic silicon-based thin-film layer between the substrate and the n-type silicon-based thin-film layer. In the crystal silicon solar cell, the substrate is as thick as not more than 150 μm, texture structures made of quadrangular pyramids are provided on an incidence-side surface and a back-side surface of the substrate, the arithmetic mean roughness on the incidence-side surface of the substrate is not more than 1,500 nm, and the arithmetic mean roughness of the back-side surface is not less than 2,000 nm. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a crystalline silicon solar cell having a heterojunction on the surface of a single crystal silicon substrate.

  A crystalline silicon solar cell using a crystalline silicon substrate has high photoelectric conversion efficiency, and has already been widely put into practical use as a photovoltaic power generation system. Among them, a crystalline silicon solar cell in which an amorphous silicon thin film having a gap different from that of single crystal silicon is formed on the surface of the single crystal and a diffusion potential is formed is called a heterojunction solar cell. Above all, a solar cell in which a thin intrinsic amorphous silicon layer is interposed between a conductive amorphous silicon thin film for forming a diffusion potential and a crystalline silicon surface is a form of a crystalline silicon solar cell having the highest conversion efficiency. One. By forming a thin intrinsic amorphous silicon layer between the crystal surface and the conductive amorphous silicon thin film, defects present on the crystal surface can be passivated. In addition, it is possible to prevent carrier introduced impurities from diffusing to the crystalline silicon surface when the conductive amorphous silicon thin film is formed.

  Crystalline silicon has an anisotropy in the electronic state that reflects its periodic structure, and the wave number vectors at the top of the valence band and the bottom of the conduction band do not match. Necessary. This is called indirect transition, and crystalline silicon is called an indirect transition type semiconductor. When using indirect transition type semiconductors for solar cells, the optical absorption coefficient is low compared to direct transition type semiconductors that do not require interaction with phonons, so it is important how to confine light in the photoelectric conversion layer. It becomes one of. In order to confine light, it is necessary to control the optical characteristics of the solar cell, and the optical characteristics are mainly determined by the interface shape having a refractive index difference and the film thickness of each layer.

  In general, a crystalline silicon solar cell has a refractive index higher than that of a transparent electrode or metal formed on the surface, and light is easily confined in a medium having a high refractive index in terms of geometric optics. In order to increase the light confinement effect, it is necessary to bend the direction of the light directly incident on the solar cell. By providing a texture structure with a size of about the wavelength at the interface with respect to the incident surface, light can be incident obliquely on the interface having a refractive index difference, and the light traveling direction is bent by refracting the light. be able to. This effect increases the probability that the light is confined on the high refractive index side (silicon side) when the incident light reaches the incident side interface or the back side interface.

  When the distance between the interfaces formed by the thin films is on the order of a wavelength, the reflected light at each interface interferes and the reflected light increases or decreases due to the principle of wave superposition. In general, in the case of a crystal solar cell, interference is controlled by controlling the film thickness of a transparent electrode (refractive index 1.9) disposed on silicon (refractive index 3.9) on the incident surface side to about 60 to 100 nm. The reflection of light in the wavelength region (500 to 700 nm) having the strongest intensity in the optical spectrum is reduced. In the case of the refractive index configuration of air / transparent electrode / silicon, an optical design that interferes with reflected light at the interface of the transparent electrode is most effective, and a texture structure that does not impair the effect of this interference is presupposed. However, in order to actually use the solar cell, it is necessary to seal with a sealing member, and the refractive index of the sealing member is about 1.5, which is higher than that of air. That is, when a solar cell that requires sealing is used, the priority of optical design that uses interference by the transparent electrode is lower than when the sealing member is not used.

  In general, a texture in which square pyramids having a base of about 5 to 20 μm are arranged on the surface of a silicon substrate of a crystalline silicon solar cell, and a transparent electrode of about 60 to 100 nm is formed on the surface. This texture size is sufficiently large, 20 to 150 times the wavelength of light intended for absorption in silicon, and the refracted light travels through the crystalline silicon as a plane wave. There is no problem when the transparent electrode forms an interface with air, but when sealing is performed using a resin or the like, the reflectance of short-wavelength light that behaves as a plane wave increases. On the other hand, when the texture size is as small as 0.1 times or less with respect to the wavelength, the influence of the texture is extremely small, and the unrefracted light travels in the crystalline silicon as a plane wave, and the geometrical optical loss is also increased. By setting the texture size to about 0.8 to 20 times the wavelength of the light to be confined, the light can be scattered efficiently, and the light that has passed through the interface can no longer maintain a plane wave. Optical loss can be reduced.

  As a method for forming a texture on the surface of the crystalline silicon substrate, the texture is formed by anisotropic etching utilizing a difference in etching rate between the (100) plane and the (111) plane of silicon. When the silicon (100) plane is etched, a quadrangular pyramid-like texture consisting of a silicon (111) plane with a very slow etching rate is formed.

  In patent document 1, it is supposed that a sensitivity can be improved by making an incident surface, a side surface, and a back surface peripheral part into a texture structure. However, there is only one type of process for creating a texture on the incident surface, and there is no description of combining textures of different sizes, and this cannot sufficiently suppress the geometric optical reflection loss at the incident side interface.

JP 2006-286820 A

  An object of the present invention is to provide a photovoltaic device having excellent photoelectric conversion efficiency in a photovoltaic device using a single crystal silicon substrate.

  As a result of intensive studies in view of the above problems, the present inventors have found that in a crystalline silicon solar cell using a single crystal silicon substrate having a thickness of 150 μm or less, a quadrangular pyramid texture having an arithmetic average roughness of 1500 nm or less on the incident surface side. Is formed, a light having a wavelength of 300 to 900 nm is scattered, and a rectangular pyramid-like texture is formed on the back surface side so that the arithmetic average roughness is 2000 nm or more, thereby scattering the long wavelength light of 800 nm or more reaching the back surface. Thus, it was found that light in a wide wavelength range can be confined more efficiently, and the photoelectric conversion efficiency is improved.

  That is, the present invention uses a single-conductivity type single crystal silicon substrate, has a p-type silicon thin film layer on one surface of the substrate, and is substantially genuine silicon between the substrate and the p type silicon thin film layer. A crystalline silicon solar cell comprising an n-type thin film layer, having an n-type silicon thin film layer on the other surface of the substrate, and a substantially authentic silicon thin film layer between the substrate and the n-type silicon thin film layer The battery has a thickness of the substrate of 150 μm or less, and has a texture structure composed of quadrangular pyramids on the incident side surface and the back side surface of the substrate, and the arithmetic average roughness on the incident side surface of the substrate is 1500 nm. It is below, It is related with the crystalline silicon solar cell characterized by arithmetic mean roughness of the back surface side surface being 2000 nm or more.

  A preferred embodiment relates to the above crystalline silicon solar cell, wherein the arithmetic average roughness on the incident-side surface of the substrate is 500 nm or less, and the arithmetic average roughness on the back-side surface is 2000 nm or more.

  A preferred embodiment relates to the above crystalline silicon solar cell, wherein the arithmetic average roughness on the incident-side surface of the substrate is 300 nm or less and the arithmetic average roughness on the back-side surface is 2000 nm or more.

  The present invention is the method for manufacturing a crystalline silicon solar cell according to any one of the above, wherein the textured structure is formed by the step of forming the texture structure, the step of oxidizing the surface of the texture structure, and the step of oxidizing. The present invention also relates to a method for manufacturing a crystalline silicon solar cell, comprising the step of removing the silicon oxide layer.

  A preferred embodiment relates to the method for producing a crystalline silicon solar cell, wherein the texture structure is formed by etching.

  In a preferred embodiment, each of the two single-conductive single-crystal silicon substrates is exposed to a medium having an etching ability in a state where the two single-conductive single-crystal silicon substrates are combined on one side. The present invention relates to the method for producing a crystalline silicon solar cell, wherein the texture structure is formed only on one side that is not combined.

  With the structure of the present invention, the optical confinement characteristics are improved, and high photoelectric conversion efficiency is obtained mainly by improving the short-circuit current.

It is typical sectional drawing of the crystalline silicon solar cell which concerns on the Example of this invention.

  The crystalline silicon solar cell according to the present invention uses a single conductivity type single crystal silicon substrate having a substrate thickness of 150 μm or less, has a p-type silicon thin film layer on one surface of the substrate, and the substrate and the p-type silicon system. A substantially authentic silicon-based thin film layer is provided between the thin film layers, an n-type silicon-based thin film layer is provided on the other surface of the substrate, and the substrate is substantially genuine between the n-type silicon-based thin film layer. A silicon-based thin film layer, a texture structure composed of quadrangular pyramids on the incident side surface and the back side surface of the substrate, the arithmetic average roughness on the incident side surface of the substrate is 1500 nm or less, and the back side surface The arithmetic average roughness in is characterized by being 2000 nm or more.

  First, the one conductivity type single crystal silicon substrate in the crystalline silicon solar cell of the present invention will be described.

  In general, a single crystal silicon substrate contains impurities for supplying electric charge to silicon in order to have conductivity. Single crystal silicon substrates are classified into an n-type supplied with phosphorus atoms for introducing electrons into Si atoms and a p-type supplied with boron atoms for introducing holes (also called holes). When used in solar cells, electron-hole pairs can be efficiently separated and recovered by providing a strong electric field with the incident-side heterojunction that absorbs the most light incident on the single crystal silicon substrate as the reverse junction. it can. Therefore, the heterojunction on the incident side is preferably a reverse junction. On the other hand, when holes and electrons are compared, the mobility is generally higher for electrons having a smaller effective mass and scattering cross section. From the above viewpoint, it is more preferable that the one conductivity type single crystal silicon substrate used in the present invention is an n type single crystal silicon substrate.

  As a preferred configuration of the present invention when an n-type single crystal silicon substrate is used, a conductive oxide layer / p-type amorphous silicon thin film layer / i type amorphous silicon thin film layer / n single crystal Examples are silicon substrate / i-type amorphous silicon-based thin film layer / n-type amorphous silicon-based thin film layer / conductive oxide layer. In this case, the back surface is preferably an n-layer for the above reasons. For example, the thickness of the conductive oxide mainly composed of zinc oxide or the like is preferably in the range of 60 to 120 nm from the viewpoint of light confinement.

  The thickness of the one conductivity type single crystal silicon substrate is preferably 150 μm or less, more preferably 120 μm or less, from the viewpoint of saving raw material silicon. When the thickness of the single-conductivity-type single crystal silicon substrate is 150 μm or less, among the light incident on the solar cell, the ratio of the long wavelength light of 900 nm or more reaching the back surface interface increases. For this reason, the structure of this invention which can scatter short wavelength light with an incident side texture, and can effectively scatter long wavelength light with a back surface texture becomes more effective. On the other hand, the lower limit of the thickness of the single crystal silicon substrate is not particularly limited, but is preferably 30 μm or more, and more preferably 60 μm or more, from the viewpoint of stability during production and light absorption.

  In the present invention, the single crystal silicon substrate has a texture structure composed of quadrangular pyramids on the incident-side surface and the back-side surface of the substrate, and each surface has a specific arithmetic average roughness. And

  By providing a texture structure on each of the incident surface and the back surface and controlling the texture size on the incident surface and the back surface side, it is possible to obtain effective scattering characteristics for light having different wavelengths on the respective main surfaces.

  The texture shape is generally a quadrangular pyramid texture that is easily obtained by anisotropic etching of crystalline silicon. This structure can be formed relatively uniformly and is preferable from the viewpoint of productivity. The apex is preferably sharp from the optical point of view, but it is preferable that the apex, particularly the valley, is rounded from the viewpoint of amorphous silicon film formation and carrier recovery. The degree of roundness is preferably rounded in the same order as the film thickness of the amorphous silicon layer to be formed.

  From the viewpoint of light confinement, the surface of the light incident side of the substrate has a texture structure composed of quadrangular pyramids so that the upper limit is 1500 nm or less, preferably 500 nm or less, particularly preferably 300 nm or less. It is preferable. From the viewpoint of short wavelength light scattering, the lower limit of the arithmetic average roughness on the light incident side surface of the substrate is preferably 40 nm or more, and more preferably 80 nm or more.

  Next, from the viewpoint of scattering long-wavelength light, the back surface of the substrate is a texture composed of quadrangular pyramids such that the lower limit is 2000 nm or more, preferably 2050 nm or more, particularly preferably 2100 nm or more. It is preferable to provide a structure. The upper limit value of the arithmetic average roughness on the back surface of the substrate is not particularly limited, but is preferably 3500 nm or less, more preferably 3000 nm or less, from the viewpoint of carrier recovery.

  The arithmetic average roughness of the incident side surface and the back side surface is calculated from, for example, the surface shape measured by AFM. A reference length is extracted in the direction of the average line of the surface curve measured by the AFM, and the absolute value of the deviation from the average line of the extracted part to the measurement curve is summed and averaged.

  The method for forming the texture structure of the substrate is not particularly limited, and for example, it can be formed by a known method such as wet etching with an alkaline solution, rubbing, blasting, plasma etching, etc. From the viewpoint of shape uniformity and light confinement, it is particularly preferable to form by wet etching with an alkaline aqueous solution.

  From the viewpoint that a texture structure can be easily formed by anisotropic etching with different etching rates of the (100) plane and the (111) plane when etching a single crystal silicon substrate, the incident surface of the single crystal silicon substrate is ( It is preferable that it is cut out so that it is a 100) plane.

  In general, the texture size tends to increase as etching progresses. For example, when the etching time is lengthened, the texture size increases. However, the texture size can be increased by increasing the etchant concentration, the supply rate, the liquid temperature, or the like so that the reaction rate increases. In addition, since the etching rate varies depending on the surface state where etching is started, it may be used that the texture size is different between the surface subjected to the mechanical process such as polishing and the other surface. Furthermore, when the quadrangular pyramidal structures formed by the (111) plane are adjacent, that is, when the surface is covered by the (111) plane, the etching rate tends to be slow. Therefore, by providing an etching starting point, the density of the texture structure can be controlled and the size of the texture can be controlled. Further, the texture density generated in the initial stage can be controlled by etching using a fine mask. The etching starting point can be formed by a mechanical process such as polishing.

  Further, by performing isotropic etching with no selectivity on the (111) plane and the (100) plane after texture formation, the shape can be rounded. This is preferable from the viewpoint of improving carrier recovery characteristics.

  Regarding the formation of the texture structure on the incident-side surface and the back-side surface of the single crystal silicon substrate, for example, in a medium having an etching capability in a state where two single-conductive single crystal silicon substrates are combined on one side. By exposing to the above, the texture structure can be formed only on one surface of the two single-conductive single crystal silicon substrates that are not combined. This method is preferable because two substrates can be processed simultaneously and a mask is not required.

  Examples of the medium having the above-described etching ability include plasma and alkaline aqueous solution, and among them, alkaline aqueous solution is more preferable from the viewpoint of in-plane shape uniformity.

  In the method for producing a crystalline silicon solar cell according to the present invention, in addition to the step of forming the texture structure, the step of oxidizing the surface of the texture structure and the silicon oxide layer formed by the step of oxidizing treatment are removed. It is preferable to include a process.

  About the process of oxidizing the surface of the texture structure, the composition in the vicinity of the surface of the texture structure can be changed by forming an oxide film on the surface. When thermally oxidized in an oxygen atmosphere, a dense oxide film is formed that is thick at the apex and thin at the valleys. When the oxidation treatment is performed in oxygen plasma, a porous oxide film is formed as compared with the case of thermal oxidation although it depends on the discharge conditions. From the viewpoint of maintaining the smoothness of the texture structure, a thermal oxidation treatment that provides a dense oxide film is preferred.

  In addition, with respect to the step of removing the silicon oxide layer formed by the oxidation treatment step, the texture shape can be controlled by reflecting the thickness of the oxide film locally different in the texture structure. Since the thick part of the oxide film can be shaved off and the thin part can be shaved down, the apex, the hypotenuse, and the trough are rounded in the quadrangular pyramid texture structure. As a method for removing the oxide film, plasma treatment in a reducing atmosphere, immersion in an HF aqueous solution, and the like can be raised. However, removal with an HF aqueous solution is preferable from the viewpoint of surface cleanliness after use and little damage. By rounding the apex, the hypotenuse and the trough, the surface shape is relaxed, and the generation of defects when forming the amorphous silicon layer can be suppressed.

  As described above, after a specific texture structure is formed on the surface of the single crystal silicon substrate, a silicon-based thin film is formed on the surface of the single crystal silicon substrate. As a film forming method, for example, a plasma CVD method is preferable.

As the formation conditions of the silicon-based thin film, for example, a substrate temperature of 100 to 300 ° C., a pressure of 20 to 2600 Pa, and a high frequency power density of 0.004 to 0.8 W / cm ² are preferably used and adjusted as necessary. Can do. As the source gas used for forming the silicon-based thin film, for example, a silicon-containing gas such as SiH ₄ or Si ₂ H ₆ or a mixture of these gases and H ₂ is preferably used. As the dopant gas for forming the p-type or n-type layer in the photoelectric conversion unit, a known gas can be used. For example, B ₂ H ₆ or PH ₃ is preferably used. Further, since the addition amount of impurities such as P and B may be small, it is preferable to use a mixed gas diluted with SiH ₄ or H ₂ in advance. Further, by adding a gas containing a different element such as CH ₄ , CO ₂ , NH ₃ , GeH ₄ or the like, it is possible to alloy and change the energy gap.

  The crystalline silicon solar cell of the present invention has a p-type silicon thin film layer on one surface of a single crystal silicon substrate, and a substantially authentic silicon thin film layer is provided between the substrate and the p type silicon thin film layer. The other surface of the substrate has an n-type silicon thin film layer, and a substantially authentic silicon thin film layer is provided between the substrate and the n-type silicon thin film layer.

  Examples of the substantially authentic i-type silicon thin film layer include i-type microcrystalline silicon, i-type hydrogenated amorphous silicon, and i-type microcrystalline silicon oxide. I-type hydrogenated amorphous silicon is preferable. This is because surface passivation can be effectively performed while suppressing impurity diffusion into the single crystal silicon substrate during CVD deposition of the i-type hydrogenated amorphous silicon layer. In addition, by changing the amount of hydrogen in the film, it is possible to give the energy gap an effective profile for carrier recovery.

  The p-type silicon thin film layer is preferably a p-type hydrogenated amorphous silicon layer or a p-type oxidized amorphous silicon layer. From the viewpoint of impurity diffusion and series resistance, a p-type hydrogenated amorphous silicon layer is preferable. On the other hand, the p-type oxide amorphous silicon layer is preferable as a wide-gap low refractive index layer in terms of reducing optical loss.

  Examples of the n-type silicon thin film layer include n-type hydrogenated amorphous silicon, n-type microcrystalline silicon, and n-type silicon nitride. However, film formation damage and impurity diffusion to the i-type silicon thin film layer are exemplified. Of these, n-type hydrogenated amorphous silicon is particularly preferable.

  The electrode layer needs to be a transparent electrode transparent to light on the incident side, and examples of the transparent electrode include tin oxide, zinc oxide, indium oxide, and titanium oxide. Indium oxide is preferable from the viewpoints of film forming temperature, resistance / film thickness ratio, and wet heat durability. An electrode layer made of metal may be formed on the back side, but it is preferable to form a transparent electrode substantially equivalent to that on the incident side from the viewpoint of matching the stress on both sides of the thin substrate.

  A collecting electrode may be formed on the electrode layer. The collector electrode can be produced by a known technique such as ink jet, screen printing, wire bonding, spraying, etc., but screen printing is preferred from the viewpoint of productivity. For the screen printing, a process of forming a collecting electrode by printing a conductive paste composed of metal particles and a resin binder by screen printing can be preferably used.

  The cell may be annealed to solidify the conductive paste that can be used for the collector electrode. By annealing, improvement of the transmittance / resistivity ratio of the transparent electrode layer (TCO) and improvement of each interface characteristic such as reduction of contact resistance and interface state can be obtained. The annealing temperature is preferably kept within a temperature range of about 100 ° C. from the deposition temperature of the amorphous silicon thin film. If the temperature is too high, dopant diffusion from the conductive amorphous silicon thin film layer to the intrinsic amorphous silicon thin film layer, formation of impurity levels by diffusion of different elements from the TCO to the silicon region, amorphous There is a possibility that the characteristics deteriorate due to the formation of defect levels in silicon.

  EXAMPLES Hereinafter, although an Example demonstrates this invention concretely, this invention is not limited to a following example.

Example 1
FIG. 1 is a schematic cross-sectional view showing a crystalline silicon solar cell of Example 1 according to the present invention. The crystalline silicon solar cell of this example is a heterojunction solar cell, and has a texture on each side of the n-type single crystal silicon substrate 1. The arithmetic average roughness of the surface of the substrate 1 is 1400 nm on the incident side and 2100 nm on the back side. The arithmetic average roughness in this example is confirmed by AFM (atomic force microscope). An i-type amorphous silicon layer 2 / p-type amorphous silicon layer 3 / indium oxide layer 7 is formed on the incident surface of the n-type single crystal silicon substrate 1. On the other hand, an i-type amorphous silicon layer 4 / n-type amorphous silicon layer 5 / indium oxide layer 6 are formed on the back surface of the substrate 1. Collector electrodes 9 and 8 are formed on the indium oxide layers 6 and 7.

  A crystalline silicon solar cell of Example 1 shown in FIG. 1 was produced as follows.

  An n-type single crystal silicon substrate having a plane orientation of the incident surface of (100) and a thickness of 150 μm was used. The incident surface of the substrate was polished with a polishing sheet having a particle size of 4000. Next, after washing in acetone, it was immersed in a 2% by weight HF aqueous solution for 5 minutes to remove the silicon oxide layer on the surface, and rinsed with ultrapure water twice. Two substrates 1 thus prepared were prepared, and as a first etching step, the polished incident surfaces were bonded together and immersed in a 5/15 wt% KOH / isopropyl alcohol aqueous solution maintained at 75 ° C. for 15 minutes. Next, after rinsing with ultrapure water twice, the two bonded substrates 1 are separated and immersed in a 5/20 wt% KOH / isopropyl alcohol aqueous solution kept at 70 ° C. for 20 minutes as a second etching step. did. Finally, it was immersed in a 2% by weight HF aqueous solution for 5 minutes, rinsed with ultrapure water twice, and dried at room temperature. When the surface of the single crystal silicon substrate 1 was observed by AFM (Nano-R manufactured by Pacific Nanotech), a square pyramid-like texture structure with an exposed (111) plane was formed on the substrate incident surface. The average roughness was 1400 nm. Similarly, a tetragonal pyramid texture structure composed of (111) planes was formed on the back surface, but the arithmetic average roughness was 2100 nm.

After the etching, the single crystal silicon substrate 1 was introduced into a CVD apparatus, and an i-type amorphous silicon layer 2 was formed to a thickness of 3 nm on the incident surface. The film forming conditions for the i-type amorphous silicon layer 2 were a substrate temperature of 170 ° C., a pressure of 120 Pa, a SiH ₄ / H ₂ flow rate ratio of 3/10, and an input power density of 0.03 W / cm ⁻² . A p-type amorphous silicon layer 3 was formed to 4 nm on the i-type amorphous silicon layer 2. The deposition conditions of the p-type amorphous silicon layer 3 are as follows: the substrate temperature is 170 ° C., the pressure is 130 Pa, the SiH ₄ / H ₂ / B ₂ H ₆ flow rate ratio is 1/10/3, and the input power density is 0.04 W / cm. ^-2 . The B ₂ H ₆ gas used above was a gas diluted with H ₂ to a B ₂ H ₆ concentration of 5000 ppm.

Next, 5 nm of i-type amorphous silicon layers 4 were formed on the back surface side. The film forming conditions for the i-type amorphous silicon layer 4 were a substrate temperature of 170 ° C., a pressure of 120 Pa, a SiH ₄ / H ₂ flow rate ratio of 3/10, and an input power density of 0.03 W / cm ⁻² . An n-type amorphous silicon layer 5 was formed on the i-type amorphous silicon layer 4 by 7 nm. The film forming conditions of the n-type amorphous silicon layer 5 were a substrate temperature of 170 ° C., a pressure of 60 Pa, a SiH ₄ / PH ₃ flow rate ratio of 1/2, and an input power density of 0.02 W / cm ⁻² . The PH ₃ gas used above was a gas diluted with H ₂ to a PH ₃ concentration of 5000 ppm. Next, indium oxide layers 7 and 6 were formed on the p-type amorphous silicon layer 3 and the n-type amorphous silicon layer 5 by sputtering, respectively, with a thickness of 80 nm and 100 nm. As the sputtering target, In ₂ O ₃ added with 5% Sn was used. A silver paste was screen-printed on the indium oxide layers 6 and 7 on both sides to form comb-shaped electrodes.

(Example 2)
In Example 2, in the second etching step, the film was immersed in a 5/25 wt% KOH / isopropyl alcohol aqueous solution maintained at 70 ° C. for 30 minutes, and the arithmetic average roughness of the incident side surface after etching was 500 nm. This was different from Example 1.

(Example 3)
In Example 3, in the second etching step, the surface was immersed in a 5/27 wt% KOH / isopropyl alcohol aqueous solution maintained at 70 ° C. for 20 minutes, and the arithmetic average roughness of the incident-side surface after etching was 210 nm. This was different from Example 1.

Example 4
In Example 4, the incident surface of the substrate was polished with a polishing sheet having a particle size of 6000, and immersed in a 5/29 wt% KOH / isopropyl alcohol aqueous solution maintained at 70 ° C. for 30 minutes in the second etching step. In addition, it was different from Example 1 in that the arithmetic average roughness of the incident side surface after etching was 130 nm.

(Example 5)
In Example 5, in the second etching step, the sample was immersed in a 5/27 wt% KOH / isopropyl alcohol aqueous solution maintained at 70 ° C. for 20 minutes, and purely twice before being immersed in a 2 wt% HF aqueous solution. The surface was thermally oxidized by rinsing at 890 ° C. for 2 hours in an oxygen atmosphere, the arithmetic average roughness of the incident side surface after the etching was 190 nm, and the arithmetic average roughness of the back side surface was 2080 nm. This was different from Example 1.

(Comparative Example 1)
In Comparative Example 1, polishing was not performed, and in the first etching step, the substrates were not bonded to each other and immersed in a 5/15 wt% KOH / isopropyl alcohol aqueous solution maintained at 75 ° C. for 13 minutes. The arithmetic average roughness after the etching was different from that of Example 1 only in that the etching was not performed and the arithmetic average roughness after the etching was 2100 nm on both the incident surface and the back surface. The reason for changing the first etching time is to make the thickness of the substrate after etching the same.

(Comparative Example 2)
In Comparative Example 2, 145 μm substrate was used, both surfaces were polished, the first etching step was not performed, and 5/27 wt% KOH / isopropyl held at 70 ° C. without bonding the substrates. Example 1 was different from Example 1 only in that it was immersed in an aqueous alcohol solution for 20 minutes and the arithmetic average roughness after completion of etching was 210 nm on both the incident surface and the back surface. The reason why the substrates having different thicknesses are used is to make the thickness of the substrate after etching the same.

(Comparative Example 3)
In Comparative Example 3, a 145 μm substrate was used, polishing was not performed, and in the first etching process, a resist film made of silicon oxide was manufactured using a mask on the back side surface excluding the peripheral edge 2 mm of the substrate. The film was immersed in a 5/15 wt% KOH / isopropyl alcohol aqueous solution maintained at 75 ° C. for 15 minutes, the second etching was not performed, and the arithmetic average roughness after the etching was calculated from the incident surface and the back surface It was different from Example 1 only in that it was 2100 nm at the peripheral part 2 mm. The reason for changing the first etching time is to make the thickness of the substrate after etching the same.

(Comparative Example 4)
In Comparative Example 4, a point using a 140 μm substrate, a point where the incident surface and the side surface peripheral part were polished, a point where the first etching process was not performed, and a back side surface excluding the peripheral part 2 mm of the substrate in the second etching A resist film made of silicon oxide was formed using a mask and immersed in a 5/27 wt% KOH / isopropyl alcohol aqueous solution kept at 70 ° C. for 20 minutes. And the difference from Example 1 only in that it was 210 nm at the peripheral edge 2 mm of the back surface. The reason for changing the first etching time is to make the thickness of the substrate after etching the same.

(Comparative Example 5)
In Comparative Example 5, polishing was not performed, and in the first etching step, the substrates were not bonded to each other and immersed in a 5/15 wt% KOH / isopropyl alcohol aqueous solution maintained at 75 ° C. for 13 minutes. The point where the etching was not performed, the surface was thermally oxidized at 890 ° C. for 2 hours by rinsing twice before being immersed in a 2 wt% HF aqueous solution, and the surface was thermally oxidized. The arithmetic average roughness was different from Example 1 only in that the incident surface and the back surface were 2080 nm. The reason for changing the first etching time is to make the thickness of the substrate after etching the same.

  Photovoltaic conversion characteristics were evaluated after laminating a PET film 11 as a protective film with the EVA resin 10 as a filler and the protective glass plate 12 as a substrate using the solar cells of the above examples and comparative examples. The evaluation results are shown in Table 1.

  When Examples 1-4 and Comparative Examples 1-4 are compared, when the arithmetic mean roughness of the incident surface is 210 nm, the conversion efficiency (Eff) is maximized, and any of the Examples has a higher conversion efficiency than any of the comparative examples. Is shown. The open circuit voltage (Voc) and the fill factor (FF) show higher values as the arithmetic mean roughness is smaller, and the influence of the arithmetic mean roughness on the incident side is stronger. This is because the gradient of the internal potential existing in the normal direction with respect to the incident surface is particularly weak in a region constituted by a quadrangular pyramid texture structure. Since the generation of short wavelength light carriers is concentrated at the incident side interface, the shape of the incident side interface has a stronger influence than the back side.

  Comparing Example 3, Comparative Example 2, and Comparative Example 4 where the incident-side arithmetic average roughness is 210 nm, in Comparative Examples 2 and 4 where the back-side arithmetic average roughness is 210 nm or 0 nm, the short-circuit current is higher than that of Example 3. (Isc) has decreased by about 1.5 mA, and the conversion efficiency has also decreased. This is because long wavelength light is emitted outside the cell without being scattered.

  Compared with Examples 1, 2, 3, 4, 5 and Comparative Examples 1, 3, the open-circuit voltage and the short-circuit current are improved in the Examples. The open-circuit voltage reflects the difference in carrier recovery efficiency due to the incident side arithmetic mean roughness as described above, and the short-circuit current difference is composed of EVA resin with a refractive index of 1.5 and indium oxide with a refractive index of 1.9. This reflects the difference in optical characteristics due to the difference in the shape of the interface. In the refractive index configuration composed of EVA resin / indium oxide / silicon, the reflectance reduction effect due to interference cannot be obtained sufficiently. Short-wavelength light behaves geometrically at the interface with a large arithmetic average roughness, so that reflection occurs depending on the wavelength and the short-circuit current decreases. On the other hand, in the interface shape having a small incident side arithmetic average roughness used in the embodiment, since the short wavelength light cannot recognize the interface, reflection can be reduced over a wide wavelength range.

  In particular, when Examples 3 to 5 are compared with Comparative Examples 1 and 5, the improvement width of the open circuit voltage of Example 5 with respect to Examples 3 and 4 is larger than the improvement width of Comparative Example 5 with respect to Comparative Example 1. Example 5 shows that the open-circuit voltage is improved over Example 4 with a smaller incident-side arithmetic average roughness, and the open-circuit voltage is improved over Comparative Example 1 where Comparative Example 5 has substantially the same incident-side arithmetic average roughness. In view of this, the open-circuit voltage is improved by an effect other than the reduction of the incident side arithmetic average roughness. Moreover, it can be said that the effect of improving the open circuit voltage is more effective as the incident side arithmetic average roughness is smaller as in the embodiment, because of the difference between the improvement width in the embodiment and the improvement width in the comparative example. Example 5 is the same as Example 3, and Comparative Example 5 is the same as Comparative Example 1 except that a thermal oxidation step is added after texture formation, and the formed thermal oxide film is removed in the final immersion step in HF aqueous solution. . Through this thermal oxide film formation and removal process, the thickness of the thermal oxide film formed on the surface is thick at the top of the texture and thinned at the valleys, resulting in a square pyramid texture after removal of the thermal oxide film. The sides, vertices, and valleys of the structure are rounded. As a result, the length of the rounded side and the number of vertices are inversely proportional to the initial arithmetic average roughness before the oxide film formation / removal step. When the amorphous silicon film is formed on the sides of the quadrangular pyramid-shaped texture structure, particularly on the sides of the valleys that form the bottom of the quadrangular pyramid, defects are likely to occur. As described above, the length of the side constituting the valley is longer as the surface has a smaller arithmetic average roughness, that is, a smaller average size of the square pyramid texture structure. It is thought that there are many defect occurrence points. Through the oxide film formation / removal step, the number of defect occurrence points can be reduced, and the degree thereof is relatively large in an embodiment having a small texture structure.

  As a result of evaluating photoelectric conversion characteristics in a state where the solar cell is sealed with an EVA resin having a refractive index of about 1.5 as described above, the open voltage and short-circuit current of the solar cell are improved in a balanced manner according to the present invention. It can be seen that the efficiency is improved.

1. 1. n-type single crystal silicon substrate 2. i-type amorphous silicon layer 3. p-type amorphous silicon layer 4. i-type amorphous silicon layer n-type amorphous silicon layer 6. 6. Indium oxide layer Indium oxide layer 8. Collector electrode 9. Collector electrode 10. EVA resin 11. PET film 12. Protective glass

Claims (6)

A single conductivity type single crystal silicon substrate, a p-type silicon thin film layer on one surface of the substrate, and a substantially authentic silicon thin film layer between the substrate and the p-type silicon thin film layer; A crystalline silicon solar cell having an n-type silicon-based thin film layer on the other surface of the substrate, and a substantially authentic silicon-based thin film layer between the substrate and the n-type silicon thin film layer;
The substrate has a thickness of 150 μm or less, has a texture structure composed of quadrangular pyramids on the incident side surface and the back side surface of the substrate, and has an arithmetic average roughness of 1500 nm or less on the incident side surface of the substrate, An arithmetic average roughness of the side surface is 2000 nm or more.   2. The crystalline silicon solar cell according to claim 1, wherein the arithmetic average roughness on the incident-side surface of the substrate is 500 nm or less, and the arithmetic average roughness on the back-side surface is 2000 nm or more.   2. The crystalline silicon solar cell according to claim 1, wherein the arithmetic average roughness of the incident side surface of the substrate is 300 nm or less, and the arithmetic average roughness of the back surface is 2000 nm or more.   It is a manufacturing method of the crystalline silicon solar cell in any one of Claims 1 thru | or 3, Comprising: It forms by the process of forming the said texture structure, the process of oxidizing the surface of the said texture structure, and the process of performing the said oxidation process A method for producing a crystalline silicon solar cell, comprising a step of removing the formed silicon oxide layer.   The method for manufacturing a crystalline silicon solar cell according to claim 4, wherein the texture structure is formed by etching.   By exposing two single-conductive single crystal silicon substrates in a medium having an etching capability in a state where the single conductive single-crystal silicon substrates are combined on each one side, the two single-conductive single crystal silicon substrates on the non-matched one side The method for manufacturing a crystalline silicon solar cell according to claim 4, wherein only the texture structure is formed.

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