WO2015045809A1 - Solar cell - Google Patents

Solar cell Download PDF

Info

Publication number
WO2015045809A1
WO2015045809A1 PCT/JP2014/073541 JP2014073541W WO2015045809A1 WO 2015045809 A1 WO2015045809 A1 WO 2015045809A1 JP 2014073541 W JP2014073541 W JP 2014073541W WO 2015045809 A1 WO2015045809 A1 WO 2015045809A1
Authority
WO
WIPO (PCT)
Prior art keywords
amorphous silicon
back surface
silicon film
light receiving
silicon substrate
Prior art date
Application number
PCT/JP2014/073541
Other languages
French (fr)
Japanese (ja)
Inventor
崇暁 中島
Original Assignee
パナソニックＩｐマネジメント株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニックＩｐマネジメント株式会社 filed Critical パナソニックＩｐマネジメント株式会社
Priority to JP2015539070A priority Critical patent/JPWO2015045809A1/en
Publication of WO2015045809A1 publication Critical patent/WO2015045809A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a solar cell.
  • Patent Document 1 in a crystalline silicon solar cell using a single crystal silicon substrate, a texture structure having an arithmetic average roughness of 1500 nm or less is formed on the incident surface side, and an arithmetic average roughness is 2000 nm or more on the back surface side. It has been proposed to form a texture structure. Thus, it is described that long wavelength light of 800 nm or more reaching the back surface can be scattered, light in a wide wavelength range can be efficiently confined, and photoelectric conversion efficiency can be improved.
  • An object of the present invention is to provide a solar cell that can improve the short-circuit current (Isc) by reflecting light that is transmitted through the crystalline silicon substrate on the back surface side of the solar cell.
  • the solar cell of the present invention includes a one-conductivity-type crystalline silicon substrate having a light-receiving surface and a back surface, a first silicon layer of another conductivity type provided on one of the light-receiving surface and the back surface, and a light-receiving surface or A second silicon layer of one conductivity type provided on the other surface of the back surface, the crystalline silicon substrate has a texture structure with an arithmetic average roughness Ra of 1000 nm or more on the light receiving surface, and an arithmetic surface on the back surface It has an uneven structure with an average roughness Ra of less than 1000 nm.
  • the short-circuit current (Isc) can be improved by reflecting the light that is transmitted through the crystalline silicon substrate on the back surface side of the solar cell.
  • FIG. 1 is a schematic cross-sectional view showing the solar cell of the first embodiment.
  • FIG. 2 is a schematic cross-sectional view showing the solar cell of the second embodiment.
  • FIG. 1 is a schematic cross-sectional view showing the solar cell of the first embodiment.
  • the solar cell 1 includes a crystalline silicon substrate 10.
  • a texture structure is formed on the light receiving surface 11 of the crystalline silicon substrate 10.
  • the crystalline silicon substrate 10 may be made of single crystal silicon or may be made of polycrystalline silicon.
  • the arithmetic average roughness Ra of the light receiving surface 11 is 1000 nm or more, preferably 1000 nm or more and 6000 nm or less, and more preferably 1000 nm or more and 4000 nm or less.
  • the arithmetic average roughness Ra of the light receiving surface 11 is smaller than the above range, the size of the texture structure becomes the same as the wavelength band mainly absorbed by the solar battery cell, and the reflection suppressing effect by the texture structure is reduced.
  • the etching amount necessary for forming the texture structure increases, so that the thickness of the crystalline silicon substrate 10 after forming the texture structure becomes thin, and photoelectric conversion is performed. In this case, light cannot be sufficiently contributed to, and the short-circuit current is reduced.
  • the arithmetic average roughness Ra of the back surface 12 is less than 1000 nm, preferably 300 nm or more and less than 1000 nm. If the arithmetic average roughness Ra of the back surface 12 is larger than the above range, the amount of etching necessary for formation increases in the same manner as the light receiving surface 11, so that the thickness of the crystalline silicon substrate 10 after formation of the texture structure becomes thin, and photoelectric conversion is performed. In this case, light cannot be sufficiently contributed to, and the short-circuit current is reduced. On the other hand, if the arithmetic average roughness Ra of the back surface 12 is too small than the above range, a surface shape close to a flat surface is obtained, and light scattering hardly occurs.
  • the crystalline silicon substrate 10 is an n-type single crystal silicon substrate.
  • a p-type amorphous silicon layer 20 as a first silicon layer is provided on the light receiving surface 11.
  • the amorphous silicon layer 20 is formed on the first i-type (intrinsic) amorphous silicon film 21 and the first i-type amorphous silicon film 21 formed on the light receiving surface 11.
  • a p-type amorphous silicon film 22 is formed on the first i-type (intrinsic) amorphous silicon film 21 and the first i-type amorphous silicon film 21 formed on the light receiving surface 11.
  • an n-type amorphous silicon layer 30 as a second silicon layer is provided on the back surface 12.
  • the amorphous silicon layer 30 is formed on the second i-type (intrinsic) amorphous silicon film 31 and the second i-type amorphous silicon film 31 formed on the back surface 12.
  • the photoelectric conversion unit 40 includes a crystalline silicon substrate 10, an amorphous silicon layer 20, and an amorphous silicon layer 30.
  • amorphous silicon in this embodiment includes microcrystalline silicon.
  • Microcrystalline silicon refers to silicon crystal precipitated in amorphous silicon.
  • a light-receiving surface side transparent electrode 50 is provided on the amorphous silicon layer 20 .
  • a back surface side transparent electrode 60 is provided on the amorphous silicon layer 30 .
  • a metal electrode 51 is provided on the transparent electrode 50.
  • a metal electrode 61 is also provided on the transparent electrode 60.
  • the first i-type amorphous silicon film 21 is, for example, an amorphous intrinsic silicon semiconductor film containing hydrogen.
  • the intrinsic semiconductor film is a case where the concentration of the p-type or n-type dopant contained is 5 ⁇ 10 18 / cm 3 or less, or when the p-type and n-type dopants are included at the same time.
  • the difference of the p-type or n-type dopant concentration of 5 ⁇ 10 18 / cm 3 means a semiconductor film or less.
  • the first i-type amorphous silicon film 21 is preferably thin so as to suppress light absorption as much as possible, and thick enough to sufficiently passivate the surface of the crystalline silicon substrate 10.
  • the film thickness of the first i-type amorphous silicon film 21 is 1 nm to 25 nm, preferably 5 nm to 10 nm.
  • the first i-type amorphous silicon film 21 can be formed by plasma enhanced chemical vapor deposition (PECVD), Cat-CVD (Catalytic Chemical Vapor Deposition), sputtering, or the like.
  • PECVD plasma enhanced chemical vapor deposition
  • Cat-CVD Catalytic Chemical Vapor Deposition
  • sputtering or the like.
  • PECVD any method such as RF plasma CVD, high-frequency VHF plasma CVD, or microwave plasma CVD may be used.
  • RF plasma CVD method a silicon-containing gas such as silane (SiH 4 ) is supplied after being diluted with hydrogen, and RF high frequency power is applied to parallel plate electrodes and the like to generate plasma and supply it to the film-forming surface of the heated crystalline silicon substrate 10.
  • the substrate temperature during film formation is preferably 150 ° C. or more and 250 ° C. or less
  • the RF power density is preferably 1 mW / cm 2 or more and 10 mW / cm 2 or less.
  • the p-type amorphous silicon film 22 is an amorphous semiconductor film containing a p-type conductive dopant.
  • the p-type amorphous silicon film 22 is formed from amorphous silicon containing hydrogen.
  • the p-type amorphous silicon film 22 has a higher concentration of p-type dopant in the film than the first i-type amorphous silicon film 21.
  • the p-type amorphous silicon film 22 preferably has a p-type dopant concentration of 1 ⁇ 10 20 / cm 3 or more.
  • the thickness of the p-type amorphous silicon film 22 is preferably thin so that light absorption can be suppressed as much as possible, while carriers generated in the crystalline silicon substrate 10 are effectively separated at the pn junction. In addition, it is preferable to increase the thickness so that the generated carriers are efficiently collected by the transparent electrode 50.
  • the p-type amorphous silicon film 22 can also be formed by PECVD, Cat-CVD, sputtering, or the like.
  • PECVD an RF plasma CVD method can be applied.
  • a silicon-containing gas such as silane (SiH 4 ) and a p-type dopant-containing gas such as diborane (B 2 H 6 ) are diluted with hydrogen and supplied, and RF high frequency power is applied to parallel plate electrodes and the like to generate plasma. Then, it can be formed by supplying it onto the i-type amorphous silicon film 21 of the heated crystalline silicon substrate 10.
  • the substrate temperature during film formation is preferably 150 ° C. to 250 ° C. and the RF power density is preferably 1 mW / cm 2 to 10 mW / cm 2 .
  • the second i-type amorphous silicon film 31 is formed on the back surface 12 of the crystalline silicon substrate 10. That is, after the first i-type amorphous silicon film 21 and the p-type amorphous silicon film 22 are formed, the front and back of the crystalline silicon substrate 10 are reversed and formed on the back surface 12 of the crystalline silicon substrate 10.
  • the second i-type amorphous silicon film 31 is an amorphous intrinsic silicon semiconductor film containing hydrogen.
  • the film thickness of the i-type amorphous silicon film 31 is 1 nm or more and 25 nm or less, preferably 5 nm or more and 10 nm or less, like the first i-type amorphous silicon film 21.
  • the second i-type amorphous silicon film 31 can be formed by PECVD, Cat-CVD, sputtering, or the like.
  • PECVD an RF plasma CVD method can be applied.
  • a silicon-containing gas such as silane (SiH 4 ) is supplied after being diluted with hydrogen, and RF high frequency power is applied to parallel plate electrodes and the like to generate plasma and supply it to the film-forming surface of the heated crystalline silicon substrate 10.
  • the substrate temperature during film formation is preferably 150 ° C. or higher and 250 ° C. or lower, and the RF power density is preferably 1 mW / cm 2 or higher and 10 mW / cm 2 or lower.
  • the n-type amorphous silicon film 32 is made of an amorphous semiconductor film containing an n-type conductive dopant.
  • the n-type amorphous silicon film 32 is formed from amorphous silicon containing hydrogen.
  • the n-type amorphous silicon film 32 has a higher n-type dopant concentration than the second i-type amorphous silicon film 31.
  • the n-type amorphous silicon film 32 preferably has an n-type dopant concentration of 1 ⁇ 10 20 / cm 3 or more.
  • the thickness of the n-type amorphous silicon film 32 is preferably thin so that light absorption can be suppressed as much as possible.
  • carriers generated in the crystalline silicon substrate 10 have a BSF (Back Surface Field) structure. It is preferable to increase the thickness of the generated carriers so that the generated carriers can be efficiently collected by the transparent electrode 60 while being effectively separated.
  • BSF Back Surface Field
  • the n-type amorphous silicon film 32 can also be formed by PECVD, Cat-CVD, sputtering, or the like.
  • PECVD an RF plasma CVD method can be applied.
  • a silicon-containing gas such as silane (SiH 4 ) and an n-type dopant-containing gas such as phosphine (PH 3 ) are diluted with hydrogen and supplied, and RF high frequency power is applied to parallel plate electrodes and the like to form plasma. It can be formed by supplying it onto the second i-type amorphous silicon film 31 of the heated crystalline silicon substrate 10.
  • the substrate temperature during film formation is preferably 150 ° C. to 250 ° C. and the RF power density is preferably 1 mW / cm 2 to 10 mW / cm 2 .
  • the crystalline silicon substrate 10 is inverted, and the first i-type amorphous silicon film 21 on the back surface 12 side is inverted.
  • the i-type amorphous silicon film 31 and the n-type amorphous silicon film 32 are formed, the order of forming them may be reversed.
  • the transparent electrodes 50 and 60 can be formed of, for example, a transparent conductive oxide such as indium tin oxide (ITO) or zinc oxide (ZnO).
  • the metal electrodes 51 and 61 can be formed of, for example, a metal such as Ag, Cu, or Sn, or an alloy or resin containing at least one of these metals.
  • a texture structure is formed on the light receiving surface 11 of the crystalline silicon substrate 10.
  • the irregularities of the texture structure formed on the light receiving surface 11 are inherited by the first i-type amorphous silicon film 21 and the p-type amorphous silicon film 22.
  • the unevenness of the surface structure formed on the back surface 12 is inherited by the second i-type amorphous silicon film 31 and the n-type amorphous silicon film 32.
  • the (100) plane of the crystalline silicon substrate 10 is anisotropic using an alkaline aqueous solution such as sodium hydroxide (NaOH) aqueous solution, potassium hydroxide (KOH) aqueous solution, or tetramethylammonium hydroxide (TMAH). It can be formed by etching.
  • an alkaline aqueous solution such as sodium hydroxide (NaOH) aqueous solution, potassium hydroxide (KOH) aqueous solution, or tetramethylammonium hydroxide (TMAH). It can be formed by etching.
  • an alkaline aqueous solution such as sodium hydroxide (NaOH) aqueous solution, potassium hydroxide (KOH) aqueous solution, or tetramethylammonium hydroxide (TMAH). It can be formed by etching.
  • the texture structure may be formed by dry etching using a mixed gas of CF 4 ) and oxygen (O 2 ).
  • the arithmetic average roughness Ra of the light receiving surface 11 is 1000 nm or more, and the arithmetic average roughness Ra of the back surface 12 is less than 1000 nm. That is, a large uneven texture structure is formed on the light receiving surface 11, and a small uneven structure is formed on the back surface 12. Therefore, different functions can be given to the light receiving surface 11 and the back surface 12.
  • the light reflectance can be increased by forming a small uneven structure. Therefore, the light that attempts to pass through the crystalline silicon substrate 10 can be efficiently reflected and re-entered into the crystalline silicon substrate 10. For this reason, a short circuit current (Isc) can be improved.
  • the following method can be cited.
  • the light receiving surface 11 and the back surface 12 are subjected to different etching processes.
  • etchants having different types or concentrations are used for the light receiving surface 11 and the back surface 12.
  • the etching method is changed between the light receiving surface 11 and the back surface 12, such as dry etching and wet etching.
  • the light-receiving surface 11 and the back surface 12 are wet-etched in a state where an etching inhibitor such as an organic substance or silicon oxide is attached to the back surface 12.
  • an etching inhibitor such as an organic substance or silicon oxide
  • the crystalline silicon substrate has dirt such as organic matter attached to its surface.
  • a process is performed to destroy the texture structure on both sides.
  • a specific treatment for example, when etching with fluoric nitric acid is performed, the light-receiving surface side of the large unevenness is round-etched only on the texture valley, but the back surface side of the small unevenness is etched until the crystal surface is not retained.
  • FIG. 2 is a schematic cross-sectional view showing the solar cell 2 of the second embodiment.
  • a metal electrode 70 is formed on the back side transparent electrode 60.
  • the metal electrode 70 can be formed by a thin film forming method such as sputtering, vapor deposition, chemical vapor deposition, printing or plating.
  • the metal electrode 70 is formed on the back surface 12 side as in this embodiment, the light that is about to pass through the crystalline silicon substrate 10 is easily absorbed by the metal electrode 70. However, in this embodiment, a small uneven structure is formed on the back surface 12. For this reason, the reflectance of light is increased, and the light that is about to pass through the crystalline silicon substrate 10 is reflected by the back surface 12, so that the photoelectric conversion efficiency in the crystalline silicon substrate 10 can be increased.
  • the texture structure is formed on the back surface 12, but the present invention is not limited to this.
  • the arithmetic average roughness Ra of the back surface 12 may be less than 1000 nm without forming a texture structure on the back surface 12.
  • the i-type amorphous silicon thin films 21 and 31 are provided in the amorphous silicon layers 20 and 30, respectively, but the present invention is not necessarily limited to this.
  • the amorphous silicon layer 20 may be formed only from the p-type amorphous silicon film 22, and the amorphous silicon layer 30 may be formed only from the n-type amorphous silicon film 32.
  • first silicon layer and the second silicon layer in the present invention may be formed by diffusing a dopant on the surface of the crystalline silicon substrate 10.
  • an n-type single crystal silicon substrate is used as the crystalline silicon substrate 10, but a p-type single crystal silicon substrate may be used.
  • the amorphous silicon layer 20 may be n-type
  • the amorphous silicon layer 30 may be p-type
  • the polarities on the light receiving surface side and the back surface side may be replaced with those in the above embodiment.

Abstract

Provided is a solar cell, the short-circuit current (Isc) of which can be improved by reflecting light that will otherwise pass through a crystal silicon substrate. The solar cell comprises: a crystal silicon substrate (10) of one conductivity type having a light receiving surface (11) and a back surface (12); a first silicon layer (20) of the other conductivity type provided on one of the light receiving surface (11) and the back surface (12); and a second silicon layer (30) of the one conductivity type provided on the other one of the light receiving surface (11) and the back surface (12). The light receiving surface (11) of the crystal silicon substrate (10) has a texture structure having an arithmetic average roughness (Ra) of 1000 nm or more, and the back surface (12) thereof has an uneven structure having an arithmetic average roughness (Ra) of less than 1000 nm.

Description

太陽電池Solar cell
　本発明は、太陽電池に関する。 The present invention relates to a solar cell.
　特許文献１では、単結晶シリコン基板を用いた結晶シリコン系太陽電池において、入射面側に、算術平均粗さが１５００ｎｍ以下のテクスチャ構造を形成し、裏面側に、算術平均粗さが２０００ｎｍ以上のテクスチャ構造を形成することが提案されている。これにより、裏面に到達した８００ｎｍ以上の長波長光を散乱させ、広い波長範囲の光を効率的に閉じ込め、光電変換効率を向上させることができる旨記載されている。 In Patent Document 1, in a crystalline silicon solar cell using a single crystal silicon substrate, a texture structure having an arithmetic average roughness of 1500 nm or less is formed on the incident surface side, and an arithmetic average roughness is 2000 nm or more on the back surface side. It has been proposed to form a texture structure. Thus, it is described that long wavelength light of 800 nm or more reaching the back surface can be scattered, light in a wide wavelength range can be efficiently confined, and photoelectric conversion efficiency can be improved.
特開２０１１－６１０３０号公報JP 2011-61030 A
　しかしながら、従来、裏面側において、乱反射光を積極的に利用した結晶シリコン基板を利用することは検討されていない。 However, hitherto, it has not been studied to use a crystalline silicon substrate that actively uses diffusely reflected light on the back side.
　本発明の目的は、太陽電池の裏面側において、結晶シリコン基板を透過しようとする光を反射させることにより、短絡電流（Ｉｓｃ）を向上させることができる太陽電池を提供することにある。 An object of the present invention is to provide a solar cell that can improve the short-circuit current (Isc) by reflecting light that is transmitted through the crystalline silicon substrate on the back surface side of the solar cell.
　本発明の太陽電池は、受光面及び裏面を有する一導電型の結晶シリコン基板と、受光面または裏面のうちの一方の面上に設けられる他導電型の第１のシリコン層と、受光面または裏面のうちの他方の面上に設けられる一導電型の第２のシリコン層とを備え、結晶シリコン基板は、受光面に算術平均粗さＲａが１０００ｎｍ以上のテクスチャ構造を有し、裏面に算術平均粗さＲａが１０００ｎｍ未満の凹凸構造を有する。 The solar cell of the present invention includes a one-conductivity-type crystalline silicon substrate having a light-receiving surface and a back surface, a first silicon layer of another conductivity type provided on one of the light-receiving surface and the back surface, and a light-receiving surface or A second silicon layer of one conductivity type provided on the other surface of the back surface, the crystalline silicon substrate has a texture structure with an arithmetic average roughness Ra of 1000 nm or more on the light receiving surface, and an arithmetic surface on the back surface It has an uneven structure with an average roughness Ra of less than 1000 nm.
　本発明によれば、太陽電池の裏面側において、結晶シリコン基板を透過しようとする光を反射させることにより、短絡電流（Ｉｓｃ）を向上させることができる。 According to the present invention, the short-circuit current (Isc) can be improved by reflecting the light that is transmitted through the crystalline silicon substrate on the back surface side of the solar cell.
図１は、第１の実施形態の太陽電池を示す模式的断面図である。FIG. 1 is a schematic cross-sectional view showing the solar cell of the first embodiment. 図２は、第２の実施形態の太陽電池を示す模式的断面図である。FIG. 2 is a schematic cross-sectional view showing the solar cell of the second embodiment.
　以下、好ましい実施形態について説明する。但し、以下の実施形態は単なる例示であり、本発明は以下の実施形態に限定されるものではない。また、各図面において、実質的に同一の機能を有する部材は同一の符号で参照する場合がある。 Hereinafter, preferred embodiments will be described. However, the following embodiments are merely examples, and the present invention is not limited to the following embodiments. Moreover, in each drawing, the member which has the substantially the same function may be referred with the same code | symbol.
　（第１の実施形態）
　図１は、第１の実施形態の太陽電池を示す模式的断面図である。図１に示すように、太陽電池１は、結晶シリコン基板１０を備えている。本実施形態において、結晶シリコン基板１０の受光面１１には、テクスチャ構造が形成されている。結晶シリコン基板１０は、単結晶シリコンから構成されていてもよいし、多結晶シリコンから構成されていてもよい。 (First embodiment)
FIG. 1 is a schematic cross-sectional view showing the solar cell of the first embodiment. As shown in FIG. 1, the solar cell 1 includes a crystalline silicon substrate 10. In the present embodiment, a texture structure is formed on the light receiving surface 11 of the crystalline silicon substrate 10. The crystalline silicon substrate 10 may be made of single crystal silicon or may be made of polycrystalline silicon.
　本実施形態において、受光面１１の算術平均粗さＲａは、１０００ｎｍ以上であり、好ましくは１０００ｎｍ以上６０００ｎｍ以下であり、さらに好ましくは１０００ｎｍ以上４０００ｎｍ以下である。受光面１１の算術平均粗さＲａが、上記範囲より小さいと、テクスチャ構造のサイズが太陽電池セルが主に吸収する波長帯と同程度になり、テクスチャ構造による反射抑制効果が低減する。また、受光面１１の算術平均粗さＲａが、上記範囲より大きすぎると、テクスチャ構造形成に必要なエッチング量が多くなることからテクスチャ構造形成後の結晶シリコン基板１０の厚みが薄くなり、光電変換に光を十分に寄与させることができず、短絡電流が減少する。 In this embodiment, the arithmetic average roughness Ra of the light receiving surface 11 is 1000 nm or more, preferably 1000 nm or more and 6000 nm or less, and more preferably 1000 nm or more and 4000 nm or less. When the arithmetic average roughness Ra of the light receiving surface 11 is smaller than the above range, the size of the texture structure becomes the same as the wavelength band mainly absorbed by the solar battery cell, and the reflection suppressing effect by the texture structure is reduced. In addition, if the arithmetic average roughness Ra of the light receiving surface 11 is too larger than the above range, the etching amount necessary for forming the texture structure increases, so that the thickness of the crystalline silicon substrate 10 after forming the texture structure becomes thin, and photoelectric conversion is performed. In this case, light cannot be sufficiently contributed to, and the short-circuit current is reduced.
　本実施形態において、裏面１２の算術平均粗さＲａは、１０００ｎｍ未満であり、好ましくは３００ｎｍ以上１０００ｎｍ未満である。裏面１２の算術平均粗さＲａが、上記範囲より大きいと、受光面１１と同様に形成に必要なエッチング量が多くなることからテクスチャ構造形成後の結晶シリコン基板１０の厚みが薄くなり、光電変換に光を十分に寄与させることができず、短絡電流が減少する。また、裏面１２の算術平均粗さＲａが、上記範囲より小さすぎると、平面に近い表面形状となり、光の散乱が生じにくくなる。 In the present embodiment, the arithmetic average roughness Ra of the back surface 12 is less than 1000 nm, preferably 300 nm or more and less than 1000 nm. If the arithmetic average roughness Ra of the back surface 12 is larger than the above range, the amount of etching necessary for formation increases in the same manner as the light receiving surface 11, so that the thickness of the crystalline silicon substrate 10 after formation of the texture structure becomes thin, and photoelectric conversion is performed. In this case, light cannot be sufficiently contributed to, and the short-circuit current is reduced. On the other hand, if the arithmetic average roughness Ra of the back surface 12 is too small than the above range, a surface shape close to a flat surface is obtained, and light scattering hardly occurs.
　本実施形態において、結晶シリコン基板１０は、ｎ型の単結晶シリコン基板である。受光面１１の上には、第１のシリコン層であるｐ型の非晶質シリコン層２０が設けられている。非晶質シリコン層２０は、受光面１１上に形成される、第１のｉ型（真性）非晶質シリコン膜２１と、第１のｉ型非晶質シリコン膜２１の上に形成される、ｐ型非晶質シリコン膜２２から構成されている。 In the present embodiment, the crystalline silicon substrate 10 is an n-type single crystal silicon substrate. A p-type amorphous silicon layer 20 as a first silicon layer is provided on the light receiving surface 11. The amorphous silicon layer 20 is formed on the first i-type (intrinsic) amorphous silicon film 21 and the first i-type amorphous silicon film 21 formed on the light receiving surface 11. , A p-type amorphous silicon film 22.
　裏面１２の上には、第２のシリコン層であるｎ型の非晶質シリコン層３０が設けられている。非晶質シリコン層３０は、裏面１２の上に形成される、第２のｉ型（真性）非晶質シリコン膜３１と、第２のｉ型非晶質シリコン膜３１の上に形成される、ｎ型非晶質シリコン膜３２から構成されている。 On the back surface 12, an n-type amorphous silicon layer 30 as a second silicon layer is provided. The amorphous silicon layer 30 is formed on the second i-type (intrinsic) amorphous silicon film 31 and the second i-type amorphous silicon film 31 formed on the back surface 12. , An n-type amorphous silicon film 32.
　光電変換部４０は、結晶シリコン基板１０、非晶質シリコン層２０及び非晶質シリコン層３０から構成されている。なお、本実施形態における「非晶質シリコン」には、微結晶シリコンを含むものとする。微結晶シリコンとは、非晶質シリコン中にシリコン結晶が析出しているものをいう。 The photoelectric conversion unit 40 includes a crystalline silicon substrate 10, an amorphous silicon layer 20, and an amorphous silicon layer 30. Note that “amorphous silicon” in this embodiment includes microcrystalline silicon. Microcrystalline silicon refers to silicon crystal precipitated in amorphous silicon.
　非晶質シリコン層２０の上には、受光面側透明電極５０が設けられている。非晶質シリコン層３０の上には、裏面側透明電極６０が設けられている。透明電極５０の上には、金属電極５１が設けられている。透明電極６０の上にも、金属電極６１が設けられている。 On the amorphous silicon layer 20, a light-receiving surface side transparent electrode 50 is provided. On the amorphous silicon layer 30, a back surface side transparent electrode 60 is provided. A metal electrode 51 is provided on the transparent electrode 50. A metal electrode 61 is also provided on the transparent electrode 60.
　第１のｉ型非晶質シリコン膜２１は、例えば、水素を含むアモルファスの真性シリコン半導体膜である。ここで、真性の半導体膜とは、含有されるｐ型又はｎ型のドーパントの濃度が５×１０１８／ｃｍ３以下である、または、ｐ型及びｎ型のドーパントが同時に含まれる場合にはｐ型又はｎ型のドーパント濃度の差が５×１０１８／ｃｍ３以下である半導体膜をいう。第１のｉ型非晶質シリコン膜２１は、光の吸収をできるだけ抑えられるように薄くし、一方で結晶シリコン基板１０の表面が十分にパッシベーションされる程度に厚くすることが好適である。第１のｉ型非晶質シリコン膜２１の膜厚は、１ｎｍ以上２５ｎｍ以下であり、好ましくは５ｎｍ以上１０ｎｍ以下である。 The first i-type amorphous silicon film 21 is, for example, an amorphous intrinsic silicon semiconductor film containing hydrogen. Here, the intrinsic semiconductor film is a case where the concentration of the p-type or n-type dopant contained is 5 × 10 18 / cm 3 or less, or when the p-type and n-type dopants are included at the same time. the difference of the p-type or n-type dopant concentration of 5 × 10 18 / cm 3 means a semiconductor film or less. The first i-type amorphous silicon film 21 is preferably thin so as to suppress light absorption as much as possible, and thick enough to sufficiently passivate the surface of the crystalline silicon substrate 10. The film thickness of the first i-type amorphous silicon film 21 is 1 nm to 25 nm, preferably 5 nm to 10 nm.
　第１のｉ型非晶質シリコン膜２１は、プラズマ化学気相成長法（ＰＥＣＶＤ）、Ｃａｔ－ＣＶＤ（Ｃａｔａｌｙｔｉｃ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）、スパッタリング法等により形成することができる。ＰＥＣＶＤは、ＲＦプラズマＣＶＤ法、周波数の高いＶＨＦプラズマＣＶＤ法、さらにはマイクロ波プラズマＣＶＤ法などいずれの手法を用いてもよい。本実施形態では、ＲＦプラズマＣＶＤ法を用いる場合について説明する。例えば、シラン（ＳｉＨ４）等のケイ素含有ガスを水素で希釈して供給し、平行平板電極等にＲＦ高周波電力を印加してプラズマ化して、加熱された結晶シリコン基板１０の成膜面に供給することによって形成することができる。成膜時の基板温度は１５０℃以上２５０℃以下、ＲＦ電力密度は１ｍＷ／ｃｍ２以上１０ｍＷ／ｃｍ２以下であることが好ましい。 The first i-type amorphous silicon film 21 can be formed by plasma enhanced chemical vapor deposition (PECVD), Cat-CVD (Catalytic Chemical Vapor Deposition), sputtering, or the like. For PECVD, any method such as RF plasma CVD, high-frequency VHF plasma CVD, or microwave plasma CVD may be used. In this embodiment, a case where an RF plasma CVD method is used will be described. For example, a silicon-containing gas such as silane (SiH 4 ) is supplied after being diluted with hydrogen, and RF high frequency power is applied to parallel plate electrodes and the like to generate plasma and supply it to the film-forming surface of the heated crystalline silicon substrate 10. Can be formed. The substrate temperature during film formation is preferably 150 ° C. or more and 250 ° C. or less, and the RF power density is preferably 1 mW / cm 2 or more and 10 mW / cm 2 or less.
　ｐ型非晶質シリコン膜２２は、ｐ型の導電型のドーパントを含む非晶質半導体膜である。例えば、ｐ型非晶質シリコン膜２２は、水素を含有するアモルファスシリコンから形成される。ｐ型非晶質シリコン膜２２は、第１のｉ型非晶質シリコン膜２１よりも膜中のｐ型のドーパントの濃度が高くされる。例えば、ｐ型非晶質シリコン膜２２は、ｐ型のドーパントの濃度を１×１０２０／ｃｍ３以上とすることが好適である。ｐ型非晶質シリコン膜２２の膜厚は、光の吸収をできるだけ抑えられるように薄くすることが好適である一方で、結晶シリコン基板１０内で発生したキャリアがｐｎ接合部で効果的に分離され、かつ、発生したキャリアが透明電極５０で効率よく収集される程度に厚くすることが好適である。 The p-type amorphous silicon film 22 is an amorphous semiconductor film containing a p-type conductive dopant. For example, the p-type amorphous silicon film 22 is formed from amorphous silicon containing hydrogen. The p-type amorphous silicon film 22 has a higher concentration of p-type dopant in the film than the first i-type amorphous silicon film 21. For example, the p-type amorphous silicon film 22 preferably has a p-type dopant concentration of 1 × 10 20 / cm 3 or more. The thickness of the p-type amorphous silicon film 22 is preferably thin so that light absorption can be suppressed as much as possible, while carriers generated in the crystalline silicon substrate 10 are effectively separated at the pn junction. In addition, it is preferable to increase the thickness so that the generated carriers are efficiently collected by the transparent electrode 50.
　ｐ型非晶質シリコン膜２２も、ＰＥＣＶＤ、Ｃａｔ－ＣＶＤ、スパッタリング法等により形成することができる。ＰＥＣＶＤは、ＲＦプラズマＣＶＤ法を適用することができる。例えば、シラン（ＳｉＨ４）等のケイ素含有ガス及びジボラン（Ｂ２Ｈ６）等のｐ型ドーパント含有ガスを水素で希釈して供給し、平行平板電極等にＲＦ高周波電力を印加してプラズマ化して、加熱された結晶シリコン基板１０のｉ型非晶質シリコン膜２１上に供給することによって形成することができる。なお、成膜時の基板温度は１５０℃以上２５０℃以下、ＲＦ電力密度は１ｍＷ／ｃｍ２以上１０ｍＷ／ｃｍ２以下とすることが好ましい。 The p-type amorphous silicon film 22 can also be formed by PECVD, Cat-CVD, sputtering, or the like. For PECVD, an RF plasma CVD method can be applied. For example, a silicon-containing gas such as silane (SiH 4 ) and a p-type dopant-containing gas such as diborane (B 2 H 6 ) are diluted with hydrogen and supplied, and RF high frequency power is applied to parallel plate electrodes and the like to generate plasma. Then, it can be formed by supplying it onto the i-type amorphous silicon film 21 of the heated crystalline silicon substrate 10. Note that the substrate temperature during film formation is preferably 150 ° C. to 250 ° C. and the RF power density is preferably 1 mW / cm 2 to 10 mW / cm 2 .
　第２のｉ型非晶質シリコン膜３１は、結晶シリコン基板１０の裏面１２上に形成される。すなわち、第１のｉ型非晶質シリコン膜２１及びｐ型非晶質シリコン膜２２を形成後、結晶シリコン基板１０の表裏を反転させ、結晶シリコン基板１０の裏面１２上に形成される。例えば、第２のｉ型非晶質シリコン膜３１は、水素を含むアモルファスの真性シリコン半導体膜とされる。ｉ型非晶質シリコン膜３１の膜厚は、第１のｉ型非晶質シリコン膜２１と同様に、１ｎｍ以上２５ｎｍ以下であり、好ましくは５ｎｍ以上１０ｎｍ以下である。 The second i-type amorphous silicon film 31 is formed on the back surface 12 of the crystalline silicon substrate 10. That is, after the first i-type amorphous silicon film 21 and the p-type amorphous silicon film 22 are formed, the front and back of the crystalline silicon substrate 10 are reversed and formed on the back surface 12 of the crystalline silicon substrate 10. For example, the second i-type amorphous silicon film 31 is an amorphous intrinsic silicon semiconductor film containing hydrogen. The film thickness of the i-type amorphous silicon film 31 is 1 nm or more and 25 nm or less, preferably 5 nm or more and 10 nm or less, like the first i-type amorphous silicon film 21.
　第２のｉ型非晶質シリコン膜３１は、ＰＥＣＶＤ、Ｃａｔ－ＣＶＤ、スパッタリング法等により形成することができる。ＰＥＣＶＤは、ＲＦプラズマＣＶＤ法を適用することができる。例えば、シラン（ＳｉＨ４）等のケイ素含有ガスを水素で希釈して供給し、平行平板電極等にＲＦ高周波電力を印加してプラズマ化して、加熱された結晶シリコン基板１０の成膜面に供給することによって形成することができる。成膜時の基板温度は、第１のｉ型非晶質シリコン膜２１と同様に、１５０℃以上２５０℃以下、ＲＦ電力密度は１ｍＷ／ｃｍ２以上１０ｍＷ／ｃｍ２以下であることが好ましい。 The second i-type amorphous silicon film 31 can be formed by PECVD, Cat-CVD, sputtering, or the like. For PECVD, an RF plasma CVD method can be applied. For example, a silicon-containing gas such as silane (SiH 4 ) is supplied after being diluted with hydrogen, and RF high frequency power is applied to parallel plate electrodes and the like to generate plasma and supply it to the film-forming surface of the heated crystalline silicon substrate 10. Can be formed. As with the first i-type amorphous silicon film 21, the substrate temperature during film formation is preferably 150 ° C. or higher and 250 ° C. or lower, and the RF power density is preferably 1 mW / cm 2 or higher and 10 mW / cm 2 or lower.
　ｎ型非晶質シリコン膜３２は、ｎ型の導電型のドーパントを含む非晶質半導体膜からなる。例えば、ｎ型非晶質シリコン膜３２は、水素を含有するアモルファスシリコンから形成される。ｎ型非晶質シリコン膜３２は、第２のｉ型非晶質シリコン膜３１よりも膜中のｎ型のドーパントの濃度が高くされる。例えば、ｎ型非晶質シリコン膜３２は、ｎ型のドーパントの濃度を１×１０２０／ｃｍ３以上とすることが好適である。ｎ型非晶質シリコン膜３２の膜厚は、光の吸収をできるだけ抑えられるように薄くすることが好適である一方で、結晶シリコン基板１０内で発生したキャリアをＢＳＦ（Ｂａｃｋ　Ｓｕｒｆａｃｅ　Ｆｉｅｌｄ）構造により効果的に分離しつつ、発生したキャリアを透明電極６０で効率よく収集される程度に厚くすることが好適である。 The n-type amorphous silicon film 32 is made of an amorphous semiconductor film containing an n-type conductive dopant. For example, the n-type amorphous silicon film 32 is formed from amorphous silicon containing hydrogen. The n-type amorphous silicon film 32 has a higher n-type dopant concentration than the second i-type amorphous silicon film 31. For example, the n-type amorphous silicon film 32 preferably has an n-type dopant concentration of 1 × 10 20 / cm 3 or more. The thickness of the n-type amorphous silicon film 32 is preferably thin so that light absorption can be suppressed as much as possible. On the other hand, carriers generated in the crystalline silicon substrate 10 have a BSF (Back Surface Field) structure. It is preferable to increase the thickness of the generated carriers so that the generated carriers can be efficiently collected by the transparent electrode 60 while being effectively separated.
　ｎ型非晶質シリコン膜３２も、ＰＥＣＶＤ、Ｃａｔ－ＣＶＤ、スパッタリング法等により形成することができる。ＰＥＣＶＤは、ＲＦプラズマＣＶＤ法を適用することができる。例えば、シラン（ＳｉＨ４）等のケイ素含有ガス及びホスフィン（ＰＨ３）等のｎ型ドーパント含有ガスを水素で希釈して供給し、平行平板電極等にＲＦ高周波電力を印加してプラズマ化して、加熱された結晶シリコン基板１０の第２のｉ型非晶質シリコン膜３１上に供給することによって形成することができる。なお、成膜時の基板温度は１５０℃以上２５０℃以下、ＲＦ電力密度は１ｍＷ／ｃｍ２以上１０ｍＷ／ｃｍ２以下とすることが好ましい。 The n-type amorphous silicon film 32 can also be formed by PECVD, Cat-CVD, sputtering, or the like. For PECVD, an RF plasma CVD method can be applied. For example, a silicon-containing gas such as silane (SiH 4 ) and an n-type dopant-containing gas such as phosphine (PH 3 ) are diluted with hydrogen and supplied, and RF high frequency power is applied to parallel plate electrodes and the like to form plasma. It can be formed by supplying it onto the second i-type amorphous silicon film 31 of the heated crystalline silicon substrate 10. Note that the substrate temperature during film formation is preferably 150 ° C. to 250 ° C. and the RF power density is preferably 1 mW / cm 2 to 10 mW / cm 2 .
　なお、上記の実施形態では受光面１１側の第１のｉ型非晶質シリコン膜２１およびｐ型非晶質シリコン膜２２を形成した後、結晶シリコン基板１０を反転させ、裏面１２側の第２のｉ型非晶質シリコン膜３１およびｎ型非晶質シリコン膜３２を形成するとしたが、これらの形成順序は逆にしてもよい。 In the above embodiment, after the first i-type amorphous silicon film 21 and the p-type amorphous silicon film 22 on the light receiving surface 11 side are formed, the crystalline silicon substrate 10 is inverted, and the first i-type amorphous silicon film 21 on the back surface 12 side is inverted. Although the i-type amorphous silicon film 31 and the n-type amorphous silicon film 32 are formed, the order of forming them may be reversed.
　透明電極５０及び６０は、例えば、インジウムスズ酸化物（ＩＴＯ）や酸化亜鉛（ＺｎＯ）などの透明導電性酸化物等から形成することができる。金属電極５１及び６１は、例えば、Ａｇ、Ｃｕ、Ｓｎなどの金属や、それらの金属の少なくとも一種を含む合金や樹脂等から形成することができる。 The transparent electrodes 50 and 60 can be formed of, for example, a transparent conductive oxide such as indium tin oxide (ITO) or zinc oxide (ZnO). The metal electrodes 51 and 61 can be formed of, for example, a metal such as Ag, Cu, or Sn, or an alloy or resin containing at least one of these metals.
　上述のように、本実施形態では、結晶シリコン基板１０の受光面１１に、テクスチャ構造が形成されている。受光面１１に形成されたテクスチャ構造の凹凸は、第１のｉ型非晶質シリコン膜２１及びｐ型非晶質シリコン膜２２に引き継がれている。裏面１２に形成された表面構造の凹凸も同様に、第２のｉ型非晶質シリコン膜３１及びｎ型非晶質シリコン膜３２に引き継がれている。 As described above, in this embodiment, a texture structure is formed on the light receiving surface 11 of the crystalline silicon substrate 10. The irregularities of the texture structure formed on the light receiving surface 11 are inherited by the first i-type amorphous silicon film 21 and the p-type amorphous silicon film 22. Similarly, the unevenness of the surface structure formed on the back surface 12 is inherited by the second i-type amorphous silicon film 31 and the n-type amorphous silicon film 32.
　テクスチャ構造は、例えば、水酸化ナトリウム（ＮａＯＨ）水溶液、水酸化カリウム（ＫＯＨ）水溶液、水酸化テトラメチルアンモニウム（ＴＭＡＨ）等のアルカリ水溶液を用いて結晶シリコン基板１０の（１００）面を異方性エッチングすることにより形成することができる。（１００）面を有する結晶シリコン基板１０をアルカリ溶液に浸漬すると、（１１１）面に沿って異方性エッチングされ、結晶シリコン基板１０の受光面１１及び裏面１２に四角錐状の凸部が多数形成される。エッチング液に含まれるアルカリ水溶液の濃度は、例えば、１．０重量％～７．５重量％であることが好ましい。 For example, the (100) plane of the crystalline silicon substrate 10 is anisotropic using an alkaline aqueous solution such as sodium hydroxide (NaOH) aqueous solution, potassium hydroxide (KOH) aqueous solution, or tetramethylammonium hydroxide (TMAH). It can be formed by etching. When the crystalline silicon substrate 10 having the (100) plane is immersed in an alkaline solution, anisotropic etching is performed along the (111) plane, and a large number of quadrangular pyramidal protrusions are formed on the light receiving surface 11 and the back surface 12 of the crystalline silicon substrate 10. It is formed. The concentration of the aqueous alkaline solution contained in the etching solution is preferably 1.0% by weight to 7.5% by weight, for example.
　また、フッ酸（ＨＦ）と硝酸（ＨＮＯ３）の混合溶液、フッ酸（ＨＦ）と硝酸（ＨＮＯ３）と酢酸（ＣＨ３ＣＯＯＨ）の混合溶液を用いたウェットエッチングや、四フッ化メタン（ＣＦ４）と酸素（Ｏ２）の混合ガスを用いたドライエッチングなどで、テクスチャ構造を形成してもよい。 Further, wet etching using a mixed solution of hydrofluoric acid (HF) and nitric acid (HNO 3 ), a mixed solution of hydrofluoric acid (HF), nitric acid (HNO 3 ), and acetic acid (CH 3 COOH), or tetrafluoromethane ( The texture structure may be formed by dry etching using a mixed gas of CF 4 ) and oxygen (O 2 ).
　本実施形態では、受光面１１の算術平均粗さＲａが１０００ｎｍ以上であり、裏面１２の算術平均粗さＲａが１０００ｎｍ未満である。すなわち、受光面１１では、大きな凹凸のテクスチャ構造が形成され、裏面１２では、小さな凹凸構造が形成されている。したがって、受光面１１と裏面１２とで、異なる機能を付与することができる。受光面１１では、大きな凹凸のテクスチャ構造を形成することにより、入射光を散乱させて、結晶シリコン基板１０における光路長を長くし、受光効率を高めることができる。一方、裏面１２では、小さな凹凸構造を形成することにより、光の反射率を高めることができる。したがって、結晶シリコン基板１０を透過しようとする光を効率よく反射し、結晶シリコン基板１０に再入射させることができる。このため、短絡電流（Ｉｓｃ）を向上させることができる。 In the present embodiment, the arithmetic average roughness Ra of the light receiving surface 11 is 1000 nm or more, and the arithmetic average roughness Ra of the back surface 12 is less than 1000 nm. That is, a large uneven texture structure is formed on the light receiving surface 11, and a small uneven structure is formed on the back surface 12. Therefore, different functions can be given to the light receiving surface 11 and the back surface 12. By forming a large uneven texture structure on the light receiving surface 11, incident light can be scattered, the optical path length in the crystalline silicon substrate 10 can be increased, and the light receiving efficiency can be increased. On the other hand, on the back surface 12, the light reflectance can be increased by forming a small uneven structure. Therefore, the light that attempts to pass through the crystalline silicon substrate 10 can be efficiently reflected and re-entered into the crystalline silicon substrate 10. For this reason, a short circuit current (Isc) can be improved.
　また、裏面１２に結晶シリコン基板の面方位に依存しない表面を有する凹凸構造とすることにより、光の入射角度に依存しない乱反射が生じるようにできる。また効果として、観察角度に因らない一様なセルの外観が得られる。透明バックシートを使用した太陽電池モジュールを裏面側から観察する場合を例に挙げると、結晶シリコン基板の面方位を使用した場合はモジュールに対する観察角度によりセル裏面側の光の反射強度が変化するが、本実施形態の面方位に依存しない表面を有するセルを使う事で観察角度に因らない一様な外観が得られる。 In addition, by forming a concavo-convex structure having a surface on the back surface 12 that does not depend on the plane orientation of the crystalline silicon substrate, irregular reflection that does not depend on the incident angle of light can occur. As an effect, a uniform cell appearance can be obtained regardless of the observation angle. Taking a case where a solar cell module using a transparent back sheet is observed from the back side as an example, when the plane orientation of the crystalline silicon substrate is used, the reflection intensity of light on the cell back side changes depending on the observation angle with respect to the module. By using the cell having a surface independent of the plane orientation of this embodiment, a uniform appearance independent of the observation angle can be obtained.
　裏面１２の表面構造の凹凸を受光面１１のテクスチャ構造の凹凸より小さくし、かつ、結晶シリコン基板の面方位に依存しない構造とする方法としては、例えば、以下の方法が挙げられる。 As a method for making the unevenness of the surface structure of the back surface 12 smaller than the unevenness of the texture structure of the light receiving surface 11 and making the structure independent of the plane orientation of the crystalline silicon substrate, for example, the following method can be cited.
　（１）受光面１１と裏面１２とで、異なるエッチング処理を施す。例えば、受光面１１と裏面１２とで、種類または濃度などが異なるエッチング液を用いる。あるいは、受光面１１と裏面１２とで、ドライエッチングとウェットエッチングなどのように、エッチング方法を変える。 (1) The light receiving surface 11 and the back surface 12 are subjected to different etching processes. For example, etchants having different types or concentrations are used for the light receiving surface 11 and the back surface 12. Alternatively, the etching method is changed between the light receiving surface 11 and the back surface 12, such as dry etching and wet etching.
　（２）裏面１２に、有機物やシリコン酸化物等のエッチング阻害物質が付着した状態で、受光面１１及び裏面１２をウェットエッチング処理する。結晶シリコン基板は、スライスされた直後においては、その表面に有機物等の汚れが付着している。この汚れを、裏面１２に対しては除去せずに残した状態で、エッチング処理する方法が挙げられる。あるいは、積極的に裏面１２に有機物等を塗布してエッチング処理してもよい。 (2) The light-receiving surface 11 and the back surface 12 are wet-etched in a state where an etching inhibitor such as an organic substance or silicon oxide is attached to the back surface 12. Immediately after being sliced, the crystalline silicon substrate has dirt such as organic matter attached to its surface. There is a method of performing an etching process in a state where the dirt is left without being removed from the back surface 12. Or you may apply | coat organic substance etc. to the back surface 12 positively, and may etch.
　（３）受光面１１に大きな凹凸のテクスチャ構造と裏面１２に小さな凹凸のテクスチャ構造を形成した後、両面にテクスチャ構造を崩すような処理を行う。具体的な処理としては、例えば、フッ硝酸によるエッチングを施すと、大きな凹凸の受光面側はテクスチャ谷部のみのラウンドエッチングとなるが、小さな凹凸の裏面側は結晶面を保持しないまでにエッチングされる。 (3) After forming a textured structure with large irregularities on the light receiving surface 11 and a textured structure with small irregularities on the back surface 12, a process is performed to destroy the texture structure on both sides. As a specific treatment, for example, when etching with fluoric nitric acid is performed, the light-receiving surface side of the large unevenness is round-etched only on the texture valley, but the back surface side of the small unevenness is etched until the crystal surface is not retained. The
　（第２の実施形態）
　図２は、第２の実施形態の太陽電池２を示す模式的断面図である。本実施形態では、図２に示すように、裏面側透明電極６０の上に、金属電極７０が形成されている。金属電極７０は、スパッタリング、蒸着、化学気相成長法、印刷やめっき等の薄膜形成方法により形成することができる。 (Second Embodiment)
FIG. 2 is a schematic cross-sectional view showing the solar cell 2 of the second embodiment. In the present embodiment, as shown in FIG. 2, a metal electrode 70 is formed on the back side transparent electrode 60. The metal electrode 70 can be formed by a thin film forming method such as sputtering, vapor deposition, chemical vapor deposition, printing or plating.
　その他の構成については、図１に示す第１の実施形態と同様である。 Other configurations are the same as those of the first embodiment shown in FIG.
　本実施形態のように、裏面１２側に金属電極７０が形成されていると、結晶シリコン基板１０を透過しようとする光は、金属電極７０に吸収されやすくなる。しかしながら、本実施形態では、裏面１２に、小さな凹凸構造が形成されている。このため、光の反射率が高められており、結晶シリコン基板１０を透過しようとする光は、裏面１２で反射されるので、結晶シリコン基板１０における光電変換効率を高めることができる。 If the metal electrode 70 is formed on the back surface 12 side as in this embodiment, the light that is about to pass through the crystalline silicon substrate 10 is easily absorbed by the metal electrode 70. However, in this embodiment, a small uneven structure is formed on the back surface 12. For this reason, the reflectance of light is increased, and the light that is about to pass through the crystalline silicon substrate 10 is reflected by the back surface 12, so that the photoelectric conversion efficiency in the crystalline silicon substrate 10 can be increased.
　上記実施形態では、裏面１２にテクスチャ構造を形成しているが、これに限定されるものではない。裏面１２にテクスチャ構造を形成せずに、裏面１２の算術平均粗さＲａを１０００ｎｍ未満にしてもよい。 In the above embodiment, the texture structure is formed on the back surface 12, but the present invention is not limited to this. The arithmetic average roughness Ra of the back surface 12 may be less than 1000 nm without forming a texture structure on the back surface 12.
　本実施形態においては、非晶質シリコン層２０及び３０に、それぞれｉ型非晶質シリコン薄膜２１及び３１を設けているが、本発明は必ずしもこれに限定されるものではない。例えば、非晶質シリコン層２０をｐ型非晶質シリコン膜２２のみから形成し、非晶質シリコン層３０をｎ型非晶質シリコン膜３２のみから形成してもよい。 In this embodiment, the i-type amorphous silicon thin films 21 and 31 are provided in the amorphous silicon layers 20 and 30, respectively, but the present invention is not necessarily limited to this. For example, the amorphous silicon layer 20 may be formed only from the p-type amorphous silicon film 22, and the amorphous silicon layer 30 may be formed only from the n-type amorphous silicon film 32.
　また、本発明における第１のシリコン層及び第２のシリコン層は、ドーパントを結晶シリコン基板１０の表面に拡散することにより形成してもよい。 Further, the first silicon layer and the second silicon layer in the present invention may be formed by diffusing a dopant on the surface of the crystalline silicon substrate 10.
　本実施形態においては、結晶シリコン基板１０として、ｎ型の単結晶シリコン基板を用いているが、ｐ型の単結晶シリコン基板を用いてもよい。また、非晶質シリコン層２０をｎ型、非晶質シリコン層３０をｐ型とし、受光面側と裏面側の極性を上記実施形態と入れ替えた構成としてもよい。 In this embodiment, an n-type single crystal silicon substrate is used as the crystalline silicon substrate 10, but a p-type single crystal silicon substrate may be used. Alternatively, the amorphous silicon layer 20 may be n-type, the amorphous silicon layer 30 may be p-type, and the polarities on the light receiving surface side and the back surface side may be replaced with those in the above embodiment.
１，２…太陽電池
１０…結晶シリコン基板
１１…受光面
１２…裏面
２０…ｐ型の非晶質シリコン層
２１…第１のｉ型非晶質シリコン膜
２２…ｐ型非晶質シリコン膜
３０…ｎ型の非晶質シリコン層
３１…第２のｉ型非晶質シリコン膜
３２…ｎ型非晶質シリコン膜
４０…光電変換部
５０…受光面側透明電極
５１…金属電極
６０…裏面側透明電極
６１…金属電極
７０…金属電極 DESCRIPTION OF SYMBOLS 1, 2 ... Solar cell 10 ... Crystalline silicon substrate 11 ... Light-receiving surface 12 ... Back surface 20 ... p-type amorphous silicon layer 21 ... 1st i-type amorphous silicon film 22 ... p-type amorphous silicon film 30 ... n-type amorphous silicon layer 31 ... second i-type amorphous silicon film 32 ... n-type amorphous silicon film 40 ... photoelectric conversion part 50 ... light-receiving surface side transparent electrode 51 ... metal electrode 60 ... back side Transparent electrode 61 ... Metal electrode 70 ... Metal electrode

Claims (4)

  1. 　受光面及び裏面を有する一導電型の結晶シリコン基板と、
    　前記受光面または裏面のうちの一方の面上に設けられる他導電型の第１のシリコン層と、
    　前記受光面または裏面のうちの他方の面上に設けられる一導電型の第２のシリコン層とを備え、
    　前記結晶シリコン基板は、前記受光面に算術平均粗さＲａが１０００ｎｍ以上のテクスチャ構造を有し、前記裏面に算術平均粗さＲａが１０００ｎｍ未満の凹凸構造を有する、太陽電池。     One conductivity type crystalline silicon substrate having a light receiving surface and a back surface;
    A first silicon layer of another conductivity type provided on one of the light receiving surface and the back surface;
    A second silicon layer of one conductivity type provided on the other surface of the light receiving surface or the back surface,
    The crystalline silicon substrate is a solar cell in which the light receiving surface has a texture structure with an arithmetic average roughness Ra of 1000 nm or more, and the back surface has an uneven structure with an arithmetic average roughness Ra of less than 1000 nm.
  2. 　前記第１のシリコン層の上に設けられる受光側透明電極、及び前記第２のシリコン層の上に設けられる裏面側透明電極をさらに備える、請求項１に記載の太陽電池。 The solar cell according to claim 1, further comprising a light-receiving side transparent electrode provided on the first silicon layer and a back-side transparent electrode provided on the second silicon layer.
  3. 　前記第１のシリコン層の上に設けられる受光側透明電極、及び前記裏面側透明電極の全面上に設けられる裏面側金属電極をさらに備える、請求項２に記載の太陽電池。 The solar cell according to claim 2, further comprising a light-receiving side transparent electrode provided on the first silicon layer and a back-side metal electrode provided on the entire surface of the back-side transparent electrode.
  4. 　前記第１のシリコン層が、第１の真性非晶質シリコン膜と、前記第１の真性非晶質シリコン膜の上に設けられる他導電型非晶質シリコン膜とから構成され、前記第２のシリコン層が、第２の真性非晶質シリコン膜と、前記第２の真性非晶質シリコン膜の上に設けられる一導電型非晶質シリコン膜とから構成される、請求項１～３のいずれか一項に記載の太陽電池。 The first silicon layer is composed of a first intrinsic amorphous silicon film and another conductivity type amorphous silicon film provided on the first intrinsic amorphous silicon film, and the second The silicon layer comprises a second intrinsic amorphous silicon film and a one-conductivity type amorphous silicon film provided on the second intrinsic amorphous silicon film. The solar cell as described in any one of these.
PCT/JP2014/073541 2013-09-27 2014-09-05 Solar cell WO2015045809A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2015539070A JPWO2015045809A1 (en) 2013-09-27 2014-09-05 Solar cell

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-201294 2013-09-27
JP2013201294 2013-09-27

Publications (1)

Publication Number Publication Date
WO2015045809A1 true WO2015045809A1 (en) 2015-04-02

Family

ID=52742956

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/073541 WO2015045809A1 (en) 2013-09-27 2014-09-05 Solar cell

Country Status (2)

Country Link
JP (1) JPWO2015045809A1 (en)
WO (1) WO2015045809A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107195720A (en) * 2016-03-10 2017-09-22 盐城金合盛光电科技有限公司 Silicon substrate heterojunction solar cell
JP2019009402A (en) * 2017-06-28 2019-01-17 国立研究開発法人物質・材料研究機構 Solar cell and manufacturing method of the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004281758A (en) * 2003-03-17 2004-10-07 Sharp Corp Solar cell and method for manufacturing the same
JP2011061030A (en) * 2009-09-10 2011-03-24 Kaneka Corp Crystal silicon-based solar cell

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004281758A (en) * 2003-03-17 2004-10-07 Sharp Corp Solar cell and method for manufacturing the same
JP2011061030A (en) * 2009-09-10 2011-03-24 Kaneka Corp Crystal silicon-based solar cell

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107195720A (en) * 2016-03-10 2017-09-22 盐城金合盛光电科技有限公司 Silicon substrate heterojunction solar cell
JP2019009402A (en) * 2017-06-28 2019-01-17 国立研究開発法人物質・材料研究機構 Solar cell and manufacturing method of the same

Also Published As

Publication number Publication date
JPWO2015045809A1 (en) 2017-03-09

Similar Documents

Publication Publication Date Title
US9023681B2 (en) Method of fabricating heterojunction battery
JP5868503B2 (en) Solar cell and method for manufacturing the same
Barrio et al. Optimisation of NaOH texturisation process of silicon wafers for heterojunction solar-cells applications
Lee et al. Solar cell implemented with silicon nanowires on pyramid-texture silicon surface
WO2014155833A1 (en) Solar battery
JP6091458B2 (en) Photoelectric conversion device and manufacturing method thereof
US20120132264A1 (en) Solar cell and method for fabricating the same
CN102712999B (en) Method of coating a substrate
JPWO2011065571A1 (en) PHOTOELECTRIC CONVERSION MODULE, ITS MANUFACTURING METHOD, AND POWER GENERATION DEVICE
US20150075613A1 (en) Solar cell
WO2012162905A1 (en) Method for manufacturing back contact crystalline silicon solar cell sheet
CN104362219A (en) Crystalline solar cell production process
Lien et al. Influence of surface morphology on the effective lifetime and performance of silicon heterojunction solar cell
WO2015045809A1 (en) Solar cell
EP2469603A1 (en) Improved method for manufacturing a photovoltaic device comprising a TCO layer
Imamura et al. Light trapping of crystalline Si solar cells by use of nanocrystalline Si layer plus pyramidal texture
JP6136024B2 (en) Manufacturing method of solar cell
Chen et al. Improvement of conversion efficiency of multi-crystalline silicon solar cells using reactive ion etching with surface pre-etching
Wu et al. Texture-Etched SnO 2 Glasses Applied to Silicon Thin-Film Solar Cells
CN110476256B (en) Solar cell, solar cell module, and method for manufacturing solar cell
Hongsingthong et al. Development of novel Al-doped zinc oxide films fabricated on etched glass and their application to solar cells
JP6502147B2 (en) Method of manufacturing solar cell and method of manufacturing solar cell module
JP2007142471A (en) Method for manufacturing solar cell
US10103282B2 (en) Direct texture transparent conductive oxide served as electrode or intermediate layer for photovoltaic and display applications
KR20120106259A (en) Solar cell and method of manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14849290

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2015539070

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14849290

Country of ref document: EP

Kind code of ref document: A1