JP2011049205A - Laminated substrate and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated substrate having a bump stabilized in height and having high connecting strength. <P>SOLUTION: The laminated substrate includes a first substrate 10 having an electrode pattern 13 on a first surface thereof, a surface layer dielectric layer 12 provided on a first surface of the first substrate, and a through-hole 20 provided on the surface layer dielectric layer 12. The through-hole 20 is provided on the electrode pattern 13 and mechanically connected to the electrode pattern 13. The substrate further includes a bump 11 filled within the through-hole 20 to protrude from the surface of the surface layer dielectric layer 12. The opening width of the through-hole 20 opposite to the first substrate is set to be smaller than the maximum opening width within the surface layer dielectric layer 12. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a laminated substrate on which bumps are formed and a method for manufacturing the same.

  In recent years, in response to miniaturization and higher functionality of devices, a device in which a functional element such as a semiconductor chip is bump-mounted on a multilayer substrate having wiring electrodes is used.

  In this case, after firing the laminated substrate, solder bumps are formed on the via holes or electrode patterns, and functional elements are mounted thereon.

  As prior art document information related to the invention of this application, for example, Patent Document 1 is known.

Japanese Patent Laid-Open No. 10-41626

  When solder bumps are formed on via holes or electrode patterns as described above, there are problems that the height of solder bumps tends to vary, or that the functional elements are likely to come off because the connection strength between via holes or electrode patterns and solder is weak. It was.

  The present invention solves these problems, and an object of the present invention is to obtain a laminated substrate in which the bump height is stable and the connection strength is strong.

  In order to achieve the above object, the present invention provides a first substrate having an electrode pattern on a first surface, a surface dielectric layer provided on the first surface of the first substrate, and a surface dielectric layer. The through hole is provided on the electrode pattern, mechanically connected to the electrode pattern, filled in the through hole, and formed with bumps protruding from the surface dielectric layer surface. In other words, the opening width of the through hole on the side opposite to the first substrate is made smaller than the maximum opening width inside the surface dielectric layer.

  As described above, in the multilayer substrate of the present invention, the bumps protruding from the surface can be integrated with those filled in the through holes provided in the surface dielectric layer, so that the strength can be increased. By making the opening width of the through hole on the opposite side of the first substrate smaller than the maximum opening width inside the surface dielectric layer, the surface dielectric layer can prevent the bump from being removed, and the electrode pattern and The strength of the bump can also be improved. Furthermore, since bumps are formed on a flat electrode pattern, there is no variation in the height of the electrode pattern, and the bump height is determined by the volume and opening diameter of the through hole, resulting in variations in bump height. The effect is that a laminated substrate having a small thickness can be obtained.

Sectional drawing of the multilayer substrate in one embodiment of this invention The enlarged view of the bump structure of the multilayer substrate in one embodiment of the present invention The layer block diagram in the green sheet state before baking of the multilayer substrate in one embodiment of this invention Sectional drawing of the laminated body before baking of the multilayer substrate in one embodiment of this invention Sectional drawing of the laminated body after baking of the laminated substrate in one embodiment of this invention Sectional drawing after removal of constraining layer of laminated substrate in one embodiment of the present invention

  Hereinafter, a laminated substrate according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view of a multilayer substrate according to an embodiment of the present invention, and FIG. 2 is an enlarged view of a bump structure. In FIG. 1, a surface dielectric layer 12 is provided on the surface of a first substrate 10 provided with an electrode pattern 13 on the surface, and bumps 11 are arranged in an electrode pattern via the surface dielectric layer 12 in order from the top layer. 13, the electrode pattern 13 is connected to the electrode layer 16 via the via electrode 15 in the dielectric layer 14, and the electrode layer 16 is connected to the lowermost back electrode 19 via the via electrode 18 in the dielectric layer 17. Connected to.

  The bump 11 is formed of a solder material, and the exposed portion has a pseudospherical shape with a diameter of 65 to 85 μm, and is connected to the electrode pattern 13 through the through hole 20 of the surface dielectric layer 12. The surface dielectric layer 12 has a sheet shape with a thickness of 10 to 30 μm, and the through holes 20 are formed in a sintered state before the bumps 11 are formed. The through-hole 20 has a circular shape with a diameter of 80 to 100 μm when viewed from the surface, and the inner opening width is 5 to 10 μm wider than the opening width on the surface side, and is filled with solder.

  By forming it in the shape of a bracket-shaped through hole in this way, the filled solder is suppressed by the surface dielectric layer 12, and it becomes difficult to come out, and the adhesion strength with the functional chip mounted on the bump is improved. Can do. Further, the through hole 20 can obtain a better effect when the opening width on the electrode pattern 13 side is larger than the opening width on the surface side.

  The electrode pattern 13 is a conductive material such as silver or copper having a thickness of 5 to 10 μm, is formed as a connection line or a GND electrode, and is connected to the via electrode 15. The via electrode 15 in the dielectric layer 14 is connected to the electrode pattern 13, but if the structure is shifted from the position of the through hole 20 and does not overlap, the bump formation surface protrusion height of the electrode pattern 13 is stabilized. Can do. That is, it is possible to stabilize the height variation of a plurality of formed bumps. The electrode layer 16 is connected to the via electrode 15, forms an inductor or capacitor pattern, and is connected to the via electrode 18.

  Next, a method for forming this laminated substrate will be described. FIG. 3 shows a layer structure in a green sheet state before firing. The dielectric layers 14 and 17 are dielectric materials mainly composed of borosilicate glass and alumina, and are materials that are sintered at around 900 ° C. and are shrunk by 85% in the plane direction when fired alone. It is.

  The constraining layers 21 and 22 are alumina-based materials, and are not sintered at 900 ° C., and have a function of constraining the dielectric layer when the dielectric layer or the like is sintered. The surface dielectric layer 12 forms the through hole 20 by a mold or laser processing. The through-hole 20 may be left hollow, or may be filled with a resin material such as a binder mixed in a green sheet that does not remain at the time of 900 ° C. baking.

  The dielectric layers 14 and 17 are formed through holes, and then filled with a conductive paste such as silver to form a via electrode, and the electrode layer 16 is formed on the dielectric layer surface using the same conductive paste such as silver. Print form. When the dielectric layers 14 and 17 are stacked so as to be sandwiched between the constraining layers 21 and 22, and finally press-bonded, the result is as shown in FIG. When the laminated body of FIG. 4 is fired at 900 ° C., the plane direction is sintered in a non-shrinked state, and the height direction is shrunk by 40 to 60%, resulting in a sintered state as shown in FIG. Here, in the through hole 20 of the surface dielectric layer 12, the surface on the constraining layer 21 side is constrained by the constraining layer 21 and thus does not shrink. Further, the surface on the electrode pattern 13 side is restrained by the electrode layer and does not shrink. However, since there is no constrained material in the middle of the through hole 20, shrinkage occurs, and the through hole 20 is formed such that the middle of the surface dielectric layer 12 has the maximum opening.

  When the constraining layers 21 and 22 in FIG. 5 are removed by blasting, a sintered body as shown in FIG. 6 is obtained, and pattern printing is performed so as to cover the through holes 20 using solder paste, and reflowing is performed at about 260 ° C. As described above, a bump structure can be formed in which a portion filled with the through-hole 20 and a portion protruding to the outside are integrated by soldering directly to the electrode pattern 13, and the through-hole 20 has a maximum opening at the middle. Therefore, it is possible to realize a bump having sufficient strength against the pulling force.

  The material of the surface dielectric layer may be the same material as that of the dielectric layer. However, when a material having low resistance to the plating solution is used for the dielectric layer, for example, zinc-based glass is used. It is desirable to use a material with excellent plating properties. By doing so, even when the back electrode is plated before the solder bumps are formed, the surface layer side is not damaged, and the strength of the bumps can be sufficiently maintained.

  The multilayer substrate according to the present invention is industrially useful because it can obtain a multilayer substrate having a stable bump height and strong connection strength.

DESCRIPTION OF SYMBOLS 10 1st board | substrate 11 Bump 12 Surface layer dielectric layer 13 Electrode pattern 14 Dielectric layer 15 Via electrode 16 Electrode layer 17 Dielectric layer 18 Via electrode 19 Back surface electrode 20 Through-hole 21 Constrained layer 22 Constrained layer

Claims (2)

A first substrate having an electrode pattern on a first surface; a surface dielectric layer provided on the first surface of the first substrate; and a through hole provided in the surface dielectric layer. A hole is provided on the electrode pattern, is mechanically connected to the electrode pattern, fills the inside of the through-hole, and forms a bump protruding from the surface dielectric layer surface. A laminated substrate in which an opening width of the through hole on the side opposite to the one substrate is made smaller than a maximum opening width inside the surface dielectric layer. A step of obtaining a green sheet made of a low-temperature sintered ceramic sheet having an electrode pattern on the first surface, and a surface dielectric sheet having a through hole provided in a portion overlapping the electrode pattern on the first surface of the green sheet A step of combining, a step of superposing a constraining layer made of a material that does not sinter at a temperature at which the green sheet, the electrode pattern, and the surface dielectric sheet are sintered on both sides, and the green sheet in the firing furnace, A step of sintering the electrode pattern and the surface dielectric sheet, a step of removing the constraining layer, a step of printing a solder paste on a portion of the through hole, and solder bumps by melting the solder paste And a step of forming the laminate substrate.

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