JP2011045214A - Inverter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter which prevents the thermal breakage of each switching element, without increasing the allowable power loss amount of each switching element. <P>SOLUTION: In the inverter 1, the product of power losses Ppu, Ppv, Ppw, Pnu, Pnv, and Pnw by the switching elements Spu, Spv, Spw, Snu, Snv, and Snw during a given period T and correction factors kpu, kpv, kpw, knu, knv, and knw reversely proportional to the allowable power loss amounts of the switching elements is determined as being allowable power loss levels P'pu, P'pv, P'pw, P'nu, P'nv and P'nw. A control unit 16 maintains the constant sum tz of a period t0 in which only all lower arm elements Snu, Snv, and Snw at each of phases U, V, and W turn on and a period t7 in which only all upper arm elements Spu, Spv and Spw at each of phases U, V, and W turn on, to adjust the ratio between the period t0 and t7 so that the largest among the allowable power loss levels P'pu, P'pv, P'pw, P'nu, P'nv and P'nw of the switching elements at each of the phases U, V and W becomes minimum during the period T. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an inverter device that controls power supply to a three-phase load, and more particularly to a technique for controlling power loss in a switch element that controls power supply.

  In the inverter device for controlling the power supply to the three-phase load, two switch elements connected in series to a predetermined DC power source are provided for each phase of the three-phase load. A voltage between them is applied to a three-phase load depending on the phase to which the two switch elements correspond, respectively. At that time, both of the two switch elements are not simultaneously turned on. Of the two switching elements for each phase, one connected to the anode side of the DC power supply is called an upper arm element, and one connected to the cathode side of the DC power supply is called a lower arm element.

  Such inverter device modulation methods include three-phase modulation and two-phase modulation. In the three-phase modulation, there are a period in which only the upper arm elements of all three phases are turned on, and a period in which only the lower arm elements of all three phases are turned on. Are equivalent in that they have the same potential. Also, the two-phase modulation is a modulation method in which the on / off state of each one-phase switch element of the three phases is fixed and the on / off states of the remaining two-phase switch elements are controlled.

  Patent Document 1 is a prior art document relating to such a technique.

JP 2007-74858 A

  In such a modulation method, power loss (more specifically, conduction loss, and so on) may be biased to a specific switch element. For example, in low-frequency operation with a three-phase load, a large power loss may occur and thermal destruction may occur only with a specific switch element. In order to prevent this, it is necessary to increase the power loss tolerance of the switch element, which causes a problem of increased cost.

  Further, in the low-frequency operation with a three-phase load, the period during which the same ON / OFF state continues in each switch element becomes longer. For this reason, a switch element with a large power loss has a problem that the temperature may rise to cause thermal destruction. On the other hand, in the high-frequency operation of the three-phase load, the on / off state of each switch element changes periodically in a short time, so that power loss is dispersed and the temperature hardly rises only with a specific switch element. .

  Further, when such an inverter device is used for controlling a compressor motor that compresses refrigerant or the like, noise and vibration are generated due to the load pulsation of the compressor at a low speed rotation of the motor. Accordingly, control is performed to suppress noise and vibration by causing the current to pulsate.

  However, in such control, the current peak of a specific phase becomes large. For this reason, the switch element of a specific phase has a power loss larger than that of the switch element of the other phase, the temperature rises, and there is a possibility of thermal destruction. In order to prevent this, it is necessary to increase the power loss tolerance of the switching element of the specific phase or reduce the current pulsation, but there is a problem that the former increases the cost, and in the latter case There is a problem that the vibration control performance is lowered.

  In addition, when the characteristics of each switch element are different, there is a problem that the merit due to the difference in the characteristics is not sufficiently exhibited. For example, when the power loss allowance of each switch element is the same, and the power loss of each switch element changes according to the magnitude of the current, the power loss depends on the magnitude of the current supplied to the three-phase load. It is desirable to control each switch element so that the ON period of the small switch element becomes long. Also, when each switch element has a different power loss tolerance (for example, each switch element has a different structure (MOSFET, IGBT, etc.), or each switch element has a different material (Si, SiC, GaN, etc.) Or when each switch element is a device with a different chip size), each switch element has a longer ON period of the switch element as the ratio of the power loss to the power loss tolerance becomes smaller. It is desirable to control Thereby, the thermal destruction of each switch element can be prevented.

  An object of the present invention is to solve the above problems, and provides an inverter device capable of preventing thermal destruction of each switch element without increasing the allowable power loss of each switch element. There is to do.

  In order to solve the above-mentioned problem, a first aspect of the present invention is an inverter device for driving and controlling a load (10), which converts electric power of a predetermined DC power supply (12) into electric power of a predetermined output system. And an inverter circuit (14) having a plurality of switch elements (Spu, Snu, Spv, Snv, Spw, Snw) to be supplied to the load, and a control circuit for driving and controlling the load by controlling the plurality of switch elements. (16), and a correction factor (Ppu, Ppv, Ppw, Pnu, Pnv, Pnw) in each switching element and a correction coefficient (inversely proportional to the power loss tolerance of the switching element). The product of kpu, kpv, kpw, knu, knv, knw) is the power loss tolerance (P′pu, P′pv, P′pw, P′nu, P′nv, P′nw). Circuit (16) is in said predetermined period, it said as the largest ones of the power loss tolerance of each switch element is minimized, the is intended for turning on and off the respective switch elements.

  A second aspect of the present invention is the inverter device according to the first aspect, wherein the inverter circuit (14) includes the predetermined DC power source (U, V, W) for each phase (U, V, W) of the load. 12) two switch elements (Spu, Snu; Spv, Snv; Spw, Snw) connected in series to each other, and the voltage between the switch elements for each phase is respectively Of the two switch elements applied to the phase and connected to the anode side of the predetermined DC power source (Spu, Spv, Spw) is used as the upper arm element and connected to the cathode side of the predetermined DC power source (Snu, Snv, Snw) is used as a lower arm element, and the control circuit (16) has a maximum one of the power loss tolerances of the switch elements of the phases in the fixed period. To be the smallest Sum (tz) of a first period (t0) in which only all the lower arm elements in each phase are turned on and a second period (t7) in which only all the upper arm elements in each phase are turned on Is kept constant, and the ratio between the first period and the second period is adjusted.

  A third aspect of the present invention is the inverter device according to the first or second aspect, wherein each of the switch elements is reversely connected between the transistor (T) and the main electrode of the transistor. The correction coefficient (kpu, kpv, kpw, knu, knv, knw) includes a first correction coefficient (kpu_t, kpv_t, kpw_t, knu_t, knv_t, knw_t) and the diode. And the second correction coefficient (kpu_d, kpv_d, kpw_d, knu_d, knv_d, knw_d), and the first correction coefficient is multiplied by the power loss (Ppu_t, Ppv_t, Ppw_t, Pnu_t, Pnv_t, Pnw_t) of the transistor. And the second correction factor is a power loss (Ppu_d, Ppv) of the diode. _d, Ppw_d, Pnu_d, Pnv_d, Pnw_d).

  A fourth aspect of the present invention is the inverter device according to the first or second aspect, wherein the correction coefficient is a reciprocal of an absolute maximum rating of power loss of the switch element.

  A fifth aspect of the present invention is the inverter device according to the third aspect, wherein the first correction coefficient is a reciprocal of an absolute maximum rating of the power loss of the transistor, and the second correction coefficient is It is the reciprocal of the absolute maximum rating of the power loss of the diode.

  A sixth aspect of the present invention is the inverter device according to any one of the second to fifth aspects, wherein the control circuit (16) has (a) the first period (t0) is zero. A first phase (X) that gives the largest of the power loss tolerances (P′pu, P′pv, P′pw) of all the upper arm elements (Spu, Spv, Spw) The power of all the lower arm elements (Snu, Snv, Snw) when the phase is specified from the phases (U, V, W) and the first period (t0) is equal to the sum (tz) A second phase (Y) giving the maximum one of the loss tolerances (P′nu, P′nv, P′nw) is identified from the respective phases (S1), (b) the first Before the second phase (Y) and the power loss tolerance (P′px) of the upper arm element (Spx) of the phase (X) of The first period (tb) and the power loss tolerance (P′b) when the power loss tolerance (P′ny) of the lower arm element (Sny) is in an equilibrium state are obtained (S2), ( c) The power loss of all the switch elements (Spu, Snu, Spv, Snv, Spw, Snw) when the first period (t0) is equal to the first period (tb) when the equilibrium state is reached. The maximum power loss tolerance (P′m) is specified from the tolerances (P′pu, P′nu, P′pv, P′nv, P′pw, P′nw) (S3), d) In the case where the power loss tolerance (P′b) in the equilibrium state and the maximum power loss tolerance (P′m) are equal (S5), the first period in the equilibrium state When (tb) is not less than zero and not more than the sum (tz) (S3), The ratio of the first period and (t0) second period (t7), adjusted to the ratio obtained from the first period of time of the equilibrium state (tb) (S8) is intended.

  According to a seventh aspect of the present invention, in the inverter device according to the sixth aspect, the control circuit (16) includes: (e) the first period (tb) in the equilibrium state is less than zero. When it is smaller or larger than the sum, the ratio between the first period (t0) and the second period (t7) is the same as the first phase when the first period (t0) is zero ( X) and the power loss tolerance (P′px) of the upper arm element (Spx) and the second phase (Y) when the first period (t0) is equal to the sum (tz). The lower arm element (Sny) is adjusted to the ratio obtained from the first period of the smaller one of the power loss tolerance (P′ny) (S7).

  An eighth aspect of the present invention is the inverter device according to the sixth aspect, wherein the control circuit (16) includes (f) the power loss tolerance (P′b) in the equilibrium state. When the maximum power loss tolerance (P′m) is not equal, the maximum power loss tolerance (P′m) is the power of any one of the upper arm elements (Spu, Spv, Spw). In the case of the loss tolerance (P′pu, P′pv, P′pw), the phase corresponding to the maximum power loss tolerance is set to the first phase (X), and the (a) On the other hand, the maximum power loss tolerance (P′m) is the power loss tolerance (P′nu, P′nv) of any one of the lower arm elements (Snu, Snv, Snw). , P′nw), the phase corresponding to the maximum power loss tolerance is the second phase. Is set to Y), it performs the (b) subsequent processing (S6) is intended.

  A ninth aspect of the present invention is the inverter device according to any one of the second to fifth aspects, wherein each current (Iu, Iv, Iw) flowing in each phase (U, V, W) is supplied. Current control sensors (17u, 17v, 17w) for detection are further provided, and the control circuit (16) (a) flows from the respective phases to the respective phases based on the detection results of the respective current detection sensors. The first phase (X) through which the maximum current absolute value of the current flows is specified (U1), (b) the upper arm element (Spx) of the first phase (X) and the lower phase The first time (tb) when the power loss tolerance (P′px, P′nx) of each arm element (Snx) is in an equilibrium state is obtained, and (c) the first time in the equilibrium state is determined. When 1 hour (tb) is not less than zero and not more than the sum (tz), the first period (t0) The second period the ratio between (t7), adjusted to the ratio obtained from the first hour (tb) of the time of the equilibrium state (U4) is intended.

  A tenth aspect of the present invention is the inverter device according to the ninth aspect, wherein (d) the first time (tb) in the equilibrium state is smaller than zero or the sum (tz). Is greater than the first phase (X) when the first period (t0) is zero, the ratio of the first period (t0) to the second period (t7). The power loss tolerance (P′px) of the arm element (Spx) and the power loss tolerance of the lower arm element (Snx) of the first phase when the first period (t0) is equal to the sum. It is adjusted (U5) to the ratio obtained from the first period, which is the smaller of the degrees (P′nx).

  An eleventh aspect of the present invention is the inverter device according to any one of the second to tenth aspects, wherein the control circuit performs the first period (t0) and the first period every the predetermined period (T). The ratio of two periods (t7) is adjusted.

  According to the first aspect of the present invention, it is possible to reduce power loss in a switch element having a large power loss tolerance, and to prevent the switch element from being thermally destroyed. Thereby, thermal destruction of each switch element can be prevented without increasing the power loss tolerance of each switch element.

  According to the second aspect of the present invention, the ratio between the first period and the second period is adjusted while keeping the sum (tz) of the first period (t0) and the second period (t7) constant. The thermal destruction of each switch element can be prevented without affecting the control of (10).

  According to the third aspect of the present invention, the power loss tolerance of each of the transistor and the diode can be considered individually.

  According to the fourth and fifth aspects of the present invention, the correction coefficient can be easily set using the absolute maximum rating of the power loss that is an existing characteristic value.

  According to the sixth aspect of the present invention, the ratio between the first and second periods is obtained by a simple method so that the maximum power loss tolerance of each switching element of each phase is minimized. Can do.

  According to the seventh aspect of the present invention, in the case where the first period in the equilibrium state is smaller than zero or larger than the sum of the first and second periods, each switch of each phase can be performed in a simple manner. The ratio between the first and second periods can be obtained so that the maximum of the power loss tolerance of the element is minimized.

  According to the 8th aspect of this invention, the largest thing of the power loss tolerance of each switch element of each phase can be specified appropriately.

  According to the ninth aspect of the present invention, since attention is paid only to the phase in which the current having the maximum absolute value among the currents flowing in the respective phases flows, it is a method with a smaller amount of calculation than in the case of the fifth aspect. The ratio between the first and second periods can be obtained so that the maximum one of the power loss tolerances of the switching elements of each phase becomes smaller.

  According to the tenth aspect of the present invention, in the case where the first period in the equilibrium state is smaller than zero or larger than the sum of the first and second periods, a method with a small amount of calculation is used. The ratio between the first and second periods can be obtained so that the maximum of the power loss tolerance of each switch element is reduced.

  According to the eleventh aspect of the present invention, the ratio between the first and second periods can be updated at regular intervals.

1 is a schematic configuration diagram of an inverter device 1 according to a first embodiment. It is the figure which showed the combination of the on-off state of each switch element Spu, Snu, Spv, Snv, Spw, Snw. It is the figure which showed space voltage vector diagram S. FIG. It is an example figure of the on-off pattern P1. It is an example of graphing of each power loss tolerance P'pu, P'nu, P'pv, P'nv, P'pw, P'nw when tb satisfies 0≤tb≤tz. It is a flowchart explaining operation | movement of the inverter apparatus which concerns on 1st Embodiment. It is an example figure of each power loss tolerance P'pu, P'nu, P'pv, P'nv, P'pw, P'nw when tb is tb> tz. The calculation formulas of the power loss tolerances P′pu, P′nu, P′pv, P′nv, P′pw, P′nw of each switch element in the case of t0 = 0 and tz are shown. It is a block schematic diagram of the inverter apparatus 1B which concerns on 2nd Embodiment. It is the figure which showed the characteristic of each current I-voltage V of device DV1, DV2. It is the figure which showed the characteristic of each on-resistance R-device temperature K of device DV3, DV4. It is a flowchart explaining operation | movement of the inverter apparatus 1B which concerns on 2nd Embodiment.

<First Embodiment>
As shown in FIG. 1, the inverter device 1 according to this embodiment includes a load (for example, a three-phase load) 10, a direct-current power source 12, and direct-current power of the direct-current power source 12 as predetermined output power (for example, three-phase alternating current power). ) And supplied to each phase U, V, W of the three-phase load 10, and a control circuit 16 that controls the inverter circuit 14.

  The three-phase load 10 is, for example, a three-phase motor, and includes position detection sensors (for example, hall sensors) Hu, Hv, and Hw that detect the rotational position thereof. In this embodiment, the rotational position of the three-phase load 10 is detected using the position detection sensor. However, the rotational position of the three-phase load 10 is determined based on the detected value such as current or voltage without using the position detection sensor. It may be detected.

  As shown in FIG. 1, the DC power source 12 includes, for example, an AC power source 12a and a smoothing circuit 12b that converts AC power of the AC power source 12a into DC power.

  The smoothing circuit 12b includes four diodes D1 to D4, a coil L, and a capacitor C that form a bridge rectifier circuit. Each of the diodes D1 and D2 is connected in series between the anode line 12p and the cathode line 12n so that the energization direction of each diode is toward the anode line 12p. Each of the diodes D3 and D4 is connected in series between the anode line 12p and the cathode line 12n so that the energization direction of each diode is toward the anode line 12p. An AC power supply 12a is interposed between the intermediate points of the diodes D1 and D2 and the intermediate points of the diodes D3 and D4. The coil L is connected to the subsequent stage of the bridge circuit in the anode wire 12p. The capacitor C is interposed between the anode line 12p and the cathode line 12n after the coil L.

  As shown in FIG. 1, the inverter circuit 14 includes a plurality (six in this case) of switch elements Spu, Snu, Spv, Snv, Spw, Snw. The switch elements Spu and Snu are connected in series between the anode line 12p and the cathode line 12n, and a voltage therebetween is applied to the U-phase electrode 11u of the three-phase load 10. The switch elements Spv and Snv are connected in series between the anode line 12p and the cathode 12n, and a DC voltage therebetween is applied to the V-phase electrode 11v of the three-phase load 10. The switch elements Spw and Snw are connected in series between the anode line 12p and the cathode line 12n, and a voltage therebetween is applied to the W-phase electrode 11w of the three-phase load 10. The switch elements Spu, Spv, Spw connected to the anode line 12p are called upper arm elements, and the switch elements Snu, Snv, Snw connected to the cathode line 12n are called lower arm elements.

  Each switch element Spu, Snu, Spv, Snv, Spw, Snw includes a transistor T and a diode D connected in the reverse direction between the main electrodes of the transistor T. The control electrodes G of the switch elements Spu, Snu, Spv, Snv, Spw, Snw are connected to the control circuit 16, respectively. As the switch elements Spu, Snu, Spv, Snv, Spw, Snw, an IGBT having a reflux diode can be used.

  In the inverter circuit 14, a control signal is applied to the control electrodes G of the switch elements Spu, Snu, Spv, Snv, Spw, Snw by the control circuit 16, and the on / off state of each of the switch elements is controlled. At that time, the U-phase switch elements Spu and Snu are not both turned on. Similarly, both the V-phase switch elements Spv and Snv are not both turned on, and neither the W-phase switch elements Spw and Snw are both turned on. In this way, the DC power of the DC power source 12 is converted into three-phase AC power, and current is supplied to the electrodes 11u, 11v, 11w of the respective phases U, V, W of the three-phase load 10, and the three-phase load is supplied. 10 is rotationally driven.

  Note that the combinations of the on / off states of the switch elements Spu, Snu, Spv, Snv, Spw, Snw are (0, 0, 0), (0, 0, 1), (0, 1, 0), (0, 1, 1), (1, 0, 0), (1, 0, 1), (1, 1, 0), (1, 1, 1). Hereinafter, these vectors are expressed as V0, V1, V2, V3, V4, V5, V6, and V7 in the same order. These vectors V0 to V7 are called voltage vectors. In particular, the vectors V0 and V7 are called zero voltage vectors. The leftmost “0” or “1” in each parenthesis indicates the on / off state of each U-phase switch element Spu, Snu, and “0” or “1” in the center in each parenthesis indicates the V-phase. The switch elements Spv and Snv are on / off states, and the rightmost “0” or “1” in each parenthesis indicates the on / off state of the W-phase switch elements Spw and Snw. “1” indicates a state in which the upper arm element is turned on and the lower arm element is turned off, and “0” indicates a state in which the lower arm element is turned on and the upper arm element is turned off.

  As shown in FIG. 3, the voltage vectors V1 to V6 are arranged such that their start points coincide with the center point 0 and their end points are radially directed outward, and the zero voltage vectors V0 and V7 are located at the center point 0. A regular hexagonal diagram arranged and arranged in FIG. In the spatial voltage vector diagram S, each equilateral triangle region composed of two adjacent voltage vectors V1 to V6 and the voltage vectors V0 and V7 is referred to as regions S1 to S6, respectively.

  The control circuit 16 controls the inverter circuit 14 so that the three-phase load 10 is rotationally driven at a desired rotational speed ω. As shown in FIG. 1, the control circuit 16 includes a rotation speed detection unit 16a, a rotation speed command value generation unit 16b, a current command value generation unit 16c, a voltage command value generation unit 16d, and a voltage command vector generation unit 16e. , An on / off pattern generation unit 16f, a zero voltage vector adjustment unit 16g, and a control signal generation unit 16h.

  The rotational speed detector 16a detects the rotational speed ω of the three-phase motor 10 based on the time change of the rotational position of the three-phase load 10 detected by the position detection sensors Hu, Hv, Hw, and generates a current command value. To the unit 16c.

  The rotation speed command value generation unit 16b generates a rotation speed command value ω * for rotating the three-phase motor 10 at a desired rotation speed ω, and outputs it to the current command value generation unit 16c.

  The current command value generation unit 16c generates a current command value I * so that the rotation speed ω from the rotation speed detection unit 16a approaches the rotation speed command value ω * from the rotation speed command value generation unit 100j. Specifically, the current command value generation unit 16c generates a current command value I * by performing a proportional differential integration operation (PID calculation) on a deviation between the rotation speed ω and the rotation speed command value ω *, and outputs the current command value I *. The value is output to the value generator 16d.

  Based on the current command value I * from the current command value generation unit 16c, the voltage command value generation unit 16d is a voltage command value signal Vu *, Vv *, Vw corresponding to the voltage to be applied to each phase U, V, W. * Is generated and output to the voltage command vector generation unit 16e.

  The voltage command vector generation unit 16e generates a voltage command vector V * from the voltage command value signals Vu *, Vv *, Vw * and outputs it to the on / off pattern generation unit 16g. The voltage command vector V * is a vector defined on the region of the spatial voltage vector diagram S in FIG.

  The on / off pattern generation unit 16g uses the voltage command vector V * to generate an on / off pattern P1 for each fixed period T that defines the on / off state of each switch element Spu, Snu, Spv, Snv, Spw, Snw by a space vector method. Generate. More specifically, the on / off pattern generation unit 16g uses the voltage command vectors V * defined on the space vector diagram S to include the voltage command vectors V * in the regions S1 to S6. (Ie, two voltage vectors Vi and Vj (i ≠ j and i, j = 1 to 6) and zero voltage vectors V0 and V7 sandwiching the voltage command vector V *) are expanded as shown in Equation 1 (ie, Each coefficient ai, aj, a0, a7 which is a real number is obtained so as to satisfy Expression 1.

  Then, the on / off pattern generation unit 16g obtains the implementation periods ti, tj, t0, and t7 of the on / off states of the switch elements Spu, Snu, Spv, Snv, Spw, and Snw defined by the voltage vectors Vi, Vj, V0, and V7. Ti = ai · T, tj = aj · T, t0 = a0 · T, t7 = a7 · T, and the voltage vectors Vi, Vj, V0, V7 arranged in a predetermined execution order are referred to as an on / off pattern P1. To do.

  As the predetermined execution order, for example, the voltage vectors Vi, Vj, V0, and V7 may be arranged so that U, V, and W are turned on and off one phase at a time when the voltage vectors are switched. It is also possible to arrange the voltage vectors so that the execution order of these voltage vectors is symmetrical between the first half and the second half of one cycle T. FIG. 4 is an example of the on / off pattern P1 when the voltage command vector V * is in the region S1. In this on / off pattern P1, the voltage vectors V0, V7, V4, V6 constituting the region S1 are symmetric in the first half and the second half of one cycle T in the execution order of V0, V4, V6, V7, V6, V4, V0. The execution periods t0, t4, t6, and t7 of these voltage vectors V0, V7, V4, V6, and V7 are t0 / 2, t4 / 2, and t6, respectively, in the first half and the second half of one cycle T. / 2, t7 / 2 are allocated.

  The zero voltage vector adjustment unit 16g is configured so that the maximum one of the power loss tolerances (that is, the ratio of the power loss to the power loss tolerance) of each switch element Spu, Snu, Spv, Snv, Spw, Snw is the smallest. Further, the on / off pattern P1 generated by the on / off pattern generation unit 16g is corrected. More specifically, the zero voltage vector adjustment unit 16g adjusts the ratio of the periods t0 and t7 while keeping the sum of the periods t0 and t7 constant with respect to the on / off pattern P1. Hereinafter, a method for adjusting the ratio between the periods t0 and t7 of the on / off pattern P1 will be described in detail by taking the case where the voltage command vector V * is in the region S1 as an example.

  First, equations necessary for explaining the method of adjusting the ratio between the periods t0 and t7 of the on / off pattern P1 will be described.

<Energization period within a fixed period T of each switch element>
The energization periods tpu, tnu, tpv, tnv, tpw, tnw within a certain period (for example, carrier period) T of each switch element Spu, Snu, Spv, Snv, Spw, Snw are, for example, in the region S1, as shown in Expression 2 Given to.

  It can be seen from Equation 2 that each energization period tpu, tpv, tpw is a decreasing function of the period t0, and each energization period tnu, tnv, tnw is an increasing function of the period t0.

<Power loss of each switch element>
Instantaneous powers fpu (Iu), fnu (Iu), fpv (Iv) of the switching elements Spu, Snu, Spv, Snv, Spw, Snw when currents Iu, Iv, Iw flow in the phases U, V, W, respectively. ), Fnv (Iv), fpw (Iw), and fnw (Iw) are respectively the instantaneous powers fpu_t (Iu), fpv_t (Iv), fpw_t (Iw) of the transistor T, and the diode D as shown in Equation 3. Of instantaneous powers fpu_d (Iu), fpv_d (Iv), and fpw_d (Iw).

  For example, the instantaneous powers fpu_t (Iu), fpu_d (Iu), fnu_t (Iu), and fnu_d (Iu) of the transistors T and the diodes D of the U-phase switch elements Spu and Snu are respectively when Iu> 0 (ie, Iu Is supplied from the inverter circuit 14 to the three-phase load 10), and is given as shown in Equation 4, and when Iu <0 (that is, when Iu flows from the three-phase load 10 to the inverter circuit 14), as shown in Equation 5 Given to.

  Specifically, when the transistor T is an IGBT and the diode D is an FRD, a linear approximation of each of the instantaneous powers fpu_t (Iu), fpu_d (Iu), fnu_t (Iu), and fnu_d (Iu) is as shown in Equation 6. The quadratic approximation is given as in Equation 7.

  In Equation 6, Vce is a voltage between the collector and emitter of the transistor T when Iu flows, and Vf is a forward voltage of the diode D. Vce (0) in Equation 7 is the voltage between the collector and emitter of the transistor T when Iu = 0, and kce is the slope of the voltage between the collector and emitter of the transistor T when Iu flows.

  More specifically, when the transistor T is a synchronous rectification MOSFET and the diode D is an FRD, a first-order approximation of each instantaneous power fpu_t (Iu), fpu_d (Iu), fnu_t (Iu), and fnu_d (Iu) Is given as Here, FRD is approximated as an ideal diode with forward voltage Vf. Note that Ron in Equation 8 is the on-resistance of the transistor T.

  It should be noted that the instantaneous powers fpv_t (Iv), fpv_d (Iv), fnv_t (Iv), fnv_d (Iv), fpw_t (Iw), fpw_d (Iw), fnw_t (Iw), fnw_d (for each phase V, W) Iw) is given in the same manner as the instantaneous powers fpu_t (Iu), fpu_d (Iu), fnu_t (Iu), and fnu_d (Iu) in the case of the U phase, and therefore their specific description is omitted.

  Note that the above approximate expression of the instantaneous power (Expression 6 to Expression 8) is an approximate expression for a change in current. However, since the characteristics of the transistor T and the diode D change depending on the device temperature in addition to the current, the device An approximation may be made in consideration of a change in temperature.

<Power loss of each switch element over a certain period T>
The power loss Ppu, Pnu, Ppv, Pnv, Ppw, Pnw of each switch element Spu, Snu, Spv, Snv, Spw, Snw in a fixed period T is expressed by the energization period tpu, It is given by the product of tnu, tpv, tnv, tpw, tnw and instantaneous powers fpu (Iu), fnu (Iu), fpv (Iv), fnv (Iv), fpw (Iw), fnw (Iw).

<Power loss tolerance of each switch element>
The power loss tolerance P′pu, P′nu, P′pv, P′nv, P′pw, P′nw of each switch element Spu, Snu, Spv, Snv, Spw, Snw is the power of the switch element, respectively. The ratio of the loss Ppu, Pnu, Ppv, Pnv, Ppw, Pnw to the power loss tolerance of the switch element is shown. Therefore, each switch element Spu, Snu, Spv, Snv, Spw, Snw has a higher possibility of thermal destruction as its power loss tolerance is higher, and its possibility of thermal destruction as its power loss tolerance is lower. Lower.

  The power loss tolerances P′pu, P′nu, P′pv, P′nv, P′pw, and P′nw of the switch elements Spu, Snu, Spv, Snv, Spw, and Snw are respectively expressed by Equations 10a to 10f. As shown in the first equation on the right side of each, the power loss Ppu (= fpu (Iu) × tpu), Pnu (= fnu (Iu) × tnu), Ppv (= fpv (Iv) × tpv), Pnv (= fnv (Iv) × tnv), Ppw (= fpw (Iw) × tpw), Pnw (= fnw (Iw) × tnw) and correction coefficients kpu and knu that are inversely proportional to the power loss tolerance of the switch element , Kpv, knv, kpw, knw are incorporated (eg multiplied). The power loss tolerance is the maximum value of power loss at which the junction temperature of the switch element can be kept below the allowable temperature. The switch element structure (eg, IGBT or MOSFET) and material (eg, Si, SiC, or GaN) , Changes depending on chip size, cooling mechanism (for example, heat spreader or heat sink), outside air temperature, and the like.

  Here, the instantaneous power tolerances f′pu, f′nu, f′pv, f′nv, f′pw, f′nw of each switch element Spu, Snu, Spv, Snv, Spw, Snw When defined as the product of the instantaneous power fpu, fnu, fpv, fnv, fpw, fnw of the element and the correction coefficients kpu, knu, kpv, knv, kpw, knw, the first expression on the right side of each of the expressions 10a to 10f is This is the second equation on the right side.

  When the correction coefficient kpu of the switch element Spu is considered as being divided into the correction coefficient kpu_t for the transistor T of the switch element Spu and the correction coefficient kpu_d for the diode D, the instantaneous power tolerance f′pu of the switch element Spu is It is given by the sum of the product of the instantaneous power fpu_t of the transistor T of the switch element Spu and the correction coefficient kpu_t and the product of the instantaneous power fpu_d of the diode D of the switch element Spu and the correction coefficient kpu_d (that is, f′pu = fpu_t * Kpu_t + fpu_d * kpu_d). Similarly, the instantaneous power tolerances f′nu, f′pv, f′nv, f′pw, and f′nw of other switch elements Snu, Spv, Snv, Spw, and Snw are also instantaneous for the transistor T of the switch element. The product of the powers fnu_t, fpv_t, fnv_t, fpw_t, fnw_t and the correction coefficients knu_t, kpv_t, knv_t, kpw_t, knw_t, and the instantaneous powers fnu_d, fpv_d, fw_d, fw_d, fw_d, fwk It is given by the sum of the product of kpv_d, knv_d, kpw_d, and knw_d. Therefore, in this case, the second expression on the right side of each of Expressions 10a to 10f becomes the third expression on the right side.

  In this way, the correction coefficients kpu, knu, kpv, knv, kpw, knw are used as the correction coefficients kpu_t, knu_t, kpv_t, knv_t, kpw_t, knw_t and the correction coefficients kpu_d, knu_d, kp_d, kv_d, kv_d, dp When divided into knw_d, the power loss tolerance of each of the transistor T and the diode D can be considered individually.

  The power loss Ppu of the switch element Spu includes a conduction loss tpu × fpu that is generated when the switch element Spu is conductive and a switching loss Epu that is generated when the switch element Spu is switched. In the above description, only the conduction loss tpu × fpu is assumed as the power loss Ppu. The power loss tolerance relating to the switching loss Epu of the switch element Spu is obtained by replacing the conduction loss tpu × fpu with the switching loss Epu of the switch element Spu in the power loss tolerance P′pu relating to the conduction loss tpu × fpu of the switch element Spu. In addition, the conduction loss tpu × fpu_t may be replaced with the switching loss Epu_t of the transistor T of the switch element Spu, and the conduction loss tpu × fpu_d may be replaced with the switching loss Epu_d of the diode D of the switch element Spu. The power loss tolerance P′pu of the switch element Spu when both the conduction loss and the switching loss are assumed is given by Equation 11.

  The power loss tolerances P′nu, P′pv, P′nv, P′pw, P′nw of other switch elements Snu, Spv, Snv, Spw, Snw when both conduction loss and switching loss are assumed Since they are given in the same manner, their specific description is omitted.

  The correction coefficients kpu, knu, kpv, knv, kpw, and knw of each switch element Spu, Snu, Spv, Snv, Spw, and Snw are set to values that are inversely proportional to the allowable power loss of the switch element. Similarly, the correction coefficients kpu_t, knu_t, kpv_t, knv_t, kpw_t, and knw_t of the transistor T are also set to values that are inversely proportional to the allowable power loss of the transistor T, and the correction coefficients kpu_d, knu_d, kpv_d, knv_d, kpw_d and knw_d are also set to values that are inversely proportional to the allowable power loss of the diode D. The correction factors kpu, knu, kpv, knv, kpw, knw are, for example, 1 / (absolute maximum rating of power loss) or 1 / (absolute maximum rating of collector loss) or (thermal resistance between junction and case) or 1 / (Absolute maximum rating of junction temperature-maximum value of case temperature) or (Thermal resistance between junction and case) / (Absolute maximum rating of junction temperature-Maximum value of case temperature) or (Thermal resistance of cooling mechanism) May be set.

  In this way, when existing characteristic values such as the absolute maximum rating of power loss, the thermal resistance between the junction and the case, and the absolute maximum rating of the junction temperature are used as each correction factor, the correction factor can be easily set.

  Note that the correction coefficient may be varied in consideration of the arrangement of each switch element. For example, when a plurality of switching elements are arranged on a cooling mechanism (for example, a heat spreader or a heat sink), the central switching element is less likely to be cooled than the other switching elements, and the maximum case temperature due to the heat flux from the other switching elements. And apparent thermal resistance increases. Therefore, the correction coefficient of the central switch element may be set larger than the correction coefficients of the other switch elements. For example, the correction coefficient is set to be inversely proportional to the maximum case temperature of each switch element when placed on the cooling mechanism, or it is corrected to be proportional to the apparent thermal resistance considering the placement of each switch element. A coefficient may be set. Further, for example, since the cooling wind is more easily cooled (that is, the apparent thermal resistance is lower), the correction coefficient may be set smaller for the switching element on the cooling wind. As a result, it is possible to reduce power loss in the switch element that easily rises in temperature and prevent the switch element from being thermally destroyed.

  Since the energization periods tpu, tpv, tpw are decreasing functions of the period t0 from the expressions 10a to 10f, the power loss tolerances P′pu, P′pv, P′pw are also decreasing functions of the period t0. I understand that. Further, since each energization period tnu, tnv, tnw is an increasing function of the period t0, it can be seen that each power loss tolerance P'nu, P'nv, P'nw is also an increasing function of the period t0. FIG. 5 shows that each power loss tolerance P′pu, P′nu, P′pv, P′nv, P′pw, and P′nw is a function of the period t0, and 0 ≦ t0 ≦ tz (tz: This is a graph in a range of a predetermined constant (for example, tz = T−ti−tj = t0 + t7).

<Equilibrium condition for power loss tolerance of two different switch elements>
Calculation of the period t0 and the power loss tolerance P′px when the power loss tolerance P′px of the X-phase upper arm element Spx and the power loss P′ny of the Y-phase lower arm element Sny are in an equilibrium condition Then, it becomes like Formula 12. The X phase and the Y phase are one of the phases U, V, and W. The X phase and the Y phase may be different phases or the same phase.

  In addition, the period t0 and the power loss tolerance P′px when the power loss tolerance P′px of the X-phase upper arm element Spx and the power loss P′py of the Y-phase upper arm element Spy are in an equilibrium condition are expressed as follows. When calculated, Equation 13 is obtained. The X phase is one of the phases U, V, and W, and the Y phase is one of the remaining two phases.

  In addition, the period t0 and the power loss tolerance P′nx when the power loss tolerance P′nx of the lower arm element Snx of the X phase and the power loss P′ny of the lower arm element Sny of the Y phase are in an equilibrium condition are obtained. When calculated, Equation 14 is obtained. The X phase is one of the phases U, V, and W, and the Y phase is one of the remaining two phases.

<Adjustment method of ratio of each period t0, t7 of on-off pattern P1>
In the method for adjusting the ratio between the periods t0 and t7 of the on / off pattern P1, in the on / off pattern P1, each switch element is maintained in a state where the period t0 is the sum tz (= t0 + t7) of the periods t0 and t7. Spu, Snu, Spv, Snv, Spw, Snw power loss tolerance P'pu, P'nu, P'pv, P'nv, P'pw, P'nw so that the largest one is the smallest Period t0 (this t0 is called ta). In other words, the period t0 of the on / off pattern P1 is adjusted to ta that satisfies 0 ≦ ta ≦ tz. For example, in FIG. 5, the period t0 of the on / off pattern P1 is adjusted to ta at the point A. Hereinafter, a detailed description will be given based on FIG.

  First, in step S1, a phase X that gives the maximum power loss tolerance P′pu, P′pv, P′pw of all upper arm elements Spu, Spv, Spw at t0 = 0 is obtained for each phase U , V, W. In FIG. 5, since the power loss tolerance P′pu is the maximum at t0 = 0, X phase = U phase. Similarly, the phase Y that gives the maximum one of the power loss tolerances P′nu, P′nv, P′nw of all the lower arm elements Snu, Snv, Snw at t0 = tz is the respective phase U, V, It is specified from W. In FIG. 5, since the power loss tolerance P′nv is maximum at t0 = tz, Y phase = V phase.

  In step S2, the power loss tolerance P′px of the X-phase upper arm element Spx and the power loss tolerance P of the Y-phase lower arm element Sny are obtained based on Expression 12 for each phase X and Y obtained in step S1. A period t0 (this t0 is called tb) and a power loss tolerance P'px (= P'ny, this 'px is called P'b) when' ny is in an equilibrium state are obtained. In FIG. 5, the power loss tolerance P ′ and the period t0 at the point B are P′b and tb, respectively.

  In step S3, it is determined whether or not tb obtained in step S2 satisfies 0 ≦ tb ≦ tz. As a result of the determination, when tb satisfies 0 ≦ tb ≦ tz, the process proceeds to step S4. On the other hand, when tb does not satisfy 0 ≦ tb ≦ tz (that is, when tb <0 or tb> tz is satisfied). ), The process proceeds to step S7. In FIG. 5, since tb satisfies 0 ≦ tb ≦ tz, the process proceeds to step S4.

  In step S7, the smaller one of the power loss tolerance P′px of the X-phase upper arm element Spx at t0 = 0 and the power loss tolerance P′ny of the Y-phase lower arm element Sny at t0 = tz. It is determined that t0 is ta. For example, in the case of FIG. 7, it is determined that ta = tz because P′nv (= P′ny) at t0 = tz is smaller than P′pu (= P′px) at t0 = 0. Is done. Then, the period t0 of the on / off pattern P1 is adjusted to ta (= tz) (that is, the ratio of the periods t0 and t7 is t0: t7 = ta: with the sum tz of the sections t0 and t7 kept constant). adjusted to tz-ta). In this manner, the ratio between the periods t0 and t7 of the on / off pattern P1 is adjusted.

  FIG. 8 shows the power loss P′pu, P′nu, P′pv, P′nv, P ′ of each upper arm element Spu, Spv, Spw and each lower arm element at t0 = 0 and t0 = tz. It is a list of pw and P'nw.

  On the other hand, in step S4, all power loss tolerances P′pu, P′nu, P′pv, P′nv, P′pw, P′nw at t0 = tb are calculated, and the maximum of them is calculated. A thing (this is called P'm) is specified. In FIG. 5, P′nw at t0 = tb is P′m. Then, the process proceeds to step S5.

  In step S5, it is determined whether P′m = P′b is satisfied with respect to P′b obtained in step S2 and P′m specified in step S4. If P′m = P′b is satisfied as a result of the determination, in step S8, tb obtained in step S2 is determined to be ta, and the period t0 of the on / off pattern P1 is adjusted to ta ( That is, the ratio of the periods t0 and t7 is adjusted to t0: t7 = ta: tz−ta while the sum tz of the sections t0 and t7 is kept constant. In this manner, the ratio between the periods t0 and t7 of the on / off pattern P1 is adjusted. On the other hand, if P′m = P′b does not hold as a result of the determination, it is determined that tb is not ta, and the process proceeds to step S6. In FIG. 5, since P′m = P′b is not established, the process proceeds to step S6.

  In step S6, P′m specified in step S4 is one of the power loss tolerances P′pu, P′pv, P′pw of each upper arm element Spu, Spv, Spw, or each lower arm. It is determined whether any of the power loss tolerances P′nu, P′nv, P′nw of the elements Snu, Snv, Snw. As a result of the determination, if P′m is one of the voltage loss tolerances P′pu, P′pv, P′pw of each upper arm element Spu, Spv, Spw, the phase corresponding to P′m Set to X phase. On the other hand, when P′m is one of the power loss tolerances P′nu, P′nv, P′nw of each lower arm element Snu, Snv, Snw, the phase corresponding to P′m is the Y phase. Is set. In FIG. 5, since P′m is the power loss tolerance P′nv of the lower arm element Snv, the V phase corresponding to P′m is set to the Y phase. Then, the process returns to step S2. In this manner, the ratio between the periods t0 and t7 of the on / off pattern P1 is adjusted.

  The on / off pattern P1 is an on / off pattern for three-phase modulation of the three-phase load 10 when 0 <ta <tz, and an on / off pattern for two-phase modulation of the three-phase load 10 when ta = 0 or tz. Become.

  In addition, the control circuit 16 generates the on / off pattern P1 and adjusts the ratio of each period t0 and t7 for every fixed period T by performing the process of steps S1-S8 for every fixed period T. Thereby, the ratio of each period t0, t7 is updated for every fixed period T.

  Based on the on / off pattern P1 adjusted by the zero voltage vector adjustment unit 16g, the control signal generation unit 16h generates a control signal for controlling the on / off operation of each switch element Spu, Snu, Spv, Snv, Spw, Snw, The voltage is applied to the control electrode G of each switch element. As a result, the switch elements are turned on / off according to the on / off pattern P1, and as a result, the power loss tolerances P′pu, P′nu, P′pv, P′nv, P′pw, P of the respective switch elements. The three-phase load 10 is rotationally driven at the rotational speed ω so that the largest one of 'nw becomes the smallest.

  In this inverter device 1, the device structure is different (that is, the power loss is different) according to the type of each device constituting each switch element Spu, Snu, Spv, Snv, Spw, Snw, but the power loss allowable amount is the same 2 When the types of devices DV1 and DV2 are mixed, by adjusting the ratio between the periods t0 and t7 of the on / off pattern P1 by the zero voltage vector adjustment unit 16g, the smaller of the two types of devices DV1 and DV2 Is adjusted so that the ON period of the device becomes longer (that is, the heat generation amount (= device temperature) of the devices DV1 and DV2 is balanced). For example, when the devices DV1 and DV2 have the characteristics of voltage V-current I as shown in FIG. 10, in the range Q1 where the current I is smaller than the current Ic at the point C, the device DV1 is more than the device DV2. Since the power loss is reduced, the device DV1 is adjusted to have a longer on-period. On the other hand, in the range Q2 where the current I is larger than the current Ic, the device DV2 has a power loss smaller than that of the device DV1, so that the ON period of the device DV2 is adjusted to be longer. The point C is an equilibrium point of the characteristics of the devices DV1 and DV2.

  In addition, there are two types of devices DV1 and DV2 that have the same power loss but different device materials (that is, different allowable temperatures) for each type of device constituting each switch element Spu, Snu, Spv, Snv, Spw, Snw. In the case of coexistence, by adjusting the ratio of the periods t0 and t7 of the on / off pattern P1 by the zero voltage vector adjustment unit 16g, the on period with the larger allowable temperature of the two types of devices DV1 and DV2 becomes longer. Adjusted to For example, when the device material of the device DV1 is Si and the device material of the device DV2 is SiC, since SiC has a higher allowable temperature, the ON period of the device DV2 is adjusted to be longer.

  In addition, when two types of devices DV1 and DV2 having different temperature characteristics are mixed in the types of devices constituting each switch element Spu, Snu, Spv, Snv, Spw, Snw, an on / off pattern by the zero voltage vector adjustment unit 16g By adjusting the ratio of the periods t0 and t7 of P1, the ON period with the smaller power loss of the two types of devices DV3 and DV4 is adjusted to be longer according to the temperature at the time of adjustment. In this case, the instantaneous powers fpu_t (Iu), fpu_d (Iu), fnu_t (Iu), fnu_d (Iu), fpv_t (Iv), fpv_d (Iv) of each switch element Spu, Snu, Spv, Snv, Spw, Snw. ), Fnv_t (Iv), fnv_d (Iv), fpw_t (Iw), fpw_d (Iw), fnw_t (Iw), and fnw_d (Iw) need to be calculated in consideration of the device temperature of the switch element. For example, as shown in FIG. 11, when the devices DV3 and DV4 have the characteristics of device temperature K-on resistance Ron, in the range Q3 where the temperature K is lower than the temperature Kd at the point D, the device DV4 is more than the device DV3. Since the on-resistance Ron is small (that is, the power loss is small), the on-period of the device DV4 is adjusted to be long. On the other hand, in the range Q4 where the temperature K is higher than the temperature Kd, since the device DV3 has a smaller on-resistance R than the device DV4 (that is, the power loss is small), the on-period of the device DV3 is adjusted to be longer. The point D is an equilibrium point of the characteristics of the devices DV1 and DV2.

  According to the inverter device 1 configured as described above, power loss in a switch element having a large power loss tolerance can be reduced, and the switch element can be prevented from being thermally destroyed. Thereby, thermal destruction of each switch element can be prevented without increasing the power loss tolerance of each switch element.

  Further, in a certain period T, the power loss tolerances P′pu, P′pv, P′pw, P′nu, P of each switching element Spu, Snu, Spv, Snv, Spw, Snw of each phase U, V, W The ratio of the periods t0 and t7 is adjusted while keeping the sum tz of the periods t0 and t7 constant so that the largest one of 'nv and P'nw becomes the smallest. The thermal destruction of each switch element can be prevented without giving

  Further, since the above-described method for adjusting the ratio of the periods t0 and t7 of the on / off pattern P1 is used, the switching elements Spu, Snu, Spv, Snv, Spw, The ratio of each period t0, t7 is calculated so that the maximum one of Snw power loss tolerances P′pu, P′nu, P′pv, P′nv, P′pw, P′nw is minimized. I can do things.

  When the ratio of the periods t0 and t7 of the on / off pattern P1 is adjusted in the flow of steps S1, S2, S3, and S7, when tb does not satisfy 0 ≦ tb ≦ tz (that is, tb <0 or tb> In the case of satisfying tz), the power loss tolerances P′pu, P′nu, P′pv of the switching elements Spu, Snu, Spv, Snv, Spw, Snw of the respective phases U, V, W are obtained by a simple method. , P′nv, P′pw, P′nw, the ratio between the periods t0 and t7 can be obtained so that the largest one becomes the smallest.

  If P′m = P′b in step S5, the X phase or the Y phase is changed in step S6, so that the switching elements Spu, Snu, Spv, Snv, Spw, It is possible to appropriately specify the maximum one of the Snw power loss tolerances P′pu, P′nu, P′pv, P′nv, P′pw, and P′nw.

Second Embodiment
This embodiment is a modification of the method for adjusting the ratio between the periods t0 and t7 of the on / off pattern P1 of the first embodiment. As shown in FIG. 9, the inverter circuit 1B according to this embodiment further includes current detection sensors 17u, 17v, and 17w that detect currents Iu, Iv, and Iw flowing through the phases U, V, and W in the first embodiment. It is provided. In addition, the same code | symbol is attached | subjected to the same component as 1st Embodiment among each component of this embodiment, and the description is abbreviate | omitted.

  The zero voltage vector adjustment unit 16gB of this embodiment adjusts the ratio of the periods t0 and t7 of the on / off pattern P1 according to FIG.

  In step U1, for example, at the start of a fixed period T, the zero voltage vector adjustment unit 16gB applies each of the phases U, V, and W to each phase based on the detection results of the current detection sensors 17u, 17v, and 17w. The phase in which the maximum current absolute value among the flowing currents Iu, Iv, and Iw flows (referred to as X phase) is specified.

  In step U2, the zero voltage vector adjuster 16gB causes the power loss tolerances P′px and P′nx of the identified upper-phase element Spx and lower-arm element Snx of the specified X phase to be in an equilibrium state. A period t0 (this t0 is called tb) is obtained.

  In step U3, the zero voltage vector adjustment unit 16gB determines whether or not the obtained tb satisfies 0 ≦ tb ≦ tz. If tb satisfies 0 ≦ tb ≦ tz as a result of the determination, in step U4, tb is set to ta (ie, power of each switch element Spu, Snu, Spv, Snv, Spw, Snw) by the zero voltage vector adjustment unit 16gB. It is determined that the loss tolerance P′pu, P′nu, P′pv, P′nv, P′pw, P′nw is a period t0) in which the maximum one is the smallest. Then, the period t0 of the on / off pattern P1 is adjusted to the ta by the zero voltage vector adjustment unit 16gB (that is, the ratio of the periods t0 and t7 is t0 while the sum tz of the sections t0 and t7 is kept constant). : T7 = ta: adjusted to tz-ta).

  On the other hand, if tb does not satisfy 0 ≦ tb ≦ tz as a result of the determination in step U3 (that is, if tb <0 or tb> tz is satisfied), in step U5, the zero voltage vector adjustment unit 16gB causes t0 = The smaller t0 of P'px at 0 and P'nx at t0 = tz is determined to be ta. Then, the period t0 of the on / off pattern P1 is adjusted to ta by the zero voltage vector adjustment unit 16gB.

  According to the inverter device 1B configured as described above, since only the phase X in which the maximum current absolute value among the currents flowing in the phases U, V, and W flows is focused, the case of the first embodiment As compared with the above, the power loss tolerances P′pu, P′nu, P′pv, P of the switching elements Spu, Snu, Spv, Snv, Spw, Snw of the respective phases U, V, W are obtained by a method having a small calculation amount. The ratio of each period t0, t7 can be obtained so that the maximum of 'nv, P'pw, P'nw becomes smaller.

  When the ratio between the periods t0 and t7 of the on / off pattern P1 is adjusted in the flow of steps U1 → U2 → U3 → U5, tb does not satisfy 0 ≦ tb ≦ tz (that is, tb <0 or tb> tz). In a case where the power loss tolerance P′pu, P′nu, P ′ of the switching elements Spu, Snu, Spv, Snv, Spw, Snw of each phase U, V, W The ratio between the periods t0 and t7 can be obtained so that the maximum of pv, P′nv, P′pw, and P′nw becomes smaller.

DESCRIPTION OF SYMBOLS 1,1B Inverter apparatus 10 Three-phase load 11u, 11v, 11w Electrode of each phase U, V, W 12 DC power supply 12a AC power supply 12b Smoothing circuit 14 Inverter circuit 16 Control circuit 17u, 17v, 17w Current detection sensor Hu, Hv, Hw Position detection sensor Iu, Iv, Iw Current flowing in each phase U, V, W
I * Current command value P1 ON / OFF pattern P'pu, P'nu, P'pv, P'nv, P'pw, P'nw Power loss tolerance Spu, Snu, Spv, Snv, Spw, Snw Switch element t0 t7, ti, tj Implementation period of V0 to V7, Vi, Vj U, V, W Each phase of 3-phase load Vu *, Vv *, Vw * Voltage command value V * Voltage command vector V0 to V7 Voltage vector ω Rotational speed ω * rotational speed command value

Claims (11)

An inverter device for driving and controlling a load (10),
An inverter circuit (14) having a plurality of switch elements (Spu, Snu, Spv, Snv, Spw, Snw) for converting electric power of a predetermined DC power source (12) into electric power of a predetermined output system and supplying the electric power to the load; ,
A control circuit (16) for driving and controlling the load by controlling on / off of the plurality of switch elements;
With
The power loss (Ppu, Ppv, Ppw, Pnu, Pnv, Pnw) in each switching element (T), and the correction coefficient (kpu, kpv, kpw, knu, inversely proportional to the power loss tolerance of the switching element) knv, knw) is a power loss tolerance (P′pu, P′pv, P′pw, P′nu, P′nv, P′nw),
The inverter characterized in that the control circuit (16) performs on / off control of each switch element so that a maximum one of the power loss tolerances of the switch elements becomes the smallest in the fixed period. apparatus. The inverter device according to claim 1,
The inverter circuit (14) includes two switch elements (Spu, Snu; Spv) connected in series to the predetermined DC power source (12) for each phase (U, V, W) of the load. , Snv; Spw, Snw), and a voltage between the switch elements for each phase is applied to each phase,
Of the two switch elements, an element connected to the anode side of the predetermined DC power source (Spu, Spv, Spw) is used as an upper arm element, and an element connected to the cathode side of the predetermined DC power source (Snu) , Snv, Snw) as the lower arm element,
The control circuit (16) includes all the lower arm elements of the respective phases so that the maximum one of the power loss tolerances of the respective switch elements of the respective phases becomes the smallest in the certain period. The first period (t0) in which only the first arm is turned on and the second period (t7) in which only all the upper arm elements of each phase are turned on are kept constant (tz) An inverter device, wherein a ratio with the second period is adjusted. The inverter device according to claim 1 or 2,
Each of the switch elements includes a transistor (T) and a diode (D) connected in a reverse direction between the main electrodes of the transistor,
The correction coefficients (kpu, kpv, kpw, knu, knv, knw) are a first correction coefficient (kpu_t, kpv_t, kpw_t, knu_t, knv_t, knw_t) for the transistor and a second correction coefficient (kpu_d, kpv_d) for the diode. , Kpw_d, knu_d, knv_d, knw_d),
The first correction coefficient is multiplied by the power loss (Ppu_t, Ppv_t, Ppw_t, Pnu_t, Pnv_t, Pnw_t) of the transistor,
The inverter device, wherein the second correction coefficient is multiplied by a power loss (Ppu_d, Ppv_d, Ppw_d, Pnu_d, Pnv_d, Pnw_d) of the diode. The inverter device according to claim 1 or 2,
The inverter device, wherein the correction coefficient is a reciprocal of an absolute maximum rating of power loss of the switch element. The inverter device according to claim 3,
The first correction factor is the reciprocal of the absolute maximum rating of the power loss of the transistor,
The inverter device, wherein the second correction coefficient is a reciprocal of an absolute maximum rating of power loss of the diode. An inverter device according to any one of claims 2 to 5,
The control circuit (16)
(A) Of the power loss tolerances (P′pu, P′pv, P′pw) of all the upper arm elements (Spu, Spv, Spw) when the first period (t0) is zero A first phase (X) that gives the largest of all of the phases (U, V, W), and the first period (t0) is equal to the sum (tz) A second phase (Y) that gives the maximum one of the power loss tolerances (P′nu, P′nv, P′nw) of the lower arm elements (Snu, Snv, Snw) Identify from the inside (S1),
(B) The power loss tolerance (P′px) of the upper arm element (Spx) of the first phase (X) and the power of the lower arm element (Sny) of the second phase (Y) Obtaining the first period (tb) and the power loss tolerance (P′b) when the loss tolerance (P′ny) is in an equilibrium state (S2);
(C) The power of all the switch elements (Spu, Snu, Spv, Snv, Spw, Snw) when the first period (t0) is equal to the first period (tb) when the equilibrium state is established The maximum power loss tolerance (P′m) is identified from the loss tolerance (P′pu, P′nu, P′pv, P′nv, P′pw, P′nw) (S3),
(D) When the power loss tolerance (P′b) in the equilibrium state is equal to the maximum power loss tolerance (P′m) (S5), the first in the equilibrium state When the period (tb) is greater than or equal to zero and less than or equal to the sum (tz) (S3), the ratio between the first period (t0) and the second period (t7) is equal to the ratio in the equilibrium state. The inverter device is adjusted to the ratio obtained from the first period (tb) (S8). The inverter device according to claim 6,
The control circuit (16)
(E) When the first period (tb) in the equilibrium state is smaller than zero or larger than the sum, the ratio between the first period (t0) and the second period (t7) The power loss tolerance (P′px) of the upper arm element (Spx) of the first phase (X) when the first period (t0) is zero, and the first period (t0) Is obtained from the smaller first time period of the power loss tolerance (P′ny) of the lower arm element (Sny) of the second phase (Y) in the case where is equal to the sum (tz). The inverter device is adjusted to the ratio (S7). The inverter device according to claim 6,
The control circuit (16)
(F) In the case where the power loss tolerance (P′b) in the equilibrium state and the maximum power loss tolerance (P′m) are not equal, the maximum power loss tolerance (P′m) ) Is the power loss tolerance (P′pu, P′pv, P′pw) of any one of the upper arm elements (Spu, Spv, Spw), it corresponds to the maximum power loss tolerance. The phase to be set is set to the first phase (X), and the processing after (a) is performed. On the other hand, the maximum power loss tolerance (P′m) is set to each of the lower arm elements (Snu, Snv). , Snw) if the power loss tolerance (P′nu, P′nv, P′nw) is selected, the phase corresponding to the maximum power loss tolerance is the second phase (Y). The inverter apparatus is characterized in that the processing after (b) is performed (S6). An inverter device according to any one of claims 2 to 5,
A current detection sensor (17u, 17v, 17w) for detecting each current (Iu, Iv, Iw) flowing in each phase (U, V, W);
The control circuit (16)
(A) Based on the detection result of each current detection sensor, the first phase (X) in which the maximum current absolute value among the currents flowing in each phase flows is identified from among the phases. (U1),
(B) When the power loss tolerance (P′px, P′nx) of each of the upper arm element (Spx) and the lower arm element (Snx) of the first phase (X) is in an equilibrium state The first time (tb) of
(C) When the first time (tb) in the equilibrium state is not less than zero and not more than the sum (tz), the ratio between the first period (t0) and the second period (t7) Is adjusted to the ratio obtained from the first time (tb) in the equilibrium state (U4). The inverter device according to claim 9,
(D) When the first time (tb) in the equilibrium state is smaller than zero or larger than the sum (tz), the first period (t0), the second period (t7), The power loss tolerance (P′px) of the upper arm element (Spx) of the first phase (X) when the first period (t0) is zero, and the first period The ratio obtained from the first period of the smaller one of the power loss tolerance (P′nx) of the lower arm element (Snx) of the first phase when (t0) is equal to the sum. An inverter device characterized by adjusting (U5). The inverter device according to any one of claims 2 to 10,
The control circuit includes:
An inverter device, wherein a ratio between the first period (t0) and the second period (t7) is adjusted every fixed period (T).

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