JP2011044847A - Multilayer circuit, and package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform impedance matching and to achieve high functions of high output and broadband etc., with a small area. <P>SOLUTION: The multilayer circuit has: at least three conductor layers each including at least one of a signal line layer 26, a circuit element layer 24 and a ground conductor layer 22; and insulator layers 32 and 34 between the conductor layers. A signal line formed in the signal line layer performs impedance matching at one end of the signal line and the other end. In order to perform the impedance matching, a microstrip line or a coplanar line is used as the signal line. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a multilayer circuit built in a package for a semiconductor device, and a package configured integrally with the multilayer circuit.

  In general, in a system that handles a high-frequency signal such as a wireless communication system, the characteristic impedance of the input / output terminal is designed to be 50Ω. The signal power in the wireless communication system is amplified by a power amplifier. In particular, the final-stage amplifier on the transmission side is configured to output a large amount of power by connecting a large number of semiconductor devices in parallel.

  A semiconductor device that can be connected in parallel and output a large amount of power has a low characteristic impedance, resulting in a mismatch with the characteristic impedance of the transmission line. As a result, power reflection occurs at the input / output terminals of the semiconductor device.

  In order to prevent this power reflection, a circuit (impedance matching circuit) for impedance matching has been built in a package including a high-frequency, high-power semiconductor device (see, for example, Patent Document 1).

  On the other hand, due to diversification of wireless communication, wireless communication systems, particularly power amplifiers therein, are required to have higher output, higher efficiency, lower distortion, wider bandwidth, and smaller size. To meet these demands, a single semiconductor substrate, active elements such as transistors, passive elements such as resistors, coils, capacitors, signal lines such as microstrip lines (MSL) and coplanar lines (CPW), and these A monolithic microwave integrated circuit (MMIC) may be used in which several functional blocks are combined to form one semiconductor device (see, for example, Patent Document 2 or 3).

JP-A-6-6151 JP-A-8-148505 JP-A-9-36611

  However, in some cases, a passive element, a stub, or the like is necessary to realize an even higher function by using an impedance matching circuit between the transmission line and the semiconductor device. When these elements are provided in the impedance matching circuit, the area of the impedance matching circuit is increased. This makes it difficult to incorporate the impedance matching circuit into the package.

  In addition, in the MMIC, it is possible to give the semiconductor device some functions. However, if the MMIC is required to increase the output, the width of the signal line needs to be increased. For this reason, the area of a semiconductor substrate becomes large, and in the case of expensive substrates, such as SiC used by GaN-HEMT, it becomes disadvantageous in terms of cost. In addition, the yield may be reduced due to the addition of a signal line. Therefore, it is difficult to increase the output of several tens to several hundreds W level with the MMIC.

  The present invention has been made in view of the above-described problems, and an object of the present invention is for a semiconductor device that enables impedance matching and further realizes high functionality such as high output in a small area. An object of the present invention is to provide a multilayer circuit incorporated in the package and a package integrally formed with the multilayer circuit.

  In order to achieve the above-described object, a multilayer circuit of the present invention includes three or more conductor layers including at least one signal line layer, a circuit element layer, and a ground conductor layer, and an insulator layer between the conductor layers. With.

  In the implementation of the multilayer circuit of the present invention, the signal line formed in the signal line layer is preferably subjected to impedance matching at one end and the other end of the signal line.

  According to a preferred embodiment of the multilayer circuit of the present invention, a signal line layer and a ground conductor layer are provided at a position sandwiching one insulator layer, a signal line, a ground electrode provided on the ground conductor layer, Thus, a microstrip line is formed.

  At this time, the thickness of the insulator layer provided between the signal line layer and the ground conductor layer may be configured to change from one end of the signal line toward the other end.

  According to another preferred embodiment of the multilayer circuit of the present invention, a coplanar line is formed in the signal line layer.

  According to another preferred embodiment of the multilayer circuit of the present invention, the dielectric constant of the insulator layer varies from layer to layer.

  The package of the present invention is a package for a semiconductor device that integrally includes a circuit for matching impedances at one end and the other end of a signal line of a high-frequency signal propagating through the signal line, and as a circuit for matching this impedance, The multilayer circuit described above is provided.

  The multilayer circuit of the present invention includes three or more conductor layers including at least one signal line layer, circuit element layer, and ground conductor layer. In this circuit element layer, for example, a passive circuit such as an inductance can be formed, so that the impedance matching circuit can be widened.

  In addition, since the circuit element layer is formed in a layer different from the signal line layer, even if an element having a relatively large occupied area such as a spiral inductor is formed, the multilayer circuit can be reduced in area.

  Forming the impedance matching circuit with a microstrip line is advantageous in that modeling is easy and simulation is easy. At this time, if the thickness of the insulator layer is changed from the input side to the output side, the thickness of the insulation layer also becomes a design parameter of the impedance matching circuit. For this reason, the freedom degree of design can be raised.

  On the other hand, when the impedance matching circuit is formed of a coplanar line, the degree of freedom in design such as the stacking order of the signal line layer, the circuit element layer, and the ground conductor layer increases.

  Further, when the multilayer circuit is formed integrally with the package for the semiconductor device, alignment between the impedance matching circuit and the package becomes unnecessary. Further, the bonding of the package lead and the impedance matching circuit becomes unnecessary.

It is the schematic (1) for demonstrating the structure of a multilayer circuit. It is a top view of the package for semiconductor devices in which the multilayer circuit was incorporated. It is the schematic (2) for demonstrating the structure of a multilayer circuit. It is the schematic for demonstrating the design of a microstrip line. It is the schematic (3) for demonstrating the structure of a multilayer circuit. It is a schematic diagram for demonstrating the manufacturing method of a multilayer circuit. It is a schematic diagram of the package for semiconductor devices.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the shape, size, and arrangement relationship of each component are merely schematically shown to the extent that the present invention can be understood. In the following, a preferred configuration example of the present invention will be described. However, the material and numerical conditions of each component are merely preferred examples. Therefore, the present invention is not limited to the following embodiments, and many changes or modifications that can achieve the effects of the present invention can be made without departing from the scope of the configuration of the present invention. In each of the drawings, there is a case where hatching is given to a plan view or a three-dimensional view in order to emphasize a required region.

(Multilayer circuit of the first embodiment)
With reference to FIG. 1 and FIG. 2, the multilayer circuit built in the package for a semiconductor device of the first embodiment will be described. FIG. 1 is a schematic diagram for explaining the structure of the multilayer circuit according to the first embodiment, and is shown by a cross-section. FIG. 2 is a plan view of a package for a semiconductor device incorporating a multilayer circuit.

  The semiconductor device 90 mounted on the semiconductor device package 100 is electrically connected to a transmission line (not shown). The characteristic impedance of the input / output terminals of the package is generally designed to be 50Ω. Here, for the lines through which signals propagate, the lines provided in the multilayer circuit in the package are referred to as signal lines, and the lines outside the package are referred to as transmission lines.

  On the other hand, a large output power may be required in a wireless communication system. In order to increase output power, a plurality of semiconductor devices 90 are provided in parallel. When the semiconductor devices 90 are connected in parallel, the impedance of the input / output terminals of the semiconductor device 90 is lowered, and mismatching with the characteristic impedance of the transmission line occurs. Therefore, a circuit (impedance matching circuit) for impedance matching is provided between the transmission line and the semiconductor device 90. This impedance matching circuit is mounted on the package 100 as with the semiconductor device 90. In FIG. 2, a frame 120 and a bottom surface 121 are shown as the package 100.

  The impedance matching circuit is configured as a multilayer circuit 10 including three or more conductor layers and an insulator layer between the conductor layers. The multilayer circuit 10 includes at least one signal line layer 26, circuit element layer 24, and ground conductor layer 22 as conductor layers. Here, a configuration example in which the multilayer circuit 10 includes the ground conductor layer 22, the circuit element layer 24, and the signal line layer 26 in order from the bottom as three conductor layers will be described. However, the number of conductor layers is described. Is not limited to 3. It is sufficient that at least three conductor layers are provided, and four or more conductor layers may be provided. In the following description, the two insulator layers are referred to as a first insulator layer 32 and a second insulator layer 34 in order from the bottom.

  The first insulator layer 32 and the second insulator layer 34 can be, for example, ceramic substrates.

  The ground conductor layer 22, the circuit element layer 24, and the signal line layer 26 can be any suitable metal film. Note that the metal film may be patterned into a desired shape. This metal film is formed by, for example, gold plating or gold vapor deposition. The patterning of the metal film can be performed by a conventionally known lift-off method.

  A ground (GND) electrode is formed on the ground conductor layer 22 which is the lowermost conductor layer. For this reason, when the package on which the multilayer circuit 10 is mounted is formed of a conductive casing, the multilayer circuit 10 is mounted on the package, so that the ground potential of the multilayer circuit 10 and the package or the package are mounted. The ground potential of the semiconductor device 90 can be easily set to the same potential.

  A signal line is formed in the signal line layer 26 which is the uppermost conductive layer. The signal line performs impedance matching between one end and the other end of the signal line, and power distribution / combination.

  The signal line is formed by a coplanar line, for example. The coplanar line includes a signal line that propagates a signal between the transmission line and the semiconductor device 90, and a pair of ground lines on both sides of the signal line. The signal line and the semiconductor device 90 and the signal line and the lead 110 of the package 100 are connected by, for example, bonding wires 92. Further, the pair of ground lines formed in the signal line layer 26 is electrically connected to the GND electrode of the ground conductor layer 22 through the through electrode 44 provided in the through hole 42.

  A circuit for realizing a desired function in the multilayer circuit 10 is formed in the circuit element layer 24 which is an intermediate conductor layer. For example, there is a case where an inductance component for adjusting the characteristic impedance of the semiconductor device is required for a package including a semiconductor device used for high output applications in order to realize a wide band and a low distortion. In this case, a spiral inductor is formed in the circuit element layer 24.

  According to the configuration described above, a circuit element corresponding to a desired function such as inductance can be formed in the circuit element layer 24, for example. For this reason, it is possible to increase the bandwidth of the multilayer circuit 10 used as the impedance matching circuit. The circuit element layer 24 is formed in a layer different from the signal line layer 26. For this reason, even if an element having a relatively large occupation area, such as a spiral inductor, is formed, the area of the multilayer circuit 10 does not increase, and the area can be reduced.

(Multilayer Circuit of Second Embodiment)
With reference to FIG. 3, the multilayer circuit built in the package for semiconductor devices of 2nd Embodiment is demonstrated. FIG. 3 is a schematic view for explaining the structure of the multilayer circuit 12 according to the second embodiment, and is shown by a cross-section.

  The multilayer circuit 10 of the first embodiment uses a coplanar line as an impedance matching circuit. On the other hand, the multilayer circuit 12 of the second embodiment uses a microstrip line as an impedance matching circuit.

  In the configuration example shown in FIG. 3, the three conductor layers are a ground conductor layer 52, a signal line layer 56, and a circuit element layer 54 in order from the bottom. The two insulator layers are a first insulator layer 62 and a second insulator layer 64 in order from the bottom.

  The first insulator layer 62 and the second insulator layer 64 can be, for example, ceramic substrates. When the dielectric constants of the first insulator layer 62 and the second insulator layer 64 are high, the length of the signal line formed on the signal line layer 56 is several mm with respect to the design value, and in some cases, several μm. Even when the unit changes, the phase of the transmitted high-frequency signal changes greatly. For this reason, higher accuracy is required as simulation accuracy and manufacturing accuracy, which may be difficult to implement. Therefore, the dielectric constant of the insulator layers 62 and 64 is preferably 200 at the maximum. The lower limit of the dielectric constant is not particularly limited, and the insulator layers 62 and 64 may be close to 1 which is a vacuum dielectric constant.

  In this configuration, the signal line layer 56 and the ground conductor layer 52 are provided at positions sandwiching the first insulator layer 62. The microstrip line is formed by a signal line formed on the signal line layer 56 and a GND electrode formed on the ground conductor layer 52.

  In addition, since the connection between the signal line and the semiconductor device is performed by, for example, wire bonding, the area of the second insulator layer 64 and the circuit element layer 54 on the signal line layer 56 is larger than the area of the signal line layer 56. The part of the signal line is exposed for bonding.

  The GND electrode formed in the circuit element layer 54 is electrically connected to the GND electrode of the ground conductor layer 52 through the through electrode 74 provided in the through hole 72.

In this embodiment, the impedance matching circuit is formed by a microstrip line. In the coplanar line, since it is not necessary to provide a signal line layer and a ground conductor layer at a position sandwiching one insulator layer, the degree of freedom in design increases. On the other hand, in the microstrip line, the signal line layer and the ground conductor layer must be provided at the position where one insulator layer is sandwiched. Is easy and easy to simulate.

  The design of the microstrip line will be described with reference to FIG. FIG. 4 is a schematic diagram for explaining the design of the microstrip line.

  In the microstrip line, it is experimentally known that the following relationship holds among the dielectric constant εr of the insulator layer 62, the width W of the signal line 56, and the thickness h of the insulator layer 62.

Accordingly, as the value of the desired characteristic impedance Z ₀ is obtained, it may be determined parameters described above. In the above equation (1) to (4), have been retracted to a constant, as a parameter for determining the characteristic impedance Z _0, the dielectric constant εr of the insulating layer 62, the width W and the insulation of the signal line In addition to the thickness h of the body layer 62, there are a frequency f of the high-frequency signal and a thickness t of the signal line 56.

  Thus, the thickness of the insulator layer 62 becomes a design parameter of the impedance matching circuit. For this reason, the freedom degree of design can be raised.

(Multilayer Circuit of Third Embodiment)
With reference to FIG. 5, the multilayer circuit 14 built in the package for semiconductor devices of 3rd Embodiment is demonstrated. FIG. 5 is a schematic diagram for explaining the structure of the multilayer circuit 14 according to the third embodiment, and is shown by a cross-section.

  The multilayer circuit 14 according to the third embodiment is characterized in that the thickness of the first insulator layer 63 between the signal line layer 56 and the ground conductor layer 52 changes stepwise from the input side to the output side. It is different from the embodiment. Other configurations are the same as those of the second embodiment, and thus redundant description is omitted.

For example, when the frequency f of the high frequency signal is 2 GHz, the dielectric constant εr of the insulator layer is 10, the thickness t of the signal line is 4 μm, and the width W of the signal line is 2 mm, the above equations (1) to (4) are obtained. When the simulation used is performed, when the thickness h of the first insulator layer 63 is 2.5 mm, the characteristic impedance Z ₀ is 54.1Ω. The thickness h of the first insulator layer 63 when 2.0 mm, the characteristic impedance _{Z 0} becomes 48.7Omu.

  Thus, by changing the thickness of the first insulator layer 63, the characteristic impedance can be changed even when the width W of the signal line is the same.

  Although FIG. 5 shows an example in which the thickness change point is one, the present invention is not limited to this example. Two or more change points of thickness may be provided. When a plurality of thickness change points are received, the amount of change in characteristic impedance at each change point can be reduced, so that conversion loss can be reduced.

(Multilayer Circuit of Fourth Embodiment)
In each of the above-described embodiments, the mutual relationship of the dielectric constant εr of each insulator layer is not specified. The first insulator layer and the second insulator layer may be formed of the same material (composition) and have the same dielectric constant.

  On the other hand, in 4th Embodiment, each insulator layer is formed with a different material, and it is set as the structure from which a dielectric constant differs for every layer.

  For example, when a microstrip line is used as the impedance matching circuit, when the frequency f of the high frequency signal is 2 GHz, the thickness h of the insulator layer is 200 μm, and the thickness t of the signal line is 4 μm, the above formulas (1) to ( A simulation using 4) is performed.

Here, if the dielectric constant εr is 40, the characteristic impedance Z ₀ is 33.6Ω when the width W of the signal line is 100 μm. When the dielectric constant εr is 80, the characteristic impedance Z ₀ is 33.7Ω when the width W of the signal line is 35 μm.

  Thus, by changing the dielectric constant of the insulator layer, the same characteristic impedance can be obtained even with different line widths. For this reason, when a large current capacity is required for a signal line, such as for high-power applications, the width of the signal line can be increased simply by forming the insulator layer between the signal line layer and the ground conductor layer with a low dielectric constant substrate. can do. As a result, the current capacity of the signal line can be increased without affecting the functions of the circuit elements formed in the circuit element layer. That is, the degree of freedom in design is improved.

(Multilayer circuit manufacturing method)
With reference to FIG. 6, the manufacturing method of a multilayer circuit is demonstrated. FIG. 6 is a schematic diagram for explaining a method of manufacturing a multilayer circuit. First, the green sheet 61 is prepared. Here, “green sheet” refers to a sheet-like material before the ceramic is fired. That is, by firing the green sheet 61, a ceramic layer as an insulator layer is obtained (FIG. 6A).

  Next, a through hole 82 is formed in the green sheet 61. The through hole 82 may be formed by any suitable conventionally known method, such as laser processing or via punch processing (FIG. 6B).

  Next, a signal line layer 56 including a signal line is formed on one surface of the green sheet 61. The signal line layer 56 may be formed by any suitable conventionally known method, for example, by screen printing. Here, an example is shown in which the impedance matching circuit is configured by a microstrip line and has a function of performing power combining or power distribution. When a microstrip line is used, a ground conductor layer 52 is formed on the opposite side of the signal line insulator layer. The ground conductor layer 52 is formed by, for example, gold plating (FIG. 6C).

  In this step, the through hole may be filled with metal.

  Next, a green sheet is laminated on the signal line layer 56, and through holes 83 and 84 are formed. Thereafter, the green sheet is fired to obtain the first insulator layer 62 and the second insulator layer 64 (FIG. 6D).

  Next, the circuit element layer 54 is formed on the second insulator layer 64. The circuit element layer 54 is formed by using, for example, a lift-off method. Specifically, first, a resist pattern is formed on the second insulator layer 64 by using a conventionally known photolithography method. Next, gold plating or gold vapor deposition is performed, and then the resist pattern is peeled off. As a result, a desired circuit pattern such as a stub 54a and a GND wiring 54b is formed on the second insulator layer 64 (FIG. 6E).

  In this step, the through holes 83 and 84 are filled with metal to form the through electrodes 73 and 74. In this configuration, the stub 54 a provided in the circuit element layer 54 is electrically connected to the signal line formed in the signal line layer 56 through the through electrode 73. Further, the GND wiring 54 b provided in the circuit element layer 54 is electrically connected to the GND electrode of the ground conductor layer 52 through the through electrode 74.

  Here, an example of manufacturing the multilayer circuit of the second embodiment described with reference to FIG. 3 has been described, but other multilayer circuits can be formed in the same manner. Moreover, the manufacturing method shown here is only an example. For example, the process of filling the through hole may be performed at a time in the process of forming the circuit element. Further, the formation of the ground electrode may not be performed in the process of forming the signal line, and may be performed in the process of forming the circuit element, for example.

(Semiconductor device package)
With reference to FIG. 7, a package for a semiconductor device including a multilayer circuit as an integral unit will be described. This package for a semiconductor device is a package for a semiconductor device that integrally includes a circuit for matching impedances at one end and the other end of a signal line of a high-frequency signal propagating through the signal line. The multilayer circuit according to each of the embodiments is configured. FIG. 7 is a schematic diagram of a package for a semiconductor device. FIG. 7A is a plan view of a package for a semiconductor device, and FIG. 7B is a side view. In FIG. 7, the frame is partially removed.

  A multi-layer circuit in which a ground conductor layer 52, a first insulator layer 62, a signal line layer 56, a second insulator layer 64, and a circuit element layer 54 are sequentially stacked is provided on the conductive housing 130. On the signal line layer 56, a lead 112 electrically connected to the signal line is attached. The lead 112 is used for electrically connecting a signal line and a transmission line outside the package. In the package 102 formed integrally with the multilayer circuit, an insulating frame 122 is provided on the lead 112, the signal line layer 56, and the like.

  As the material of the lead 112 and the frame 122, any suitable known material may be used depending on the design. Further, each component may be connected by any suitable method, such as brazing.

  A semiconductor device 90 is mounted on the conductive housing 130. The semiconductor device and the signal line of the multilayer circuit are electrically connected by a bonding wire 92 or the like.

  If the multilayer circuit is formed integrally with the package for the semiconductor device, alignment between the impedance matching circuit and the package becomes unnecessary. Further, the bonding of the package lead and the impedance matching circuit becomes unnecessary.

10, 12, 14 multilayer circuit
22, 52 Grounding conductor layer
24, 54 Circuit element layer
26, 56 Signal line layer
32, 62, 63 First insulator layer 34, 64 Second insulator layer 42, 72, 82, 83, 84 Through hole 44, 73, 74 Through electrode 54a Stub 54b GND wiring 61 Green sheet 90 Semiconductor device 92 Bonding wire 100, 102 Package 110, 112 Lead 120, 122 Frame 121 Bottom

Claims (12)

Three or more conductor layers including at least one signal line layer, circuit element layer, and ground conductor layer;
A multilayer circuit comprising an insulator layer between the conductor layers. 2. The multilayer circuit according to claim 1, wherein the signal line formed in the signal line layer performs impedance matching at one end and the other end of the signal line. A signal line layer and a ground conductor layer are provided at a position sandwiching one insulator layer,
The multilayer circuit according to claim 2, wherein a microstrip line is formed by the signal line and a ground electrode provided on the ground conductor layer. 4. The multilayer circuit according to claim 3, wherein a thickness of an insulator layer provided between the signal line layer and the ground conductor layer changes from one end of the signal line toward the other end. The multilayer circuit according to claim 2, wherein a coplanar line is formed in the signal line layer. The multilayer circuit according to claim 1, wherein the dielectric constant of the insulator layer is different for each layer. A package for a semiconductor device integrally including a circuit for matching impedances at one end and the other end of a signal line of a high-frequency signal propagating through a signal line,
A conductive housing;
Three or more conductor layers including at least one signal line layer, circuit element layer, and ground conductor layer on the bottom surface of the housing;
A package comprising an insulator layer between the conductor layers. The package according to claim 7, wherein the signal line formed in the signal line layer performs impedance matching at one end and the other end of the signal line. A signal line layer and a ground conductor layer are provided at a position sandwiching one insulator layer,
9. The package according to claim 8, wherein a microstrip line is formed by the signal line and a ground electrode provided on the ground conductor layer. The package according to claim 9, wherein a thickness of an insulating layer provided between the signal line layer and the ground conductor layer changes from one end to the other end of the signal line. 9. The package according to claim 8, wherein a coplanar line is formed in the signal line layer. The package according to any one of claims 7 to 11, wherein a dielectric constant of the insulator layer is different for each layer.

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