JP2011044640A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a silicide layer 12b of a wiring layer 12 comprising the silicide layer 12b as an uppermost layer formed on an element isolation insulating film 8a and a polysilicon layer 12a as a lower layer from being overetched to disappear when a contact hole 20a etc., are formed by dry etching in an inter-layer insulating film IL having its surface ground in a CMP step to be flattened. <P>SOLUTION: A level difference is generated even on a surface of an N-type epitaxial layer 4 owing to a silicon level difference formed during formation of an N+ type buried layer 2. The element isolation insulating film 8a is formed on a P-type separation layer 5 formed at a high part of the level difference. The wiring layer 12 comprising the silicide layer 12b as the upper layer and the polysilicon layer 12a as the lower layer is formed on the element isolation insulating film 8a, but before the wiring layer 12 is formed, the element isolation insulating film 8a is made thin to make the level difference between a surface of the silicide layer 12b as the uppermost layer and a surface of the N+ type source layer 15 and the like smaller than it has been before the element isolation insulating film 8a is made thin. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device made of BiCMOS, and in particular, when a contact hole is formed in an interlayer insulating film flattened by CMP (Chemical Mechanical Polishing), the uppermost layer formed on the element isolation insulating film is silicided. The present invention relates to a manufacturing method for preventing disappearance of silicide in a polysilicon wiring layer made of

  BiCMOS integrated circuits in which bipolar circuits and CMOS circuits coexist on a single silicon substrate are widely used in order to take advantage of the high speed of bipolar elements and the high integration and low power consumption of CMOS. The digital logic processing is an effective LSI in the case of performing analog / digital processing in which processing is performed by a CMOS circuit and processing results are processed by a bipolar circuit. In such LSIs, from the viewpoint of cost reduction and performance improvement, it is necessary to form a circuit element having a fine pattern, and the fine processing level is being pursued to the limit.

  For processing in the photolithography process, for example, a stepper using an excimer laser is employed to ensure resolution. In this case, since the depth of focus becomes shallow, it becomes difficult to form a pattern at a large stepped portion, and a so-called CMP process is employed to chemically and mechanically form an uneven surface on the silicon substrate. We deal with it by cutting and flattening its main surface.

  Regarding such flattening technology, various technical literatures and the like are disclosed, and are also described in Patent Literature 1 and Patent Literature 2 below.

JP 2001-085431 A Japanese Patent Laying-Open No. 2005-064314

  The cause of poor flatness of the main surface of the silicon substrate that has undergone various processes is an oxide film step, a nitride film step, a polysilicon step, a metal step, and the like when various patterns are formed on the silicon substrate. The influence of these steps on pattern formation becomes more serious as the processing pattern becomes finer. Therefore, a CMP process has been introduced to solve the steps formed and accumulated in the respective steps at once and to flatten the semiconductor substrate. In the CMP process, a semiconductor substrate is sandwiched between an upper plate and a lower plate arranged in parallel, and the semiconductor substrate is chemically and mechanically ground, so that the surface of the semiconductor substrate having an uneven surface can be easily flattened. .

  However, when the object to be ground is an interlayer insulating film and a contact hole is formed in the ground interlayer insulating film, there may be a problem. For example, since the depth from the surface of the ground interlayer insulating film differs greatly between the source layer of the MOS transistor and the wiring layer formed on the element isolation insulating film, the wiring layer on the element isolation insulating film extends from the contact hole. Even after the exposure, the etching to the source layer etc. at a deeper position is continued. As a result, the surface of the wiring layer is exposed to the etching atmosphere for a considerably long time, and the uppermost silicide layer may be lost by over-etching. The problem is to prevent the disappearance of the silicide layer constituting the uppermost layer of the wiring layer located relatively shallow from the surface of the ground interlayer insulating film.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: preparing a first conductive type semiconductor substrate; forming a second conductive type buried layer on the semiconductor substrate; and on a surface of the semiconductor substrate including the buried layer. Forming a second conductivity type epitaxial layer on the entire surface; forming a plurality of element isolation insulating films in a predetermined region of the epitaxial layer; thinning the element isolation insulating film; A step of forming a wiring layer made of polysilicon whose uppermost layer is silicide, and a step of forming an interlayer insulating film covering the entire surface of the semiconductor substrate including the wiring layer; A step of chemically mechanically polishing and planarizing the interlayer insulating film, and a contact hole extending from the planarized surface of the interlayer insulating film to the semiconductor substrate surface and the wiring layer surface Forming, characterized in that it comprises a.

  Further, in the method for manufacturing a semiconductor device of the present invention, by thinning the element isolation insulating film, the surface of the element isolation insulating film is at a position equal to or less than the surface of the source layer of the second conductivity type, and The device isolation insulating film has a desired film thickness.

  In the method for manufacturing a semiconductor device according to the present invention, the buried layer is also formed on the semiconductor substrate below the first conductive type isolation layer, whereby the wiring layer formed on the element isolation insulating film is formed. A step between the surface of the silicide layer and the surface of the source layer is reduced.

  The method for manufacturing a semiconductor device according to the present invention is characterized in that the buried layer formed in the semiconductor substrate below the isolation layer is formed in a range overlapping the silicide layer region exposed in the contact hole. To do.

  The method for manufacturing a semiconductor device according to the present invention is characterized in that the semiconductor device is a BiCMOS.

  According to the method for manufacturing a semiconductor device of the present invention, the silicide layer constituting the uppermost layer portion of the wiring layer formed on the element isolation insulating film remains without being completely etched when the contact hole is formed. The electrical connection between the tungsten layer filling the contact hole and the polysilicon wiring layer, the uppermost layer of which is made of silicide, is smoothly performed, and the problem of contact resistance does not occur.

It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in conventional embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device in embodiment as a comparative example.

  A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

  The present invention relates to a manufacturing method of BiCMOS, and the gist of the invention is that the surface of the interlayer insulating film ground by CMP and planarized, and the uppermost layer formed on the element isolation insulating film is made of silicide. Since the present invention relates to a method of reducing the depth difference between the silicon wiring layer 12 and the like and the N + type source layer 15 and the like of the MOS transistor, the drawings will be described focusing on that portion.

  Before describing the embodiment of the present invention, the planarization technique and the state of contact holes in an embodiment that has a low degree of miniaturization and that does not require a CMP process will be briefly described with reference to FIG. In a predetermined region of the P-type semiconductor substrate 1, an N-type epitaxial layer 4, an N + buried layer 2, a P-type buried isolation layer 3, a P-type isolation layer 5 continuous with the P-type buried isolation layer 3, and a P-type well layer 6 , An N type drift layer 7, an N type source layer 13, an N + type source layer 15, a P + type contact layer 30, and an N + type drain layer 16 are formed.

  An element isolation insulating film 8c is formed on the surface of the N-type drift layer 7, an element isolation insulating film 8b is formed on a part of the surface of the P-type well layer 6, and an element isolation insulating film 8a is formed on the surface of the P-type isolation layer 5. Is formed. Further, a wiring layer 12 composed of a silicide layer 12b and a polysilicon layer 12a is formed on the element isolation insulating film 8a. A wiring layer 11 composed of a silicide layer 11b and a polysilicon layer 11a is formed on the element isolation insulating film 8b. On the insulating film 8c, a gate electrode 10 made of a silicide layer 10b and a polysilicon layer 10a extending from the gate insulating film 9 to the element isolation insulating film 8c is formed. Note that the element isolation insulating film 8b is not formed, and all the wiring layers including the gate electrode 10 connected to the metal wiring layer 31 may be concentrated on the element isolation insulating film 8a.

  The BPSG layer 17 and the SOG layer 18 are deposited on the surface of the wiring layer 12 and the like so as to flatten the surface. Further, a TEOS layer 19 is formed on the surface, and constitutes an interlayer insulating film IL as a whole. Contact holes 20a, 20b, 20c indicated by thin dotted lines are formed by dry etching from the uppermost layer of the interlayer insulating film IL, and the surfaces of the wiring layer 11, the wiring layer 12, the N + type source layer 15 and the N + type drain layer 16 are formed. It is exposed in each contact hole. In this case, the difference between the depth from the surface of the interlayer insulating film IL to the surface of the wiring layer 12 and the like and the depth to the surface of the N + -type source layer 15 and the like is a film of the SOG layer 18 having a relatively low etching rate. Only for thickness.

  Therefore, the etching time required from the exposure of the uppermost silicide layer 12b or the like such as the wiring layer 12 in the contact hole 20a to the exposure of the N + type source layer 15 or the like in the contact hole 20b is short. The uppermost silicide layer 12b etc. such as 12 did not disappear due to overetching. Further, when flatness is ensured by reflow of the BPSG layer 17, the SOG layer 18 may not be formed. Therefore, the surface of the uppermost silicide layer 12b such as the wiring layer 12 and the N + type source layer 15 and the like Since the surface is exposed in the contact hole 20a etc. almost simultaneously, it is not necessary to consider overetching of the silicide layer 12b etc.

  However, when miniaturization advances and a flattening process employing CMP is unavoidable, the following problems arise. That is, as shown in FIG. 13, when the CMP process is simply applied to the conventional manufacturing method and the upper layer is ground from the portion indicated as the CMP surface by the thick chain line, the ground surface of the interlayer insulating film IL shown as the CMP surface The depth from the surface of the silicide layer 12b of the uppermost wiring layer 12 on the element isolation insulating film 8a is shallower than the depth from the ground surface of the interlayer insulating film IL to the surface of the N + type source layer 15 and the like.

  Therefore, when the contact hole 20a and the like are formed by dry etching the interlayer insulating film IL, the surface of the N + type source layer 15 and the like is formed even after the contact hole 20a is opened and the uppermost silicide layer 12b of the wiring layer 12 is exposed. Dry etching is continued until is exposed in the contact hole 20b. During this time, the silicide layer 12b is exposed to overetching by dry etching, and all the silicide layer 12b may be etched away.

  In the present invention, the uppermost silicide layer 12b of the wiring layer 12 formed on the element isolation insulating film 8a is prevented from disappearing due to overetching when a contact hole is formed.

[First Embodiment]
A first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a state where an entire surface of a P-type semiconductor substrate 1 including a wiring layer 12 and the like is covered with an interlayer insulating film IL. In FIG. 1, a surface indicated by a thick dotted line as a CMP surface indicates a ground surface obtained by grinding the interlayer insulating film IL above the CMP surface in the CMP process. Contact holes 20a, 20b and 20c are formed from the ground surface. Compared to FIG. 13, it is recognized that the depth from the ground surface of the interlayer insulating film IL to the silicide layer 12b of the uppermost layer of the wiring layer 12 is deep. After forming the gate insulating film 9, a part of the gate insulating film 9 and the element isolation insulating film 8c where the gate electrode 10 is to be extended is covered with a resist mask, and the other element isolation insulating film 8a and the like are etched from the surface. This is the effect of thinning the film.

  The plurality of element isolation insulating films 8a and the like are required to have a predetermined film thickness in order to avoid the influence of various semiconductor elements formed on the P-type semiconductor substrate 1 and peripheral wirings. It is formed in a lump. Regarding the element isolation insulating film 8a formed on the surface of the P-type isolation layer 5, since the surface concentration of the P-type isolation layer 5 is relatively high, there is a risk of field inversion due to the potential of the wiring layer 12 formed thereon. The film thickness can be reduced. Therefore, the rate of reduction due to over-etching of the silicide layer 12b, which is the uppermost layer of the wiring layer 12 formed on the element isolation insulating film 8a when the contact hole 20a and the like are formed, and the silicide layer 12b and the via connected through the contact hole 20a are described later. The etching amount of the element isolation insulating film 8a and the like was determined in consideration of the influence on the contact resistance with the tungsten layer 32.

  In this case, the etching amount of the element isolation insulating film 8a and the like is determined by the selection ratio of the silicide layer 12b and the interlayer insulating film IL to dry etching. The height from the surface of the N + -type source layer 15 and the like to the surface of the uppermost silicide layer 12b of the wiring layer 12 is generally composed of the following steps. First, the step from the initial silicon surface height of 258 nm of the element isolation insulating film 8a formed by the step of 120 nm of the N type epitaxial layer 4 due to the silicon step at the time of forming the N + type buried layer 2 and the entire film thickness of 460 nm is performed thereafter. The level difference is about 550 nm which is the sum of the thickness of 210 nm obtained by subtracting the amount of etching and 220 nm of polysilicon. On the other hand, the average thickness of the silicide layer 12b is 40 nm.

  If the etching rate of the interlayer insulating film IL is 20 times that of the silicide layer 12b, that is, if the selection ratio is 20, the thickness of the silicide 12b etched during etching of the interlayer insulating film IL550nm is 20 minutes. 1 is 28 nm. In this case, 12 nm, which is 30% of the thickness of the silicide layer 12b, which was 40 nm at the beginning, remains, and no significant problem occurs. However, when the selection ratio is only about 10, the thickness of the silicide 12b etched while etching the interlayer insulating film IL550nm is 55nm and the silicide layer 12b disappears completely.

  In this case, if the 210 nm protruding from the initial silicon surface of the element isolation insulating film 8a in the structure having a step of 550 nm is etched, the step can be lowered to 340 nm. Then, the silicide layer 12b is over-etched by 34 nm while the interlayer insulating film IL 340 nm is etched, and the film thickness of the remaining silicide layer 12b is about 6 nm. Therefore, the etching amount of the element isolation insulating film 8a must be determined so that the silicide layer 12b remains after the contact hole is formed by the selection ratio of dry etching. The selection ratio in this embodiment is 15 or more, and the film thickness of the remaining silicide layer is 10 nm or more by making the etching amount of the element isolation insulating film 8a 130 nm or more.

  By reducing the thickness of the element isolation insulating film 8a, it is possible to shorten the etching time from the time when the uppermost silicide layer 12b of the wiring layer 12 is exposed to the time when the N + type source layer 15 and the like are exposed. It was possible to prevent the silicide layer 12b from disappearing due to overetching.

  A method for manufacturing the semiconductor device according to the first embodiment will be described below with reference to FIGS. First, as shown in FIG. 2, a P-type semiconductor substrate 1 is prepared. Next, using a silicon oxide film (not shown) having an opening at a predetermined position of the P-type semiconductor substrate 1 as a mask, Sb is diffused from an SOG film (not shown) containing antimony (Sb), which is an N-type impurity, An N + type buried layer 2 is formed in the P type semiconductor substrate 1.

  In this case, since the treatment is performed in an oxidizing atmosphere, a silicon oxide film is formed on the surface of the N + type buried layer 2. Thereafter, when the silicon oxide film is entirely removed, there is a difference in level between the area where the silicon oxide film mask was formed and the area where the N + type buried layer 2 is formed because the thickness of the newly formed silicon oxide film is different. As a result, as shown in FIG. 2, the N + type buried layer 2 formation region is recessed from the peripheral region. In this embodiment, a step of 120 nm occurred.

  Next, after forming a P-type buried isolation layer 3 in the peripheral region of the N + type buried layer 2 by ion implantation of boron or the like, an N type that covers the entire surface of the P-type semiconductor substrate 1 through a predetermined process. Epitaxial layer 4 is formed. As shown in FIG. 2, the surface of the N-type epitaxial layer 4 also reflects the level difference of the N + type buried layer, and shows a stepped shape in which the region overlapping the N + type buried layer 2 has a depression. Next, a P-type isolation layer 5 is formed by ion implantation of boron or the like on the surface of the N-type epitaxial layer 4 overlapping the P-type buried isolation layer 3 using a resist mask (not shown). Further, boron or the like is ion-implanted at a predetermined position using a resist mask (not shown) to form a P-type well layer 6. Next, a PN separation layer in which the P-type buried separation layer 3 and the P-type separation layer 5 are integrated is formed by performing heat treatment in a high-temperature furnace and diffusing impurities.

  Next, as shown in FIG. 3, through a predetermined process, a mask (not shown) such as a SiN film is formed, and phosphorus or the like is ion-implanted into a predetermined region using the resist and the SiN film as a mask to form an N-type drift layer 7. Form. Thereafter, an element isolation insulating film (LOCOS) 8a or the like is formed using the SiN film or the like as a mask. The element isolation insulating film 8a on the P-type isolation layer 5 is formed at a position higher than the element isolation insulating films 8b and 8c formed in the N-type epitaxial layer 4 reflecting the step formed in the N-type epitaxial layer 4. Is done.

  In this state, when the wiring layer 12 is formed on the element isolation insulating film 8a, the depth from the interlayer insulating film IL ground by CMP to the uppermost silicide layer 12b of the wiring layer 12 is shallow as shown in FIG. Become. Therefore, as shown in FIG. 4, after the gate insulating film 9 is formed, a resist mask (not shown) covers the gate insulating film on which the gate electrode 10 is to be formed later and a part of the element isolation insulating film 8c. Then, the other gate insulating film and element isolation insulating film are etched from the surface. Thereby, the element isolation insulating film 8a and the like are thinned. Thereafter, through a predetermined process, the wiring layer 12 is formed on the element isolation insulating film 8a, the wiring layer 11 is formed on the element isolation insulating film 8b, and the gate electrode 10 extending from the gate insulating film 9 to the element isolation insulating film 8c is formed. Form.

  Thereafter, as shown in FIG. 5, an N-type source layer 13 is formed through a predetermined process such as ion implantation. Next, a silicon oxide film (not shown) that covers the entire surface of the P-type semiconductor substrate 1 including the wiring layer 12 and the like is deposited by CVD or the like, and the silicon oxide film or the like is etched from the surface to the spacer. 14 is formed, and an N + type source layer 15 is formed using the spacer 14 as a mask. At the same time, an N + type drain layer 16 is formed and a P + type contact layer 30 is formed. Due to the P + type contact layer 30, the N + type source layer 15 and the P type well layer 6 have the same potential.

  Next, about 30 nm of titanium (Ti) or the like is deposited on the entire surface of the P-type semiconductor substrate 1 including the surface of the wiring layer 12 and the like by sputtering. Thereafter, a lamp anneal (RTA) process is performed to form a silicide layer 12b or the like on the uppermost layer of the wiring layer 12 or the like. At the same time, a silicide layer is also formed on the surface of the N + type source layer 15 and the like. Thereafter, unreacted Ti and the like are removed with a wet etching solution. By performing the RTA process, the Ti film of about 30 nm becomes the silicide layer 12b of about 350 to 450 nm.

  Thereafter, the entire surface of the P-type semiconductor substrate 1 including the wiring layer 12 is covered with an interlayer insulating film IL mainly composed of the BPSG layer 17 and the TEOS layer 19. If necessary, the TEOS layer 19 may be formed after the SOG layer 18 is formed on the BPSG layer 17. Next, as shown in FIG. 6, grinding is performed by CMP from the outermost surface of the interlayer insulating film IL. A semiconductor substrate having an interlayer insulating film IL whose top surface is cleanly flattened by CMP processing can be obtained, and necessary resolution and depth of focus can be obtained, and fine processing can be realized.

  Next, as shown in FIG. 7, contact etching is performed by dry etching from the outermost surface of the interlayer insulating film IL flattened by the CMP process using a resist mask (not shown) to reach the surface of the wiring layer 12, etc. A contact hole 20b etc. reaching the N + type source layer 15 etc. is formed.

  Compared to the case of FIG. 13, since the step between the uppermost silicide layer 12b of the wiring layer 12 and the N + type source layer 15 and the like is small, the silicide layer 12b disappears due to overetching during dry etching. No.

  Next, after filling the contact hole 20a and the like with a tungsten layer 32 through a predetermined process, a metal film mainly composed of aluminum (Al) is deposited on the entire surface of the P-type semiconductor substrate. Thereafter, the metal wiring layer 31 is formed through a predetermined photoetching process. The contact hole 20a and the like may be filled with another metal, such as aluminum, instead of tungsten. Finally, a desired semiconductor device is completed by covering with a protective film made of SiN film or the like.

[Second Embodiment]
A second embodiment will be described below with reference to FIG. Compared with FIG. 1 showing the first embodiment, the outermost surface of the element isolation insulating film 8a and the like is almost the same as the surface of the N + type source layer 15 even though the element isolation insulating film 8a and the like are thick. The following points are thinned by etching or the like. With such a configuration, the step between the surface of the uppermost silicide layer 12b and the like such as the wiring layer 12 and the surface of the N + type source layer 15 and the like becomes smaller than that of the first embodiment, and the contact hole 20a and the like are formed. The amount of overetching of the silicide layer 12b and the like is further reduced.

  Then, the manufacturing method of the semiconductor device in 2nd Embodiment is demonstrated below based on FIG. 9, FIG. In the case of the first embodiment, problems such as field inversion occur even if the element isolation insulating film 8a and the like are thinned by etching or the like because of the selection ratio between the interlayer insulating film IL and the silicide layer 12b. There is a fear, there is a limit to the thin film.

  Therefore, as shown in FIG. 9, in the second embodiment, the initial film thickness of the element isolation insulating film 8a and the like is formed thicker than that in the first embodiment. Therefore, the film thickness formed in the silicon substrate from the surface of the silicon substrate before oxidation, such as the element isolation insulating film 8a, becomes thicker than that in the first embodiment. Thereafter, before the gate insulating film 9 is formed, the element isolation insulating film 8a and the like are thinned by etching or the like. As shown in FIG. 9, the surface of the P where the N + type source layer 15 and the like are to be formed is formed. It is characterized by being equal to or less than the surface of the mold well layer 6 and the like.

  With such a configuration, the step difference between the uppermost silicide layer 12b and the like formed on the element isolation insulating film 8a and the like and the surface of the N + type source layer 15 and the like can be reduced, and in some cases, it can be reduced to zero. Is also possible. Accordingly, it is possible to expose the surface of the silicide layer 12b and the like and the surface of the N + type source layer 15 and the like in the contact hole 20a and the like at the time of forming the contact hole, so that the silicide layer 12b and the interlayer insulating film IL can be exposed. Even when the selectivity during dry etching is considerably small, overetching of the silicide layer 12b and the like can be reduced.

  Since the initial element isolation insulating film 8a and the like are formed thicker than those in the first embodiment, etching is performed from the surface of the element isolation insulating film 8a and the like to make the surface of the element isolation insulating film 8a and the like an N + type source layer. Even when the thickness is reduced to a level equal to or less than 15 or the like, it is possible to secure the element isolation insulating film 8a and the like having a sufficient film thickness that does not cause side effects such as field inversion.

Next, as shown in FIG. 10, the gate insulating film 9 is formed through a predetermined process, and the wiring layer 12 and the like and the gate electrode 10 are formed. The subsequent steps are the same as those in the first embodiment.
Note that the gate insulating film 9 may be formed before the element isolation insulating film 8a or the like is thinned.

[Third Embodiment]
A third embodiment will be described below with reference to FIG.

  In the third embodiment, a silicon step generated when the N + type buried layer 2 is formed is also formed on the P type semiconductor substrate 1 under the element isolation insulating film 8a on which the wiring layer 12 and the like are formed. For this purpose, as shown in FIG. 11, an N + type buried layer 2 is also formed in the P type semiconductor substrate 1 immediately below the element isolation insulating film 8a where the wiring layer 12 is formed. As a result, as shown in FIG. 11, the N + type buried layer 2 in the step 550 nm formed between the surface of the uppermost silicide layer 12b and the like such as the wiring layer 12 and the surface of the N + type source layer 15 and the like. This eliminates the 120 nm step generated during the formation.

  When the contact hole 20a is formed from the ground surface of the flattened interlayer insulating film IL, which is shown as a CMP surface by a thick dotted line in FIG. 11, overetching of the uppermost silicide layer 12b such as the wiring layer 12 is Only minutes are eliminated. The effect can be heightened by using together with 1st Embodiment or 2nd Embodiment. The manufacturing method of the semiconductor device of the third embodiment is the same as that of the first embodiment except that the N + type buried layer 2 is also formed in the P type semiconductor substrate 1 immediately below the wiring layer 12 described above.

  In this embodiment, the device is described as an example of an N-type MOS transistor. Among them, there are a high breakdown voltage MOS transistor having a thick gate insulating film and a low breakdown voltage MOS transistor having a thin gate insulating film. Also included are CMOS transistors including P-type MOS transistors having different polarities.

1 P-type semiconductor substrate 2 N + type buried layer 3 P-type buried isolation layer
4 N-type epitaxial layer 5 P-type isolation layer 6 P-type well layer
7 N-type drift layer 8a, 8b, 8c Element isolation insulating film 9 Gate insulating film 10 Gate electrode 10a Silicide layer 10b Polysilicon layer 11, 12 Wiring layer 11b, 12b Silicide layer
11a, 12a Polysilicon layer 13 N type source layer 14 Spacer 15 N + type source layer 16 N + type drain layer 17 BPSG
18 SOG 19 TEOS 20a, 20b, 20c Contact hole IL Interlayer insulating film 31 Metal wiring layer 32 Tungsten layer

Claims (5)

Preparing a first conductivity type semiconductor substrate,
Forming a second conductivity type buried layer on the semiconductor substrate;
Forming a second conductivity type epitaxial layer over the entire surface of the semiconductor substrate including the buried layer;
Forming a plurality of element isolation insulating films in a predetermined region of the epitaxial layer;
Thinning the element isolation insulating film;
Forming a wiring layer made of polysilicon whose uppermost layer is silicide on the thinned element isolation insulating film;
Forming an interlayer insulating film covering the entire surface of the semiconductor substrate including the wiring layer;
Polishing and planarizing the interlayer insulating film chemically and mechanically;
Forming a contact hole extending from the planarized surface of the interlayer insulating film to the surface of the semiconductor substrate and the surface of the wiring layer. By thinning the element isolation insulating film, the surface of the element isolation insulating film becomes a position equal to or less than the surface of the second conductivity type source layer and becomes an element isolation insulating film having a desired film thickness. The method of manufacturing a semiconductor device according to claim 1. The buried layer is also formed on the semiconductor substrate below the isolation layer of the first conductivity type, so that the surface of the silicide layer and the surface of the source layer of the wiring layer formed on the element isolation insulating film are formed. The method of manufacturing a semiconductor device according to claim 1, wherein the step is lowered. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the buried layer formed in the semiconductor substrate below the isolation layer is formed in a range overlapping the silicide layer region exposed in a contact hole. . The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a BiCMOS.

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