JP2011039540A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems wherein it is preferable when Vgs is increased to reduce the influence of variation in threshold voltage in view of the electric characteristic of a transistor, it is preferable when Vgs is decreased to enlarge the operation range of a saturation region in view of the characteristic of a light emitting element, and thus a trade-off relationship exists between reduction of influence of variation in threshold voltage and enlargement of the operation range of the saturation region to prevent luminance reduction by deterioration of the light emitting element. <P>SOLUTION: This display device increases the current capability of a driving transistor so that it operates in a large saturation region. As a result, even when high gradation display is performed, Vgs is prevented from increasing, and the saturation region serving as the operation range can be kept large. Further, each pixel includes a circuit (lighting period control circuit) 18 for controlling the lighting period so as to individually change the lighting period of each pixel. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display device having a self-luminous light emitting element and a driving method thereof. In particular, the present invention relates to a pixel configuration of a display device.

  In recent years, research and development of display devices using light-emitting elements (self-light-emitting elements) have been advanced. Such a display device is widely used as a display screen of a mobile phone or a monitor of a personal computer by taking advantage of high image quality, thinness, and light weight. In particular, such a display device has features such as a fast response speed suitable for moving image display, low voltage, low power consumption drive, etc. Applications are expected.

  The light emitting element is also called an organic light emitting diode (OLED), and an anode, a cathode, and a layer having an organic compound (hereinafter referred to as an organic compound layer) are sandwiched between the anode and the cathode. Have a structure. There is a fixed relationship between the amount of current flowing through the light emitting element and the luminance of the light emitting element, and the light emitting element emits light with luminance according to the amount of current flowing through the organic compound layer.

  By the way, as a driving method when displaying a multi-gradation image on a display device using a light emitting element, there are an analog driving method (analog gradation method) and a digital driving method (digital gradation method). The difference between the two systems is in the method of controlling the light emitting element in each of the light emitting and non-light emitting states of the light emitting element.

  The analog driving method is a method in which gradation is obtained by continuously controlling the magnitude of a current flowing through a light emitting element. The digital driving method is a method in which the light-emitting element is driven only in two states, an on state (a state where the luminance is approximately 100%) and an off state (a state where the luminance is approximately 0%).

  However, since the digital driving method can display only two gradations as it is, a driving method for displaying a multi-gradation image in combination with the time gradation method or the area gradation method has been proposed. For example, the time gradation display is to divide one frame into several subframes, put a weight on each light emission time, and perform gradation display by selection. The area gradation method is a method in which sub-pixels are provided in a pixel, the light emitting area is weighted, and gradation display is performed by selection.

  In addition, when inputting a signal to a pixel, a voltage input method is often used. The voltage input method is a method in which a voltage is input to a gate electrode of a driving element as a video signal input to a pixel, and the luminance of the light emitting element is controlled using the driving element.

  Refer to Non-Patent Document 1 for the driving method of the display device, the multi-gradation display method, and the like as described above.

“Material technology and device fabrication in organic EL displays” Technical Information Association, January 2002, p. 179-196

  When the voltage input method as described above is used, if the current characteristics of a transistor for driving (supplying current) the light emitting element (hereinafter referred to as a driving transistor) varies, the luminance of the light emitting element also varies. It was. In particular, when low gradation display is performed in the case of the analog gradation method, the influence of variations in the electrical characteristics of the driving transistor has become large. This is because the current characteristic of the transistor is determined depending on (Vgs−Vth). Therefore, when low gradation display is performed, Vgs is small and relatively influenced by Vth. The Vth of a transistor is a threshold voltage, and variation greatly appears depending on manufacturing processes such as film formation conditions and film thickness. In particular, in a semiconductor element having a polycrystalline silicon film that has undergone a crystallization process, Vth varies due to crystal grain boundaries and orientation.

Specific description is made using the transistor and the light-emitting element illustrated in FIG. FIG. 11B shows Ids-Vds characteristics of a light-emitting element and a transistor in the case of performing low gradation display, and the intersection is an operating point. As shown in FIG. 11B, when low gradation display is performed, the current value (Ids) supplied from the transistor to the light-emitting element is displayed.
It can be seen that Vgs is small and Vgs is also small, and it is relatively susceptible to variations in Vth. As a result, in a display device having a transistor and a light-emitting element, luminance unevenness occurs, causing deterioration in quality. In order to reduce the influence of the threshold voltage as described above, it is conceivable to design the transistor with a smaller channel size W / L and to increase the Vgs.

  On the other hand, the transistor is operated in a saturation region so that a constant current flows through the light-emitting element even when the voltage-current characteristics of the light-emitting element fluctuate. As shown in FIG. 11C, the saturation region is a range of Vds> (Vgs−Vth), and the source / drain current does not change even if the source-drain voltage of the transistor changes. Therefore, a constant current can always be supplied to the light emitting element.

  However, when high gradation display is performed, the saturation region of the transistor is narrowed. FIG. 11C shows transistor characteristics and Ids-Vds characteristics of light-emitting element characteristics in high gradation display. As can be seen from FIG. 11C, as the light emitting element deteriorates, the light emitting element characteristics shift to a lower voltage side and Vds decreases. As a result, it has been considered that the saturation region, which is the operation range of the transistor, is narrowed, and further that the transistor operates in the linear region.

  In order to solve such problems in high gradation display, it is preferable to widen the operating range of the saturation region. For example, it is conceivable to increase the voltage between α and β shown in FIG. As a result, even if the light emitting element is deteriorated, it can operate in a saturated region. However, in this case, since the voltage increases, the power consumption increases. As another method, the channel size W / L of the transistor is designed to be larger and Vgs can be reduced.

  In view of these, it is preferable to design the channel size W / L to be small and increase Vgs in order to reduce the influence of the variation in threshold voltage in terms of the electrical characteristics of the transistor. In order to widen the operating range of the saturation region, it was preferable to design the channel size W / L so as to reduce Vgs. Thus, there is a trade-off relationship between reducing the influence of variation in threshold voltage and widening the operating range in the saturation region in order to prevent a decrease in luminance due to deterioration of the light emitting element.

  Accordingly, the present invention is a display device including a semiconductor element having a polycrystalline silicon film or an amorphous silicon film, and operates a driving transistor in a saturation region in high gradation display and low gradation display, and the transistor It is an object of the present invention to provide a display device and a driving method thereof in which variation in threshold voltage is reduced.

  In view of the above problems, the present invention is characterized in that the current capability of a driving transistor is increased so as to operate in a wide saturation region. As a result, even when high gradation display is performed, it is possible to prevent Vgs from increasing and to keep a wide saturation region as an operation range. Further, according to the present invention, each pixel includes a circuit (lighting period control circuit) that controls the lighting period so as to individually change the lighting period of each pixel. When low gradation display is performed, the lighting period of the light emitting element is controlled to be shortened. Note that the lighting period control circuit may be disposed at a position where the light emitting element can be controlled to emit no light in a predetermined period. As a result, when low gradation display is performed, operation can be performed with Vgs increased. Since Vgs is thus large, the influence of variations in threshold voltage can be reduced.

  That is, the present invention can widen the saturation region even when high gradation display is performed, and can reduce the influence of Vth variation even when low gradation display is performed. In order to realize this, the W / L of the transistor is designed, and the lighting period of each pixel is changed in accordance with the size of the gradation.

  As a specific design policy, W / L may be increased. For example, in order to operate in the saturation region, it is preferable that the length of L is several hundred to several tens of μm. That is, the current capability of the driving transistor may be increased. As another method, the crystallinity of the driving transistor may be increased. For example, the crystallinity may be increased using a continuous wave laser.

  In the present invention, a plurality of driving transistors may be arranged in parallel. Note that the transistor may be formed using a polycrystalline silicon thin film transistor, an amorphous silicon thin film transistor, or another transistor, that is, the present invention is not limited to the structure of the transistor.

  In the case of using an amorphous silicon thin film transistor, it is preferable that all are formed of n-channel thin film transistors. Thus, when it comprises only one polarity, a bootstrap circuit etc. should just be utilized and the description of Japanese Patent Application No. 2002-327498 should just be referred.

  As described above, the W / L of the driving transistor can be designed so as to ensure a wide saturation region according to the present invention. As a result, a wide saturation region as an operation region of the transistor can be ensured, and even when low gradation display is performed by the lighting period control circuit, it is difficult to be affected by variations, and accurate display can be performed.

  According to the present invention, at least the W / L of the driving transistor can be designed so as to ensure a wide saturation region. As a result, a wide saturation region as an operation region of the transistor can be secured, and accurate display can be performed even with low gradation display.

FIG. 14 illustrates a pixel structure of a display device of the present invention. FIG. 14 illustrates a pixel structure of a display device of the present invention. FIG. 14 illustrates a pixel structure of a display device of the present invention. FIG. 14 illustrates a pixel structure of a display device of the present invention. FIG. 14 illustrates a pixel structure of a display device of the present invention. FIG. 14 illustrates a pixel structure of a display device of the present invention. FIG. 14 illustrates a pixel structure of a display device of the present invention. FIG. 6 illustrates a display device of the present invention. FIG. 11 is a timing chart of a display device of the present invention. FIG. 6 illustrates a display device of the present invention. FIG. 6 shows characteristics of a light-emitting element and a transistor. FIG. 14 illustrates an electronic device of the invention. FIG. 11 is a timing chart of a display device of the present invention. FIG. 11 is a timing chart of a display device of the present invention. FIG. 6 is a top view illustrating a pixel structure of a display device of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment mode, a pixel structure which performs a driving method in which an analog signal, particularly an analog voltage, is input as a video signal will be described.

  FIG. 1 illustrates an active matrix pixel configuration including a signal line 10, a scanning line 11, and a light emitting element 12. An n-channel switching transistor Tr14 connected to the signal line 10 and the scanning line 11 is provided, and when the Tr14 is selected by the scanning line 11 and is turned on, an analog voltage having a desired luminance is input from the signal line 10. Is done. Based on the input analog voltage, charges are accumulated in the capacitive element Cs16 disposed between the Tr14 and the power supply line 15. Cs16 plays a role of holding the gate-source voltage of the p-channel type driving transistor Tr15. Thereafter, when Tr17 is turned on, the light emitting element 12 is supplied with a current based on the electric charge stored in Cs16 and emits light with a predetermined luminance.

  At this time, in the present invention, W / L of Tr17 is set so as to ensure a wide saturation region. Therefore, the driving transistor can be prevented from operating in the linear region even when the light emitting element is affected by deterioration with time.

  When low gradation display is performed in such a pixel configuration, the lighting period control circuit 18 controls the lighting period of the light emitting element to be short. That is, the lighting period control circuit 18 has a circuit configuration for controlling a lighting period (also referred to as a light emission period) of the light emitting element. That is, the lighting period control circuit discharges the charge held in Cs16 at a predetermined timing, prevents a current from flowing through Tr17, and controls the lighting period of the light emitting element. Note that the lighting period control circuit may be disposed at any place where the lighting period of the light emitting element can be controlled, and is connected to both ends of Cs 16 in FIG. In the present invention, since the lighting period control circuit is provided for each pixel, the charge held in Cs16 can be discharged for each pixel. Note that a period in which the light emitting element does not emit light by the lighting period control circuit is referred to as an erasing operation period.

  Therefore, in designing the transistor W / L so as to secure a wider saturation region, an erase operation period is provided to control the current supply to the light emitting element while preventing the | Vgs | Low gradation display can be performed.

  Therefore, even if the W / L of the driving transistor is designed so that a wide saturation region can be secured, low gradation display can be performed accurately, and when performing high gradation display, the saturation region that is the operation range is widened. Can be secured.

  In the present invention, the lighting period control circuit may be arranged so as to control the time for supplying a predetermined current to the light emitting element. For example, as shown in FIG. 1B, the lighting period control circuit is provided between the light emitting element and the driving transistor Tr17. Such an arrangement is also conceivable.

  When the lighting period control circuit is arranged as shown in FIG. 1B, an erasing operation period can be provided regardless of the characteristics of the driving transistor Tr17, in particular, the threshold voltage Vth. That is, even when the Tr17 characteristic is normally on, in which a current flows when the voltage is zero, the lighting period control circuit short-circuits the connection between the light emitting element and the Tr17, so that the erasure is surely performed. An operation period can be provided and low gradation display can be performed.

  In the present invention, a p-channel type driving transistor has been described, but an n-channel type transistor may be used. Further, in order to simplify the manufacturing process, all the polarities of the transistors can be n-channel or p-channel.

  As described above, according to the present invention, even when the W / L of a transistor is designed so as to ensure a wide saturation region, low gradation display can be accurately performed by providing a lighting period control circuit for each pixel. Make it possible. The configuration and polarity of the transistors included in the lighting period control circuit and the pixels, and further the pixel configuration and the arrangement of the lighting period control circuits are not limited to those in FIG.

(Embodiment 2)
In this embodiment, a specific example of a pixel structure in which lighting period control circuits are arranged at both ends of a capacitor as illustrated in FIG. 1A will be described with reference to FIG.

  The pixel shown in FIG. 2A includes a switching transistor Tr14 connected to the signal line 10 and the scanning line 11, a capacitor Cs16 connected to the switching transistor Tr14, a switching transistor, and a gate to Cs16. A driving transistor Tr17 to which an electrode is connected and a light emitting element 12 connected to the driving transistor Tr17 are provided. A lighting period control circuit 18 having transistors Tr22 and Tr23 connected in series is provided at both ends of the capacitive element Cs16. The gate electrode of Tr22 is connected to the erasing signal line 20, and the gate electrode of Tr23 is used for erasing. It is connected to the scanning line 21. In this embodiment, Tr14, 22, and 23 are n-channel transistors, and Tr17 is a p-channel transistor.

  The operation of such a pixel configuration will be described. When the transistor 14 is selected by the scanning line 11 and the Tr 14 is turned on, an analog voltage corresponding to each gradation is input from the signal line 10. Charges are accumulated in Cs16 based on the analog voltage, and when the driving transistor Tr17 is turned on, a predetermined current is supplied to the light emitting element to emit light.

  In the case of low gradation display, the charge accumulated in Cs16 is discharged after a predetermined period, so that the light emitting element does not emit light. Specifically, control is performed so that both Tr22 and 23 are turned on, and low gradation display is performed. At this time, the analog voltage input from the signal line has a magnitude corresponding to the lighting period.

  Next, the operation of Tr22 and 23 will be described. When the light emitting element is made to emit no light, the erasing scanning line 21 is selected, and the Tr 23 of each pixel connected to the erasing scanning line in the same column is turned on. At this time, an erasing signal is input from the erasing signal line 20. Specifically, a high signal is input to Tr22 included in a pixel that displays a low gradation display, and Tr22 is turned on. That is, both Tr22 and 23 are turned on, and the charge of Cs16 is discharged. As a result, the light emitting element does not emit light, and low gradation display can be performed. That is, only the pixel in which both Tr22 and Tr23 are turned on can be made to emit no light. Therefore, the lighting period can be controlled for each pixel.

  Actual pixels are arranged in a matrix, scanning lines are sequentially selected, and analog voltages are input. Accordingly, the timing at which the erasing scanning line 21 is selected is later than the timing at which the scanning line 11 is selected, and is sequentially selected. The practitioner can set the timing for selecting the erasing scanning line according to the length of the lighting period.

  FIG. 2B shows a timing chart in which the timing for selecting the erasing scan line is n × T (0 <n <1). As time elapses, scanning lines in each row are sequentially selected, Tr 14 is turned on for each column, and an analog voltage is supplied from the signal line 10. Thereafter, charges based on the analog voltage are accumulated in Cs16, and Tr17 is turned on. Thereafter, the light emitting element 12 starts to emit light with a luminance corresponding to each analog voltage.

  Then, after n × T, the erasing scanning lines in each row are sequentially selected, and Tr23 is turned on for each column. However, the number of pixels that are actually desired to be erased, that is, for which low gradation display is desired, varies for each column. Therefore, an erasure signal is input to the Tr 22 via the erasing signal line 20 only for the pixel for which low gradation display is desired. As a specific erasing signal, a high signal is input from the erasing signal line 20, whereby the n-channel Tr 22 is turned on. That is, in synchronization with the timing at which the erasing scanning line 21 is selected, the light emitting element 12 of the pixel to which the erasing signal is input from the erasing signal line 20 does not emit light, and low gradation display is performed.

  Next, a specific number of gradations will be described to explain timing for selecting a low gradation display, a scanning line, and an erasing scanning line.

  For example, when performing 64-gradation display, a scanning line is selected in one frame period T, and an analog voltage of each gradation is input from the signal line to the pixel. In the low gradation region from the first to the eighth gradation, the lighting period is shortened.

When the erasing operation is started after (1/8) T, the erasing scanning line is selected after (1/8) T when the scanning line is selected. For example, when 2 gradations are displayed, 2 / (1/8)
= A video signal corresponding to 16 gradations is input. At this time, since the lighting period is (1/8) T, display of two gradations is actually performed. Similarly, when displaying 8 gradations, a video signal corresponding to 8 ÷ (1/8) = 64 gradations is input. Since the lighting period is (1/8) T, display of 8 gradations is actually performed. When displaying nine gradations or more, a video signal having the same gradation is input. At this time, since the lighting period is T, display is performed with the same gradation.

  The low gradation display may be appropriately determined by the practitioner. However, when the 64 gradation display is performed as in this example and the erasing operation is started after (1 / N) T, the gradation of 64 / N gradation or lower is set. It is preferable to use a tone display. Of course, even when displaying 64 / N gradations or more, the lighting period can be shortened by the lighting period control circuit. However, for example, when displaying 9 gradations, it is necessary to input 72 gradations (9 gradations × 8) as analog voltages, and an analog voltage of 64 gradations or more is input, which is not preferable.

  That is, it is preferable to set the gradation range for low gradation display in consideration of the timing of the erase operation (the length of the lighting period) so as not to exceed the maximum gradation determined by the specifications of the display device.

  FIG. 15 shows an example of a top view of a pixel corresponding to the circuit diagram of FIG. Tr17 may be designed so that W / L becomes large. In order to operate in the saturation region, it is preferable that the length of L is several hundred to several tens of μm and the length of W is several μm. Therefore, the semiconductor film is formed on a rectangle and the area of the gate metal is increased.

  Even in the case where low gradation display is performed using such a driving transistor Tr17, the lighting period can be shortened by the lighting period control circuit, and accurate gradation display in which the influence of the variation in Vth is reduced. It can be performed.

  As described above, the W / L of the transistor can be designed so as to ensure a wide saturation region. As a result, even when Vgs becomes large, low gradation display can be performed by providing a lighting period control circuit. . That is, according to the present invention, it is possible to reduce both the influence of the variation in threshold voltage and to widen the operating range in the saturation region in order to prevent a decrease in luminance due to deterioration of the light emitting element.

(Embodiment 3)
In the present embodiment, as shown in FIG. 1A, the lighting period control circuits are arranged at both ends of the capacitor, and unlike the second embodiment, an example in which the length of the lighting period is further increased. This will be described with reference to FIG.

  The lighting period control circuit 18 shown in FIG. 3A has four transistors Tr22, 23, 24, and 25. The gate electrodes of the Trs 22 and 24 are connected to the first and second erasing signal lines 20a and 20b, respectively. The gate electrodes of Tr23 and 25 are connected to the first and second erasing scanning lines 21a and 21b, respectively. Note that in this embodiment, Tr22, 23, 24, and 25 are n-channel transistors.

  When there are two erasing scan lines and two erasing signal lines in this manner, as shown in FIG. 3B, a case where the lighting period is n × T and a case after m × T can be provided. . That is, the first erase operation starts after n × T, and the second erase operation starts after m × T. That is, there are three types of lighting periods: T, n × T, and m × T.

  For example, a specific number of gradations will be described. For example, when displaying two gradations, a video signal corresponding to 2 ÷ (1/8) = 16 gradations is input. At this time, since the lighting period is (1/8) T, display of two gradations is actually performed. Similarly, when displaying 8 gradations, a video signal corresponding to 8 ÷ (1/8) = 64 gradations is input. Since the lighting period is (1/8) T, display of 8 gradations is actually performed. When displaying 9 gradations, a video signal corresponding to 9 ÷ (1/4) T = 36 gradations is input. At this time, since the lighting period is (1/4) T, display of nine gradations is actually performed. Similarly, when displaying 16 gradations, a video signal corresponding to 16 ÷ (1/4) = 64 gradations is input. Since the lighting period is (1/4) T, display of 16 gradations is actually performed. When displaying 17 gradations or more, a video signal having the same gradation is input. At this time, since the lighting period is T, display is performed with the same gradation.

  In the present invention, a plurality of erasing operations can be provided in accordance with the erasing scanning line, the erasing signal line, and the transistors connected to each. In addition, the practitioner can appropriately determine the timing, number, and the like of starting the erasing operation.

  Note that there is a concern that the aperture ratio will decrease as the number of wirings and transistors increases. However, it is possible to prevent the aperture ratio from being lowered by designing the arrangement of wirings and transistors and adopting the top emission method in which the light emitting element emits light in the direction opposite to the transistor arrangement. Note that the top emission method can be applied to any pixel configuration of the present invention.

(Embodiment 4)
In this embodiment mode, as shown in FIG. 1A, a pixel configuration in which lighting period control circuits are arranged at both ends of a capacitor element, and a specific example of Tr different from that in Embodiment Modes 2 and 3 is shown in FIG. Will be described.

  As shown in FIG. 4, the transistor Tr26 connected to the erasing signal line 20, the transistor Tr22 whose gate electrode is connected to the drain electrode of Tr26, and the transistor 22 connected in series, and the gate electrode connected to the erasing scanning line 21. Tr23 connected to the gate electrode, the gate electrode of Tr22, and the erasing Cs27 provided between the power supply line 15. Note that in this embodiment, Tr22, 23, and 26 are n-channel transistors.

  The operation of this pixel configuration will be described. First, Tr14 and Tr26 are simultaneously selected by the scanning line 11, and an analog voltage and an erasing signal are input from the signal line 10 and the erasing signal line 20, respectively. At this time, charges are accumulated in the erasing Cs 27 based on the erasing signal, and the Tr 22 is turned on. When Tr23 is turned on by the erasing scanning line 21 after a predetermined period has passed in this state, the capacitive element Cs16 is discharged, the light emitting element is non-light emitting, and low gradation display can be performed.

Specifically, a high signal is input from the erasing signal line 21 to the Tr 26 of the pixel that performs low gradation display, and the erasing Cs 27 holds the state in which the Tr 22 is turned on.
On the other hand, a low signal is input to the Tr 26 of the pixel that performs high gradation display, and the erasing Cs 27 holds the state in which the Tr 22 is turned off. After a predetermined period of time has elapsed in this state, when the erasing scanning lines are sequentially selected and both the Trs 22 and 23 are turned on, the light emitting element does not emit light. That is, in this embodiment, the control is performed by selecting the erasing scanning line at the erasing timing.

  As in the first to third embodiments, an analog voltage corresponding to each gradation is input to the Tr 14 from the signal line 10, charges corresponding to the analog voltage are accumulated in the capacitor Cs16, and light is emitted when the Tr 17 is turned on. The element 12 emits light with a desired luminance.

  With such a lighting period control circuit of this embodiment, it is not necessary to synchronize the erase signal from the erase signal line and the timing at which the erase scan line is selected, so that the drive circuit can be controlled easily. Can do.

(Embodiment 5)
In this embodiment mode, a pixel structure in which a lighting period control circuit is provided as illustrated in FIG. 1B will be described with reference to FIG.

In FIG. 5, the light emitting element 12 provided at the intersection of the signal line 10 and the scanning line 11, the driving transistor 17 connected to the light emitting element 12 through the lighting period control circuit 18, and the signal line 10 And a switching transistor Tr14 connected to the scanning line 11, a pixel that holds an analog voltage input through the Tr14, and includes a capacitive element 16 provided between the gate electrode of the Tr17 and the power supply line 15 The configuration is shown. The lighting period control circuit 18 is connected to the transistors Tr32 connected to the scanning line 11 and the erasing signal line 20, Tr32 and Tr17, Tr30 and 31 connected in parallel to each other, and the gate electrode of Tr30. It has an erasing scanning line 21 connected, and an erasing capacitive element Cs17 connected to the Tr 32 and the power supply line 15.
Note that in this embodiment, Tr30 and 31 are p-channel transistors, and Tr32 is an n-channel transistor.

  The operation of such a pixel configuration will be described. Note that the operation in which the analog voltage is input from the signal line and the light emitting element 12 emits light with a predetermined luminance based on the charge held in the Cs 16 is the same as in Embodiments 1 to 4.

  First, the case of low gradation display will be described. When the scanning line 11 is selected, Tr32 is turned on simultaneously with Tr14. Then, an erasing signal is input from the erasing signal line 20, and electric charge is held in the erasing capacitive element Cs27. That is, a high signal is input as an erasing signal, and the charge for turning off Tr31 is accumulated in Cs27. At this time, Tr17 is turned on, and the light emitting element 12 emits light with a predetermined luminance based on the electric charge accumulated in Cs16. Next, in the erasing operation, when the erasing scanning line 21 is sequentially selected and a High signal is input, the p-channel Tr 31 is turned off, and the light emitting element does not emit light.

  On the other hand, when high gradation display is performed, the charge that turns on Tr31 is held in Cs27. Therefore, even when the erasing scanning line 21 is selected, a High signal is input, and the Tr 30 is turned off, the light emitting element emits light.

  Thus, by arranging the lighting period control circuit between the light emitting element 12 and the driving transistor Tr17, even if the characteristic of Tr17 is normally on, the light emitting element accurately emits no light.

  In FIG. 5, Tr14 and Tr27 are connected to a common scanning line, but may be connected to different scanning lines. In this case, as in the second embodiment, the light emitting element does not emit light when the timing for selecting the erasing signal line and the erasing scanning line is synchronized.

(Embodiment 6)
The voltage input method has been described so far, but the present invention can also be applied to the current input method. The current input method is a method in which the luminance of a light-emitting element is controlled by passing a current (also referred to as a signal current) as a video signal through the light-emitting element. In the case of the current input method, multiple gradations are displayed according to the value of the signal current flowing to the light emitting element. Therefore, in this embodiment, the case where the lighting period control circuit is applied to a current input type pixel to which an analog current is supplied as a video signal will be described.

  FIG. 6 shows an example of a current input type pixel, which is provided between the switch Sw41 connected to the signal line 10, the drive transistor Tr17 connected to Sw41, and the gate electrode of Tr17 and the power supply line 15. Capacitance element Cs16, lighting period control circuit 18 provided at both ends of Cs16, Sw42 connected to light emitting element 12, gate electrode of Tr17, Cs16, lighting period control circuit 18, and Sw43 provided between Sw42 Have.

  In the case of such a current input type pixel, a very small current is input from the signal line when performing low gradation display. Then, there is a possibility that an accurate current value cannot be supplied due to wiring resistance such as a signal line. However, by providing a lighting period control circuit as in the present invention, a lighting period can be controlled by supplying a current larger than a predetermined current value, writing speed is improved, and accurate low gradation display is performed. It becomes possible.

  FIG. 7 shows a pixel configuration of a current input method different from that in FIG. A switch Sw41 connected to the signal line 10, a transistor Tr35 connected to Sw41, a Tr36 that forms a current mirror with Tr35, a common gate electrode of Tr35 and Tr36, a Sw44 connected to Sw41, and a Tr35 It has the common gate electrode of Tr36, the capacitive element Cs16 connected to the power supply line 15, the lighting period control circuit 18 connected to both ends of Cs16, and the light emitting element 12 connected to Tr36.

  In a pixel configuration having such a current mirror circuit, when low gradation display is performed, there is a concern that the current input via the signal line 10 becomes very small as in FIG. However, by providing a lighting period control circuit as in the present invention, a large current value can be passed even when low gradation display is performed.

  As described above, the lighting period control circuit of the present invention can be applied to any current input type pixel, and the lighting period control circuit may employ any of the configurations of Embodiments 1 to 5.

(Embodiment 7)
In this embodiment mode, an overall structure including pixels to which the lighting period control circuit in FIG. 2 is applied will be described.

  8 includes Sw 804 and 805 respectively connected to wirings to which an erasing signal and a video signal are input, and a shift register 800 that controls on / off of the Sw 804 and 805. The video signal is input to the signal line 10 via Sw805.

  In addition, an initialization power supply line 808 and an initialization signal line 809 are provided, and Sw 806 is provided between the initialization power supply line 808 and Sw 804. The selection shift register 802 includes a flip-flop circuit and the like, and has a function of controlling the scanning lines 11 to be sequentially selected. Similarly, the erasing shift register 801 has a Philip flop circuit and the like, and has a function of controlling the erasing scanning lines 21 to be sequentially selected. However, an AND circuit 807 to which a pulse width signal is input is provided between the erasing shift register 801 and the erasing scanning line 21.

  Next, the reason why the AND circuit is provided will be described. In the pixel configuration shown in FIG. 2, when the erase scanning line 21 is selected and the signal for turning on the Tr 22 is input to the erase signal line 20, the charge of the capacitive element Cs16 is discharged. That is, if the signal to be erased in the previous row is held as it is in the erasing signal line 20, the charge of Cs16 is discharged, and the erasing signal line 20 is turned off after the erasing scanning line 21 is selected. Even if a signal is input, the charge does not return. Therefore, when an erasing scanning line in a certain row is selected, it is necessary to initialize the potentials of the erasing signal lines in all columns at one end so that the charge of the capacitor Cs16 is not discharged. For this reason, an AND circuit 807 to which a pulse width signal is input is provided. Further, an initialization power supply line 808 and an initialization signal line 809 are provided, and the initialization signal is set to be input before the erasing scanning line 21 is selected.

  A timing chart of such operation will be described. FIG. 9 shows low gradation display for the pixels in (i + 1) th row, first column, ith row, jth column, ith row (j + 1) th column, (i + 1) th row (j + 1) th column, that is, a lighting period. An example of shortening is shown. First, the timing at which the erasing scanning line in the i-th row and the (i + 1) -th row is selected and the timing at which the initialization signal line is selected will be described. A pulse width signal is input from the erasing shift register 801 to one terminal of the AND circuit 807. Another pulse width signal is input to the other terminal of the AND circuit 807. The AND circuit outputs a high signal only when a high signal is input from both terminals. Therefore, the selection of the erasing scan line is controlled so that the timing of selecting the initialization signal line and the timing of non-selection of the erasing scan line are synchronized with the timing of inputting a low signal as another pulse width signal. . As a result, before the erase scanning line of each row is selected, a period in which a high signal is input from the initialization signal line and the erase scanning line for initializing the potential of the erase signal line is not selected is provided. be able to.

  An erasing signal input to each pixel for low gradation display, the first column, the jth column, and the (j + 1) th column will be described. The erase signal is written in order from the erase signal line when the lighting period is erased. A high erasing signal is input before the erasing scanning line of a predetermined pixel to be erased is selected. In other words, in the erase operation period, when the erase signal line for the first column is selected as the erase scan line for the (i + 1) th row, the erase scan line for the jth column is selected for the erase signal line for the jth column. When the erasing signal line in the (j + 1) th column is selected, High is input as the erasing signal when the erasing scanning line in the i-th row and the (i + 1) -th row is selected. In synchronization with the selection of the erasing scanning line and the erasing signal from the erasing signal line, the light emitting element does not emit light.

  In this manner, the light emitting element is made non-light emitting in each pixel, and low gradation display can be performed.

(Embodiment 8)
In this embodiment mode, an overall structure including pixels to which the lighting period control circuit of FIG. 4 is applied will be described.

  10 includes Sw 804 and 805 connected to wirings to which an erasing signal and a video signal are input, and a shift register 800 that controls on / off of the Sw 804 and 805, respectively. Further, an erasing shift register 801 for controlling selection of the erasing scanning line 21 and a selection shift register 802 for controlling selection of the scanning line 11 are provided. The video signal is input to the signal line 10 via Sw805.

  In such a pixel configuration, a video signal and an erasure signal may be input. Therefore, there is no need to provide a switch or other logic circuits, and the configuration of the display device can be simplified.

(Embodiment 9)
In this embodiment, another effect of providing a lighting period control circuit in each pixel will be described.

  When the multi-grayscale display is performed by using the digital grayscale method as described above and applying the time grayscale method using a subframe obtained by dividing one frame, a problem of pseudo contour occurs. Therefore, by using the lighting period control circuit of the present invention, the order of subframes is changed for each pixel to prevent false contours. For example, control is performed so that the order of the subframes, the time at which the subframe period starts or ends, and the like are changed in each row and further in each pixel so that light emission and non-light emission occur randomly in each pixel. As a result, the area of the portion where light emission or non-light emission continues is reduced to reduce the pseudo contour recognized by the human eye.

  Specifically, as shown in FIG. 13, a case where the lighting period control circuit changes the end of the lighting period in the subframe between the kth row and the (k + 1) th row will be described.

  FIG. 13A shows a timing chart in which one frame: T is divided into four subframe periods: t1 to t4, and 4-bit, 16 gradation display is performed. Referring to FIG. 13A, each of the period t1 to t4 has a writing operation period Tw1 to Tw4 in which writing is performed from the signal line, and an erasing operation Te is provided in the period t1 and t4.

  FIG. 13B shows the state of the k-th row and the (k + 1) -th row in the case of 16 gradations, that is, white display that emits light in all subframe periods. In the t1 period, writing Tw1 is performed in the k-th row, and the lighting period Ta1 is reached. At this time, in the (k + 1) th row, writing Tw1 is similarly performed, and then erasing is performed by the erasing operation Te, and the lighting period Ta4 is entered. In the t2 period, the writing Tw2 is performed in the k-th row, and the lighting period Ta2. At this time, in the (k + 1) th row, writing Tw2 is similarly performed and the lighting period Ta2 is reached. In the t3 period, writing Tw3 is performed in the k-th row, and the lighting period Ta3 is reached. At this time, in the (k + 1) th row, the writing Tw3 is similarly performed and the lighting period Ta3 is reached. In the t4 period, writing Tw4 is performed in the k-th row, and then erasing is performed by the erasing operation Te, and the lighting period Ta4 is entered. At this time, in the (k + 1) th row, the writing Tw4 is similarly performed and the lighting period Ta1 is reached.

  Further, the order of the lighting periods may be changed in the same manner even in cases other than the white display. Further, the order of the lighting periods may be changed in the same manner for other than 16 gradations.

  Specifically, in the erasing operation period, erasing scanning lines are sequentially selected. At this time, when an erase signal is input from the erase signal line, no light is emitted. Therefore, the length of the lighting period can be controlled, and as a result, the order of the lighting periods can be changed. In FIG. 13, the lighting time of the lighting period Ta4 can be changed greatly depending on the row.

  In FIG. 13, erase operations are provided at two locations. For example, a lighting period control circuit as shown in FIG. 3 may be used. Of course, any lighting period control circuit other than FIG. 3 can be used.

  FIG. 14A shows a timing chart in which one frame: T is divided into five subframe periods: t1 to t5 and 32 gradation display is performed. At this time, a second erase operation SE is provided. When the time gray scale method is used, multiple gray scales are displayed, that is, as the subframe becomes shorter, the duty ratio becomes lower. Therefore, an erasing period SE can be provided, the light emitting element can be made non-light emitting, a writing operation period can be provided, and a reduction in duty ratio can be prevented.

  Referring to FIG. 14A, each of the period t1 to t5 has a writing operation period Tw1 to Tw5 in which writing is performed from the signal line, and in the period t1, t3 and t5, the first erasing operation Te and t4 period. Is provided with a second erase operation SE.

  FIG. 14B shows the state of the k-th row and the (k + 1) -th row in the case of white display that emits light in 32 gradations, that is, in all subframe periods. In the t1 period, writing Tw1 is performed in the k-th row, and the lighting period Ta1 is reached. At this time, in the (k + 1) th row, writing Tw1 is similarly performed, and then erasing is performed by the first erasing operation Te, and the lighting period Ta3 is entered. In the t2 period, the writing Tw2 is performed in the k-th row, and the lighting period Ta2. At this time, in the (k + 1) th row, writing Tw2 is similarly performed and the lighting period Ta2 is reached. In the t3 period, writing Tw3 is performed in the k-th row, and the lighting period Ta3 is reached. At this time, in the (k + 1) th row, writing Tw3 is similarly performed, and then erasing is performed by the first erasing operation Te, and the lighting period Ta5 is entered. In the t4 period, writing Tw4 is performed in the k-th row, and then erasing is performed in the erasing period SE, and the lighting period Ta4 is reached. At this time, in the (k + 1) th row, writing Tw4 is similarly performed, and then erasing is performed in the erasing period SE, and the lighting period Ta4 is reached. In the period t5, writing Tw5 is performed in the k-th row, and then erasing is performed in the first erasing operation Te, and the lighting period Ta5 is entered. At this time, in the (k + 1) th row, the writing Tw5 is similarly performed, and the lighting period Ta1 is reached.

  Moreover, what is necessary is just to change the order of a lighting period similarly except white display. Furthermore, the order of the lighting periods may be changed in the same way for displays other than 32 gradations.

  Specifically, in the erasing operation period, the erasing scanning lines are sequentially selected. At this time, when an erase signal is input from the erase signal line, no light is emitted. Therefore, the length of the lighting period can be controlled, and as a result, the order of the lighting periods can be changed.

  In FIG. 14, three first erase operations are provided. For example, if a lighting period control circuit as shown in FIG. 3 is applied to increase the number of erase scan lines, erase signal lines, and transistors, Good. Furthermore, other lighting period control circuits may be applied.

  Note that the order of replacing the subframes and the number of erasing operations are not limited to those shown in FIGS. Further, any of the lighting period control circuits shown in Embodiment Modes 1 to 5 may be used.

  As described above, the pseudo contour can be prevented by changing the order of the lighting periods in each row, that is, by changing the end of the lighting period. Further, the order of the lighting periods may be changed in each row, each column, and each pixel. In particular, it is preferable to prevent the pseudo contour by changing the order of the lighting periods in adjacent pixels.

(Embodiment 10)
The active matrix substrate manufactured according to the present invention can be applied to various electronic devices. Examples of the electronic device include a portable information terminal (a mobile phone, a mobile computer, a portable game machine, an electronic book, etc.), a video camera, a digital camera, a goggle type display, a display display, a navigation system, and the like. Specific examples of these electronic devices are shown in FIGS.

  FIG. 12A illustrates a display, which includes a housing 4001, an audio output portion 4002, a display portion 4003, and the like. According to the present invention, the display portion 4003 having a light emitting element can be completed. The display device includes all information display devices such as a personal computer, a TV broadcast reception, and an advertisement display.

  FIG. 12B illustrates a mobile computer, which includes a main body 4101, a stylus 4102, a display portion 4103, operation buttons 4104, an external interface 4105, and the like. According to the present invention, the display portion 4103 having a light emitting element can be completed.

  FIG. 12C illustrates a game machine, which includes a main body 4201, a display portion 4202, operation buttons 4203, and the like. In accordance with the present invention, the display portion 4202 having a light-emitting element can be completed. FIG. 12D illustrates a cellular phone, which includes a main body 4301, an audio output portion 4302, an audio input portion 4303, a display portion 4304, operation switches 4305, an antenna 4306, and the like. According to the present invention, the display portion 4304 having a light emitting element can be completed.

  FIG. 12E illustrates an electronic book reader that includes a display portion 4401 and the like. In accordance with the present invention, the display portion 4202 having a light-emitting element can be completed.

  As described above, the applicable range of the present invention is so wide that the present invention can be used for electronic devices in various fields. In particular, thin and light weight can be realized by using a flexible substrate as the insulating substrate of the active matrix substrate.

Claims (9)

A display device including first to third signal lines, first to third scanning lines, a power supply line, first to sixth transistors, a capacitor element, and a light emitting element.
A gate of the first transistor is connected to the first scan line;
One of the source and the drain of the first transistor is connected to the first signal line,
The other of the source and the drain of the first transistor is connected to one of the electrodes of the capacitor,
A gate of the second transistor is connected to the other of the source and the drain of the first transistor;
One of the source and the drain of the second transistor is connected to the power line,
The other of the source and the drain of the second transistor is connected to the light emitting element,
A gate of the third transistor is connected to the second signal line;
One of the source and the drain of the third transistor is connected to one of the electrodes of the capacitor,
The other of the source and the drain of the third transistor is connected to one of the source and the drain of the fourth transistor;
A gate of the fourth transistor is connected to the second scanning line;
The other of the source and the drain of the fourth transistor is connected to the other of the electrodes of the capacitor,
A gate of the fifth transistor is connected to the third signal line;
One of the source and the drain of the fifth transistor is connected to one of the electrodes of the capacitor,
The other of the source and the drain of the fifth transistor is connected to one of the source and the drain of the sixth transistor;
A gate of the sixth transistor is connected to the third scanning line;
The display device is characterized in that the other of the source and the drain of the sixth transistor is connected to the other of the electrodes of the capacitor.   2. The display device according to claim 1, wherein the first transistor and the third to sixth transistors are n-channel transistors, and the second transistor is a p-channel transistor.   3. The display device according to claim 1, wherein the third to sixth transistors constitute a circuit for controlling a lighting period of the light emitting element. A display having first and second signal lines, first and second scanning lines, a power supply line, first to fifth transistors, first and second capacitor elements, and a light emitting element. A device,
A gate of the first transistor is connected to the first scan line;
One of the source and the drain of the first transistor is connected to the first signal line,
The other of the source and the drain of the first transistor is connected to one of the electrodes of the first capacitor,
A gate of the second transistor is connected to the other of the source and the drain of the first transistor;
One of the source and the drain of the second transistor is connected to the power line,
The other of the source and the drain of the second transistor is connected to the light emitting element,
A gate of the third transistor is connected to the first scanning line;
One of the source and the drain of the third transistor is connected to the second signal line,
The other of the source and the drain of the third transistor is connected to one of the electrodes of the second capacitor,
A gate of the fourth transistor is connected to the other of the source and the drain of the third transistor;
One of the source and the drain of the fourth transistor is connected to one of the electrodes of the first capacitor,
The other of the source and the drain of the fourth transistor is connected to one of the source and the drain of the fifth transistor,
A gate of the fifth transistor is connected to the second scanning line;
The other of the source and the drain of the fifth transistor is connected to the other of the electrodes of the first capacitor.   5. The display device according to claim 4, wherein the first transistor and the third to fifth transistors are n-channel transistors, and the second transistor is a p-channel transistor.   6. The display device according to claim 4, wherein the third to fifth transistors and the second capacitor element form a circuit for controlling a lighting period of the light emitting element. A display having first and second signal lines, first and second scanning lines, a power supply line, first to fifth transistors, first and second capacitor elements, and a light emitting element. A device,
A gate of the first transistor is connected to the first scan line;
One of the source and the drain of the first transistor is connected to the first signal line,
The other of the source and the drain of the first transistor is connected to one of the electrodes of the first capacitor,
A gate of the second transistor is connected to the other of the source and the drain of the first transistor;
One of the source and the drain of the second transistor is connected to the power line,
The other of the source and drain of the second transistor is connected to one of the source and drain of the fourth transistor and one of the source and drain of the fifth transistor;
A gate of the third transistor is connected to the first scanning line;
One of the source and the drain of the third transistor is connected to the second signal line,
The other of the source and the drain of the third transistor is connected to one of the electrodes of the second capacitor,
A gate of the fourth transistor is connected to the other of the source and the drain of the third transistor;
The other of the source and the drain of the fourth transistor is connected to the light emitting element,
A gate of the fifth transistor is connected to the second scanning line;
The other of the source and the drain of the fifth transistor is connected to the light emitting element.   8. The method according to claim 7, wherein the first transistor and the third transistor are n-channel transistors, and the second transistor, the fourth transistor, and the fifth transistor are p-channel transistors. Characteristic display device.   9. The display device according to claim 7, wherein the third to fifth transistors and the second capacitor element form a circuit for controlling a lighting period of the light emitting element.

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