JP4566523B2 - Display device - Google Patents

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JP4566523B2
JP4566523B2 JP2003138326A JP2003138326A JP4566523B2 JP 4566523 B2 JP4566523 B2 JP 4566523B2 JP 2003138326 A JP2003138326 A JP 2003138326A JP 2003138326 A JP2003138326 A JP 2003138326A JP 4566523 B2 JP4566523 B2 JP 4566523B2
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Prior art keywords
current
transistor
current source
pixel
source circuit
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JP2004046129A (en
JP2004046129A5 (en
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肇 木村
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株式会社半導体エネルギー研究所
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Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device using a light emitting element and a driving method thereof. In particular, the present invention relates to an active matrix display device in which a light emitting element is provided for each pixel and a transistor for controlling light emission of the light emitting element is provided, and a driving method thereof.
[0002]
[Prior art]
Development of a display device having a light emitting element has been advanced in recent years. In particular, an active matrix display device in which a light-emitting element and a transistor for controlling light emission of the light-emitting element are provided for each pixel has been developed.
[0003]
In the active matrix display device, either a method of inputting luminance information to each pixel by a voltage signal or a method of using a current signal is mainly used. The former is called a voltage writing type, and the latter is called a current writing type. These configurations and driving methods will be described in detail below.
[0004]
First, an example of a voltage writing type pixel is shown in FIG. 26, and its configuration and driving method will be described. Each pixel is provided with two TFTs (selection TFT 3001 and drive TFT 3004), a storage capacitor 3007, and an EL element 3006. Here, the first electrode 3006a of the EL element 3006 is referred to as a pixel electrode, and the second electrode 3006b is referred to as a counter electrode.
[0005]
A method for driving the pixel will be described. When the selection TFT 3001 is turned on by a signal input to the gate signal line 3002, charges are accumulated and held in the storage capacitor 3007 by the voltage of the video signal input to the source signal line 3003. An amount of current corresponding to the charge held in the storage capacitor 3007 flows from the power supply line 3005 to the EL element 3006 through the driving TFT 3004, and the EL element 3006 emits light.
[0006]
In a voltage writing type pixel, a video signal input to the source signal line 3003 may be an analog method or a digital method. Driving using an analog video signal is called an analog system, and driving using a digital video signal is called a digital system.
[0007]
In the voltage writing analog method, the gate voltage (gate-source voltage) of the driving TFT 3004 of each pixel is controlled by an analog video signal. Then, a drain current having a value corresponding to the gate voltage flows through the EL element 3006, whereby the luminance is controlled and the gray scale is displayed. Therefore, in general, in the voltage writing type analog method, in order to display a halftone, the driving TFT 3004 is operated in a region where the change of the drain current is large with respect to the gate voltage.
[0008]
On the other hand, in the voltage writing digital method, the EL element 3006 is selected to emit light by using a digital video signal, thereby controlling the light emission period of the EL element and displaying the gradation. That is, the driving TFT 3004 serves as a switch. Therefore, in general, in the voltage writing digital method, when the EL element 3006 is caused to emit light, the driving TFT 3004 is operated in a linear region, more specifically, in a region where the absolute value of the gate voltage is particularly large in the linear region.
[0009]
The operation region of the driving TFT in the voltage writing digital method and the voltage writing analog method will be described in detail with reference to FIG. FIG. 27A illustrates only the driving TFT 3004, the power supply line 3005, and the EL element 3006 in the pixel illustrated in FIG. 26 for simplicity. Each of the curves 3101a and 3101b in FIG. 27B indicates the value of the drain current Id with respect to the gate voltage Vgs of the driving TFT 3004. A curve 3101b indicates a characteristic when the threshold voltage of the driving TFT 3004 changes with respect to the curve 3101a.
[0010]
In the voltage writing analog method, the driving TFT 3004 operates in the operation region indicated by (1) in the figure. In the operating region (1), the gate voltage V gs1 When the current characteristics of the driving TFT 3004 vary from 3101a to 3101b when the voltage is applied, the drain current becomes I d1 To I d2 To change. That is, the voltage writing analog method has a problem that the luminance of the EL element 3006 varies between pixels because the drain current varies when the current characteristics of the driving TFT 3004 vary.
[0011]
On the other hand, the driving TFT in the voltage writing type digital system operates in the operation region indicated by (2) in the figure. The operation area (2) corresponds to a linear area. The driving TFT 3004 operating in the linear region has the same gate voltage V gs2 Is applied, the variation in drain current due to the variation in characteristics such as mobility and threshold voltage is small, and a substantially constant current I d3 Shed. Therefore, in the voltage writing digital method in which the driving TFT 3004 operates in the operation region (2), even if the current characteristics of the driving TFT 3004 vary from 3101a to 3101b, the current flowing through the EL element 3006 is difficult to vary, and the light emission luminance also varies. It can be suppressed.
[0012]
Therefore, it can be said that the variation in luminance of the EL element due to the variation in the current characteristics of the driving TFT 3004 is smaller in the voltage writing digital method than in the voltage writing analog method.
[0013]
Next, a structure and a driving method of a current writing type pixel will be described.
[0014]
In a current writing type display device, a current (signal current) of a video signal is input to each pixel from a source signal line. The signal current has a current value corresponding to a linear shape in luminance information. The input signal current becomes a drain current of a TFT included in the pixel. The gate voltage of the TFT is held in the capacitor portion of the pixel. Even after the signal current is not input, the drain current of the TFT is kept constant by the held gate voltage, and the EL element emits light by inputting the drain current to the EL element. Thus, in the current writing type display device, the current flowing through the EL element is changed by changing the magnitude of the signal current, and the light emission luminance of the EL element is controlled to express gradation.
[0015]
Hereinafter, two configurations of the current writing type pixel will be exemplified, and the configuration and the driving method will be described in more detail.
[0016]
[Patent Document 1]
JP-T-2002-517806
[Non-Patent Document 1]
IDW'00 p235-p238: Active Matrix PolyLED Displays
[0017]
FIG. 28 shows a configuration of a pixel described in Patent Document 1 and Non-Patent Document 1. A pixel illustrated in FIG. 28 includes an EL element 3306, a selection TFT 3301, a driving TFT 3303, a storage capacitor 3305, a storage TFT 3302, and a light emitting TFT 3304. Reference numeral 3307 denotes a source signal line, 3308 denotes a first gate signal line, 3309 denotes a second gate signal line, 3310 denotes a third gate signal line, and 3311 denotes a power supply line. The current value of the signal current input to the source signal line 3307 is controlled by the video signal input current source 3312.
[0018]
A driving method of the pixel in FIG. 28 will be described with reference to FIG. In FIG. 29, the selection TFT 3301, the holding TFT 3302, and the light emitting TFT 3304 are illustrated as switches.
[0019]
In the period TA1, the selection TFT 3301 and the holding TFT 3302 are turned on. At this time, the power supply line 3311 is connected to the source signal line 3307 through the driving TFT 3303 and the storage capacitor 3305. The source signal line 3307 has a current amount I determined by the video signal input current source 3312. Video Flows. Therefore, when the time has passed and the steady state is reached, the drain current of the driving TFT 3303 is I Video It becomes. The drain current I Video The gate voltage corresponding to is held in the holding capacitor 3305. The drain current of the driving TFT 3303 is I Video Then, the period TA2 is started and the holding TFT 3302 is turned off.
[0020]
Next, a period TA3 is started, and the selection TFT 3301 is turned off. Further, when the light emitting TFT 3304 is turned on in the period TA4, the signal current I Video Is input to the EL element 3306 from the power supply line 3311 through the driving TFT 3303. Thus, the EL element 3306 has the signal current I Video It emits light with a brightness corresponding to. In the pixel shown in FIG. 28, the signal current I Video The gradation can be expressed by changing the signal in an analog manner.
[0021]
In the above current writing type display device, the drain current of the driving TFT 3303 is determined by the signal current input from the source signal line 3307, and the driving TFT 3303 operates in the saturation region. Therefore, the gate voltage of the driving TFT 3303 automatically changes so that a constant drain current flows through the light emitting element even if the characteristics of the driving TFT 3303 vary. Thus, in the current writing type display device, variation in current flowing through the EL element can be suppressed even if the TFT characteristics vary. As a result, variation in emission luminance can be suppressed.
[0022]
Next, another example of the current writing type pixel which is different from FIG. 28 will be described. FIG. 30A shows a pixel described in Patent Document 2 below.
[0023]
[Patent Document 2]
JP 2001-147659 A
[0024]
A pixel shown in FIG. 30A includes an EL element 2906, a selection TFT 2901, a driving TFT 2903, a current TFT 2904, a storage capacitor 2905, a storage TFT 2902, a source signal line 2907, a first gate signal line 2908, and a second gate signal line 2909. The power line 2911 is configured. The driving TFT 2903 and the current TFT 2904 need to have the same polarity. Here, for simplicity, I of the driving TFT 2903 and the current TFT 2904 d -V gs Assume that the characteristics (relationship between drain current and gate-source voltage) are the same. The current value of the signal current input to the source signal line 2907 is controlled by the video signal input current source 2912.
[0025]
A method for driving the pixel illustrated in FIG. 30A will be described with reference to FIGS. Note that in FIGS. 30B to 30D, the selection TFT 2901 and the holding TFT 2902 are illustrated as switches.
[0026]
When the selection TFT 2901 and the holding TFT 2902 are turned on in the period TA1, the power supply line 2911 is connected to the source signal line 2907 through the current TFT 2904, the selection TFT 2901, the holding TFT 2902, and the holding capacitor 2905. The source signal line 2907 has a current amount I determined by the video signal input current source 2912. Video Flows. For this reason, when sufficient time has passed and the steady state is reached, the drain current of the current TFT 2904 becomes I Video And the drain current I Video Is held in the holding capacitor 2905.
[0027]
The drain current of the current TFT 2904 is I Video Then, the period TA2 is started and the holding TFT 2902 is turned off. At this time, the driving TFT 2903 has I Video The drain current is flowing. Thus, the signal current I Video Is input to the EL element 2906 from the power supply line 2911 through the driving TFT 2903. The EL element 2906 has a signal current I Video It emits light with a brightness corresponding to.
[0028]
Next, when the period TA3 is started, the selection TFT 2901 is turned off. Even after the selection TFT 2901 is turned off, the signal current I Video Is continuously input to the EL element 2906 from the power supply line 2911 through the driving TFT 2903, and the EL element 2906 continues to emit light. The pixel shown in FIG. 30A has a signal current I Video The gradation can be expressed by changing the signal in an analog manner.
[0029]
In the pixel illustrated in FIG. 30A, the driving TFT 2903 operates in a saturation region.
The drain current of the driving TFT 2903 is determined by the signal current input from the source signal line 2907. Therefore, if the current characteristics of the drive TFT 2903 and current TFT 2904 in the same pixel are aligned, the gate voltage of the drive TFT 2903 is automatically set so that a constant drain current continues to flow through the light emitting element even if the characteristics of the drive TFT 2903 vary. Changes.
[0030]
[Problems to be solved by the invention]
In an EL element, the relationship between the voltage between the electrodes and the amount of current flowing (IV characteristics) changes due to the influence of environmental temperature, deterioration with time, and the like. Therefore, in a display device that operates the driving TFT in the linear region as in the voltage writing digital method described above, even if the voltage value between the electrodes of the EL element is the same, the amount of current flowing between the electrodes of the EL element Will fluctuate.
[0031]
FIG. 31 is a diagram showing a change in operating point when the IV characteristic of the EL element is changed due to deterioration or the like in the voltage writing type digital system. In FIG. 31, the same parts as those in FIG.
[0032]
FIG. 31A shows only the driving TFT 3004 and the EL element 3006 extracted from FIG. The source-drain voltage of the driving TFT 3004 is V ds It shows with. The voltage between both electrodes of the EL element 3006 is V EL It shows with. The current flowing through the EL element 3006 is I EL It shows with. Current I EL Is the drain current I of the drive TFT 3004 d be equivalent to. The potential of the power supply line 3005 is V dd It shows with. In addition, the potential of the counter electrode of the EL element 3006 is 0 (V).
[0033]
In FIG. 31B, 3202a indicates the voltage V of the EL element 3006 before deterioration. EL And current amount I EL It is a curve which shows the relationship (IV characteristic). On the other hand, 3202b is a curve showing the IV characteristics of the EL element 3006 after deterioration. 3201 indicates that the gate voltage in FIG. gs2 The voltage V between the source and drain of the driving TFT 3004 in the case of ds And drain current I d (I EL ). The operating conditions (operating points) of the driving TFT 3004 and the EL element 3006 are determined by the intersection of these two curves. That is, the operating conditions of the driving TFT 3004 and the EL element 3006 before deterioration of the EL element 3006 are determined by the intersection 3203a of the curve 3202a and the curve 3201 in the linear region shown in the drawing. In addition, the operating conditions of the drive TFT 3004 and the EL element 3006 after deterioration of the EL element 3006 are determined by the intersection 3203b of the curve 3202b and the curve 3201 in the linear region shown in the drawing. The operating points 3203a and 3203b are compared.
[0034]
In the pixel for which the light emitting state is selected, the driving TFT 3004 is on. At this time, the voltage between both electrodes of the EL element 3006 is V A1 It is. When the EL element 3006 deteriorates and its IV characteristic changes, the voltage between both electrodes of the EL element 3006 becomes V. A1 Is almost the same as EL1 To I EL2 To change. In other words, the current flowing through the EL element 3006 depends on the degree of deterioration of the EL element 3006 of each pixel. EL1 To I EL2 Therefore, the emission luminance varies.
[0035]
As a result, image sticking tends to occur in a display device having a type of pixel in which the driving TFT is operated in a linear region.
[0036]
On the other hand, in the current writing type pixels shown in FIGS. 28 and 30, the image burn-in is reduced. This is because in a current writing type pixel, the driving TFT always operates so as to pass a substantially constant current.
[0037]
In the current writing type pixel, the change in the operating point when the IV characteristic of the EL element changes due to deterioration or the like will be described by taking the pixel in FIG. FIG. 32 is a diagram showing a change in the operating point when the IV characteristic of the EL element is changed due to deterioration or the like in the current writing type. In FIG. 32, the same parts as those in FIG.
[0038]
FIG. 32A illustrates only the driving TFT 3303 and the EL element 3306 in FIG. The voltage between the source and drain of the driving TFT 3303 is V ds It shows with. The voltage between the cathode and anode of the EL element 3306 is V EL It shows with. The current flowing through the EL element 3306 is expressed as I EL It shows with. Current I EL Is the drain current I of the driving TFT 3303 d be equivalent to. The potential of the power supply line 3305 is V dd It shows with. In addition, the potential of the counter electrode of the EL element 3306 is 0 (V).
[0039]
In FIG. 32B, reference numeral 3701 denotes a curve showing the relationship between the source-drain voltage and the drain current of the driving TFT 3303. 3702a is a curve showing the IV characteristic of the EL element 3306 before deterioration. On the other hand, 3702b is a curve showing the IV characteristic of the EL element 3306 after deterioration. The operating conditions of the driving TFT 3303 and the EL element 3306 before deterioration of the EL element 3306 are determined by an intersection 3703a of the curve 3702a and the curve 3701. The operating conditions of the driving TFT 3303 and the EL element 3306 after deterioration of the EL element 3306 are determined by an intersection 3703b of the curve 3702b and the curve 3701. Here, the operating points 3703a and 3703b are compared.
[0040]
In the current writing type pixel, the driving TFT 3303 operates in a saturation region. Before and after the deterioration of the EL element 3306, the voltage between both electrodes of the EL element 3306 is V B1 To V B2 However, the current flowing through the EL element 3306 is substantially constant I EL1 To be kept. Thus, even when the EL element 3306 deteriorates, the current flowing through the EL element 3306 is kept substantially constant. Therefore, the problem of image burn-in is reduced.
[0041]
However, in the conventional current writing type driving method, it is necessary to hold the charge corresponding to the signal current in the holding capacitor of each pixel. The operation of holding a predetermined charge in the holding capacitor requires a longer time as the signal current is smaller due to the cross capacitance of the wiring through which the signal current flows. Therefore, it is difficult to write signal current quickly. When the signal current is small, the influence of noise such as leakage current generated from a plurality of pixels connected to the same source signal line as the pixel to which the signal current is written is large. Therefore, there is a high risk that the pixel cannot emit light with accurate luminance.
[0042]
Further, in a pixel having a current mirror circuit typified by the pixel shown in FIG. 30, it is desirable that current characteristics of a pair of TFTs constituting the current mirror circuit are uniform. However, in practice, it is difficult to completely align the current characteristics of these paired TFTs, resulting in variations.
[0043]
In the pixel shown in FIG. 30, the threshold values of the driving TFT 2903 and the current TFT 2904 are V tha , V thb Suppose that Threshold V of both transistors tha , V thb Scatter, V tha Absolute value | V tha | Is V thb Absolute value | V thb Consider the case where black display is performed when it becomes smaller than |. The drain current flowing through the current TFT 2904 is a current value I determined by the video signal input current source 2912. Video And 0. However, even if the drain current does not flow through the current TFT 2904, | V thb There is a possibility that a voltage slightly lower than | is held. Where | V thb | > | V tha Therefore, there is a possibility that the drain current of the driving TFT 2903 is not zero. Even in the case of performing black display in this way, a drain current flows through the driving TFT 2903 and the EL element 2906 may emit light, resulting in a problem that the contrast is lowered.
[0044]
Further, in a conventional current writing type display device, a video signal input current source for inputting a signal current to each pixel is provided for each column (each pixel column). It is necessary to make the current characteristics of all these video signal input current sources uniform and to accurately change the output current value in an analog manner. However, a transistor using a polycrystalline semiconductor or the like has a large variation in transistor characteristics, and it is difficult to manufacture a video signal input current source having uniform current characteristics. Therefore, in the conventional current writing type display device, the video signal input current source is manufactured on a single crystal IC substrate. On the other hand, a substrate on which pixels are formed is generally manufactured on an insulating substrate such as glass from the viewpoint of cost and the like. Therefore, it is necessary to paste a single crystal IC substrate on which a video signal input current source is manufactured on a substrate on which pixels are formed. The display device having such a structure has a problem that the cost is high, the area required for attaching the single crystal IC substrate is large, and the area of the frame cannot be reduced.
[0045]
In view of the above circumstances, an object of the present invention is to provide a display device that can emit light from a light-emitting element with constant luminance without being affected by deterioration with time, and a driving method thereof. In addition, the present invention is capable of accurate gradation expression, can speed up video signal writing to each pixel, and suppresses the influence of noise such as leakage current, and a driving method thereof. I will provide a. Furthermore, it is an object of the present invention to provide a display device and a driving method thereof that are low in cost and have a small frame area to realize a reduction in size.
[0046]
[Means for Solving the Problems]
In order to solve the above problems, the present invention has taken the following measures.
[0047]
Each pixel included in the display device of the present invention includes a plurality of switch portions and a plurality of current source circuits. One switch unit and one current source circuit operate as a pair. There are a plurality of pairs of switch units and current source circuits in one pixel.
[0048]
Each of the plurality of switch units is selected to be turned on / off by a digital video signal. When the switch unit is turned on (conductive state), a current is supplied from the current source circuit corresponding to the switch unit to the light emitting element, and the light emitting element emits light. The current supplied from one current source circuit to the light emitting element is constant. In accordance with Kirchhoff's current law, the value of the current flowing through the light emitting element corresponds to a value obtained by adding the currents supplied to the light emitting elements from all the current source circuits corresponding to the conductive switch portions. The pixel of the present invention can express gradation by changing the value of the current flowing through the light-emitting element depending on which of the plurality of switch portions is in a conductive state. On the other hand, the current source circuit is set so as to always output a certain current. Therefore, variation in current flowing through the light emitting element can be prevented.
[0049]
The configuration and operation of the pixel of the present invention will be described with reference to FIG. 1 schematically showing the configuration of the pixel of the display device of the present invention. In FIG. 1, the pixel includes two current source circuits (current source circuit a and current source circuit b in FIG. 1), two switch portions (switch portion a and switch portion b in FIG. 1), and a light emitting element. And have. In FIG. 1, a pixel having two pairs of switch units and current source circuits in one pixel is illustrated, but the number of pairs of switch units and current source circuits in one pixel can be any number. .
[0050]
The switch part (switch part a, switch part b) has an input terminal and an output terminal. The conduction / non-conduction between the input terminal and the output terminal of the switch unit is controlled by the digital video signal. A state in which the input terminal and the output terminal of the switch unit are in a conductive state is referred to as turning on the switch unit. In addition, a state where the input terminal and the output terminal of the switch unit are in a non-conductive state is referred to as turning off the switch unit. Each switch unit is controlled to be turned on / off by a corresponding digital video signal.
[0051]
The current source circuit (current source circuit a, current source circuit b) has an input terminal and an output terminal, and has a function of flowing a constant current between the input terminal and the output terminal. The current source circuit a receives a constant current I by a control signal a. a Is controlled to flow. Further, the current source circuit b is supplied with a constant current I by the control signal b. b Is controlled to flow. The control signal may be a signal different from the video signal. The control signal may be a current signal or a voltage signal. The operation for determining the current flowing through the current source circuit by the control signal in this way is called a current source circuit setting operation or a pixel setting operation. The timing for performing the setting operation of the current source circuit may be synchronized with the operation of the switch unit or may be asynchronous, and can be set at an arbitrary timing. The setting operation may be performed only for one current source circuit, and information on the current source circuit that has performed the setting operation may be shared with other current source circuits. The setting operation of the current source circuit can suppress variations in the current output from the current source circuit.
[0052]
For example, an example of a pixel of the display device of the present invention when a control signal input to the current source circuit is a current signal will be given. The pixel is supplied with a control current, a plurality of current source circuits that output a constant current corresponding to the control current as an output current, and the output current from each of the plurality of current source circuits to the light emitting element by a digital video signal And a plurality of switch units for selecting the input of.
[0053]
Here, each of the plurality of current source circuits selectively includes a first transistor, a second transistor connected in series with the first transistor, and the control current as a drain current of the first transistor. The first means for inputting to the second transistor, the second means for holding the gate voltage of the first transistor, the third means for selecting the connection between the gate and the drain of the first transistor, and the held And a fourth means for using the drain current of the second transistor as the gate voltage that is a part of the gate voltage of the first transistor as the output current.
[0054]
Alternatively, one of the plurality of current source circuits includes a first transistor, a second transistor connected in series with the first transistor, and the control current as a drain current of the first transistor. A first means for selectively inputting; a second means for holding a gate voltage of the first transistor; a third means for selecting connection between a gate and a drain of the first transistor; And a fourth means for setting the drain current of the second transistor as the gate current to a part of the gate voltage of the first transistor as the output current,
Another one of the plurality of current source circuits includes a third transistor and a fourth transistor, fifth means for selectively inputting the control current as a drain current of the third transistor, A sixth means for holding a gate voltage of the third transistor; a seventh means for selecting connection between a gate and a drain of the third transistor; and a gate voltage of the held third transistor as a gate voltage. And an eighth means for using the drain current of the fourth transistor as the output current.
[0055]
A light emitting element means an element whose luminance changes depending on the amount of current flowing between the electrodes. Examples of the light emitting element include an EL (electroluminescence) element and an FE (Field Emission) element. However, the present invention can also be applied to the case where an arbitrary element whose state is controlled by current, voltage, or the like is used instead of the light emitting element.
[0056]
Of the two electrodes (anode and cathode) of the light emitting element, one electrode (first electrode) is electrically connected to the power line via the switch part a and the current source circuit a in this order. Further, the first electrode is electrically connected to the power supply line through the switch part b and the current source circuit b in this order. When the switch part a is turned off, the current determined by the current source circuit a is prevented from flowing between the light emitting elements, and when the switch part b is turned off, the current determined by the current source circuit b emits light. The circuit configuration is not limited to the circuit configuration in FIG. 1 as long as it does not flow between elements.
[0057]
In the present invention, one current source circuit and one switch unit are paired, and they are connected in series. In the pixel of FIG. 1, there are two pairs of such switch units and current source circuits, and these two pairs are connected in parallel to each other.
[0058]
Next, the operation of the pixel shown in FIG. 1 will be described.
[0059]
As shown in FIG. 1, in a pixel having two switch units and two current source circuits, there are a total of three paths for currents input to the light emitting elements. The first path is a path through which a current supplied from one of the two current source circuits is input to the light emitting element. The second path is a path through which the current supplied from the other current source circuit different from the current source circuit that supplied the current in the first path is input to the light emitting element. The third path is a path through which currents supplied from two current source circuits are input to the light emitting element. In the case of the third path, a current obtained by adding the currents supplied from the current source circuits is supplied to the light emitting element.
[0060]
More specifically, the first path is the current I flowing through the current source circuit a. a Only the path that is input to the light emitting element. This path is selected when the switch part a is turned on and the switch part b is turned off by the digital video signal a and the digital video signal b. The second path is the current I flowing through the current source circuit b. b Only the path that is input to the light emitting element. This path is selected when the switch part a is turned off and the switch part b is turned on by the digital video signal a and the digital video signal b. The third path is the current I flowing through the current source circuit a. a Current I flowing through the current source circuit b b And the current I a + I b Is a path inputted to the light emitting element. This path is selected when both the switch unit a and the switch unit b are turned on by the digital video signal a and the digital video signal b. That is, the current I is expressed by the digital video signal a and the digital video signal b. a + I b Will flow to the light emitting element, so that the pixel performs the same operation as the digital / analog conversion.
[0061]
Next, a basic method for gradation expression in the display device of the present invention will be described. First, a constant current flowing through each current source circuit is appropriately determined by the setting operation of the current source circuit. A plurality of current source circuits included in each pixel can set different current values for each current source circuit. Since the light emitting element emits light with luminance corresponding to the amount of current (current density) flowing, the luminance of the light emitting element can be set by controlling which current source circuit supplies the current. Therefore, the luminance of the light emitting element can be selected from a plurality of luminance levels by selecting the path of the current input to the light emitting element. Thus, the luminance of the light emitting element of each pixel can be selected from a plurality of luminance levels by the digital video signal (hereinafter, each light emitting state is selected). Note that when all the switch portions are turned off by a digital video signal, no current is input to the light emitting element, so that the luminance can be zero (hereinafter, referred to as a non-light emitting state). Thus, gradation can be expressed by changing the luminance of the light emitting element of each pixel.
[0062]
However, there are cases where the number of gradations is small by the above method alone. Therefore, in order to increase the number of gradations, it can be combined with other gradation methods. There are two main methods.
[0063]
The first is a method combined with the time gray scale method. The time gradation method is a method of expressing gradation by controlling a light emission period within one frame period. One frame period corresponds to a period for displaying an image for one screen. Specifically, one frame period is divided into a plurality of subframe periods, and the light emission state or non-light emission state of each pixel is selected for each subframe period. In this way, gradation is expressed by the combination of the light emission period of the pixel and the light emission luminance. The second is a method combined with the area gradation method. The area gradation method is a method of expressing gradation by changing the area of a light emitting portion in one pixel. For example, each pixel is composed of a plurality of subpixels. Here, the configuration of each sub-pixel is the same as the pixel configuration of the display device of the present invention described above. In each subpixel, a light emitting state or a non-light emitting state is selected. In this way, gradation is expressed by the combination of the area of the light emitting portion of the pixel and the light emission luminance. Note that a method combined with the time gray scale method and a method combined with the area gray scale method may be combined.
[0064]
Next, an effective technique for further reducing the luminance variation in the above-described gradation display technique will be described. This is an effective method when the luminance varies even when the same gradation is expressed between pixels due to, for example, noise.
[0065]
Two or more current source circuits among a plurality of current source circuits of each pixel are set to output the same constant current. Then, when expressing the same gradation, different current source circuits that output the same constant current are used. In this way, even if the output current of the current source circuit varies, the current flowing through the light emitting element is averaged over time. Therefore, it is possible to visually reduce the luminance variation due to the variation in the output current of the current source circuit between the pixels.
[0066]
In the present invention, the current flowing through the light-emitting element when displaying an image is kept at a predetermined constant current, so that the light-emitting element can emit light with a constant luminance regardless of a change in current characteristics due to deterioration or the like. Since each light emitting state or non-light emitting state of each pixel is selected by selecting the on / off state of the switch unit with a digital video signal, writing of the video signal to the pixel can be accelerated. In the pixel in which the non-light emitting state is selected by the video signal, the current input to the light emitting element is completely blocked by the switch unit, so that an accurate gradation can be expressed. That is, it is possible to eliminate the problem of contrast reduction caused by leakage current when displaying black. In addition, according to the present invention, the current value of the constant current flowing through the current source circuit can be set to be large to some extent, so that the influence of noise generated when writing a small signal current can be reduced. Furthermore, the display device of the present invention does not require a drive circuit for changing the value of the current flowing through the current source circuit arranged in each pixel, and is an external drive circuit manufactured on another substrate such as a single crystal IC substrate. Therefore, cost reduction and downsizing can be realized.
[0067]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
An embodiment of the present invention will be described with reference to FIG. In this embodiment, a case where there are two pairs of a switch unit and a current source circuit in one pixel will be described.
[0068]
2A, each pixel 100 includes switch portions 101a and 101b, current source circuits 102a and 102b, a light emitting element 106, video signal input lines Sa and Sb, scanning lines Ga and Gb, and a power supply line W. The switch unit 101a and the current source circuit 102a are connected in series to form one pair. The switch unit 101b and the current source circuit 102b are connected in series to form one pair. These two pairs are connected in parallel. The two parallel circuits are connected in series with the light emitting element 106.
[0069]
The pixel shown in FIG. 2 is provided with two pairs of a switch unit and a current source circuit. Hereinafter, focusing on the pair of the switch unit 101a and the current source circuit 102a, the current source circuit 102a and the switch unit 101a will be described. The configuration of will be described with reference to FIG.
[0070]
First, the current source circuit 102a will be described with reference to FIG. In FIG. 2A, the current source circuit 102a is indicated by a circle and an arrow in the circle. It is defined that a positive current flows in the direction of the arrow. Further, the potential of the terminal A is defined to be higher than the potential of the terminal B. Next, a detailed structure of the current source circuit 102a will be described with reference to FIG. The current source circuit 102 a includes a current source transistor 112 and a current source capacitor 111. Note that the current source capacitor 111 can be omitted by using the gate capacitor of the current source transistor 112 or the like. The gate capacitance is a capacitance formed between the gate and the channel of the transistor. The drain current of the current source transistor 112 becomes the output current of the current source circuit 102a. The current source capacitor 111 holds the gate potential of the current source transistor 112.
[0071]
One of a source terminal and a drain terminal of the current source transistor 112 is electrically connected to the terminal A, and the other is electrically connected to the terminal B. The gate electrode of the current source transistor 112 is electrically connected to one electrode of the current source capacitor 111. The other electrode of the current source capacitor 111 is electrically connected to the terminal A ′. Note that the current source transistor 112 constituting the current source circuit 102a may be an N-channel type or a P-channel type.
[0072]
In the case where a P-channel transistor is used as the current source transistor 112, the source terminal is electrically connected to the terminal A, and the drain terminal is electrically connected to the terminal B. In addition, in order to hold the voltage between the gate and the source of the current source transistor 112, the terminal A ′ is preferably electrically connected to the source terminal of the current source transistor 112. Therefore, it is desirable that the terminal A ′ is electrically connected to the terminal A.
[0073]
On the other hand, when an N-channel transistor is used as the current source transistor 112, the drain terminal of the current source transistor 112 is electrically connected to the terminal A, and the source terminal is electrically connected to the terminal B. In addition, in order to hold the voltage between the gate and the source of the current source transistor 112, the terminal A ′ is preferably electrically connected to the source terminal of the current source transistor 112. Therefore, it is desirable that the terminal A ′ is electrically connected to the terminal B.
[0074]
Note that, regardless of whether a P-channel transistor or an N-channel transistor is used as the current source transistor 112, the terminal A ′ may be connected so that the potential of the gate electrode of the current source transistor 112 can be held. Therefore, the terminal A ′ may be connected to a wiring maintained at a constant potential for at least a predetermined period. The certain time here is a period during which the current source circuit outputs a current and a period during which a control current that determines the current output from the current source circuit is input to the current source circuit.
[0075]
Note that in Embodiment 1, a case where a P-channel transistor is used as the current source transistor 112 will be described.
[0076]
Next, the switch unit 101a will be described with reference to FIG. The switch unit 101a has a terminal C and a terminal D. A conduction / non-conduction state between the terminal C and the terminal D is selected by the digital video signal. By selecting a conduction / non-conduction state between the terminal C and the terminal D, a current flowing through the light emitting element 106 is changed. Here, turning on the switch unit 101a means selecting a conduction state between the terminal C and the terminal D. Turning off the switch unit 101a means selecting a non-conduction state between the terminal C and the terminal D. Next, a detailed configuration of the switch portion 101a will be described with reference to FIG. The switch unit 101 a includes a first switch 181, a second switch 182, and a holding unit 183.
[0077]
In FIG. 2C, the first switch 181 includes a control terminal r, a terminal e, and a terminal f. In the first switch 181, a conduction / non-conduction state between the terminal e and the terminal f is selected by a signal input to the control terminal r. Here, when the terminal e and the terminal f are in a conductive state, it is said that the first switch 181 is turned on. Further, when the terminal e and the terminal f are in a non-conduction state, the first switch 181 is called off. The same applies to the second switch 182.
[0078]
The first switch 181 controls input of a digital video signal to the pixel. That is, the signal of the scanning line Ga is input to the control terminal r of the first switch 181, and the on / off of the first switch 181 is selected.
[0079]
When the first switch 181 is turned on, a digital video signal is input to the pixel from the video signal input line Sa. The digital video signal input to the pixel is held by the holding unit 183. Note that the holding unit 183 can be omitted by using a gate capacitance of a transistor included in the second switch 182 or the like. The digital video signal input to the pixel is input to the control terminal r of the second switch 182. Thus, on / off of the second switch 182 is selected. When the second switch 182 is turned on, the terminal C and the terminal D are brought into conduction, and current is supplied from the current source circuit 102 a to the light emitting element 106. Even after the first switch 181 is turned off, the digital video signal is continuously held in the holding means 183, and the second switch 182 is kept in the on state.
[0080]
Next, the structure of the light-emitting element 106 is described. The light emitting element 106 has two electrodes (anode and cathode). The light emitting element 106 emits light with luminance according to the current flowing between the two electrodes. One of the two electrodes of the light emitting element 106 is electrically connected to a power supply reference line (not shown). Potential V by power supply reference line com Is referred to as a counter electrode 106b, and the other electrode is referred to as a pixel electrode 106a.
[0081]
As a light-emitting element, an EL element using electroluminescence has attracted attention. The EL element has a structure including an anode, a cathode, and an EL layer sandwiched between the anode and the cathode. By applying a voltage between the anode and the cathode, the EL element emits light. The EL layer may be formed of an organic material or an inorganic material. Moreover, you may form from both organic substance and inorganic substance. In addition, the EL element includes one or both of one that uses light emission (fluorescence) from singlet excitons and one that uses light emission (phosphorescence) from triplet excitons.
[0082]
Next, the connection relation of the pixel components will be described with reference to FIG. Again, pay attention to the pair of the switch unit 101a and the current source circuit 102a. The terminal A is electrically connected to the power supply line W, the terminal B is electrically connected to the terminal C, and the terminal D is electrically connected to the pixel electrode 106 a of the light emitting element 106. A current flows through the light-emitting element from the pixel electrode 106a to the counter electrode 106b. The pixel electrode 106a is an anode, and the counter electrode 106b is a cathode. The potential of the power line W is the potential V com Set higher.
[0083]
Note that the connection relation between the components of the pixel is not limited to the structure illustrated in FIG. The switch unit 101a and the current source circuit 102a may be connected in series. Further, the anode and the cathode of the light emitting element 106 may be reversed. That is, the pixel electrode 106a may be a cathode and the counter electrode 106b may be an anode. Note that since it is defined that a positive current flows from the terminal A to the terminal B, in the configuration in which the pixel electrode 106a is a cathode and the counter electrode 106b is an anode, the terminal A and the terminal B are interchanged. That is, the terminal A is electrically connected to the terminal C of the switch unit 101a, and the terminal B is electrically connected to the power supply line W. The potential of the power line W is the potential V com Set lower.
[0084]
Note that in this embodiment, each pixel is provided with two pairs of a switch unit and a current source circuit. The configuration of each pair of the switch unit and the current source circuit is as described above, but the connection between these pairs needs to consider the following points. That is, the sum of the currents supplied from the current source circuits 102a and 102b is input to the light emitting element, that is, two pairs of the switch unit and the current source circuit are parallel to each other. And further connected in series with the light emitting element. Note that the direction in which the current of the current source circuit 102a flows and the direction in which the current of the current source circuit 102b flows are preferably the same direction. That is, it is desirable that the addition of the positive current flowing through the current source circuit 102a and the positive current flowing through the current source circuit 102b flows to the light emitting element. In this way, an operation similar to digital / analog conversion can be performed in the pixel.
[0085]
Next, an outline of the operation of the pixel will be described. A conduction / non-conduction state between the terminal C and the terminal D is selected by the digital video signal. The current source circuit is set to flow a constant current. The current supplied from the current source circuit is input to the light emitting element through the switch unit that is in a conductive state between the terminal C and the terminal D. One digital video signal controls one switch unit. Therefore, when there are a plurality of pairs of switch units and current source circuits, the plurality of switch units are controlled by digital video signals corresponding to each of the plurality of switch units. The value of the current flowing through the light emitting element varies depending on which of the plurality of switch units is turned on. In this way, the current flowing through the light emitting element is changed to express gradation and display an image.
[0086]
Next, the operation of the above-described pixel will be described in detail. In the description, the operation of the pair of the switch unit 101a and the current source circuit 102a will be described as an example.
[0087]
First, the operation of the switch unit 101a will be described. A row selection signal is input from the scanning line Ga to the switch unit 101a. The row selection signal is a signal that controls the timing of inputting a digital video signal to the pixel. Further, when the scanning line Ga is selected, a digital video signal is input to the pixel from the video signal input line Sa. That is, the digital video signal is input to the second switch 182 through the first switch 181 that is turned on. The on / off state of the second switch 182 is selected by the digital video signal. In addition, since the digital video signal is held by the holding unit 183, the on / off state of the second switch 182 is maintained.
[0088]
Next, the operation of the current source circuit 102a will be described. In particular, the operation of the current source circuit 102a when a control signal is input will be described. The drain current of the current source transistor 112 is determined by the control signal. The gate voltage of the current source transistor 112 is held by the current source capacitor 111. The current source transistor 112 operates in the saturation region. In the transistor operating in the saturation region, if the gate voltage is the same, the drain current is kept constant even if the drain-source voltage changes. Therefore, the current source transistor 112 outputs a constant current. In this way, the current source circuit 102a passes a constant current determined by the control signal. A constant output current of the current source circuit 102a is input to the light emitting element. Once the pixel setting operation is performed, the pixel setting operation is repeated according to the discharge of the current source capacitor 111.
[0089]
The operation of each of the plurality of pairs of the switch unit and the current source circuit is as described above. Note that in the display device of the present invention, digital video signals input to each of a plurality of pairs of switch units and current source circuits of a pixel may be the same or different. Further, the control signals input to each of the plurality of current source circuits in a pair of the switch portion and the current source circuit included in the pixel may be the same or different.
[0090]
(Embodiment 2)
In this embodiment mode, a specific configuration example of each switch portion of a plurality of pairs of a switch portion and a current source circuit included in a pixel in the display device of the present invention is shown. The operation of the pixel having the switch portion will be described.
[0091]
A configuration example of the switch unit is shown in FIG. The switch unit 101 includes a selection transistor 301, a driving transistor 302, an erasing transistor 304, and a storage capacitor 303. Note that the storage capacitor 303 can be omitted by using a gate capacitor of the driving transistor 302 or the like. The transistor included in the switch portion 101 may be a single crystal transistor, a polycrystalline transistor, or an amorphous transistor. Alternatively, an SOI transistor may be used. A bipolar transistor may be used. A transistor using an organic material such as a carbon nanotube may be used.
[0092]
The gate electrode of the selection transistor 301 is connected to the scanning line G. One of the source terminal and the drain terminal of the selection transistor 301 is connected to the video signal input line S, and the other is connected to the gate electrode of the driving transistor 302. One of the source terminal and the drain terminal of the driving transistor 302 is connected to the terminal C, and the other is connected to the terminal D. One electrode of the storage capacitor 303 is connected to the gate electrode of the driving transistor 302, and the other electrode is a wiring W co It is connected to the. Note that the storage capacitor 303 only needs to hold the gate potential of the driving transistor 302. Therefore, in FIG. co The electrode connected to the wiring W co Other than the above, it may be connected to a wiring having a constant voltage at least for a certain period. The gate electrode of the erasing transistor 304 is connected to the erasing signal line RG. One of the source terminal and the drain terminal of the erasing transistor 304 is connected to the gate electrode of the driving transistor 302, and the other is the wiring W co It is connected to the. Note that since the driving transistor 302 may be turned off by turning on the erasing transistor 304, the wiring W co You may connect other than.
[0093]
Next, the basic operation of the switch unit 101 will be described with reference to FIG. When the selection transistor 301 is turned on by a row selection signal input to the scanning line G while the erasing transistor 304 is non-conductive, a digital video signal is input from the video signal input line S to the gate electrode of the driving transistor 302. The The voltage of the input digital video signal is held in the holding capacitor 303. On / off of the driving transistor 302 is selected by the input digital video signal, and a conduction / non-conduction state between the terminal C and the terminal D of the switch unit 101 is selected. Next, when the erasing transistor 304 is turned on, the charge held in the holding capacitor 303 is discharged, the driving transistor 302 is turned off, and the terminal C and the terminal D of the switch unit 101 are turned off. In the above operation, the selection transistor 301, the driving transistor 302, and the erasing transistor 304 function as simple switches. Thus, these transistors operate in a linear region in the on state.
[0094]
Note that the driving transistor 302 may be operated in a saturation region. By operating the driving transistor 302 in the saturation region, the saturation region characteristic of the current source transistor 112 can be supplemented. Here, the saturation region characteristic indicates a characteristic that the drain current is kept constant with respect to the voltage between the source and drain terminals. Complementing the saturation region characteristic means that, even in the current source transistor 112 operating in the saturation region, the drain current is prevented from increasing as the source-drain terminal voltage increases. In order to obtain the above effect, the driving transistor 302 and the current source transistor 112 must have the same polarity.
[0095]
The effect of supplementing the above saturation region characteristics will be described below. For example, attention is paid to a case where the voltage between the source and drain terminals of the current source transistor 112 increases. The current source transistor 112 and the drive transistor 302 are connected in series. Therefore, the potential of the source terminal of the driving transistor 302 changes due to a change in the voltage between the source and drain terminals of the current source transistor 112. When the voltage between the source and drain terminals of the current source transistor 112 increases, the absolute value of the source-gate voltage of the drive transistor 302 decreases. Then, the IV curve of the drive transistor 302 changes. The direction of this change is the direction in which the drain current decreases. Thus, the drain current of the current source transistor 112 connected in series with the driving transistor 302 is reduced. Similarly, when the voltage between the source and drain terminals of the current source transistor decreases, the drain current of the current source transistor increases. In this way, the effect of keeping the current flowing through the current source transistor constant can be obtained.
[0096]
The basic operation of the switch unit and the current source circuit pair has been described focusing on one switch unit, but the same applies to the operation of the other switch units. When each pixel has a plurality of pairs of switch units and current source circuits, a scanning line and a video signal input line are provided according to each pair.
[0097]
Next, a gradation display method will be described. In the display device of the present invention, gradation is expressed by on / off control of the switch unit. For example, the ratio of the magnitudes of currents output from a plurality of current source circuits of each pixel is 2 0 : 2 1 : 2 2 : 2 Three ... Allows the pixel to have the role of D / A conversion, and can express multiple gradations. Here, if a sufficient number of pairs of switch units and current source circuits are provided in one pixel, gradation can be sufficiently expressed only by the control by these. In that case, it is not necessary to perform an operation combined with a time gray scale method, which will be described later.
[0098]
Next, a method for further increasing the number of gradations by combining the gradation display method and the time gradation method will be described with reference to FIGS.
[0099]
As shown in FIG. 4, one frame period F is changed to the first subframe period SF. 1 To n-th (n is a natural number) subframe period SF n Divide into In each subframe period, the scanning line G of each pixel is selected in order. In the pixel corresponding to the selected scanning line G, a digital video signal is input from the video signal input line S. Here, a period during which a digital video signal is input to all pixels of the display device is referred to as an address period Ta. In particular, the address period corresponding to the k-th subframe period (k is a natural number equal to or less than n) is Ta. k Is written. Each pixel enters a light emitting state or a non-light emitting state depending on a digital video signal input in the address period. This period is referred to as a display period Ts. In particular, the display period corresponding to the kth subframe period is Ts. k Is written. In FIG. 4, the first subframe period SF 1 ~ K-1 subframe period SF k-1 In each, an address period and a display period are provided.
[0100]
Since it is impossible to simultaneously select scanning lines G of different pixel rows and input digital video signals, the address periods cannot be overlapped. Therefore, by using the following method, the display period can be made shorter than the address period without overlapping the address period.
[0101]
After a digital video signal is written to each pixel and a predetermined display period has elapsed, the erasing signal line RG is sequentially selected. A signal for selecting an erasing signal line is called an erasing signal. When the erasing transistor 304 is turned on by the erasing signal, each pixel row can be sequentially brought into a non-light emitting state. A period until all the erasing signal lines RG are selected in this way and all the pixels are brought into a non-light emitting state is referred to as a reset period Tr. In particular, the reset period corresponding to the kth subframe period is defined as Tr. k Is written. In addition, a period in which pixels after the reset period Tr uniformly emit no light is referred to as a non-display period Tus. In particular, the non-display period corresponding to the kth subframe period is Tus. k Is written. By providing the reset period and the non-display period, the pixel can be brought into a non-light emitting state before the next subframe period starts. Thus, a display period shorter than the address period can be set. In FIG. 4, the k-th subframe period SF k To n-th subframe period SF n Provides a reset period and a non-display period, and a display period Ts shorter than the address period. k ~ Ts n Is set. Here, the length of the display period of each subframe period can be determined as appropriate.
[0102]
In this way, the length of the display period of each subframe period constituting one frame period is set. As described above, the display device of the present invention can achieve multiple gradations in combination with the time gradation method.
[0103]
Next, a configuration in which the switch unit illustrated in FIG. 3 is different from the arrangement method of the erasing transistor 304 and a configuration in which no erasing transistor is provided will be described. The same parts as those in FIG. 3 are denoted by the same reference numerals and description thereof is omitted.
[0104]
FIG. 5A shows an example of the switch portion. In FIG. 5A, the erasing transistor 304 is arranged in series on a path for inputting current to the light emitting element, and the erasing transistor 304 is turned off so that no current flows through the light emitting element. Note that the erasing transistor 304 may be arranged anywhere as long as it is in series on a path for inputting current to the light emitting element. By turning off the erasing transistor 304, the pixels can be brought into a non-light emitting state uniformly. Thus, a reset period and a non-display period can be set. Note that in the case of the switch portion having the structure shown in FIG. 5A, the erase transistor 304 is not arranged in each switch portion of a plurality of pairs of the switch portion and the current source circuit included in the pixel but may be arranged collectively. it can. Thus, the number of transistors in the pixel can be suppressed. FIG. 35 shows a pixel configuration when the erase transistor 304 is shared by a plurality of pairs of the switch portion and the current source circuit. Note that here, a pixel having two pairs of a switch unit and a current source circuit will be described as an example, but the present invention is not limited to this. 35, the same portions as those in FIGS. 2A and 3 are denoted by the same reference numerals. It should be noted that the part corresponding to the switch part 101a is indicated by adding a after the reference numeral in FIG. Further, the part corresponding to the switch part 101b is indicated by adding b after the reference numeral in FIG. In FIG. 35, by turning off the erasing transistor 304, both currents output from the current source circuit 102a and the current source circuit 102b can be simultaneously cut off.
[0105]
Note that the erase transistor 304 shared by a plurality of switch units may be disposed on a path connecting the power supply line W and the current source circuits 102a and 102b. That is, the power supply line W and the current source circuits 102a and 102b may be connected via the erase transistor 304 shared by a plurality of switch units. The erasing transistor 304 shared by the plurality of switch units may be provided anywhere as long as both currents output from the current source circuit 102a and the current source circuit 102b are simultaneously cut off. For example, the erasing transistor 304 may be arranged at the path X in FIG. In other words, the erasing transistor 304 may select the connection between the power supply line W and the terminal A of the current source circuit 102a and the terminal A of the current source circuit 102b.
[0106]
FIG. 5B illustrates another structure of the switch portion. In FIG. 5B, a predetermined voltage is applied to the gate electrode of the driving transistor 302 via the source and drain terminals of the erasing transistor 304 to turn off the driving transistor. In this example, one of the source terminal and the drain terminal of the erasing transistor 304 is connected to the gate electrode of the driving transistor, and the other is connected to the wiring Wr. The potential of the wiring Wr is appropriately determined. Thus, the driving transistor in which the potential of the wiring Wr is input to the gate electrode through the erasing transistor is turned off.
[0107]
In the structure shown in FIG. 5B, a diode may be used instead of the erasing transistor 304. This structure is shown in FIG. The potential of the wiring Wr is changed. Thus, the potential of the electrode not connected to the gate electrode of the driving transistor 302 among the two electrodes of the diode 3040 is changed. As a result, the gate voltage of the driving transistor can be changed, and the driving transistor can be turned off. Note that a diode-connected transistor (a gate electrode and a drain terminal are electrically connected) may be used as the diode 3040. At this time, the transistor may be an N-channel transistor or a P-channel transistor.
[0108]
Note that the scanning line G may be used instead of the wiring Wr. FIG. 5D illustrates a structure in which the scanning line G is used instead of the wiring Wr in FIG. However, in this case, it is necessary to pay attention to the polarity of the selection transistor 301 in consideration of the potential of the scanning line G.
[0109]
Next, a method of providing a reset period and a non-display period without providing an erase transistor will be described.
[0110]
The first method is a method in which the driving transistor 302 is turned off by changing the potential of the electrode on the side of the storage capacitor 303 that is not connected to the gate electrode of the driving transistor 302. This structure is shown in FIG. The electrode on the side of the storage capacitor 303 that is not connected to the gate electrode of the driving transistor 302 is a wiring W co It is connected to the. Wiring W co , And the potential of one electrode of the storage capacitor 303 is changed. Then, since the charge held in the storage capacitor is stored, the potential of the other electrode of the storage capacitor 303 also changes. In this manner, the potential of the gate electrode of the driving transistor 302 can be changed so that the driving transistor 302 is turned off.
[0111]
The second method will be described. A period in which one scanning line G is selected is divided into the first half and the second half. A digital video signal is input to the video signal input line S in the first half (denoted as the first half of the gate selection period), and an erasure signal is input to the video signal input line S in the second half (denoted as the second half of the gate selection period). It is characterized by that. The erasing signal in this method is a signal that turns off the driving transistor 302 when input to the gate electrode of the driving transistor 302. Thus, a display period shorter than the writing period can be set. Hereinafter, the second method will be described in more detail.
[0112]
First, the configuration of the entire display device when using the above method will be described. FIG. 6B is used for the description. The display device includes a pixel portion 901 having a plurality of pixels arranged in a matrix, a video signal input line driver circuit 902 that inputs a signal to the pixel portion 901, a first scanning line driver circuit 903A, A scan line driver circuit 903B, a switching circuit 904A, and a switching circuit 904B are included. Each pixel included in the pixel portion 901 includes a plurality of switch portions 101 and a current source circuit as illustrated in FIG. Here, the first scanning line driving circuit 903A is a circuit that outputs a signal to each scanning line G in the first half of the gate selection period. The second scan line driver circuit 903B is a circuit that outputs a signal to each scan line G in the second half of the gate selection period. The switching circuit 904A and the switching circuit 904B select the connection between the first scanning line driving circuit 903A and the scanning line G of each pixel or the connection between the second scanning line driving circuit 903B and the scanning line G of each pixel. The The video signal input line driver circuit 902 outputs a video signal in the first half of the gate selection period. On the other hand, an erasing signal is output in the second half of the gate selection period.
[0113]
Next, a method for driving the display device having the above structure will be described. The timing chart in FIG. 6C is used for the description. In addition, the same part as FIG. 4 is shown using the same code | symbol, and description is abbreviate | omitted. In FIG. 6C, the gate selection period 991 is divided into a gate selection period first half 991A and a gate selection period second half 991B. In 903A corresponding to the writing period Ta, each scanning line is selected by the first scanning line driving circuit, and a digital video signal is input. In 903B corresponding to the reset period Tr, each scanning line is selected by the second scanning line driving circuit, and an erasing signal is input. Thus, a display period Ts shorter than the address period Ta can be set.
[0114]
In FIG. 6C, an erasing signal is input in the latter half of the gate selection period, but a digital video signal in the next subframe period may be input instead.
[0115]
The third method will be described. The third method is a method of providing a non-display period by changing the potential of the counter electrode of the light emitting element. That is, in the display period, the potential of the counter electrode is set so as to have a predetermined potential difference between the potential of the power supply line. On the other hand, in the non-display period, the potential of the counter electrode is set to substantially the same potential as that of the power supply line. Thus, in the non-display period, the pixels can be brought into a non-light emitting state uniformly regardless of the digital video signal held in the pixels. In this method, a digital video signal is input to all pixels during a non-display period. That is, an address period is provided during the non-display period.
[0116]
In the pixel having the switch portion having the above structure, each wiring can be shared. Thus, the pixel configuration can be simplified and the aperture ratio of the pixel can be increased. Hereinafter, an example in which each wiring is shared will be described. In the description, an example in which wiring is shared in a configuration in which the switch unit having the configuration illustrated in FIG. 3 is applied to the pixel illustrated in FIG. 2 is used. The following configuration can be freely applied to the switch unit having the configuration shown in FIGS.
[0117]
Hereinafter, wiring sharing will be described. Here are six examples of wiring sharing. 7 and 8 are used for the description. 7 and 8, the same parts as those in FIGS. 2 and 3 are denoted by the same reference numerals, and description thereof is omitted.
[0118]
FIG. 7A shows wiring W of a plurality of switch portions. co An example of the configuration of a pixel sharing the above. In FIG. 7B, the wiring W co And a configuration of a pixel sharing the power supply line W. In FIG. 7C, the wiring W co Instead, a configuration of a pixel using a scanning line of another pixel row is illustrated. The configuration in FIG. 7C utilizes the fact that the potentials of the scanning lines Ga and Gb are kept constant while the video signal is not written. In FIG. 7C, the wiring W co Instead of the scanning line Ga of the previous pixel row i-1 And Gb i-1 Is used. However, in this case, it is necessary to pay attention to the polarity of the selection transistor 301 in consideration of the potentials of the scanning lines Ga and Gb. FIG. 8A illustrates a structure of a pixel sharing the signal line RGa and the signal line RGb. This is because the first switch unit and the second switch unit may be turned off simultaneously. The shared signal lines are collectively referred to as RGa. FIG. 8B illustrates a structure of a pixel sharing the scan line Ga and the scan line Gb. The shared scanning lines are collectively expressed as Ga. FIG. 8C illustrates a configuration of a pixel sharing the video signal input line Sa and the video signal input line Sb. The shared video signal input lines are collectively referred to as Sa.
[0119]
It is also possible to combine FIG. 7 (A) to FIG. 7 (C) and FIG. 8 (A) to FIG. 8 (C). Note that the present invention is not limited to this, and each wiring included in the pixel can be shared as appropriate. Moreover, each wiring between pixels can be shared as appropriate.
[0120]
Note that this embodiment mode can be freely combined with Embodiment Mode 1.
[0121]
(Embodiment 3)
In this embodiment mode, a structure and an operation of a current source circuit included in each pixel of the display device of the present invention will be described in detail.
[0122]
Focusing on one pair of current source circuits among a plurality of pairs of switch units and current source circuits included in each pixel, the configuration will be described in detail. In this embodiment, five configuration examples of the current source circuit are given, but another configuration example may be used as long as the circuit operates as a current source. Note that the transistor forming the current source circuit may be a single crystal transistor, a polycrystalline transistor, or an amorphous transistor. Alternatively, an SOI transistor may be used. A bipolar transistor may be used. A transistor using an organic material such as a carbon nanotube may be used.
[0123]
First, a current source circuit having a first structure will be described with reference to FIG. Note that in FIG. 9A, the same portions as those in FIG. 2 are denoted by the same reference numerals.
[0124]
The current source circuit having the first configuration illustrated in FIG. 9A includes a current source transistor 112 and a current transistor 1405 that forms a current mirror circuit in a pair with the current source transistor 112. A current input transistor 1403 and a current holding transistor 1404 functioning as switches are included. Here, the current source transistor 112, the current transistor 1405, the current input transistor 1403, and the current holding transistor 1404 may be a P-channel type or an N-channel type. However, it is desirable that the current source transistor 112 and the current transistor 1405 have the same polarity. Here, the current source transistor 112 and the current transistor 1405 are examples of P-channel transistors. It is desirable that the current source transistor 112 and the current transistor 1405 have the same current characteristics. A current source capacitor 111 that holds the gate potentials of the current source transistor 112 and the current transistor 1405 is provided. Note that the current source capacitor 111 can be omitted by positively using the gate capacitor of the transistor. Further, a signal line GN for inputting a signal to the gate electrode of the current input transistor 1403 and a signal line GH for inputting a signal to the gate electrode of the current holding transistor 1404 are provided. Moreover, it has the current line CL into which a control signal is input.
[0125]
The connection relationship of these components will be described. The gate electrodes of the current source transistor 112 and the current transistor 1405 are connected. The source terminal of the current source transistor 112 is connected to the terminal A, and the drain terminal is connected to the terminal B.
One electrode of the current source capacitor 111 is connected to the gate electrode of the current source transistor 112, and the other electrode is connected to the terminal A. The source terminal of the current transistor 1405 is connected to the terminal A, and the drain terminal is connected to the current line CL via the current input transistor 1403. The gate electrode and drain terminal of the current transistor 1405 are connected via a current holding transistor 1404. The source terminal or drain terminal of the current holding transistor 1404 is connected to the current source capacitor 111 and the drain terminal of the current transistor 1405. However, the side of the current holding transistor 1404 that is not connected to the current source capacitor 111 at the source terminal or drain terminal may be connected to the current line CL. This configuration is shown in FIG. 36, the same portions as those in FIG. 9A are denoted by the same reference numerals. With this configuration, the voltage between the source and drain terminals of the current holding transistor 1404 can be reduced by adjusting the potential of the current line CL when the current holding transistor 1404 is off. As a result, the off-state current of the current holding transistor 1404 can be reduced. Thus, charge leakage from the current source capacitor 111 can be reduced.
[0126]
FIG. 33A shows an example in which the current source transistor 112 and the current transistor 1405 are N-channel transistors in the structure of the current source circuit shown in FIG. Note that the current source circuit having the configuration shown in FIG. 33A is different from the current source circuit having the configuration shown in FIG. 9A in the setting operation of the current source circuit 102. In order to prevent the current flowing between the current line CL and the terminal A through the drain from flowing between the source and drain of the current source transistor 112 and the terminal B, the transistors 1441 and 1442 need to be provided. Further, in order to prevent a current from flowing between the source and the drain of the current transistor 1405 when a constant current is passed between the terminal A and the terminal B in the display operation, the transistor 1443 needs to be provided. Thus, the current source circuit 102 can accurately output a current having a predetermined current value.
[0127]
Further, in the circuit having the structure shown in FIG. 9A, the arrangement of the current holding transistors 1404 may be changed to have a circuit structure as shown in FIG. 9B. In FIG. 9B, the gate electrode of the current transistor 1405 and one electrode of the current source capacitor 111 are connected through a current holding transistor 1404. At this time, the gate electrode and the drain terminal of the current transistor 1405 are connected by wiring.
[0128]
Next, the setting operation of the current source circuit having the first configuration will be described. 9A and 9B, the setting operation is the same. Here, the setting operation will be described using the circuit shown in FIG. 9A as an example. 9C to 9F are used for the description. In the current source circuit having the first configuration, the setting operation is performed through the states of FIGS. 9C to 9F in order. In the description, for simplicity, the current input transistor 1403 and the current holding transistor 1404 are described as switches. Here, an example is shown in which the control signal for setting the current source circuit 102 is a control current. In the figure, a path through which current flows is indicated by a thick arrow.
[0129]
In a period TD1 illustrated in FIG. 9C, the current input transistor 1403 and the current holding transistor 1404 are turned on. At this stage, since the source-gate voltage of the current transistor 1405 is small and the current transistor 1405 is off, current flows from the current line CL through the path shown in the figure, and the electric charge is held in the current source capacitor 111.
[0130]
In a period TD2 illustrated in FIG. 9D, the voltage between the gate and the source of the current transistor 1405 becomes equal to or higher than the threshold voltage due to the charge held in the current source capacitor 111. Then, a current flows through between the source and drain terminals of the current transistor 1405.
[0131]
When sufficient time elapses and a steady state is reached, a current flowing between the source and drain terminals of the current transistor 1405 is determined as a control current as in a period TD3 shown in FIG. Thus, the gate voltage when the control current is the drain current is held in the current source capacitor 111.
[0132]
In a period TD4 illustrated in FIG. 9F, the current holding transistor 1404 and the current input transistor 1403 are turned off. Thus, no control current is input to the pixel. Note that the timing for turning off the current holding transistor 1404 is preferably earlier or at the same time as the timing for turning off the current input transistor 1403. This is to prevent the electric charge held in the current source capacitor 111 from being discharged. When a voltage is applied between the source and drain terminals of the current source transistor 112 after the period TD4, a drain current corresponding to the control current flows. That is, when a voltage is applied between the terminal A and the terminal B, the current source circuit 102 outputs a current corresponding to the control current.
[0133]
Here, the channel width / channel length ratio W1 / L1 of the current source transistor 112 may be changed with respect to the channel width / channel length ratio W2 / L2 of the current transistor 1405. Thus, the current value of the current output from the current source circuit 102 can be changed with respect to the control current input to the pixel. For example, each transistor is designed so that the control current input to the pixel is larger than the current output from the current source circuit 102. Thus, the setting operation of the current source circuit 102 is performed using the control current having a large current value. As a result, the setting operation of the current source circuit can be speeded up. It is also effective for reducing the influence of noise.
[0134]
Thus, the current source circuit 102 outputs a predetermined current.
[0135]
In the current source circuit configured as described above, when a signal is input to the signal line GH and the current holding transistor is in the on state, the current line CL must be set to always flow a constant current. This is because if the current holding transistor 1404 and the current input transistor 1403 are both turned on during a period when no current is input to the current line CL, the charge held in the current source capacitor 111 is discharged. Therefore, when a constant current is selectively input to a plurality of current lines CL corresponding to all pixels to perform a pixel setting operation, that is, when a constant current is not always input to the current line CL, A current source circuit having the following configuration is used.
[0136]
In the current source circuit shown in FIGS. 9A and 9B, a switching element for selecting connection between the gate electrode and the drain terminal of the current source transistor 112 is added. This switching element is turned on / off by a signal different from the signal input to the signal line GH. FIG. 33B illustrates an example of the above structure. In FIG. 33B, a dot sequential transistor 1443 and a dot sequential line CLP are provided. Thus, an arbitrary pixel is selected pixel by pixel, and a pixel setting operation is performed so that at least a constant current is input to the current line CL of the selected pixel.
[0137]
Each signal line of the current source circuit of the first configuration can be shared. For example, in the configurations shown in FIGS. 9A, 9B, and 33, there is no problem in operation if the current input transistor 1403 and the current holding transistor 1404 are switched on and off at the same timing. Therefore, the current input transistor 1403 and the current holding transistor 1404 can have the same polarity, and the signal line GH and the signal line GN can be shared.
[0138]
Next, a current source circuit having a second configuration will be described. Refer to FIG. 10 for the description. 10A, the same portions as those in FIG. 2 are denoted by the same reference numerals.
[0139]
The components of the current source circuit having the second configuration will be described. The current source circuit having the second configuration includes a current source transistor 112. In addition, a current input transistor 203, a current holding transistor 204, and a current stop transistor 205 functioning as a switch are included. Here, the current source transistor 112, the current input transistor 203, the current holding transistor 204, and the current stop transistor 205 may be a P-channel type or an N-channel type. Here, the current source transistor 112 is an example of a P-channel transistor. Further, it has a current source capacitor 111 that holds the gate potential of the current source transistor 112. Note that the current source capacitor 111 can be omitted by positively using the gate capacitor of the transistor.
In addition, a signal line GS for inputting a signal to the gate electrode of the current stop transistor 205, a signal line GH for inputting a signal to the gate electrode of the current holding transistor 204, and a signal line for inputting a signal to the gate electrode of the current input transistor 203 GN. Moreover, it has the current line CL which inputs a control current.
[0140]
The connection relationship of these components will be described. The gate electrode of the current source transistor 112 is connected to one electrode of the current source capacitor 111. The other electrode of the current source capacitor 111 is connected to the terminal A. The source terminal of the current source transistor 112 is connected to the terminal A. The drain terminal of the current source transistor 112 is connected to the terminal B through the current stop transistor 205, and is connected to the current line CL through the current input transistor 203. The gate electrode and the drain terminal of the current source transistor 112 are connected via the current holding transistor 204.
[0141]
In the structure shown in FIG. 10A, the source terminal or drain terminal of the current holding transistor 204 is connected to the current source capacitor 111 and the drain terminal of the current source transistor 112. However, the side of the current holding transistor 204 that is not connected to the current source capacitor 111 may be connected to the current line CL. The above structure is shown in FIG. With this configuration, the voltage between the source and drain terminals of the current holding transistor 204 can be reduced by adjusting the potential of the current line CL when the current holding transistor 204 is off. As a result, the off-state current of the current holding transistor 204 can be reduced. Thus, charge leakage from the current source capacitor 111 can be reduced.
[0142]
Next, a setting method of the current source circuit having the second structure illustrated in FIG. FIG. 10B to FIG. 10E are used for the description. In the current source circuit having the second configuration, the setting operation is performed through the states shown in FIGS. 10B to 10E in order. In the description, for simplicity, the current input transistor 203, the current holding transistor 204, and the current stop transistor 205 are described as switches. Here, an example is shown in which the control signal for setting the current source circuit 102 is a control current. In the figure, a path through which current flows is indicated by a thick arrow.
[0143]
In a period TD1 illustrated in FIG. 10B, the current input transistor 203 and the current holding transistor 204 are turned on. Further, the current stop transistor 205 is in an off state. Thus, a current flows from the current line CL through the path shown in the figure, and the electric charge is held in the current source capacitor 111.
[0144]
In the period TD2 illustrated in FIG. 10C, the gate-source voltage of the current source transistor 112 becomes equal to or higher than the threshold voltage due to the held charges. Then, a drain current flows through the current source transistor 112.
[0145]
When a sufficient time has elapsed and a steady state is reached, the drain current of the current source transistor 112 is determined as the control current as in a period TD3 shown in FIG. In this way, the gate voltage of the current source transistor 112 when the control current is the drain current is held in the current source capacitor 111.
[0146]
In a period TD4 illustrated in FIG. 10E, the current input transistor 203 and the current holding transistor 204 are turned off. Thus, no control current is input to the pixel. Note that the timing for turning off the current holding transistor 204 is preferably earlier or at the same time as the timing for turning off the current input transistor 203. This is to prevent the electric charge held in the current source capacitor 111 from being discharged. Further, the current stop transistor 205 is turned on. When a voltage is applied between the source and drain terminals of the current source transistor 112 after the period TD4, a drain current corresponding to the control current flows. That is, when a voltage is applied between the terminal A and the terminal B, the current source circuit 102 flows a drain current corresponding to the control current. Thus, the current source circuit 102 outputs a predetermined current.
[0147]
Note that the current stop transistor 205 is not necessarily required. For example, when the setting operation is performed only when at least one of the terminal A or the terminal B is in an open state, the current stop transistor 205 is not necessary. Specifically, the current stop transistor 205 is not necessary in the current source circuit that performs the setting operation only when the paired switch units are in the OFF state.
[0148]
In the current source circuit having the above-described configuration, when a signal is input to the signal line GH and the current holding transistor 204 is in the on state, the current line CL must be set to always flow a constant current. This is because if the current holding transistor 204 and the current input transistor 203 are both turned on during a period when no current is input to the current line CL, the charge held in the current source capacitor 111 is discharged. Therefore, when a constant current is selectively input to a plurality of current lines CL corresponding to all pixels to perform a pixel setting operation, that is, when a constant current is not always input to the current line CL. Uses a current source circuit having the following configuration.
[0149]
A switching element for selecting connection between the gate electrode and the drain terminal of the current source transistor 112 is added. This switching element is turned on / off by a signal different from the signal input to the signal line GH. FIG. 34B illustrates an example of the above structure. In FIG. 34B, a dot sequential transistor 245 and a dot sequential line CLP are provided. Thus, an arbitrary pixel is selected pixel by pixel, and a pixel setting operation is performed so that at least a constant current is input to the current line CL of the selected pixel.
[0150]
Each signal line of the current source circuit of the second configuration can be shared. For example, if the current input transistor 203 and the current holding transistor 204 are switched on and off at the same timing, there is no problem in operation. Therefore, the current input transistor 203 and the current holding transistor 204 can have the same polarity, and the signal line GH and the signal line GN can be shared. In addition, the current stop transistor 205 does not have a problem in operation even if the current input transistor 203 is turned on at the same time. Therefore, the polarity of the current input transistor 203 and the current stop transistor 205 can be made different so that the signal line GN and the signal line GS can be shared.
[0151]
FIG. 37 shows a structural example in the case where the current source transistor 112 is an N-channel transistor. The same parts as those in FIG. 10 are denoted by the same reference numerals.
[0152]
Next, a current source circuit having a third configuration will be described. Refer to FIG. 11 for the description. In FIG. 11A, the same portions as those in FIG. 2 are denoted by the same reference numerals.
[0153]
The components of the current source circuit having the third configuration will be described. The current source circuit having the third configuration includes a current source transistor 112. In addition, a current input transistor 1483, a current holding transistor 1484, a light emitting transistor 1486, and a current reference transistor 1488 functioning as a switch are included. Here, the current source transistor 112, the current input transistor 1483, the current holding transistor 1484, the light emitting transistor 1486, and the current reference transistor 1488 may be either a P-channel type or an N-channel type. Here, the current source transistor 112 is an example of a P-channel transistor. Further, it has a current source capacitor 111 that holds the gate potential of the current source transistor 112. Note that the current source capacitor 111 can be omitted by positively using the gate capacitor of the transistor. In addition, a signal line GN for inputting a signal to the gate electrode of the current input transistor 1483, a signal line GH for inputting a signal to the gate electrode of the current holding transistor 1484, a signal line GE for inputting a signal to the gate electrode of the light emitting transistor 1486, and a current A signal line GC for inputting a signal to the gate electrode of the reference transistor 1488; Furthermore, it has a current line CL to which a control signal is input and a current reference line SCL maintained at a constant potential.
[0154]
The connection relationship of these components will be described. The gate electrode and the source terminal of the current source transistor 112 are connected via a current source capacitor 111. The source terminal of the current source transistor 112 is connected to the terminal A through the light emitting transistor 1486 and is connected to the current line CL through the current input transistor 1483. The gate electrode and the drain terminal of the current source transistor 112 are connected via a current holding transistor 1484. The drain terminal of the current source transistor 112 is connected to the terminal B, and is also connected to the current reference line SCL via the current reference transistor 1488.
[0155]
Note that the side of the current holding transistor 1484 that is not connected to the current source capacitor 111 of the source terminal or drain terminal is connected to the drain terminal of the current source transistor 112, but may be connected to the current reference line SCL. . The above configuration is shown in FIG. With this configuration, the voltage between the source and drain terminals of the current holding transistor 1484 can be reduced by adjusting the potential of the current reference line SCL when the current holding transistor 1484 is in the off state. As a result, the off-state current of the current holding transistor 1484 can be reduced. Thus, the charge leaking from the current source capacitor 111 can be reduced.
[0156]
Next, a method for setting the current source circuit having the third configuration will be described. 11B to 11E are used for the description. In the current source circuit of the third configuration, the setting operation is performed through the states of FIGS. 11B to 11E in order. In the description, for simplicity, the current input transistor 1483, the current holding transistor 1484, the light emitting transistor 1486, and the current reference transistor 1488 are described as switches. Here, an example in which the control signal for setting the current source circuit 102 is a control current is shown. In the figure, a path through which current flows is indicated by a thick arrow.
[0157]
In a period TD1 illustrated in FIG. 11B, the current input transistor 1483, the current holding transistor 1484, and the current reference transistor 1488 are turned on. In this way, a current flows from the illustrated path, and electric charge is held in the current source capacitor 111. Note that the light-emitting transistor 1486 is off.
[0158]
In the period TD2 illustrated in FIG. 11C, the voltage between the gate and the source of the current source transistor 112 becomes equal to or higher than the threshold voltage due to the charge held in the current source capacitor 111. Then, a drain current flows through the current source transistor 112.
[0159]
When a sufficient time elapses and a steady state is reached, the drain current of the current source transistor 112 is determined as the control current as in a period TD3 shown in FIG. Thus, the gate voltage when the control current is the drain current is held in the current source capacitor 111.
[0160]
In a period TD4 illustrated in FIG. 11E, the current input transistor 1483 and the current holding transistor 1484 are turned off. Thus, no control current is input to the pixel. Note that the timing for turning off the current holding transistor 1484 is preferably earlier or at the same time as the timing for turning off the current input transistor 1483. This is to prevent the electric charge held in the current source capacitor 111 from being discharged. Further, the current reference transistor 1488 is turned off. After that, the light-emitting transistor 1486 is turned on. When a voltage is applied between the source and drain terminals of the current source transistor 112 after the period TD4, a drain current corresponding to the control current flows through the current source transistor 112. That is, when a voltage is applied between the terminal A and the terminal B, the current source circuit 102 flows a current corresponding to the control current. Thus, the current source circuit 102 outputs a predetermined current.
[0161]
Note that the current reference transistor 1488 and the current reference line SCL are not necessarily required. For example, in a current source circuit that performs a setting operation only when a pair of switch units is in an on state, it is only necessary to pass a current to the terminal B instead of a current to the current reference line SCL in the periods TD1 to TD3. The current reference transistor 1488 and the current reference line SCL are not necessary.
[0162]
Each signal line of the current source circuit of the third configuration can be shared. For example, the current input transistor 1483 and the current holding transistor 1484 have no operational problem as long as they are switched on and off at the same timing. Therefore, the current input transistor 1483 and the current holding transistor 1484 can have the same polarity, and the signal line GH and the signal line GN can be shared. In addition, the current reference transistor 1488 and the current input transistor 1483 have no operational problem as long as they are switched on and off at the same timing. Therefore, the current reference transistor 1488 and the current input transistor 1483 have the same polarity, and the signal line GN and the signal line GC can be shared. Further, there is no problem in operation even if the light-emitting transistor 1486 is turned on and the current input transistor 1483 is turned off at the same time. Thus, the signal line GE and the signal line GN can be shared by making the light emitting transistor 1486 and the current input transistor 1483 have different polarities.
[0163]
FIG. 39A shows a structural example in the case where the current source transistor 112 is an N-channel transistor. Note that the same portions as those in FIG. 11 are denoted by the same reference numerals. In the configuration of FIG. 39A, the side of the current holding transistor 1484 that is not connected to the current source capacitor 111 of the source terminal or drain terminal is connected to the drain terminal of the current source transistor 112, but the current line CL It may be connected to. The above structure is shown in FIG. With this structure, the voltage between the source and drain terminals of the current holding transistor 1484 can be reduced by adjusting the potential of the current line CL when the current holding transistor 1484 is in the off state. As a result, the off-state current of the current holding transistor 1484 can be reduced. Thus, charge leakage from the current source capacitor 111 can be reduced.
[0164]
Next, a current source circuit having a fourth configuration will be described. Refer to FIG. 12 for the description. In FIG. 12A, the same portions as those in FIG. 2 are denoted by the same reference numerals.
[0165]
Components of the current source circuit having the fourth configuration will be described. The current source circuit having the fourth configuration includes a current source transistor 112 and a current stop transistor 805. Further, a current input transistor 803 and a current holding transistor 804 functioning as switches are provided. Here, the current source transistor 112, the current stop transistor 805, the current input transistor 803, and the current holding transistor 804 may be a P-channel type or an N-channel type. However, the current source transistor 112 and the current stop transistor 805 need to have the same polarity. Here, the current source transistor 112 and the current stop transistor 805 are examples of P-channel transistors. Further, it is desirable that the current source transistor 112 and the current stop transistor 805 have the same current characteristics. Further, it has a current source capacitor 111 that holds the gate potential of the current source transistor 112. Note that the current source capacitor 111 can be omitted by positively using the gate capacitor of the transistor. Further, a signal line GN for inputting a signal to the gate electrode of the current input transistor 803 and a signal line GH for inputting a signal to the gate electrode of the current holding transistor 804 are provided. Furthermore, it has a current line CL to which a control signal is input.
[0166]
The connection relationship of these components will be described. The source terminal of the current source transistor 112 is connected to the terminal A. The gate electrode and the source terminal of the current source transistor 112 are connected via a current source capacitor 111. The gate electrode of the current source transistor 112 is connected to the gate electrode of the current stop transistor 805, and is connected to the current line CL via the current holding transistor 804. The drain terminal of the current source transistor 112 is connected to the source terminal of the current stop transistor 805, and is connected to the current line CL via the current input transistor 803. The drain terminal of the current stop transistor 805 is connected to the terminal B.
[0167]
Note that in FIG. 12A, the arrangement of the current holding transistors 804 may be changed to have a circuit configuration as shown in FIG. In FIG. 12B, the current holding transistor 804 is connected between the gate electrode and the drain terminal of the current source transistor 112.
[0168]
Next, a method for setting the current source circuit having the fourth configuration will be described. In FIG. 12A and FIG. 12B, the setting operation is the same. Here, the setting operation will be described using the circuit shown in FIG. 12A as an example. 12C to 12F are used for the description. In the current source circuit of the fourth configuration, the setting operation is performed through the states of FIGS. 12C to 12F in order. In the description, for simplicity, the current input transistor 803 and the current holding transistor 804 are shown as switches. Here, an example in which the control signal for setting the current source circuit is a control current is shown. In the figure, a path through which current flows is indicated by a thick arrow.
[0169]
In a period TD1 illustrated in FIG. 12C, the current input transistor 803 and the current holding transistor 804 are turned on. At this time, the current stop transistor 805 is off. This is because the potentials of the source terminal and the gate electrode of the current stop transistor 805 are kept equal by the current holding transistor 804 and the current input transistor 803 that are turned on. In other words, the transistor that is turned off when the source-gate voltage is zero is used as the current stopping transistor 805, so that the current stopping transistor 805 is turned off in the period TD1. In this way, a current flows from the illustrated path, and electric charge is held in the current source capacitor 111.
[0170]
In the period TD2 illustrated in FIG. 12D, the gate-source voltage of the current source transistor 112 becomes equal to or higher than the threshold voltage due to the held charges. Then, a drain current flows through the current source transistor 112.
[0171]
When a sufficient time has elapsed and a steady state is reached, the drain current of the current source transistor 112 is determined as the control current as in a period TD3 shown in FIG. In this way, the gate voltage of the current source transistor 112 when the control current is the drain current is held in the current source capacitor 111. Thereafter, the current holding transistor 804 is turned off. Then, the charge held in the current source capacitor 111 is also distributed to the gate electrode of the current stop transistor 805. In this way, the current holding transistor 804 is turned off, and at the same time, the current stop transistor 805 is automatically turned on.
[0172]
In the period TD4 illustrated in FIG. 12F, the current input transistor 803 is turned off. Thus, no control current is input to the pixel. Note that the timing for turning off the current holding transistor 804 is preferably earlier or simultaneous with the timing for turning off the current input transistor 803. This is to prevent the electric charge held in the current source capacitor 111 from being discharged. When a voltage is applied between the terminal A and the terminal B after the period TD4, a constant current is output via the current source transistor 112 and the current stop transistor 805. That is, when the current source circuit 102 outputs a constant current, the current source transistor 112 and the current stop transistor 805 function as one multi-gate transistor. Therefore, the value of the constant current to be output can be set small with respect to the input control current. Therefore, the setting operation of the current source circuit can be speeded up. Note that the current stop transistor 805 and the current source transistor 112 must have the same polarity. It is desirable that the current stop transistor 805 and the current source transistor 112 have the same current characteristics. This is because, in each current source circuit 102 having the fourth configuration, when the characteristics of the current stop transistor 805 and the current source transistor 112 are not uniform, the output current of the current source circuit varies.
[0173]
In the current source circuit of the fourth configuration, not only the current stop transistor 805 but also a transistor (current source transistor 112) that receives a control current and converts the input control current into a corresponding gate voltage is used. A current is output from the current source circuit 102. On the other hand, in the current source circuit of the first configuration, a control current is input, a transistor (current transistor) that converts the input control current into a corresponding gate voltage, and a transistor (current) that converts the gate voltage into a drain current. Source transistor) was completely different. Therefore, the influence of the variation in the current characteristics of the transistors on the output current of the current source circuit 102 can be reduced in the fourth configuration than in the first configuration.
[0174]
Each signal line of the current source circuit of the fourth configuration can be shared. For example, the current input transistor 803 and the current holding transistor 804 have no problem in operation if they are switched on / off at the same timing. Therefore, the current input transistor 803 and the current holding transistor 804 can have the same polarity, and the signal line GH and the signal line GN can be shared.
[0175]
Next, a current source circuit having a fifth configuration will be described. Refer to FIG. 13 for the description. In FIG. 13A, the same portions as those in FIG. 2 are denoted by the same reference numerals.
[0176]
The components of the current source circuit having the fifth configuration will be described. The current source circuit having the fifth configuration includes a current source transistor 112 and a light emitting transistor 886. In addition, a current input transistor 883, a current holding transistor 884, and a current reference transistor 888 functioning as a switch are included. Here, the current source transistor 112, the light emitting transistor 886, the current input transistor 883, the current holding transistor 884, and the current reference transistor 888 may be P-channel type or N-channel type. However, the current source transistor 112 and the light emitting transistor 886 need to have the same polarity. Here, the current source transistor 112 and the light emitting transistor 886 are examples of P-channel transistors. Further, it is desirable that the current source transistor 112 and the light emitting transistor 886 have the same current characteristics. Further, it has a current source capacitor 111 that holds the gate potential of the current source transistor 112. Note that the current source capacitor 111 can be omitted by positively using the gate capacitor of the transistor. Further, a signal line GN for inputting a signal to the gate electrode of the current input transistor 883 and a signal line GH for inputting a signal to the gate electrode of the current holding transistor 884 are provided. Furthermore, it has a current line CL to which a control signal is input and a current reference line SCL that is kept at a constant potential.
[0177]
The connection relationship of these components will be described. The source terminal of the current source transistor 112 is connected to the terminal B, and is connected to the current reference line SCL via the current reference transistor 888. The drain terminal of the current source transistor 112 is connected to the source terminal of the light emitting transistor 886, and is connected to the current line CL via the current input transistor 883. The gate electrode and the source terminal of the current source transistor 112 are connected via a current source capacitor 111. The gate electrode of the current source transistor 112 and the gate electrode of the light emitting transistor 886 are connected, and are connected to the current line CL via the current holding transistor 884. The drain terminal of the light emitting transistor 886 is connected to the terminal A.
[0178]
Note that in FIG. 13A, the arrangement of the current holding transistors 884 may be changed to have a circuit configuration as shown in FIG. In FIG. 13B, the current holding transistor 884 is connected between the gate electrode and the drain terminal of the current source transistor 112.
[0179]
Next, a method for setting the current source circuit having the fifth configuration will be described. In FIG. 13A and FIG. 13B, the setting operation is the same. Here, the setting operation will be described using the circuit shown in FIG. 13A as an example. 13C to 13F are used for the description. In the current source circuit of the fifth configuration, the setting operation is performed through the states of FIGS. 13C to 13F in order. In the description, for simplicity, the current input transistor 883, the current holding transistor 884, and the current reference transistor 888 are represented as switches. Here, an example in which the control signal for setting the current source circuit is a control current is shown. In the figure, a path through which current flows is indicated by a thick arrow.
[0180]
In a period TD1 illustrated in FIG. 13C, the current input transistor 883, the current holding transistor 884, and the current reference transistor 888 are turned on. At this time, the light-emitting transistor 886 is in an off state. This is because the potentials of the source terminal and the gate electrode of the light-emitting transistor 886 are kept equal by the current holding transistor 884 and the current input transistor 883 which are turned on. In other words, the transistor that is turned off when the source-gate voltage is zero is used for the light-emitting transistor 886, so that the light-emitting transistor 886 is turned off in the period TD1. In this way, a current flows from the illustrated path, and electric charge is held in the current source capacitor 111.
[0181]
In a period TD2 illustrated in FIG. 13D, the voltage between the gate and the source of the current source transistor 112 becomes equal to or higher than the threshold voltage due to the charge held in the current source capacitor 111. Then, a drain current flows through the current source transistor 112.
[0182]
When a sufficient time elapses and a steady state is reached, the drain current of the current source transistor 112 is determined as the control current as in a period TD3 shown in FIG. In this way, the gate voltage of the current source transistor 112 when the control current is the drain current is held in the current source capacitor 111. Thereafter, the current holding transistor 884 is turned off. Then, the charge held in the current source capacitor 111 is also distributed to the gate electrode of the light emitting transistor 886. Thus, the current holding transistor 884 is turned off, and at the same time, the light emitting transistor 886 is automatically turned on.
[0183]
In a period TD4 illustrated in FIG. 13F, the current reference transistor 888 and the current input transistor 883 are turned off. Thus, no control current is input to the pixel. Note that the timing for turning off the current holding transistor 884 is preferably earlier or at the same time as the timing for turning off the current input transistor 883. This is to prevent the electric charge held in the current source capacitor 111 from being discharged. When a voltage is applied between the terminal A and the terminal B after the period TD4, a constant current is output through the current source transistor 112 and the light emitting transistor 886. That is, when the current source circuit 102 outputs a constant current, the current source transistor 112 and the light emitting transistor 886 function as one multi-gate transistor. Therefore, the value of the constant current to be output can be set small with respect to the input control current. Thus, the setting operation of the current source circuit can be speeded up. Note that the polarities of the light emitting transistor 886 and the current source transistor 112 need to be the same. The current characteristics of the light emitting transistor 886 and the current source transistor 112 are preferably the same. This is because in each current source circuit 102 having the fifth configuration, when the characteristics of the light emitting transistor 886 and the current source transistor 112 are not uniform, the output current varies.
[0184]
In the current source circuit of the fifth configuration, a current from the current source circuit 102 is also obtained by using a transistor (current source transistor 112) that receives the control current and converts the input control current into a corresponding gate voltage. Output. On the other hand, in the current source circuit of the first configuration, a control current is input, a transistor (current transistor) that converts the input control current into a corresponding gate voltage, and a transistor (current) that converts the gate voltage into a drain current. Source transistor) was completely different. Therefore, the influence of variations in transistor current characteristics on the output current of the current source circuit 102 can be reduced as compared with the first configuration.
[0185]
Note that the current reference line SCL and the current reference transistor 888 are not required when a current is supplied to the terminal B in the period TD1 to the period TD3 in the setting operation.
[0186]
Each signal line of the current source circuit of the fifth configuration can be shared. For example, the current input transistor 883 and the current holding transistor 884 have no operational problem as long as they are switched on and off at the same timing. Therefore, the current input transistor 883 and the current holding transistor 884 can have the same polarity, and the signal line GH and the signal line GN can be shared. In addition, the current reference transistor 888 and the current input transistor 883 have no problem in operation as long as they are switched on and off at the same timing. Therefore, the current reference transistor 888 and the current input transistor 883 have the same polarity, and the signal line GN and the signal line GC can be shared.
[0187]
Next, the current source circuits having the first to fifth configurations described above are grouped together in a slightly larger framework for each feature.
[0188]
The five current source circuits described above are roughly classified into a current mirror type current source circuit, an identical transistor type current source circuit, and a multi-gate type current source circuit. These will be described below.
[0189]
An example of the current mirror type current source circuit is a current source circuit having a first configuration. In the current mirror type current source circuit, the signal input to the light emitting element is a current obtained by increasing or decreasing the control current input to the pixel by a predetermined magnification. For this reason, it is possible to set the control current large to some extent. Therefore, the setting operation of the current source circuit of each pixel can be performed quickly. However, if the current characteristics of a pair of transistors constituting the current mirror circuit included in the current source circuit are different, there is a problem that image display varies.
[0190]
Examples of the same transistor type current source circuit include a current source circuit having a second configuration and a third configuration. In the same transistor type current source circuit, the signal input to the light emitting element is equal to the current value of the control current input to the pixel. Here, in the same transistor type current source circuit, the transistor to which the control current is input and the transistor that outputs the current to the light emitting element are the same. Therefore, image unevenness due to variation in current characteristics of transistors is reduced.
[0191]
Examples of the multi-gate type current source circuit include a current source circuit having a fourth configuration and a fifth configuration. In the multi-gate type current source circuit, the signal input to the light emitting element is a current obtained by increasing or decreasing the control current input to the pixel by a predetermined magnification. For this reason, it is possible to set the control current large to some extent. Therefore, the setting operation of the current source circuit of each pixel can be performed quickly. In addition, a part of the transistor that outputs current to the light emitting element is shared with the transistor to which the control current is input. Therefore, image unevenness due to variations in current characteristics of transistors is reduced as compared with a current mirror type current source circuit.
[0192]
Next, the relationship between the setting operation and the operation of the paired switch units in each of the above-described three categories of current source circuits will be described.
[0193]
The relationship between the setting operation in the case of the current mirror type current source circuit and the operation of the corresponding switch unit is shown below. In the case of a current mirror type current source circuit, a predetermined constant current can be output even while a control current is being input. Therefore, it is not necessary to synchronize the operation of the paired switch units and the setting operation of the current source circuit.
[0194]
The relationship between the setting operation in the case of the same transistor type current source circuit and the operation of the corresponding switch unit is shown below. In the case of the same transistor type current source circuit, a constant current cannot be output while the control current is input. Therefore, it is necessary to synchronize the operation of the paired switch units and the setting operation of the current source circuit. For example, the setting operation of the current source circuit can be performed only when the switch unit is in an off state.
[0195]
The relationship between the setting operation in the case of the multi-gate type current source circuit and the operation of the corresponding switch unit is shown below. In the case of a multi-gate current source circuit, a constant current cannot be output while a control current is input. Therefore, it is necessary to synchronize the operation of the paired switch units and the setting operation of the current source circuit. For example, the setting operation of the current source circuit can be performed only when the switch unit is in an off state.
[0196]
Next, in the case where the setting operation of the current source circuit and the operation of the paired switch unit are synchronized, the operation when combined with the time gray scale method will be described in detail.
[0197]
Here, attention is paid to the case where the setting operation of the current source circuit is performed only when the switch unit is in the OFF state. Note that the detailed description of the time gray scale method is the same as the method described in the second embodiment, and thus the description thereof is omitted here. When the time gray scale method is used, it is a non-display period that the switch portion is always in an off state. Therefore, the setting operation of the current source circuit can be performed in the non-display period.
[0198]
The non-display period starts by sequentially selecting each pixel row in the reset period. Here, the setting operation of each pixel row can be performed at the same frequency as the frequency for sequentially selecting the scanning lines. For example, attention is paid to the case where the switch unit having the configuration shown in FIG. The setting operation of the current source circuit can be performed by selecting each pixel row at the same frequency as the frequency for sequentially selecting the scanning line G and the erasing signal line RG.
[0199]
However, it may be difficult to sufficiently perform the setting operation of the current source circuit with the length of the selection period for one row. In that case, the setting operation of the current source circuit may be performed slowly using a selection period for a plurality of rows. Slowly performing the setting operation of the current source circuit indicates that the operation of accumulating a predetermined charge in the current source capacity of the current source circuit is performed slowly over a long time.
[0200]
As described above, each row is selected using a selection period for a plurality of rows and using the same frequency as the frequency for selecting the erasing signal line RG and the like in the reset period. Will do. Therefore, in order to perform the setting operation for pixels in all rows, it is necessary to perform the setting operation in a plurality of non-display periods.
[0201]
Next, a configuration of the display device and a driving method when the above method is used will be described in detail. First, a driving method for performing a setting operation for pixels in one row using a period having the same length as a period in which a plurality of scanning lines are selected will be described. FIG. 14 is used for the description. In the figure, as an example, a timing chart for performing the setting operation of pixels in one row during a period in which ten scanning lines are selected is shown.
[0202]
FIG. 14A shows the operation of each row in each frame period. Note that the same portions as those in the timing chart shown in FIG. 4 in the second embodiment are denoted by the same reference numerals, and description thereof is omitted. Here, one frame period is divided into three subframe periods SF. 1 ~ SF Three An example of the division is shown. The subframe period SF 2 And SF Three In each case, a non-display period Tus is provided. A pixel setting operation is performed during the non-display period Tus (period A and period B in the figure).
[0203]
Next, operations in the period A and the period B will be described in detail. FIG. 14B is used for the description. In the drawing, the period during which the pixel setting operation is performed is shown as the period during which the signal line GN is selected. In general, the signal line GN of the pixel in the i-th row (i is a natural number) is GN i It showed in. First, the first frame period F 1 In period A, GN 1 , GN 11 , GN twenty one , ... selected one after another. Thus, the pixel setting operation for the first row, the eleventh row, the twenty-first row,... Is performed (period 1). Then, the first frame period F 1 In period B of GN 2 , GN 12 , GN twenty two , ... are selected. Thus, the pixel setting operation for the second row, the twelfth row, the twenty-second row,... Is performed (period 2). By repeating the above operation for a period of 5 frames, the setting operation for all the pixels is performed in a single operation.
[0204]
Here, a period that can be used for the setting operation of pixels in one row is denoted as Tc.
When the above driving method is used, Tc can be set to 10 times the selection period of the scanning line G. Thus, the time used for the setting operation per pixel can be lengthened. In addition, the pixel setting operation can be performed efficiently and accurately.
[0205]
If a single setting operation is not sufficient, the above operation may be repeated a plurality of times to gradually perform the pixel setting operation.
[0206]
Next, a structure of a driver circuit when the above driving method is used will be described with reference to FIG. FIG. 15 shows a drive circuit for inputting a signal to the signal line GN. However, the same applies to signals input to other signal lines of the current source circuit. Two configuration examples of a driving circuit for performing a pixel setting operation are given.
[0207]
The first example is a driving circuit configured to switch the output of the shift register by a switching signal and output the signal to the signal line GN. An example of the structure of this drive circuit (setting operation drive circuit) is shown in FIG. The setting operation drive circuit 5801 includes a shift register 5802, an AND circuit, an inverter circuit (INV), and the like. Note that here, an example of a driver circuit having a structure in which one signal line GN is selected is four times the pulse output period of the shift register 5802.
[0208]
The operation of the setting operation drive circuit 5801 will be described. The output of the shift register 5802 is selected by the switching signal 5803 and is output to the signal line GN through the AND circuit.
[0209]
The second example is a driving circuit configured to latch a signal for selecting a specific row by the output of the shift register. An example of the structure of this drive circuit (setting operation drive circuit) is shown in FIG. The setting operation drive circuit 5811 includes a shift register 5812, a latch 1 circuit 5813, and a latch 2 circuit 5814.
[0210]
The operation of the setting operation drive circuit 5811 will be described. Based on the output of the shift register 5812, the latch 1 circuit 5813 holds the row selection signal 5815 in order. Here, the row selection signal 5815 is a signal for selecting an arbitrary output among the outputs of the shift register 5812. The signal held in the latch 1 circuit 5813 is transferred to the latch 2 circuit 5814 by the latch signal 5816. Thus, a signal is input to the specific signal line GN.
[0211]
Even in the display period, the setting operation can be performed in the case of a current mirror type current source circuit. Even in the same transistor type current source circuit or multi-gate type current source circuit, a driving method is used in which the display period is temporarily interrupted, the setting operation of the current source circuit is performed, and then the display period is restarted. Also good.
[0212]
This embodiment mode can be implemented by being freely combined with Embodiment Mode 1 and Embodiment Mode 2.
[0213]
(Embodiment 4)
In this embodiment, the structure and operation of each pixel will be described. Note that a case where each pixel has two pairs of a switch unit and a current source circuit is taken as an example. An example will be described in which the configurations of the two current source circuits of the two pairs are selected from the configurations of the five current source circuits shown in the third embodiment and combined.
[0214]
A first combination example is shown. In the first combination example, each of the two current source circuits (the first current source circuit and the second current source circuit) included in the pixel is the current source circuit having the fourth configuration illustrated in FIG. It is. Note that the configuration of these current source circuits is the same as that of the third embodiment, and thus detailed description thereof is omitted.
[0215]
FIG. 16 shows the configuration of the pixels of the first combination example. Note that in FIG. 16, the same portions as those in FIG. 12A are denoted by the same reference numerals. Note that a part corresponding to the first current source circuit is indicated by adding a after the reference in FIG. Further, the part corresponding to the second current source circuit is indicated by adding b after the reference in FIG. In addition, the configuration of two switch units (a first switch unit and a second switch unit) of a pair of a switch unit and a current source circuit included in each pixel is referred to Embodiment Mode 2, and the description thereof is omitted here.
[0216]
Here, the first current source circuit 102a and the second current source circuit 102b can share wirings and elements. A signal line can be shared. For example, the signal line GNa and the signal line GNb can be shared. Further, the signal line GHa and the signal line GHb can be shared. This structure is shown in FIG. Alternatively, the current line CLa and the current line CLb can be shared. This structure is shown in FIG.
Note that the structures in FIGS. 17A and 17B can be freely combined.
[0217]
The setting method of each of the current source circuits 102a and 102b is the same as that in the third embodiment. The current source circuits 102a and 102b are multi-gate type current source circuits. Therefore, the setting operation is desirably performed in synchronization with the operation of the switch unit.
[0218]
This embodiment mode can be implemented freely combining with Embodiment Modes 1 to 3.
[0219]
(Embodiment 5)
In this embodiment, the structure and operation of each pixel will be described. An example in which each pixel has two pairs of a switch unit and a current source circuit will be described. An example will be described in which the configurations of the two current source circuits of the two pairs are selected from the configurations of the five current source circuits shown in the third embodiment and combined.
[0220]
A second combination example that is different from the first combination example shown in the fourth embodiment will be described. In the second combination example, one of the two current source circuits included in the pixel (first current source circuit) is the current source circuit having the fourth configuration illustrated in FIG. Another current source circuit (second current source circuit) is the current source circuit having the first configuration shown in FIG. Note that the configuration of these current source circuits is the same as that of the third embodiment, and thus detailed description thereof is omitted.
[0221]
FIG. 18 shows a pixel configuration of the second combination example. Note that in FIG. 18, the same portions as those in FIGS. 12A and 9A are denoted by the same reference numerals. Note that a part corresponding to the first current source circuit is indicated by adding a after the reference in FIG. Further, the part corresponding to the second current source circuit is indicated by adding b after the reference numeral in FIG. In addition, the configuration of two switch units (a first switch unit and a second switch unit) of a pair of a switch unit and a current source circuit included in each pixel is referred to Embodiment Mode 2, and the description thereof is omitted here.
[0222]
Here, the first current source circuit 102a and the second current source circuit 102b can share wirings and elements. It is possible to share the current transistor 1405b between different pixels. In addition, the current source capacity can be shared. This configuration is shown in FIG. Further, the signal line can be shared. For example, the signal line GNa and the signal line GNb can be shared. Further, the signal line GHa and the signal line GHb can be shared. This structure is shown in FIG. Alternatively, the current line CLa and the current line CLb can be shared. This structure is shown in FIG.
Note that the structures in FIGS. 40, 19A, and 19B can be freely combined.
[0223]
The setting method of each of the current source circuits 102a and 102b is the same as that in the third embodiment. The current source circuit 102a is a multi-gate type current source circuit. Therefore, the setting operation is desirably performed in synchronization with the operation of the switch unit. On the other hand, the current source circuit 102b is a current mirror type current source circuit. Therefore, the setting operation can be performed asynchronously with the operation of the switch unit.
[0224]
In the pixel configuration of this embodiment, when different current values are output from the multi-gate current source circuit and the current mirror-type current source circuit of each pixel, the output of the multi-gate current source circuit It is desirable to set the current value larger than the current value of the output current of the current mirror type current source circuit. The reason will be described below.
[0225]
As described in Embodiment 3, the multi-gate type current source circuit shares a part of the transistor that outputs current to the light emitting element and the transistor to which the control current is input. These transistors are separate in the source circuit. For this reason, the current mirror type current source circuit can input a control current having a larger current value than the output current value than the multi-gate type current source circuit. By using a control current having a large current value, the setting operation of the current source circuit can be performed accurately because it is fast and hardly affected by noise. Therefore, if an output current having the same current value is set, the setting operation of the current source circuit is slower in the multi-gate type current source circuit than in the current mirror type current source circuit. Therefore, in the multi-gate type current source circuit, the current value of the output current is made larger than the current mirror type current source circuit, the current value of the control current is increased, and the setting operation of the current source circuit is performed quickly and accurately. It is desirable to do.
[0226]
Further, as described in the third embodiment, the current mirror type current source circuit has a large variation in output current compared to the multi-gate type current source circuit. The larger the current value of the output current of the current source circuit, the greater the influence of variation. Therefore, if output currents having the same current value are set, the current mirror type current source circuit has a larger variation in output current than the multi-gate type current source circuit. Therefore, in the current mirror type current source circuit, it is desirable to reduce the variation in the output current by reducing the current value of the output current compared to the multi-gate type current source circuit.
[0227]
As described above, in the pixel configuration of this embodiment, when the current values of the currents output from the multi-gate type current source circuit and the current mirror type current source circuit of each pixel are different, the multi-gate type current source It is desirable that the current value of the output current of the circuit is set larger than the current value of the output current of the current mirror type current source circuit.
[0228]
When the pixel configuration of FIG. 40 is used, it is desirable that the output current of the current source circuit 102a be set larger than the output current of the current source circuit 102b. Thus, the setting operation can be performed quickly by increasing the output current of the current source circuit 102a that performs the setting operation. Further, in the current source circuit 102b in which the drain current of the transistor 112b different from the transistor to which the control current is input is used as the output current, the influence of the variation can be reduced by setting the output current small.
[0229]
This embodiment mode can be implemented freely combining with Embodiment Modes 1 to 3.
[0230]
(Embodiment 6)
In this embodiment, the structure and operation of each pixel will be described. An example in which each pixel has two pairs of a switch unit and a current source circuit will be described. An example will be described in which the configurations of the two current source circuits of the two pairs are selected from the configurations of the five current source circuits shown in the third embodiment and combined.
[0231]
Note that a third combination example different from the first combination example and the second combination example shown in the fourth and fifth embodiments will be described. In the third combination example, one of the two current source circuits included in the pixel (first current source circuit) is the current source circuit having the fourth configuration illustrated in FIG. Another current source circuit (second current source circuit) is the current source circuit having the third configuration shown in FIG. Note that the configuration of these current source circuits is the same as that of the third embodiment, and thus detailed description thereof is omitted.
[0232]
FIG. 20 shows the configuration of the pixels of the third combination example. Note that in FIG. 20, the same portions as those in FIGS. 12A and 11A are denoted by the same reference numerals. Note that a part corresponding to the first current source circuit is indicated by adding a after the reference in FIG. Further, the part corresponding to the second current source circuit is indicated by adding b after the reference numeral in FIG. In addition, the configuration of two switch units (a first switch unit and a second switch unit) of a pair of a switch unit and a current source circuit included in each pixel is referred to Embodiment Mode 2, and the description thereof is omitted here.
[0233]
Here, the first current source circuit 102a and the second current source circuit 102b can share wirings and elements. For example, the current source capacity can be shared. This configuration is the same as in FIG. A signal line can be shared. For example, the signal line GNa and the signal line GNb can be shared. Further, the signal line GHa and the signal line GHb can be shared. This structure is shown in FIG. Alternatively, the current line CLa and the current line CLb can be shared. This structure is shown in FIG. Alternatively, the signal line Sb can be used instead of the current line CLb. This structure is shown in FIG. 40 and FIGS. 21A to 21C can be freely combined.
[0234]
The setting method of each of the current source circuits 102a and 102b is the same as that in the third embodiment. The current source circuit 102a is a multi-gate type current source circuit. Therefore, it is desirable to perform the setting operation in synchronization with the operation of the switch unit. The current source circuit 102b is the same transistor type current source circuit. Therefore, the setting operation is desirably performed in synchronization with the operation of the switch unit.
[0235]
In the pixel configuration of this embodiment, when different current values are output from the same transistor type current source circuit and multi-gate type current source circuit of each pixel, the output of the same transistor type current source circuit It is desirable to set the current value larger than the current value of the output current of the multi-gate type current source circuit. The reason will be described below.
[0236]
As described in the third embodiment, it is necessary to input a control current having the same current value as that of the output current in the same transistor type current source circuit. However, in the multi-gate type current source circuit, the current value of the output current is changed. On the other hand, it is possible to input a control current having a large current value. By using a control current having a large current value, the setting operation of the current source circuit can be performed accurately because it is fast and hardly affected by noise. Therefore, if an output current having the same current value is set, the setting operation of the current source circuit is slower in the same transistor type current source circuit than in the multi-gate type current source circuit. Therefore, in the same transistor type current source circuit, the current value of the output current is made larger than the multi-gate type current source circuit, the current value of the control current is increased, and the setting operation of the current source circuit can be performed quickly and accurately. It is desirable to do.
[0237]
As described in the third embodiment, the multi-gate type current source circuit has a large variation in output current as compared with the same transistor type current source circuit. The larger the current value of the output current of the current source circuit, the greater the influence of variation. For this reason, if output currents having the same current value are set, variation in output current is larger in the multi-gate type current source circuit than in the same transistor type current source circuit. Therefore, in a multi-gate type current source circuit, it is desirable to reduce the output current variation by making the current value of the output current smaller than that of the same transistor type current source circuit.
[0238]
As described above, in the pixel configuration of this embodiment, when different current values are output from the same transistor type current source circuit and multi-gate type current source circuit of each pixel, the same transistor type current source It is desirable that the current value of the output current of the circuit is set larger than the current value of the output current of the multi-gate type current source circuit.
[0239]
This embodiment mode can be implemented freely combining with Embodiment Modes 1 to 3.
[0240]
(Embodiment 7)
In this embodiment, the structure and operation of each pixel will be described. An example in which each pixel has two pairs of a switch unit and a current source circuit will be described. An example will be described in which the configurations of the two current source circuits of the two pairs are selected from the configurations of the five current source circuits shown in the third embodiment and combined.
[0241]
Note that a fourth combination example different from the first to third combination examples shown in the fourth to sixth embodiments will be described. In the fourth combination example, one of the two current source circuits included in the pixel (first current source circuit) is the current source circuit having the fourth configuration illustrated in FIG. Another current source circuit (second current source circuit) is the current source circuit having the second configuration shown in FIG. Note that the configuration of these current source circuits is the same as that of the third embodiment, and thus detailed description thereof is omitted.
[0242]
FIG. 22 shows the configuration of the pixels of the fourth combination example. Note that in FIG. 22, the same portions as those in FIGS. 10A and 12A are denoted by the same reference numerals. Note that the part corresponding to the first current source circuit is indicated by adding a after the reference in FIG. Further, the part corresponding to the second current source circuit is indicated by adding b after the reference in FIG. In addition, the configuration of two switch units (a first switch unit and a second switch unit) of a pair of a switch unit and a current source circuit included in each pixel is referred to Embodiment Mode 2, and the description thereof is omitted here.
[0243]
Here, the first current source circuit 102a and the second current source circuit 102b can share wirings and elements. A signal line can be shared. For example, the signal line GNa and the signal line GNb can be shared. Further, the signal line GHa and the signal line GHb can be shared. This structure is shown in FIG. Alternatively, the current line CLa and the current line CLb can be shared. This structure is shown in FIG. Further, the signal line Sb can be used instead of the current line CLb. This structure is shown in FIG. Note that the structures in FIGS. 23A to 23C can be freely combined.
[0244]
The setting method of each of the current source circuits 102a and 102b is the same as that in the third embodiment. The current source circuit 102a is a multi-gate type current source circuit. Therefore, it is desirable to perform the setting operation in synchronization with the operation of the switch unit. The current source circuit 102b is the same transistor type current source circuit. Therefore, the setting operation is desirably performed in synchronization with the operation of the switch unit.
[0245]
In the pixel configuration of this embodiment, when different current values are output from the same transistor type current source circuit and multi-gate type current source circuit of each pixel, the output of the same transistor type current source circuit It is desirable to set the current value larger than the current value of the output current of the multi-gate type current source circuit. The reason for this is the same as in the sixth embodiment, and a description thereof will be omitted.
[0246]
This embodiment mode can be implemented freely combining with Embodiment Modes 1 to 3.
[0247]
(Embodiment 8)
In this embodiment, the structure and operation of each pixel will be described. An example in which each pixel has two pairs of a switch unit and a current source circuit will be described. An example will be described in which the configurations of the two current source circuits of the two pairs are selected from the configurations of the five current source circuits shown in the third embodiment and combined.
[0248]
Note that a fifth combination example different from the first to fourth combination examples shown in the fourth to seventh embodiments will be described. In the fifth combination example, one of the two current source circuits included in the pixel (first current source circuit) is the current source circuit having the fourth configuration illustrated in FIG. Another current source circuit (second current source circuit) is the current source circuit having the fifth configuration shown in FIG. Note that the configuration of these current source circuits is the same as that of the third embodiment, and thus detailed description thereof is omitted.
[0249]
FIG. 24 shows the pixel configuration of the fifth combination example. Note that in FIG. 24, the same portions as those in FIGS. 12A and 13A are denoted by the same reference numerals. Note that the part corresponding to the first current source circuit is indicated by adding a after the reference in FIG. Further, the part corresponding to the second current source circuit is indicated by adding b after the reference in FIG. In addition, the configuration of two switch units (a first switch unit and a second switch unit) of a pair of a switch unit and a current source circuit included in each pixel is referred to Embodiment Mode 2, and the description thereof is omitted here.
[0250]
Here, the first current source circuit 102a and the second current source circuit 102b can share wirings and elements. A signal line can be shared. For example, the signal line GNa and the signal line GNb can be shared. Further, the signal line GHa and the signal line GHb can be shared. This structure is shown in FIG. Alternatively, the current line CLa and the current line CLb can be shared. This structure is shown in FIG.
Note that the structures in FIGS. 25A and 25B can be freely combined.
[0251]
The setting method of each of the current source circuits 102a and 102b is the same as that in the third embodiment. The current source circuit 102a is a multi-gate type current source circuit. Therefore, it is desirable to perform the setting operation in synchronization with the operation of the switch unit. The current source circuit 102b is a multi-gate type current source circuit. Therefore, it is desirable to perform the setting operation in synchronization with the operation of the switch unit.
[0252]
This embodiment mode can be implemented freely combining with Embodiment Modes 1 to 3.
[0253]
(Embodiment 9)
In this embodiment mode, four specific examples in the case of expressing gradation in combination with a time gradation method in the pixel configuration of the present invention are shown. Note that the basic description of the time gray scale method has been given in Embodiment 2, and therefore the description thereof is omitted here. In this embodiment, a case where 64 gradations are expressed is illustrated.
[0254]
A first example is shown. By appropriately determining the output currents of the plurality of current source circuits of each pixel, the current value (I) of the current flowing through the light emitting element is changed to a ratio of 1: 2. At this time, one frame period is divided into three subframe periods, and the ratio of the display period length (T) of each subframe period is set to 1: 4: 16. Thus, as shown in Table 1, 64 gradations can be expressed by the combination of the current flowing through the light emitting element (denoted as current I) and the length of the display period (denoted as period T).
[0255]
[Table 1]
[0256]
A second example is shown. By appropriately determining the output currents of the plurality of current source circuits of each pixel, the current value (I) of the current flowing through the light emitting element is changed to a ratio of 1: 4. At this time, one frame period is divided into three subframe periods, and the ratio of the display period lengths (T) of each subframe period is set to 1: 2: 16. Thus, as shown in Table 2, 64 gradations can be expressed by the combination of the current I flowing through the light emitting element and the period T.
[0257]
[Table 2]
[0258]
A third example is shown. By appropriately determining the output currents of the plurality of current source circuits of each pixel, the current value (I) of the current flowing through the light emitting element is changed to a ratio of 1: 2: 4. At this time, one frame period is divided into two subframe periods, and the ratio of the length (T) of the display period of each subframe period is set to 1: 8. Thus, as shown in Table 3, 64 gradations can be expressed by the combination of the current I flowing through the light emitting element and the period T.
[Table 3]
[0259]
A fourth example is shown. By appropriately determining the output currents of the plurality of current source circuits included in each pixel, the current value (I) of the current flowing through the light emitting element is changed to a ratio of 1: 4: 16. At this time, one frame period is divided into two subframe periods, and the ratio of the display period length (T) of each subframe period is set to 1: 2. Thus, as shown in Table 4, 64 gradations can be expressed by the combination of the current I flowing through the light emitting element and the period T.
[0260]
[Table 4]
[0261]
Note that this embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 8.
[0262]
(Embodiment 10)
In the first to ninth embodiments, each pixel has a plurality of pairs of current source circuits and switch units. However, each pixel may have only one pair of a current source circuit and a switch unit.
[0263]
For example, FIG. 42 shows the configuration of a pixel having only one pair of the current source circuit and the switch unit of the fourth configuration.
[0264]
If each pixel has one switch unit and current source circuit pair, two gradations can be expressed. Note that multiple gradations are possible by combining with other gradation display methods. For example, gradation display can be performed in combination with the time gradation method.
[0265]
This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 9.
[0266]
(Embodiment 11)
Each pixel may have three or more current source circuits. For example, in the first combination example to the fifth combination example shown in the fourth to eighth embodiments, an arbitrary circuit is added among the current source circuits having the five configurations shown in the third embodiment. be able to.
[0267]
This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 10.
[0268]
(Embodiment 12)
In this embodiment mode, a structure of a driver circuit that inputs a control current to each pixel in the display device of the present invention will be described.
[0269]
If the control current input to each pixel varies, the current value of the current output from the current source circuit of each pixel also varies. Therefore, a drive circuit configured to output a substantially constant control current to each current line is required. An example of such a drive circuit is shown below.
[0270]
For example, a signal line driver circuit having a configuration shown in Japanese Patent Application No. 2001-333462, Japanese Patent Application No. 2001-333466, Japanese Patent Application No. 2001-333470, Japanese Patent Application No. 2001-335917, or Japanese Patent Application No. 2001-335918 can be used. That is, the output current of the signal line driver circuit can be input to each pixel as a control current.
[0271]
In the display device of the present invention, by applying the signal line driver circuit, a substantially constant control current can be input to each pixel. In this way, it is possible to further reduce variations in image brightness.
[0272]
This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 11.
[0273]
(Embodiment 13)
In this embodiment mode, a display system to which the present invention is applied will be described.
[0274]
Here, the display system means a memory for storing a video signal input to the display device, a circuit for outputting a control signal (clock pulse, start pulse, etc.) input to each drive circuit of the display device, and a controller for controlling them. Etc.
[0275]
An example of the display system is shown in FIG. In addition to the display device, the display system includes an A / D conversion circuit, a memory selection switch A, a memory selection switch B, a frame memory 1, a frame memory 2, a controller, a clock signal generation circuit, and a power generation circuit.
[0276]
The operation of the display system will be described. The A / D conversion circuit converts the video signal input to the display system into a digital video signal. The frame memory A or the frame memory B stores the digital video signal. Here, by using the frame memory A or the frame memory B for each period (every one frame period, every subframe period), it is possible to provide a margin for writing a signal to the memory and reading a signal from the memory. . The frame memory A or the frame memory B is selectively used by switching the memory selection switch A and the memory selection switch B by the controller. The clock generation circuit generates a clock signal or the like by a signal from the controller. The power generation circuit generates a predetermined power according to a signal from the controller. A signal read from the memory, a clock signal, a power supply, and the like are input to the display device via the FPC.
[0277]
Note that the display system to which the present invention is applied is not limited to the configuration shown in FIG. The present invention can be applied to display systems having any known configuration.
[0278]
This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 12.
[0279]
(Embodiment 14)
The present invention can be applied to various electronic devices. That is, the components of the present invention can be applied to a portion (display unit) that performs image display of various electronic devices.
[0280]
As an example of the electronic apparatus of the present invention, a video camera, a digital camera, a goggle type display (head-mounted display), a navigation system, an audio playback device (car audio, audio component, etc.), a notebook type personal computer, a game machine, a portable information terminal (Mobile computer, mobile phone, portable game machine, electronic book or the like), image playback device provided with a recording medium (specifically, a device provided with a display that can play back a recording medium such as a DVD and display the image) ) And the like.
[0281]
Note that the present invention can be applied to various electronic devices without being limited to the above electronic devices.
[0282]
This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 13.
[0283]
(Embodiment 15)
In the display device of the present invention, the current source transistor operates in the saturation region. Therefore, in this embodiment, an optimum range of the channel length of the current source transistor that can suppress the power consumption of the display device and can maintain the linearity of the operation in the saturation region of the current source transistor will be described. .
[0284]
The current source transistor included in the display device of the present invention operates in the saturation region, and its drain current I d Is represented by Equation 1 below. V gs Is the gate voltage, μ is the mobility, C 0 Is the gate capacitance per unit area, W is the channel width, L is the channel length, V th Is the threshold and drain current is I d And
[0285]
[Formula 1]
I d = ΜC 0 W / L (V gs -V th ) 2 / 2
[0286]
From Equation 1, μ, C 0 , V th , W is fixed, I d Is V ds L and V without depending on the value of gs It can be seen that it is determined by the value of.
[0287]
Incidentally, power consumption corresponds to the product of current and voltage. I d Is proportional to the luminance of the light-emitting element, so when the luminance is determined, I d The value of is fixed. Therefore, when considering reduction of power consumption, | V gs It can be seen that a lower | is desirable, and therefore a smaller value of L is desirable.
[0288]
However, as the value of L decreases, the linearity of the saturation region is not gradually maintained due to the Early effect or the kink effect. That is, the operation of the current source transistor does not follow the above equation 1, and I d Value of V gradually ds Depends on. V ds The value of V is due to deterioration of the light emitting element. EL In order to increase with decreasing d The value of is easily affected by the deterioration of the light emitting element.
[0289]
In other words, it is not desirable that the value of L is too small in consideration of the linearity of the saturation region, and if it is too large, power consumption cannot be suppressed. Most preferably, the value of L is made smaller as long as the linearity of the saturation region is maintained.
[0290]
In FIG. 44, W = 4 μm, V ds L and ΔI in a P-channel TFT when = 10V d The relationship is shown. ΔI d Is I d Is a value obtained by differentiating L with respect to L. d It corresponds to the slope of. Therefore ΔI d The smaller the value of, the higher the I in the saturation region d This means that the linearity is maintained. As shown in FIG. 44, when L is increased, L is increased from about 100 μm to ΔI. d It can be seen that the value of has decreased dramatically. Therefore, in order to maintain the linearity of the saturation region, it can be seen that L is preferably about 100 μm or larger.
[0291]
In view of power consumption, it is more desirable that L is smaller. Therefore, in order to satisfy both conditions, it is most desirable that L is 100 ± 10 μm. That is, by setting the range of L to 90 μm ≦ L ≦ 110 μm, it is possible to suppress power consumption of a display device having a current source transistor and maintain linearity in a saturation region of the current source transistor.
[0292]
This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 14.
[0293]
(Embodiment 16)
In the present embodiment, the driving method for further reducing the luminance variation described in the means for solving the problem, that is, the driving method for selectively using a plurality of current source circuits set to the same output current when expressing the same gradation. The structural example of the pixel which uses is shown.
[0294]
The pixel shown in this embodiment has a structure in which a plurality of current source circuits are provided and a switch unit paired with the plurality of current source circuits is shared. One digital video signal is input to each pixel, and an image is displayed by selectively using a plurality of current source circuits. Thus, the number of elements included in each pixel can be reduced and the aperture ratio can be increased. The plurality of current source circuits sharing the switch unit are set to output the same constant current. Then, when expressing the same gradation, different current source circuits that output the same constant current are used. In this way, even if the output current of the current source circuit varies, the current flowing through the light emitting element is averaged over time. Therefore, it is possible to visually reduce the luminance variation due to the variation in the output current of the current source circuit between the pixels.
[0295]
FIG. 43 shows a structure of the pixel of this embodiment mode. 7 and 8 are denoted by the same reference numerals, and description thereof is omitted.
[0296]
FIG. 43A shows a configuration in which the selection transistor 301 is shared in the switch portions 101a and 101b corresponding to the current source circuit. FIG. 43B shows a configuration in which the selection transistor 301 and the driving transistor 302 are shared in the switch portions 101a and 101b corresponding to the current source circuits 102a and 102b. Note that although not shown in FIG. 43, an erasing transistor 304 as shown in Embodiment Mode 2 may be provided. The connection method of the erasing transistor 304 in the pixel can be the same as that in the second embodiment.
[0297]
As the current source circuits 102a and 102b, the current source circuits having the first to fifth configurations described in Embodiment 3 can be freely applied. However, in the configuration in which a switch unit paired with a plurality of current source circuits is shared as in the present embodiment, conduction / non-conduction between terminal A and terminal B is selected for each of the current source circuits 102a and 102b. A function is necessary. The reason is that it is not possible to select a current source circuit that supplies current to the light emitting element from the plurality of current source circuits 102a and 102b by one switch unit arranged for the plurality of current source circuits. is there.
[0298]
For example, in the third embodiment, the current source circuits having the second to fifth configurations shown in FIGS. 10, 11, 12, and 13 are connected between the terminals A and B in the current source circuit 102 itself. There is a function to select conduction / non-conduction. That is, in the current source circuit having such a configuration, the terminal A and the terminal B are made non-conductive during the setting operation of the current source circuit, and the terminal A and the terminal B are made conductive when performing image display. be able to. On the other hand, in the third embodiment, the current source circuit having the first configuration shown in FIG. 9 or the like does not have a function of selecting conduction / non-conduction between the terminal A and the terminal B in the current source circuit 102 itself. That is, in the current source circuit having such a configuration, the terminal A and the terminal B are in a conductive state both when the current source circuit is set and when an image is displayed. Therefore, when the current source circuit having the configuration shown in FIG. 9 is used as the current source circuit of the pixel of this embodiment mode shown in FIG. 43, each current is generated by a signal different from the digital video signal. It is necessary to provide means for controlling conduction / non-conduction between the terminal A and the terminal B of the source circuit.
[0299]
In the pixel having the configuration of this embodiment, a display operation is performed using another current source circuit while the setting operation of one current source circuit is being performed among a plurality of current source circuits sharing the switch unit. be able to. Therefore, in the case of using the current source circuits of the second configuration to the fifth configuration in which the setting operation of the current source circuit and the current output cannot be performed simultaneously with the pixel configuration of the present embodiment, the current source circuit The setting operation and the display operation can be performed simultaneously.
[0300]
This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 15.
[0301]
【The invention's effect】
In the display device of the present invention, the current flowing through the light emitting element is maintained at a predetermined constant current when performing image display. Therefore, the light emitting element can emit light with a constant luminance regardless of changes in current characteristics due to deterioration or the like. Is possible. In addition, by selecting the on / off state of the switch unit with a digital video signal, each light emitting state or non-light emitting state of each pixel is selected. Therefore, the writing of the video signal to the pixel can be accelerated. Further, in the pixel in which the non-light emitting state is selected by the video signal, the current input to the light emitting element is completely cut off by the switch unit, so that accurate gradation expression is possible.
[0302]
In the conventional current writing type analog system pixel configuration, it is necessary to reduce the current input to the pixel in accordance with the luminance. Therefore, there is a problem that the influence of noise is large. On the other hand, in the pixel configuration of the display device of the present invention, the influence of noise can be reduced if the current value of the constant current flowing through the current source circuit is set to be large to some extent.
[0303]
In addition, the light-emitting element can emit light with a constant luminance regardless of changes in current characteristics due to deterioration, etc., and the signal writing speed to each pixel is fast, and an accurate gradation can be expressed. Thus, a display device that can be reduced in size at low cost and a driving method thereof can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic diagram illustrating a structure of a pixel of a display device of the present invention.
FIG. 2 is a schematic diagram illustrating a structure of a pixel of a display device of the present invention.
FIG. 3 is a diagram showing a structure of a switch portion of a pixel of a display device of the present invention.
FIG. 4 is a diagram showing a driving method of a display device of the present invention.
FIG. 5 is a diagram showing a structure of a switch portion of a pixel of a display device of the present invention.
6A and 6B are diagrams illustrating a structure of a switch portion of a pixel and a driving method of a display device of the present invention.
FIG. 7 is a diagram showing a structure of a pixel of a display device of the present invention.
FIG. 8 illustrates a structure of a pixel of a display device of the present invention.
9A and 9B are diagrams showing a structure and a driving method of a current source circuit of a pixel of a display device of the present invention.
10A and 10B are diagrams illustrating a structure and a driving method of a current source circuit of a pixel of a display device of the present invention.
11A and 11B illustrate a structure and a driving method of a current source circuit of a pixel in a display device of the present invention.
12A and 12B illustrate a structure and a driving method of a current source circuit of a pixel in a display device of the present invention.
FIGS. 13A and 13B illustrate a structure and a driving method of a current source circuit of a pixel of a display device of the present invention. FIGS.
FIG 14 is a diagram showing a driving method of a display device of the present invention;
FIG. 15 is a diagram showing a structure of a driver circuit of a display device of the present invention.
FIG 16 is a diagram showing a structure of a pixel of a display device of the present invention;
FIG. 17 is a diagram showing a structure of a pixel of a display device of the present invention.
FIG. 18 is a diagram showing a structure of a pixel of a display device of the present invention.
FIG 19 is a diagram showing a structure of a pixel of a display device of the present invention.
FIG. 20 is a diagram showing a structure of a pixel of a display device of the present invention.
FIG. 21 is a diagram showing a structure of a pixel of a display device of the present invention.
FIG 22 shows a structure of a pixel of a display device of the present invention.
FIG 23 shows a structure of a pixel of a display device of the present invention.
FIG 24 is a diagram showing a structure of a pixel of a display device of the present invention.
FIG. 25 is a diagram showing a structure of a pixel of a display device of the present invention.
FIG. 26 shows a structure of a pixel of a conventional display device.
FIG. 27 is a diagram showing an operation region of a driving TFT of a conventional display device.
FIG. 28 is a diagram showing a structure of a pixel of a conventional display device.
FIG. 29 is a diagram showing an operation of a pixel of a conventional display device.
30 is a diagram showing a configuration and operation of a pixel of a conventional display device.
FIG. 31 is a diagram showing an operation region of a driving TFT of a conventional display device.
FIG. 32 is a diagram showing an operation region of a driving TFT of a conventional display device.
FIG. 33 is a diagram showing a structure of a current source circuit of a pixel of a display device of the present invention.
34 is a diagram showing a structure of a current source circuit of a pixel in a display device of the present invention. FIG.
FIG 35 shows a structure of a pixel of a display device of the present invention.
FIG 36 is a diagram showing a structure of a current source circuit of a pixel in a display device of the present invention.
FIG. 37 is a diagram showing a structure of a current source circuit of a pixel of a display device of the present invention.
FIG. 38 is a diagram showing a structure of a current source circuit of a pixel in a display device of the present invention.
FIG. 39 is a diagram showing a structure of a current source circuit of a pixel in a display device of the present invention.
FIG. 40 is a diagram showing a structure of a pixel of a display device of the present invention.
41 is a schematic diagram showing a configuration of a display system of the present invention. FIG.
FIG. 42 is a diagram showing a structure of a pixel of a display device of the present invention.
FIG. 43 is a diagram showing a structure of a pixel of a display device of the present invention.
FIG. 44 shows channel length L and ΔI. d The graph which shows the relationship.

Claims (4)

  1. A control current is supplied, and a plurality of current source circuits that output a constant current corresponding to the control current as an output current, and a digital video signal is used to input the output current from each of the plurality of current source circuits to the light emitting element. A pixel having a plurality of switch portions to be selected,
    Each of the plurality of current source circuits includes:
    A first transistor and a second transistor having a source connected to the drain of the first transistor;
    First means for selectively inputting the control current as a drain current of the first transistor;
    Second means for holding a gate voltage of the first transistor;
    Third means for selecting an electrical connection between the gate and drain of the first transistor;
    Display device characterized by comprising a fourth means for the drain current of the second transistor and the gate voltage of the gate voltage of the first transistor, wherein held and the output current.
  2. A control current is supplied, and a plurality of current source circuits that output a constant current corresponding to the control current as an output current, and a digital video signal is used to input the output current from each of the plurality of current source circuits to the light emitting element. A pixel having a plurality of switch portions to be selected,
    One of the plurality of current source circuits is
    A first transistor and a second transistor having a source connected to the drain of the first transistor;
    First means for selectively inputting the control current as a drain current of the first transistor;
    Second means for holding a gate voltage of the first transistor;
    Third means for selecting an electrical connection between the gate and drain of the first transistor;
    The drain current of the second transistor and the gate voltage of the gate voltage of the first transistor, wherein held and a fourth means to said output current,
    Another one of the plurality of current source circuits is:
    A third transistor and a fourth transistor;
    Fifth means for selectively inputting the control current as a drain current of the third transistor;
    Sixth means for holding a gate voltage of the third transistor;
    A seventh means for selecting an electrical connection between the gate and drain of the third transistor;
    And an eighth means for setting the drain current of the fourth transistor as the output current using the held gate voltage of the third transistor as the gate voltage.
  3. In claim 1 or claim 2,
    The display device characterized in that current values of the output currents of the plurality of current source circuits are set to different values.
  4. In any one of Claims 1 thru | or 3,
    The display device characterized in that the current values of the control currents input to each of the plurality of current source circuits are set to different values.
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EP1777691A3 (en) * 2005-10-21 2010-08-11 Semiconductor Energy Laboratory Co., Ltd. Display device and method of driving the same
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