JP2011033393A - Semiconductor device having membrane part, and method for manufacturing the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device technique shortening a processing time of Si anisotropic wet etching for forming a bridge structure by removing an Si (100) substrate itself under a membrane part and beam parts. <P>SOLUTION: The membrane part 51 and the beam parts 52-55 are formed in the <100> direction of the Si (100) substrate, and the beam parts 52-55 support the membrane part 51 only on two facing sides of the membrane part 51, and a length of the shortest part of the beam parts 52-55 is constituted to be longer than the width. A heat-sensitive part 90 (in the case of an infrared sensor) for detecting an infrared ray and an infrared absorption film 91 are formed on the membrane part 51, and a signal generated by the detected infrared ray is guided from the heat-sensitive part 90 to the outside through the membrane part 51 and the beam parts 53, 55 by wires 92, 93. The membrane part 51 is protected from etching solution by a bottom surface protection layer 94, an interlayer film 95 and an upper surface protection layer 96. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device technology in which a membrane part is arranged on a substrate, and in particular, a semiconductor in which a sensor such as an infrared sensor or an acceleration sensor is formed in a membrane part and the membrane part is supported in a hollow state by a plurality of beams. The present invention relates to an apparatus and a manufacturing method thereof.

  Conventionally, there has been proposed a semiconductor device in which a sensing part of an infrared sensor or an acceleration sensor is formed on a thin film membrane part, and the membrane part is supported on a substrate in a hollow state by a bridge structure by a plurality of beams. It is already known that such a bridge structure can be formed by anisotropic wet etching of Si using a difference in etching rate depending on the crystal orientation of Si.

  However, in the case of the conventional bridge structure, there is a problem that it takes a long etching process time to etch Si in the lower part of the membrane part and the beam part to form a hollow bridge structure.

  As a conventional example of a semiconductor device in which a membrane portion is supported by a bridge structure on a substrate, there is one disclosed in Japanese Patent Application Laid-Open No. 2001-264441 “Calories and manufacturing method thereof” (Patent Document 1).

  Japanese Patent Laid-Open No. 2001-264441 (Patent Document 1) aims to shorten the time required for etching Si under the membrane part. For this purpose, the membrane part is formed in the <100> direction. It is what you do.

  However, what is described in Patent Document 1 is that the membrane part is formed in the <100> direction in order to etch Si in the lower part of the membrane part in a short time. This relates to the structure, and no consideration is given to the reliable removal of Si below both the membrane part and the beam part of the bridge structure in a short time.

  In addition, what is described in Patent Document 1 is that an SOI layer of an SOI substrate is subjected to anisotropic wet etching, and the Si substrate portion of the SOI substrate or the Si (100) substrate itself is subjected to anisotropic wet etching. It is not what you have.

  Therefore, the present invention has a membrane portion and a beam that supports the membrane portion only on two opposite sides of the membrane portion, and removes the Si (100) substrate itself under the membrane portion and the beam portion to form a bridge. It is an object of the present invention to provide a semiconductor device having a membrane part capable of shortening the processing time of Si anisotropic wet etching for forming a structure, and a manufacturing method thereof.

  In the present invention, the membrane part and the beam part are formed in the <100> direction of the Si (100) substrate, the beam part supports the membrane part only on two opposite sides of the membrane part, and the length of the shortest part of the beam part. It is characterized by having a structure that is longer than the width of the beam part, so that the etching of Si proceeds at the shortest distance from the opposite two sides without the beam of the membrane part to the center part of the membrane part, The processing time of Si anisotropic wet etching for removing the Si (100) substrate itself under the membrane part and the beam part is shortened.

Hereinafter, the configuration of the present invention will be described more specifically.
a) A semiconductor device according to the present invention is a semiconductor device having a substrate and a membrane portion that is provided in a hollow state by a plurality of beam portions on the substrate. Formed in the <100> direction of the Si (100) substrate, the plurality of beam portions are formed only on two opposite sides of the membrane portion, and the length of the shortest portion of the beam portion is longer than the width of the beam portion It is characterized by that.

b) In the above, the membrane portion includes a sensor element and a wiring for outputting a signal detected by the sensor element.

c) In the above, the sensor element is a temperature sensor, and the temperature sensor is any one of a pyroelectric temperature sensor, a thermopile, a thermistor, a PN junction diode, and a work function difference type temperature sensor. It is characterized by that.

d) Further, in the above, the membrane part has an infrared absorption film, and further has an infrared reflection film in a lower layer than the infrared absorption film with respect to the infrared incident direction.

e) In the above, an infrared antireflection film is formed on the membrane part, an infrared lens is formed on the back surface of the substrate, and an infrared antireflection film is formed on the back surface of the substrate. It is characterized by.

f) Further, the present invention is characterized in that a dummy wiring for making the internal stress of the beam portion caused by the wiring uniform is provided at a position symmetrical to the wiring.

g) The sensor element is a piezoelectric element, and the substrate is an SOI substrate.

h) In addition, a signal processing circuit unit for processing an output signal of the sensor element is provided, and the sensor element and the signal processing circuit unit are formed on the same substrate.

i) Further, the semiconductor device is arranged in a two-dimensional array, and has a signal processing circuit unit for processing an output signal from each semiconductor device arranged in the array, and the semiconductor arranged on the two-dimensional array The apparatus and the signal processing circuit portion are formed on the same substrate.

j) The semiconductor device is hermetically sealed by a wafer level chip size package (WL-CSP).

k) A method for manufacturing a semiconductor device according to the present invention includes a substrate and a membrane portion supported in a hollow state by a plurality of beam portions on the substrate. Forming a beam part that supports the membrane part only on two opposite sides of the membrane part in the <100> direction of the Si (100) substrate, the length of which is longer than the width; And a step of removing the Si under the membrane by performing anisotropic wet etching from the outer periphery of the membrane portion to the central portion of the membrane portion.

  According to the present invention, it is possible to shorten the processing time of Si anisotropic wet etching necessary for etching Si under the membrane part and the beam part of the bridge structure. Further, since the etching processing time is shortened, the production efficiency is increased and the cost can be reduced. Furthermore, since the process restrictions required to withstand long-time etching are relaxed, the degree of freedom in element layout and wiring layout is increased, leading to an improvement in product performance. In addition, since the process restrictions required to withstand long-time etching are eased, the thickness of the etching protective layer can be reduced, and when applied to infrared sensors, the heat capacity can be reduced. As a result, the performance of the infrared sensor is improved.

It is a figure which shows the outline | summary at the time of performing Si anisotropic etching using the mask pattern formed in the <110> direction on the Si (100) substrate surface. It is a figure which shows the outline | summary at the time of performing Si anisotropic etching using the mask pattern formed in the <100> direction on the Si (100) board | substrate surface. It is a figure which shows the etching shape of Si substrate at the time of performing anisotropic wet etching using the mask pattern which has a side of directions other than <110>. It is a figure which shows an example of the bridge | bridging structure which formed the membrane part in the <100> direction and formed the beam part in the <110> direction. It is a figure which shows an example of the bridge | bridging structure which formed the membrane part in the <110> direction and formed the beam part in the <100> direction. It is a figure which shows an example of the bridge structure which formed the membrane part and the beam part in the <100> direction. It is a figure which shows another example of the bridge structure which formed the membrane part and the beam part in the <100> direction. It is a figure for demonstrating the bridge structure of this invention. It is a figure for demonstrating the infrared sensor which concerns on Example 1 of this invention. It is a figure for demonstrating the acceleration sensor which concerns on Example 2 of this invention. It is a figure for demonstrating the infrared sensor which concerns on Example 3 of this invention. It is a figure for demonstrating the infrared sensor which concerns on Example 4 of this invention. It is a figure for demonstrating the infrared sensor which concerns on Example 5 of this invention. It is a figure for demonstrating the infrared sensor chip which made the infrared sensor element which concerns on Example 7 of this invention, and the signal processing circuit into the one chip on the same board | substrate. It is a figure for demonstrating the structure of the infrared sensor which concerns on Example 8 of this invention. It is a figure which shows the structure of the infrared sensor array which concerns on Example 9 of this invention. It is a figure which shows the structure of the sensor element which concerns on Example 10 of this invention.

(Overview)
In the present invention, when the membrane part forming the bridge structure and the Si under the beam part are removed by anisotropic wet etching,
(1) The membrane part and the beam part are formed in the <100> direction of the Si (100) substrate. (2) The beam part supports the membrane part only on two opposite sides of the membrane part. (3) The shortest of the beam part. By adopting a configuration in which the length of the part is longer than the width of the beam part, etching of Si proceeds at the shortest distance from the opposite two sides without the beam of the membrane part to the center part of the membrane part, and Si surrounded by the {111} plane is prevented from appearing, and the membrane portion of the bridge structure and the Si under the beam portion can be reliably removed by etching in a short time.

(Description of Embodiment)
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, characteristics of anisotropic wet etching of Si important for the present invention will be described. FIG. 1 is a diagram showing an outline when Si anisotropic etching is performed using a mask pattern formed in the <110> direction on the surface of a Si (100) substrate.

  In a normal substrate, the <110> direction is a direction parallel or perpendicular to an orientation flat (orientation flat = a straight line portion provided on the outer periphery of the wafer for indicating the crystal direction of the wafer). FIG. 1A shows the state of the substrate surface before etching, and FIG. 1B shows a cross-sectional view taken along line A-A ′ of FIG.

  As the Si etching solution, for example, a hydrazine aqueous solution, a KOH (potassium hydroxide) aqueous solution, or tetramethylammonium hydroxide (TMAH) is used, and the temperature of the solution is set to about 50 to 100 degrees. As a mask used for etching, silicon oxide, silicon nitride, or the like having resistance to these etching solutions is used.

  In FIGS. 1A and 1B, the mask pattern is formed in the <110> direction, and the Si {100} plane is exposed in the opening of the mask. Anisotropic wet etching is performed from the mask opening. The state of the substrate surface after anisotropic wet etching is shown in FIG. A cross-sectional view of B-B ′ is shown in FIG.

  As shown in FIGS. 1C and 1D, when the mask pattern is formed in the <110> direction, the Si {111} plane appears along the shape of the mask pattern, so that etching is performed only in the depth direction. Proceed to. This is because the {111} plane of Si has a significantly slower etching rate than the {100} plane and the {110} plane.

  For example, when the KOH solution is used, the etching rate ratio between the {111} plane and the {100} plane or the {111} plane and the {110} plane is about 1: several hundred, and 1 when the TMAH solution is used. : It is known that it is about several tens. Si anisotropic wet etching utilizes such a difference in etching rate depending on the plane orientation.

  FIG. 2 is a diagram showing an outline when Si anisotropic etching is performed using a mask pattern formed in the <100> direction on the Si (100) substrate surface.

  In a normal Si substrate, the direction having an angle of 45 ° or 135 ° with respect to the orientation flat is the <100> direction. FIG. 2A shows the state of the substrate surface before etching, and FIG. 2B shows a cross-sectional view taken along the line C-C ′ of FIG. The state of the substrate surface after anisotropic wet etching is shown in FIG. A cross-sectional view of D-D ′ is shown in FIG.

  As shown in FIG. 2C, when the mask pattern is formed in the <100> direction, etching proceeds in the <100> direction perpendicular to each side of the mask pattern, and Si is a broken line in FIG. Etched as follows. This is because, unlike the case where the mask pattern is formed in the <110> direction shown in FIG. 1, the {111} plane of Si does not appear at a position along the mask pattern.

  In addition, as shown in FIG. 2D, when the mask pattern is formed in the <100> direction, Si under the mask can be etched, so that this can be used to form a bridge structure or the like. Is possible.

  FIG. 3 is a diagram showing an etching shape of the Si substrate when anisotropic wet etching is performed using a mask pattern having sides in directions other than <110>. A solid line indicates a mask pattern, and a broken line indicates the shape of Si after etching.

  As shown in FIGS. 2C and 3, when the mask pattern has sides in directions other than <110>, the Si substrate includes the mask pattern with respect to the mask pattern, and all sides are <110. Etched to the smallest rectangular shape in the> direction. By considering this characteristic, it is possible to predict to some extent how the Si substrate is etched with respect to the mask pattern.

Here, a conventional bridge structure will be described.
FIG. 4 is a diagram illustrating an example of a bridge structure in which the membrane portion is formed in the <100> direction and the beam portion is formed in the <110> direction. FIG. 4A shows the shape of the bridge structure and the mask pattern.

  In the example of FIG. 4 (a), the membrane part 1 at the center is supported by a hollow body with four beams 2-5, and the membrane part 1 and the beams are used using mask patterns 6-9. The Si substrate under the portions 2 to 5 is etched to form a bridge structure.

  FIG. 4B shows the etched state of the Si substrate after performing wet etching for a certain time. As shown in FIG. 4B, the etching of the Si substrate stops in the shape of squares 10 to 13 painted with diagonal lines. This is because the {111} plane appears around the squares 10-13.

  FIG. 4C shows a cross-sectional view taken along line E-E ′ in FIG. As shown in FIG. 4C, the Si substrate surrounded by the {111} plane remains in the lower part of the membrane part. Since the {111} plane has a very slow etching rate, etching for a very long time is required to completely etch the remaining Si. Therefore, in the case of the bridge structure having the configuration shown in FIG. 4, there is a very high possibility that the cross-shaped Si substrate remains below the membrane portion 1 and the beam portions 2 to 5.

  FIG. 5 is a diagram illustrating an example of a bridge structure in which the membrane portion is formed in the <110> direction and the beam portion is formed in the <100> direction. FIG. 5A shows the shape of the bridge structure and the mask pattern.

  As shown in FIG. 5A, the central membrane portion 21 is supported by four beams 22 to 25 in a hollow shape, and the membrane portion 21 and the beam portions 22 to 25 are formed by mask patterns 26 to 29. The lower Si substrate is etched to form a bridge structure. The width of the membrane portion 21 is a [μm], and the width of the beam portions 22 to 25 is b [μm].

  FIG. 5B shows the etched shape of the Si substrate after performing wet etching for a certain time. When etching is performed for a certain period of time, the Si substrate is etched into a shape painted with diagonal lines. At this time, the lower part of the membrane part 21 is surrounded by the {111} plane, but unlike the case of the configuration of FIG. 4, the etching of Si in the lower part of the membrane part 21 starts from each apex part of the membrane part 21. Proceed toward the center of the membrane portion 21.

  FIG. 5C shows the etched shape of the Si substrate after etching for a certain period of time from FIG. 5B. As shown in FIG. 5C, the etching proceeds from each apex portion of the membrane portion 21 to the central portion, and finally the Si under the membrane portion 21 and the beam portions 22 to 25 is etched to complete the bridge structure. To do.

  Assuming that the etching rate of Si in the <100> direction is X [μm / min], in the case of the configuration of FIG. 5, the time until the Si under the membrane portion 21 is completely etched is approximately (b / 2). + a / √2) / X [min].

This will be described with reference to FIG.
When wet etching is started, first, Si under the beam portion is etched, and Si surrounded by {111} planes appears along the shape of the membrane portion 21. This is due to the Si anisotropic wet etching characteristic described with reference to FIG. Assuming that the vertex of the membrane portion is a point F, the etching proceeds from the point F toward the center point G of the membrane portion 21 at the same time as the point F appears.

  Assuming that the intersection of the perpendicular drawn from the point F to the mask pattern 29 and the mask pattern 29 is a point H, the shortest path through which the Si etching surface reaches the center of the membrane portion 21 is a path H → F → G. . The distance from the point F to the point G is a / √2 [μm], and the distance from the point H to the point F is b / 2 [μm].

  Therefore, if the etching rate of Si in the <100> direction is X [μm / min], the time from the etching of Si under the membrane portion 21 to the completion of the bridge structure is approximately (b / 2 + a / √2) / X [min].

  FIG. 6 is a diagram illustrating an example of a bridge structure in which a membrane portion and a beam portion are formed in the <100> direction. FIG. 6A shows the shape of the bridge structure and the mask pattern.

  As shown in FIG. 6A, the central membrane portion 31 is supported by four beams 32 to 35 in a hollow state, and the membrane portion 31 and the beam portions 32 to 35 are formed by mask patterns 36 to 39. The lower Si substrate is etched to form a bridge structure. The width of the membrane portion 31 is a [μm], and the width of the beam portions 32 to 35 is b [μm].

  FIG. 6B shows the etched shape of the Si substrate after performing wet etching for a certain time. When etching is performed for a certain period of time, the Si substrate is etched into a shape painted with diagonal lines. At this time, as shown in FIG. 6B, a {111} plane appears at the lower part of the coupling portion of the membrane portion 31 and the beam portions 32 to 35. As in the case of FIG. Proceeding from the apex to the center of the membrane 31.

  FIG. 6C shows the etching shape of the Si substrate after etching for a certain time from the state of FIG. 6B. As shown in FIG. 6C, the etching proceeds to the central portion of the membrane portion 31, and finally, the Si under the membrane portion 31 and the beam portions 32 to 35 is etched to complete the bridge structure.

  Assuming that the etching rate of Si in the <100> direction is X [μm / min], in the case of the configuration of FIG. 6, the time until the Si at the lower part of the central portion of the membrane portion 31 is etched is approximately (b + a / 2) / X [min]. This will be described with reference to FIG. In order to etch the Si at the lower part of the membrane part, it is necessary to go through the state shown in FIG.

  Assuming that the intersection of the {111} plane appearing at the lower part of the connecting portion of the membrane portion 31 and the beam portions 32 to 35 is a point I, the point I is directed from the point I toward the center point J of the membrane portion 31 at the same time. Then, etching of Si under the membrane portion 31 starts.

  Assuming that the intersection of the perpendicular drawn from the point I to the mask pattern 39 and the mask pattern 39 is a point K, the shortest path through which the Si etching surface reaches the center of the membrane part 31 is a path of K → I → J. .

  The distance from the point I to the point J is b / 2 + a / 2 [μm], and the distance from the point K to the point I is b / 2 [μm]. Therefore, if the etching rate of Si in the <100> direction is X [μm / min], the time from when Si under the membrane portion 31 is etched to form a bridge structure is approximately (b + a / 2) / X [min].

  FIG. 7 is a diagram showing another example of a bridge structure in which a membrane part and a beam part are formed in the <100> direction. FIG. 7A shows the shape of the bridge structure and the mask pattern.

  As shown in FIG. 7A, the membrane portion 41 in the center is supported in a hollow shape by four beams 42 to 45, and the membrane portion 41 and the beam portions 42 to 42 are formed by mask patterns 46 to 49. Etching the lower Si substrate 45. The width of the membrane portion 41 is a [μm], and the width of the beam portions 42 to 45 is b [μm].

  FIG. 7B shows the etched shape of the Si substrate after performing wet etching for a certain time. When etching is performed for a certain period of time, the Si substrate is etched into a shape painted with diagonal lines. This is because the {111} plane appears at the portion indicated by the arrow in FIG. The etched shape of the Si substrate after further etching is shown in FIG.

  As shown in FIG. 7C, the Si substrate remaining in the central portion is etched from the apex portion toward the central portion, and finally the Si under the membrane portion 41 and the beam portions 42 to 45 are etched to form a bridge. The structure is complete. Assuming that the etching rate of Si in the <100> direction is X [μm / min], in the case of the configuration of FIG. 7, the time until Si in the lower part of the membrane portion 41 is etched to become a hollow state is approximately (b + a / 2) / X [min].

  This will be described with reference to FIG. In order for the membrane part 41 to be in a hollow state, it is first necessary to be in the state of FIG.

  In order to be in the state of FIG. 7C, the etching must proceed from the point L on the mask pattern 46 to the vertex M of Si remaining in a square shape. The distance from the point L to the point M is a / 2 [μm].

  Furthermore, the etching needs to proceed from the point M to the center point N of the membrane portion 41, and the distance from the point M to the point N is b [μm]. Therefore, if the etching rate of Si in the <100> direction is X [μm / min], the time from when Si under the membrane portion 41 is etched to complete the bridge structure is approximately (b + a / 2). ) / X [min].

  When forming a bridge structure having a membrane part with a width of a [μm] under the condition that the etching rate of Si in the <100> direction is X [μm / min], the shortest distance from the periphery of the membrane part to the center part of the membrane part As the etching proceeds, the shortest time required until the bridge structure is formed is (a / 2) / X [min]. However, in the case of the configuration shown in FIGS. 4 to 7, the etching time is longer than (a / 2) / X [min].

Next, the bridge structure of the present invention will be described.
FIG. 8 is a diagram for explaining the bridge structure of the present invention.
FIG. 8A shows the bridge structure of the present invention. This bridge structure is comprised from the membrane part 51 and the four beam parts 52-55 on the same plane, and the membrane part 51 is supported by the beam parts 52-55 in the hollow state.

  It is assumed that one side of the membrane portion 51 is a [μm], the width of the beam portions 52 to 55 is b [μm], and the length of the shortest portion of the beam portions 52 to 55 is c [μm]. The bridge structure of the present invention has three features.

  The first feature is that the membrane portion 51 and the beam portions 52 to 55 are all formed in directions other than the <110> direction of the Si (100) substrate. However, in the following text and drawings, the case where the membrane portion 51 and the beam portions 52 to 55 are all formed in the <100> direction is shown for simplification of explanation.

  As shown in FIG. 8A, when the membrane part 51 and the beam parts 52 to 55 are formed in the <100> direction, the etching rate is remarkably slow at positions along the sides of the membrane part 51 and the beam parts 52 to 55. Since the 111} surface does not appear, the etching of Si under the membrane portion 51 and the beam portions 52 to 55 proceeds smoothly, and the bridge structure can be formed in a short time. The second feature is that the beam portions 52 to 55 support the membrane portion 51 only on two opposite sides of the membrane portion 51.

  In FIG. 8A, the membrane portion 51 is supported on two opposite sides 57 and 59 among the four sides 56 to 59. Since the beam portion is provided only on the two opposite sides 57 and 59 of the membrane portion 51, there is no structure that prevents etching on the other two opposite sides 56 and 58.

  FIG. 8B shows the etched shape of the Si substrate when anisotropic wet etching of Si is performed for a certain time.

  In FIG. 8B, the point O is the center point of the membrane portion 51, the points P and Q are the midpoints of the sides 56 and 58, and the polygons 60 to 63 show the wet etching mask pattern. When wet etching is performed for a certain period of time, etching proceeds from each side 56 to 59 of the membrane portion 51 toward the center point O of the membrane portion 51, and the Si substrate is etched into the shape indicated by the oblique lines in FIG. Is done. When further etching is performed, the Si substrate is etched as shown in FIG. 8C, and finally the Si under the membrane portion 51 and the beam portions 52 to 55 is etched to complete the bridge structure.

  In the case of this configuration, there is nothing that hinders etching on the sides 56 and 58, so the etching of the Si substrate starts uniformly from the entire sides 56 and 58. Therefore, the etching of the Si substrate proceeds from the points P and Q to the point O at the shortest distance a / 2 [μm].

  If the etching rate of Si in the <100> direction is X [μm / min], the time t until the Si under the membrane part 51 is etched and the bridge structure is completed is approximately (a / 2) / X [ min]. This is the shortest etching time for forming a square membrane portion having a side length of a [μm].

  In the case of the configuration of FIGS. 5, 6, and 7, since the beam is provided on each side of the membrane portion, the final etching time t is t> (a / 2) / X [min]. . The third characteristic is that the relationship between the length c of the shortest part of the beam part and the width b of the beam part is c> b with respect to the beam parts 52 to 55.

FIG. 8D shows a bridge structure having a configuration of c <b under the reverse condition.
The beams 72 to 75 all have c <b. FIG. 8 (e) shows the etched shape of Si when anisotropic wet etching of Si is performed for a certain time in the configuration of FIG. 8 (d). After a certain period of time, Si is etched into the shape indicated by the hatched portion in FIG.

  As shown in FIG. 8E, since Si in the lower part of the central portion of the membrane portion 71 is etched in the <100> direction from the mask patterns 80 and 82, about t = (a / 2) / X [min]. However, since the {111} plane appears at eight locations indicated by the arrows in the figure, the Si surrounded by the {111} plane is lower than the Si at the lower center of the membrane portion 71. Etched late.

  That is, in the case of FIG. 8D, the time t for completing the bridge is t> (a / 2) / X [min]. Therefore, in order to form a bridge structure in the shortest time t = (a / 2) / X [min], it is necessary to satisfy the condition of c> b so that Si surrounded by {111} faces does not appear. .

  As described above, the membrane part and the beam part are formed in the <100> direction of the Si (100) substrate, and the beam part supports the membrane part only on two opposite sides of the membrane part, and the shortest part of the beam part is supported. By making the length longer than the width of the beam part, Si etching proceeds at the shortest distance from the periphery of the membrane part to the center part of the membrane part, and Si surrounded by the {111} plane appears. Therefore, the bridge structure can be formed in the shortest time. In FIG. 8, the membrane portion has a square shape, but there is no problem even if it is a rectangle.

<Example 1>
Hereinafter, a semiconductor device according to the present invention to which the above bridge structure is applied will be described.

  The above bridge structure can be applied to any device as long as it is a semiconductor device using a conventional bridge structure. In particular, a bridge structure is often applied to an infrared sensor, an acceleration sensor, or the like. Therefore, a case where the above bridge structure is applied to an infrared sensor will be described.

FIG. 9 is a diagram for explaining the infrared sensor according to the first embodiment of the present invention.
FIG. 9A illustrates an infrared sensor according to the present embodiment. Since the shape of the bridge structure is the same as that described with reference to FIG. 8A, the same numbers are used for the same components.

  The membrane part 51 and the beam parts 52 to 55 are formed in the <100> direction of the Si (100) substrate, and the beam parts 52 to 55 support the membrane part 51 only on the two opposite sides of the membrane part 51. The length of the shortest part of the parts 52 to 55 is longer than the width. A temperature sensor 90 for detecting infrared rays and an infrared absorption film 91 are formed on the membrane portion 51, and output signals from the temperature sensor 90 are wiring 92 and 93 formed on the membrane portion 51 and the beam portions 53 and 55. It is led to the outside through.

  The infrared sensor of the present embodiment is of a type called a thermal infrared sensor, which detects infrared rays by absorbing infrared rays with an infrared absorption film 91 and detecting a temperature change caused by the infrared absorption with a temperature sensor 90. Is.

  The temperature sensor 90 may be any temperature sensor that can detect a temperature change due to infrared absorption, such as a pyroelectric temperature sensor, a thermopile, a thermistor, a PN junction diode, and a work function difference type temperature sensor. Also good.

  The infrared absorption film 91 is generally made of gold-black, but silicon oxide, silicon nitride, or the like may be used and is not particularly limited. The wiring is formed of a metal material such as Al or Cu, but the number or the like varies depending on the element type of the heat sensitive portion 90.

  The shape shown in FIG. 9A is an example, and any other configuration or shape may be used as long as the bridge shape condition is satisfied.

  FIG. 9B is a cross-sectional view taken along the line R-R ′ in FIG. The periphery of the membrane 51 is protected by a bottom protective layer 94, an interlayer film 95, and a top protective layer 96. When performing anisotropic wet etching of Si, the thermal sensitive part 90, the infrared absorbing film 91, and the wirings 92, 93 are provided. Is protected from the etching solution.

  The bottom protective layer 94, the interlayer film 95, and the top protective layer 96 are all made of silicon oxide or silicon nitride. These layer structures can be formed by existing semiconductor processes such as photolithography, thermal oxidation, and CVD. In addition, since silicon oxide and silicon nitride absorb infrared rays, these layers can be used as an infrared absorption film.

  The layer configuration shown in FIG. 9B is an example, and any layer configuration can be used as long as the heat sensitive portion 90, the infrared absorbing film 91, and the wirings 92 and 93 are protected from the etching solution. The present invention can be applied to any material. By applying the bridge structure of the present invention, the etching time of Si anisotropic wet etching can be shortened, so that the thickness of the bottom protective layer 94, the interlayer film 95, and the top protective layer 96 can be reduced. It is.

  These protective films are gradually etched at a very slow rate with respect to the etching solution. If the protective layer penetrates during the etching, the heat sensitive part 90, the infrared absorption film 91, the wirings 92, 93 and the like are etched, so that the thickness of the protective layer is determined with a certain margin.

  In this embodiment, the side surface of the membrane portion is in a state where the interlayer film 95 is exposed, but a side surface protective film 97 may be formed on the side surface of the membrane portion as shown in FIG. At this time, the upper surface protective layer 96 and the side surface protective film 97 are preferably formed of silicon nitride, which has a particularly low etching rate with respect to an alkaline etching solution.

  In the infrared sensor, in order to improve the response speed, it is necessary to reduce the heat capacity of the sensor. If each protective layer can be made thin, the heat capacity can be reduced and the sensor performance can be improved.

  In addition, the area where the heat sensitive part 90, the infrared absorption film 91, and the wirings 92 and 93 can be arranged can be increased, and the degree of freedom in layout and the size of elements increases, leading to improvement in sensor performance. In addition, since the etching processing time is shortened, the manufacturing cost can be reduced.

<Example 2>
A case where the semiconductor device of the present invention is applied to an acceleration sensor will be described.
FIG. 10 is a diagram for explaining the acceleration sensor according to the second embodiment of the invention.

  FIG. 10A is a diagram illustrating the acceleration sensor according to the present embodiment. Since the shape of the bridge structure is the same as the structure described in FIGS. 9A and 9B, the same numbers are used for the same components.

  The membrane part 51 and the beam parts 52 to 55 are formed in the <100> direction of the Si (100) substrate, and the beam parts 52 to 55 support the membrane part 51 only on the two opposite sides of the membrane part 51. The length of the shortest part of the parts 52 to 55 is longer than the width.

  A piezoelectric element 100 for detecting acceleration and a wiring 101 for outputting a detection signal are formed on the beam portions 52 to 55. The piezoelectric element 100 may be formed of any material as long as it is a piezoelectric element such as PZT, lithium tantalate, or lithium niobate. The wiring is formed of a metal material such as Al or Cu.

  The shape shown in FIG. 10A is an example, and any other configuration or shape may be used as long as the bridge shape condition is satisfied.

  FIG. 10B shows a cross-sectional view of S-S ′. As in the case of the infrared sensor, the membrane part 51 is protected at its periphery by a bottom protective layer 94, an interlayer film 95, and a top protective layer 96. When performing anisotropic wet etching of Si, the piezoelectric element 100, the wiring 101 is protected from the etching solution. The bottom protective layer 94, the interlayer film 95, and the top protective layer 96 are all made of silicon oxide or silicon nitride.

  These layer structures can be formed by existing semiconductor processes such as photolithography, thermal oxidation, and CVD. The layer configuration shown in FIG. 10-2 is an example, and any material may be used for any layer configuration as long as the piezoelectric element 100 and the wiring 101 are protected from the etching solution. However, the present invention is applicable.

  By applying the bridge structure of the present invention, the etching time of Si anisotropic wet etching can be shortened, which has an effect of reducing the manufacturing cost. In addition, since the area where the piezoelectric element 100 and the wiring 101 can be arranged can be increased, the degree of freedom in layout and the size of the element increase, leading to improvement in sensor performance. Further, if the thickness of the etching protective layer can be reduced, the mass of the membrane portion 51 is reduced, and hence acceleration at a higher frequency can be detected.

<Example 3>
In the infrared sensor to which the present invention is applied, a configuration in which an infrared reflecting film is formed below the infrared absorbing film in the infrared incident direction will be described.

  FIG. 11 is a diagram for explaining the configuration of the infrared sensor according to the third embodiment of the present invention. FIG. 11A shows the configuration of the infrared sensor described in this embodiment. The feature of this configuration is that it has an infrared reflecting film 102 as shown in FIG. A cross-sectional view of T-T ′ is shown in FIG.

  FIG. 11B shows a configuration when infrared rays are incident from the upper surface of the membrane portion 51. In this case, the infrared reflecting film 102 is formed on the bottom protective layer 94, and the infrared rays that are not absorbed by the infrared absorbing film 91 but transmitted to the lower layer are reflected by the infrared reflecting film 102 toward the infrared absorbing film 91. Therefore, it is possible to increase the infrared absorption rate.

  In this configuration, the infrared reflecting film 102 is formed on the bottom protective layer 94, but may be formed directly below the infrared absorbing film 91 or in the middle of the interlayer film 95. There is no problem even if it is formed anywhere below the infrared absorption film 91. The infrared reflective film 102 may be formed of any material that reflects infrared rays, such as aluminum or titanium nitride.

  FIG. 11C shows a configuration when infrared rays are incident from the back side of the Si substrate. Since Si does not absorb infrared rays, such a configuration can be used. In this case, as shown in FIG. 11C, the infrared reflection film 102 is formed between the infrared absorption film 91 and the upper surface protective layer 96. The infrared reflection film 102 is formed below the infrared absorption film 91 with respect to the incident direction of infrared rays.

  In this way, even when infrared rays are incident from the back side of the Si substrate, the infrared rays that are transmitted without being absorbed by the infrared absorption film 91 are reflected by the infrared reflection film 102 in the direction of the infrared absorption film 91. It is possible to increase the absorption rate.

<Example 4>
In the infrared sensor to which the present invention is applied, a configuration in which an infrared antireflection film is formed on the surface of the membrane portion 51 will be described.

  FIG. 12A shows the configuration of the infrared sensor described in the fourth embodiment. The feature of this configuration is that it has an infrared antireflection film 103 as shown in FIG. A cross-sectional view of U-U ′ is shown in FIG.

  The infrared antireflection film 103 is formed on the upper surface protective layer 96. By forming the infrared reflection preventing film 103, it is possible to suppress the incident infrared rays from being reflected on the surface of the membrane portion 51, increase the amount of infrared rays incident on the infrared absorption film 91, and improve the sensitivity of the infrared sensor. It is.

  When the material of the infrared antireflection film 103 has etching resistance to the etching solution used for the anisotropic wet etching of Si, the infrared antireflection film 103 may be formed before the wet etching, and the material is etching resistant. In the case of not having an infrared ray, it is necessary to form the infrared antireflection film 103 after wet etching.

  It is necessary to select the material of the infrared antireflection film 103 so that the infrared reflectance on the surface of the membrane portion 51 becomes small in consideration of the optical constants of the lower layer, etc. In addition, the present invention can be applied.

  12 (a) and 12 (b) show the structure without the infrared reflecting film described in the third embodiment. However, if the infrared reflecting film is present, the infrared absorption rate is further increased, so the performance of the infrared sensor. Will improve.

<Example 5>
In the infrared sensor to which the present invention is applied, a configuration in which dummy wiring is formed will be described.

  FIG. 13A shows the configuration of the infrared sensor described in the fifth embodiment. The feature of this configuration is that it has dummy wirings 104 and 105 that are not connected anywhere. For example, in the case of the configuration of the infrared sensor of FIG. 9A, the wires 53 and 55 pass through the wires 93 and 92, but the beams 52 and 54 do not pass through the wires.

  In such a case, since the internal stress in each beam portion becomes non-uniform, the bridge structure may be destroyed. Therefore, by forming the dummy wirings 104 and 105 at positions symmetrical to the wirings 93 and 92, it is possible to equalize the internal stress of each of the beam portions 52 to 55 and prevent the bridge structure from being broken. It is.

<Example 6>
In the sixth embodiment, a case where an SOI (Silicon On Insulator) substrate is used in an infrared sensor to which the present invention is applied will be described. Although not particularly illustrated, the SOI substrate to be used is a substrate in which a BOX (Buried Oxide) layer and an SOI layer are formed on a Si (100) substrate.

  The feature of the present invention is that the BOX layer of the SOI substrate is used for the bottom protective layer 94 described in the first to sixth embodiments. When an SOI substrate is used, it is not necessary to form the bottom protective layer 94, and thus the process can be simplified. In addition, when an SOI substrate is used, the parasitic capacitance of the semiconductor element can be reduced, and high-speed operation of the circuit and low power consumption can be achieved. Therefore, when the sensor element and the signal processing circuit are formed monolithically on the same substrate, the advantage of using the SOI substrate is particularly great.

<Example 7>
In the seventh embodiment, a configuration of an infrared sensor chip in which an infrared sensor element and a signal processing circuit are formed on the same substrate and formed into one chip will be described.

  FIG. 14 is a schematic diagram of an example of an infrared sensor chip in which the infrared sensor element and the signal processing circuit according to the seventh embodiment are formed as one chip on the same substrate.

  As shown in FIG. 14, the infrared sensor chip according to the present embodiment has a sensor element unit 107 and a signal processing circuit unit 108 formed monolithically on a Si substrate 106. There is no problem even if the substrate is an SOI substrate. In the case where the sensor element unit 107 and the signal processing circuit unit 108 are separate, the wiring processing and package costs for connecting these two substrates increase, but as shown in FIG. By making the element portion 107 and the signal processing circuit portion 108 into one chip, such an increase in cost can be suppressed.

  In particular, if a thermal element that can be created by a CMOS process such as a PN junction diode or a work function difference output circuit is employed as the thermal element, the sensor element and the signal processing circuit can be simultaneously formed on the same substrate. It is possible to provide a lower cost infrared sensor.

<Example 8>
In Example 8, a configuration in which an infrared lens is formed on the back surface of a Si substrate in an infrared sensor to which the present invention is applied will be described.

  FIG. 15 is a diagram for explaining the configuration of the infrared sensor according to the eighth embodiment of the present invention. The present embodiment is an infrared sensor configured such that infrared light is incident from the back surface of the Si substrate, and the infrared lens 110 is formed on the back surface of the Si substrate. The membrane portion 51 has the same configuration as that shown in FIG.

  The infrared lens 110 shown in FIG. 15 is a Fresnel lens, and is formed by directly processing a Si substrate by anisotropic dry etching or etch back. In addition to the shape shown in FIG. 15, the infrared lens may be a Fresnel lens formed by etching a Si substrate concentrically or a convex lens. By forming the infrared lens in this manner, the infrared absorption efficiency can be increased, and the sensor sensitivity can be improved.

<Example 9>
Example 9 describes a two-dimensional sensor array in which sensor elements are arranged in a two-dimensional array and a signal processing circuit is formed on the same substrate.

FIG. 16 is a diagram illustrating a configuration of an infrared sensor array described in the ninth embodiment.
As shown in FIG. 16A, this configuration is characterized in that an infrared sensor 111 is arranged on a Si substrate 106 in a two-dimensional array, and a signal processing circuit 112 that processes output signals from these infrared sensor arrays is provided. It was formed on the same substrate.

  As the signal processing circuit 112, a signal processing circuit similar to that used in a CMOS image sensor or the like can be used. FIG. 16A shows the case where the signal processing circuit 112 is formed around the infrared sensor array. However, the signal processing circuit 112 may be formed on the same substrate as the infrared sensor array, and its shape and layout are not limited. .

A cross-sectional view taken along line VV ′ in FIG. 16A is shown in FIG.
An infrared sensor 111 is formed in an array, and an infrared lens 110 is formed on the back surface of the Si substrate 106 for each infrared sensor. Thus, by forming the infrared lens, the aperture ratio and sensitivity of the two-dimensional infrared sensor array can be improved. In addition, although the infrared lens 110 is shown as an example of a convex lens, there is no problem with lenses having other shapes such as a Fresnel lens. The membrane portion 51 has the same configuration as that shown in FIG.

<Example 10>
In Example 10, a configuration in which a sensor element to which the present invention is applied is hermetically sealed by a wafer level chip size package (WL-CSP) will be described.

FIG. 17 is a diagram illustrating the configuration of the sensor element described in the tenth embodiment.
A feature of this configuration is that the Si substrate 106 on which the infrared sensor is formed and the glass substrate 120 serving as a lid are bonded together using anodic bonding or the like, and then dicing is performed to form a wafer level chip size package (WL -CSP).

  In the glass substrate 120, a cavity is formed at a position facing the infrared sensor portion formed on the Si substrate 106, and the membrane portion 51 does not contact the glass substrate 120. Further, a getter 121 for adsorbing gas and maintaining a high vacuum state may be formed in the hollow portion of the glass substrate 120.

  Further, a through via 122 is formed in the glass substrate 120, and the through via 122 is embedded with a conductive metal by a method such as electroplating. When the Si substrate 106 and the glass substrate 120 are bonded together by a method such as anodic bonding, the electrode on the Si substrate 106 side and the conductive metal in the through via 122 on the glass substrate 120 side are bonded to each other, thereby outputting an output signal. The external electrode 123 is extracted.

  Regarding the substrate serving as the lid, a ceramic substrate or the like can be used as long as it is a substrate capable of anodic bonding in addition to the glass substrate. In particular, an LTCC substrate having a thermal expansion coefficient close to that of Si is preferably used. The cavity, through-via, getter, electroplating, external electrode, etc. to be formed on the glass substrate 120 are often formed before bonding, but the through-via, electroplating, external electrode, etc. are formed after pasting. Also good. After wafer bonding, dicing between the sensors completes an airtightly sealed wafer level chip size package (WL-CSP) infrared sensor.

  Further, the method for forming the wafer level chip size package (WL-CSP) described here is an example, and any method may be used. Since the wafer level chip size package (WL-CSP) formed in this way maintains internal airtightness, it can be vacuum sealed or gas sealed.

  In particular, in the case of an infrared sensor, since the heat insulation between the membrane portion 51 and the surrounding area greatly contributes to the improvement of sensitivity, this package that enables vacuum sealing is very effective. Further, the problem of damage to the bridge structure during dicing can be solved by applying this WL-CSP. The wafer level chip size package (WL-CSP) can also be applied to a two-dimensional infrared sensor array.

1, 21, 31, 41, 51, 71: Membrane portions 2-5, 22-25, 32-35, 42-45, 52-55, 72-75: Beam portions 6-9, 26-29, 36- 39, 46 to 49, 80, 82; mask pattern 56 to 59: side of membrane 51 10 to 13: square 60 to 63: polygon c: length of the shortest part of the beam part b: width of the beam part 90: heat sensitive Portion 91: Infrared absorbing film 92, 93, 101: Wiring 94: Bottom protective layer 95: Interlayer film 96: Upper surface protective layer 100: Piezoelectric element 102: Infrared reflecting film 103: Infrared antireflection film 104, 105: Dummy wiring 106: Si substrate 107: Sensor element unit 1087: Signal processing circuit unit 110: Infrared lens 111: Infrared sensor 112: Signal processing circuit 120: Glass substrate 121: Getter 122: Through-hole 123: External electrode

JP 2001-264441 A

Claims (16)

In a semiconductor device having a substrate and a membrane portion that is supported in a hollow state by a plurality of beam portions on the substrate,
The membrane part and the beam part are all formed in the <100> direction of the Si (100) substrate, the plurality of beam parts are formed only on two opposite sides of the membrane part, and the length of the shortest part of the beam part A semiconductor device characterized in that the length is longer than the width of the beam portion. The membrane part is
A sensor element;
The semiconductor device according to claim 1, further comprising a wiring for outputting a signal detected by the sensor element. The semiconductor device according to claim 2, wherein the sensor element is a temperature sensor.   4. The semiconductor device according to claim 3, wherein the temperature sensor is any one of a pyroelectric temperature sensor, a thermopile, a thermistor, a PN junction diode, and a work function difference type temperature sensor. The membrane part is
The semiconductor device according to claim 3, further comprising an infrared absorption film. The membrane part is
With respect to the direction of infrared incidence
6. The semiconductor device according to claim 5, further comprising an infrared reflecting film below the infrared absorbing film. On the membrane part,
The semiconductor device according to claim 5, wherein an infrared antireflection film is formed. The semiconductor device according to claim 5, wherein an infrared lens is formed on a back surface of the substrate. The semiconductor device according to claim 5, wherein an infrared antireflection film is formed on the back surface of the substrate. 10. The semiconductor device according to claim 3, wherein dummy wirings for equalizing internal stress of the beam portion due to the wirings are provided at positions symmetrical to the wirings. 10. The semiconductor device according to claim 2, wherein the sensor element is a piezoelectric element. The semiconductor device according to claim 1, wherein the substrate is an SOI substrate. A signal processing circuit unit for processing an output signal of the sensor element;
The semiconductor device according to claim 2, wherein the sensor element and the signal processing circuit unit are formed on the same substrate. A semiconductor device according to any one of claims 1 to 12 is arranged in a two-dimensional array, and has a signal processing circuit unit that processes an output signal from each semiconductor device arranged in an array.
A semiconductor device, wherein the semiconductor device arranged on the two-dimensional array and the signal processing circuit portion are formed on the same substrate. The semiconductor device according to claim 1, wherein the semiconductor device is hermetically sealed by a wafer level chip size package (WL-CSP). In a method for manufacturing a semiconductor device having a substrate and a membrane portion supported in a hollow state by a plurality of beam portions on the substrate,
The <100> direction of the Si (100) substrate includes a membrane portion and a beam portion that has a shape in which the length of the shortest portion is longer than the width and supports the membrane portion only on two opposite sides of the membrane portion. Forming the step,
And a step of removing the Si under the membrane by performing anisotropic wet etching from the outer periphery of the membrane portion to the central portion of the membrane portion.

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