JP2011029532A - Ferroelectric capacitor and ferroelectric memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a ferroelectric thin film that has larger residual polarization (111) than PZT with an excellent orientation in a ferroelectric capacitor and a ferroelectric memory device. <P>SOLUTION: A ferroelectric film with a preferred orientation (111) is formed by adding, to tetragonal Pb(Zr<SB>x</SB>Ti<SB>1-x</SB>)O3, a material having a tetragonal perovskite structure with a larger c axis/a axis ratio than tetragonal Pb(Zr<SB>x</SB>Ti<SB>1-x</SB>)O3. Furthermore, an upper electrode and a lower electrode are provided so as to sandwich the ferroelectric film. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to a ferroelectric capacitor and a ferroelectric memory device. For example, a configuration for increasing the residual polarization amount of a tetragonal perovskite ferroelectric including PZT [Pb (Zr, Ti) O ₃ ]. About.

  In recent years, a non-volatile RAM that retains the immediately preceding memory even when the power is turned off and can be randomly accessed is a promising device in the field of personal authentication and security as a device that forms the basis of a ubiquitous society.

  Among various non-volatile random access memories, non-volatile memories (FeRAM) using ferroelectrics with spontaneous polarization in the dielectric layers of capacitors are expected as next-generation memories in the mobile field due to their low power consumption. (For example, refer to Patent Document 1).

  Currently, a one-transistor one-capacitor (1T1C) type FeRAM is in practical use. This type of FeRAM is used as a nonvolatile memory element by utilizing the fact that charges remain in a ferroelectric capacitor even when the power is turned off.

A material that is currently in practical use is a ferroelectric material such as PZT [Pb (Zr, Ti) O ₃ ] or SBT (SrBi ₂ Ta ₂ O ₉ ). The former remanent polarization is relatively large. However, at present, the maximum value of the residual polarization amount of PZT obtained from a thin film that can be used for a semiconductor memory cell is around 30 μC / cm ² . On the other hand, the maximum value of the latter remanent polarization amount is around 10 μC / cm ² .

Japanese Patent Laid-Open No. 2001-073328 JP 2007-129232 A

Appl. Phys. Lett. , Vol. 86, p. 262905, 2005 Chem. Mater. , Vol. 18, p. 4987, 2006

  As described above, the 1T1C type FeRAM is currently in practical use. However, since one transistor and one ferroelectric capacitor are required for one memory cell, a cell area larger than a certain size is required.

  Since the amount of charge that can be stored in a ferroelectric capacitor is proportional to the area, if the PZT and SBT described above are miniaturized, the amount of charge necessary for memory retention cannot be maintained, making it difficult to realize a large-capacity memory. It has become.

  For example, with these materials, a maximum memory capacity of 64 Mbit is the limit of miniaturization in the process of 150 nm rule at the maximum. In the future, in order to increase the capacity of the ferroelectric memory, it is necessary to increase the charge amount of the ferroelectric capacitor.

  For this purpose, it is necessary to increase the accumulated charge of the ferroelectric film. By increasing the amount of charge in the capacitor, it is possible to cope with a reduction in the capacitor area due to miniaturization, and thus it is possible to increase the scale.

Therefore, a ferroelectric material having a larger remanent polarization than PZT is desired, but there is no stable ferroelectric material having a high remanent polarization. For example, BZT [Bi (Zn, Ti) O ₃ ] is expected to have a remanent polarization amount of 100 μC / cm ² or more in theoretical prediction, but in practice, BZT substantially exhibiting ferroelectric characteristics is obtained. It is not done.

  Accordingly, an object of the present invention is to obtain a ferroelectric thin film having a remanent polarization larger than that of PZT.

From one aspect of the present invention, tetragonal _{Pb (Zr x Ti 1-x} ) to _{O 3,} the tetragonal _{Pb (Zr x Ti 1-x} ) c -axis / a-axis ratio than _{O 3} is large tetragonal perovskite structure There is provided a ferroelectric capacitor comprising a ferroelectric film added with a material having (111) preferential orientation, a lower electrode and an upper electrode sandwiching the ferroelectric film.

From another viewpoint of the present invention, a semiconductor substrate, a field effect transistor provided on the semiconductor substrate, and a tetragonal crystal Pb (Zr _x Ti _1-x ) are provided in an upper layer portion than the field effect transistor. the O _3, and the tetragonal _{Pb (Zr x Ti 1-x} ) O 3 was added to materials having from c-axis / a-axis ratio is greater tetragonal perovskite structure (111) strongly preferentially oriented dielectric film, A ferroelectric capacitor including a lower electrode and an upper electrode sandwiching the ferroelectric film, and electrically connecting one of the source electrode or the drain electrode of the field effect transistor and one of the upper electrode or the lower electrode; A ferroelectric memory device is provided in which the other of the upper electrode and the lower electrode is connected to a plate line.

  According to the disclosed ferroelectric capacitor and ferroelectric memory device, there is provided a ferroelectric memory device including a ferroelectric capacitor having a remanent polarization larger than PZT and a ferroelectric capacitor having a remanent polarization larger than PZT. Realization is possible.

1 is a schematic cross-sectional view of a ferroelectric capacitor according to an embodiment of the present invention. It is explanatory drawing of the orientation of a ferroelectric film. It is explanatory drawing of the BZT molar ratio dependence of a hysteresis characteristic. It is a hysteresis characteristic figure of 3% BZT-PZT. It is explanatory drawing of the principle of the increase in the amount of remanent polarization by addition of BZT. It is explanatory drawing of the temperature dependence of c-axis / a-axis ratio of PZT and 5% BZT-PZT. It is explanatory drawing of the manufacturing process to the middle of the stack type FeRAM of Example 1 of this invention. It is explanatory drawing of the manufacturing process until the middle of FIG. 7 after the stack type FeRAM of Example 1 of this invention. It is explanatory drawing of the manufacturing process after FIG. 8 of stack type FeRAM of Example 1 of this invention. FIG. 3 is an equivalent circuit diagram of the memory cell according to the first embodiment of the present invention. It is a schematic principal part sectional drawing of the planar type FeRAM of Example 2 of this invention.

Here, with reference to FIG. 1 thru | or FIG. 6, embodiment of this invention is described. FIG. 1 is a schematic cross-sectional view of a ferroelectric capacitor according to an embodiment of the present invention. As shown in FIG. 1, in the ferroelectric capacitor according to the embodiment of the present invention, a lower electrode 2, a (111) main-oriented ferroelectric film 3 and an upper electrode 4 are sequentially laminated on a base insulating film 1. Formed. Ferroelectric film 3 in this case, with respect to _{Pb (Zr x Ti 1-x} ) O 3 tetragonal perovskite structure, tetragonal _{Pb (Zr x Ti 1-x} ) O 3 than c-axis / a-axis ratio material _{Bi (M y R 1-y} ) O 3 ( where, M: Zn, Mg, R : Ti, Zr, Sn, Nb, W) having a large tetragonal perovskite structure is formed by adding.

In this case, the composition x of Pb (Zr _x Ti _1-x ) O ₃ is 0.25 to 0.45, and more preferably 0.35 to 0.45. Note that when x exceeds 0.45, the crystal structure becomes unstable, and when x> 0.55, it becomes orthorhombic rather than tetragonal. On the other hand, when x <0.25, a sufficient amount of remanent polarization cannot be obtained.

Bi (M _y R _1-y ) O ₃ (M: Zn, Ti, R: Ti, Zr, Sn, Nb, W) is Bi (Zn _y Ti with M = Zn and R = Ti). _1-y ) O ₃ is typical, and the composition ratio y of Bi (M _y R _1-y ) O ₃ is preferably in the range of 0.45 to 0.55.

_The amount of _{Bi (M y R 1-y} ) O 3 , _i.e., the molar ratio of _{Pb (Zr x Ti 1-x} ) O 3 and _{Bi (M y R 1-y} ) O 3 will be described later Thus, the range of 98: 2 to 92: 8 is suitable.

In this case, the lower electrode 2 is preferably a conductive material layer having (111) orientation. For example, Pt, Ir, Ru, IrO ₂ or RuO ₂ is used, but a ferroelectric film is used. Since it consists of an oxide, IrO ₂ or RuO ₂ which is the same oxide is more preferable.

Further, SrRuO ₃ (SRO) with (111) orientation or SrTiO ₃ with conductivity, for example, Nb-doped SrTiO _3, may be used as the lower electrode 2. Further, a stacked structure in which SrRuO ₃ or SrTiO ₃ imparted with conductivity is provided as a conductive oxide buffer layer on a conductive layer made of Pt, Ir, Ru, IrO ₂ , or RuO ₂ may be used. By using such a laminated structure, the (111) orientation of the ferroelectric film 3 can be improved.

As the upper electrode _{4, Pt, Ir, Ru,} IrO 2, RuO 2, SRO, Nb -doped SrTiO _{3, IrO} 2 / SRO layered _{structure, YBCO (YBa 2 Cu 3 O} 7-x), LSCO (La 2 using _-x Sr _x CuO _4).

  Further, as a method of forming the ferroelectric film 3, a sol-gel method may be used, an MOCVD method (metal organic chemical vapor deposition method) may be used, or a sputtering method may be used. When the sol-gel method is used, an acetylacetone complex (AcAc) of each metal is used as a solution raw material.

For example, when using Bi (Zn _y Ti _1-y ) O ₃ as Bi (M _y R _1-y ) O _3, as the PZT sol-gel solution,
Pb: Pb (AcAc)
Zr: Zr (AcAc)
Ti: Ti (AcAc)
A solution in which is dissolved in a solvent is used. Moreover, as a BZT sol-gel solution,
Bi: Bi (AcAc)
Zn: Zn (AcAc)
Ti: Ti (AcAc)
A solution in which is dissolved in a solvent is used.

  In this case, for example, if the concentration of the sol-gel solution is 0.25 mol / L, the PZT sol-gel solution and the BZT sol-gel solution are 98: 100 nm so that a film thickness of 50 nm to 100 nm, for example, 60 nm can be obtained. After mixing at a molar ratio of 2 to 92: 8, the mixture is dropped on the lower electrode and spin coated. In this case, first, it is rotated at 300 rpm to 600 rpm for 5 seconds to 10 seconds, and then rotated at 2500 rpm to 4000 rpm for 20 seconds to 30 seconds.

  Next, after preliminary calcination at a temperature of 200 ° C. to 360 ° C. for 3 minutes to 5 minutes in air or an oxygen atmosphere, drying is performed for 1 minute to 6 minutes in air or an oxygen atmosphere. After repeating this process until the total film thickness reaches 120 nm to 300 nm, crystallization annealing is performed at a temperature of 550 ° C. to 650 ° C. in an oxygen atmosphere.

In addition, when a film is formed using the MOCVD method, as a PZT source,
Pb: Pb (C ₁₁ H ₁₉ O ₂ ) ₂
Zr: Zr (Ot-C ₄ H ₉ ) ₄
Ti: Ti (O—I—C ₃ H ₇ ) ₄
Is used. As a BZT source,
Bi: Bi ((CH ₃ ) ₂ [2- (CH ₃ ) ₂ NCH ₂ C ₆ H ₄ ])
Zz: Zr (C ₁₄ H ₂₅ O ₂ ) ₂
Ti: Ti (O—I—C ₃ H ₇ ) ₄
Is used.

  In this case, in a state where the substrate temperature is set to 550 ° C. to 670 ° C., the supply ratio of each source is adjusted so as to be a set composition ratio and sent to the film formation chamber to perform crystallization film formation.

When sputtering is used, an amorphous film is formed on the lower substrate by Ar / O ₂ sputtering using a PZT target to which BZT is added at 2% to 8%, more preferably 3% to 5%. After that, crystallization annealing is performed at a temperature of 550 ° C. to 670 ° C.

  FIG. 2 is an explanatory view of the orientation of the ferroelectric film, and shows the measurement result of the PZT-BZT film formed by the sol-gel method on the (111) -oriented Pt lower electrode. The upper electrode is also Pt. As shown in the figure, it is understood that the (111) orientation is considerably deteriorated when the molar ratio of BZT is 10%.

FIG. 3 is an explanatory diagram of the dependence of hysteresis characteristics on the BZT molar ratio. The hysteresis characteristics when a voltage of 10 V is applied to a ferroelectric capacitor in which a PZT-BZT film having a thickness of 200 nm is sandwiched between Pt electrodes are shown. Show. As is apparent from the figure, the amount of remanent polarization is
PZT 35μC / cm ²
3% BZT-PZT 45 μC / cm ²
5% BZT-PZT 46 μC / cm ²
8% BZT-PZT 41 μC / cm ²
10% BZT-PZT 41 μC / cm ²
Met.

  Considering FIG. 3 together with FIG. 2 above, it is preferable to add 2% or more, more preferably 3% or more in order to sufficiently exhibit the effect of adding BZT. On the other hand, when (10)% or more is added, the (111) orientation is lowered, so the addition amount is preferably 8% or less, more preferably 5% or less.

  FIG. 4 is a hysteresis characteristic diagram of 3% BZT-PZT, and the amount of remanent polarization increases as the applied voltage increases.

Next, with reference to FIG. 5, the principle of increasing the amount of remanent polarization by adding BZT will be described. FIG. 5A is a crystal structure diagram of PZT, which is an ABO ₃ type tetragonal perovskite structure. In this case, the atom at the A site is Pb, and the atom at the B site is Zr or Ti. In PZT, although it depends on the composition ratio, the c-axis / a-axis ratio at 30 ° C. is about 1.023. In this case, by applying a voltage in the c-axis direction, atoms at the B site move in the voltage application direction, and even when the voltage is set to 0 V, it does not return to the lattice position, which causes residual polarization.

FIG. 5B is a crystal structure diagram of 3% BZT-PZT, and the c-axis / a-axis ratio of BZT [Bi (Zn _0.5 Ti _0.5 ) O ₃ ] at room temperature is 1.21. Therefore, 3% BZT-PZT has a crystal structure extending in the c-axis direction.

  Therefore, when a voltage is applied in the c-axis direction, the movement space of the B site atoms is expanded, and the movement of the B site atoms is facilitated, and the residual polarization amount is accordingly increased. However, in the case of BZT itself, ferroelectric characteristics cannot be obtained, and as shown in FIG. 2, the (111) orientation of 10% BZT-PZT when 10% is added decreases. There is an upper limit to the amount added.

  FIG. 6 is an explanatory diagram of the temperature dependence of the c-axis / a-axis ratio of PZT and 5% BZT-PZT, and the effect of increasing the c-axis / a-axis ratio by adding BZT was confirmed up to around 300 ° C. . Therefore, PZT which shows excellent ferroelectric properties does not show sufficient ferroelectric properties by itself, but by adding a material having a tetragonal perovskite structure with a c-axis / a-axis ratio from PZT. Movement of atoms at the B site is facilitated, and the amount of remanent polarization increases at normal operating temperatures.

  Based on the above, the stack type FeRAM according to the first embodiment of the present invention will be described next with reference to FIGS. 7 to 10, but will be described as one memory cell. First, as shown in FIG. 7A, after forming a p-type well region 12 in a p-type silicon substrate 11, an element isolation insulating film 13 having an STI (Shallow Trench Isolation) structure is formed. Note that an n-type well region for forming a p-channel transistor is also formed in another region of the p-type silicon substrate 11, but the illustration and description are omitted here for the sake of simplicity.

  Next, a gate electrode 15 made of polycrystalline silicon is formed in the p-type well region 12 through the gate insulating film 14, and ions such as As are implanted using the gate electrode 15 as a mask to form an n-type extension region 16. To do.

Next, an SiO ₂ film or the like is deposited on the entire surface, and anisotropic etching is performed to form the sidewalls 17. Then, As and the like are ion-implanted again to form the n ⁺ -type drain region 18 and the n ⁺ -type source region. 19 is formed.

Next, after an interlayer insulating film 20 made of a thick SiO ₂ film or the like is formed and planarized, contact holes reaching the n ⁺ type drain region 18 and the n ⁺ type source region 19 are formed, and this contact hole is formed as a TiN film ( W plugs 21 and 22 are formed by embedding with W via (not shown).

  Next, as shown in FIG. 7B, for example, a Pt film 23 having a thickness of, for example, 200 nm is deposited on the entire surface to serve as the lower electrode. In this case, the Pt film 23 becomes a (111) main alignment film by self-alignment.

Next, the ferroelectric film 25 is formed using a sol-gel method. For example, a sol-gel solution in which 3 mol% Bi (Zn _0.5 Ti _0.5 ) O ₃ is added to Pb (Zr _0.4 Ti _0.6 ) O ₃ is dropped on the Pt film 23 and spin coating is performed. Form a film. As the sol-gel solution, an acetylacetone complex of each metal is used as described above.

  First, a sol-gel solution is dropped on the Pt film 23, rotated at 300 rpm to 600 rpm for 5 seconds to 10 seconds, for example, 500 rpm for 5 seconds, and then rotated at 2500 rpm to 4000 rpm, for example, 3000 rpm for 20 seconds. Make it thick.

  Next, for example, after calcining on a hot plate at 200 ° C. to 360 ° C., for example, 330 ° C. for 3 minutes to 5 minutes, for example, for 4 minutes in the atmosphere or oxygen, subsequently, for 1 minute in the air or oxygen Allow to dry for ~ 6 minutes. In this step, for example, a 67 nm coating film 24 is formed. This process is repeated until the total film thickness becomes 120 nm to 300 nm, for example, 200 nm.

  Next, as shown in FIG. 8C, the coating film 24 is crystallized by holding at 550 ° C. to 650 ° C., for example, 600 ° C. for 30 minutes in an oxygen atmosphere using an RTA (rapid thermal annealing) furnace, and PZT. A ferroelectric film 25 made of BZT is used.

  Next, as shown in FIG. 8D, a Pt film 26 having a thickness of, for example, 100 nm as an upper electrode is deposited again on the ferroelectric film 25 by sputtering.

  Next, as shown in FIG. 9 (e), the Pt film 26, the ferroelectric film 25, and the Pt film 23 are sequentially etched using the resist pattern (not shown) as a mask to thereby form the upper electrode 29 / ferroelectric film 25. / A ferroelectric capacitor 27 composed of the lower electrode 28 is formed.

  Next, in order to recover the damage received by the ferroelectric film 25 by etching or the like, for example, heat treatment is performed at 600 ° C. for about 30 minutes in an atmospheric pressure oxygen atmosphere.

Next, as shown in FIG. 9F, after forming a protective film 30 made of thin Al ₂ O ₃ or the like on the entire surface, an interlayer insulating film 31 made of SiO ₂ or the like having a thickness of 1.5 μm, for example. To flatten the surface.

Next, contact holes reaching the W plug 21 and the upper electrode 29 are formed. Next, a TiN film, an Al film, a Ti film, and a TiN film are sequentially deposited on the entire surface and then patterned to form a bit line 32 connected to the n ⁺ -type drain region 18 and connected to the upper electrode 29. A plate line 33 is formed. Note that the gate electrode 15 is connected to a word line.

  Although not shown in the drawings, depending on the requirements of the circuit configuration, wiring of three to five layers is performed, and various insulating films such as an interlayer insulating film, a silicon oxide film, and a silicon nitride film are formed to form a device. Protect moving parts.

  Finally, an external lead electrode is formed, and polyimide is formed on the other portions to form a protective layer, thereby completing the basic structure of the stacked FeRAM according to the first embodiment of the present invention.

FIG. 10 is an equivalent circuit diagram of the memory cell shown in FIG. 9F. The gate electrode 15 is connected to the word line 34, while the ferroelectric capacitor 27 is connected to the plate line (ground line) 33 and the n ⁺ type. Connected to the source region 19.

As described above, in the stack type FeRAM according to the first embodiment of the present invention, PZT-BZT having a c-axis / a-axis ratio larger than PZT is used as the dielectric film constituting the ferroelectric capacitor. Greater than 35 μC / cm ² . In addition, since one memory cell can be miniaturized, a large-capacity FeRAM can be realized.

Next, referring to FIG. 11, a planar type FeRAM according to the second embodiment of the present invention will be described. First, an n-channel transistor is formed by the same process as in the first embodiment, and W plugs 21 and 22 for the n ⁺ -type drain region 18 and the n ⁺ -type source region 19 are formed.

Next, after depositing a thin SiN film 41 and SiO ₂ film 42 on the entire surface by using the CVD method, for example, a RuO ₂ film 43 having a thickness of, for example, 200 nm and a thickness of, for example, 100 nm are formed as the lower electrode. SrRuO ₃ films 44 are sequentially deposited. In this case, the RuO ₂ film 43 becomes a (111) main alignment film by self-alignment, and the (111) orientation is further improved by providing the SrRuO ₃ film 44.

Next, a ferroelectric film 45 is formed using MOCVD. For example, the flow rate ratio of each source is set so that the molar ratio of Bi (Zn _0.5 Ti _0.5 ) O ₃ and Pb (Zr _0.4 Ti _0.6 ) O ₃ is 3:97. Note that as the source, the source described in the above embodiment mode is used, and the substrate temperature is 550 ° C. to 670 ° C., for example, 600 ° C., and crystallization is performed.

Next, again, a RuO ₂ film having a thickness of, for example, 200 nm to be an upper electrode is deposited on the ferroelectric film 45 by sputtering. Next, the RuO ₂ film, the ferroelectric film 45, the SrRuO ₃ film 44, and the RuO ₂ film 43 are sequentially etched using the resist pattern (not shown) as a mask to sequentially etch the upper electrode 48 / ferroelectric film 45 / lower electrode 47. A ferroelectric capacitor 46 is formed.

  Next, in order to recover the damage received by the ferroelectric film 45 by etching or the like, for example, heat treatment is performed at 600 ° C. for about 30 minutes in an atmospheric pressure oxygen atmosphere.

Next, after forming a thin insulating film 49 made of Al ₂ O ₃ or the like on the entire surface, a contact hole reaching the W plug 22 and a contact hole for the upper electrode 48 are provided. Next, a local internal wiring 50 is formed by depositing and patterning a TiN film on the entire surface.

Next, an interlayer insulating film 51 made of, for example, a 1.5 μm thick SiO ₂ film is deposited and planarized on the entire surface, and then a contact hole reaching the W plug 21 is formed. Next, a TiN film, an Al film, a Ti film, and a TiN film are sequentially deposited on the entire surface and then patterned to form the bit line 52 connected to the n ⁺ -type drain region 18. The gate electrode 15 is connected to the word line, and the lower electrode 47 is connected to the plate line.

  Although not shown in the drawings, depending on the requirements of the circuit configuration, wiring of three to five layers is performed, and various insulating films such as an interlayer insulating film, a silicon oxide film, and a silicon nitride film are formed to form a device. Protect moving parts. Finally, an external lead electrode is formed, and polyimide is formed on the other portions to form a protective layer, thereby completing the basic structure of the planar FeRAM according to the second embodiment of the present invention.

Also in the planar type FeRAM according to the second embodiment of the present invention, only the connection structure is different and PZT-BZT is used as the dielectric film constituting the ferroelectric capacitor. Therefore, the residual polarization amount is 35 μC / cm ^{2 of} PZT. Can be bigger. In addition, since one memory cell can be miniaturized, a large-capacity FeRAM can be realized.

  Each example of the present invention has been described above, but the present invention is not limited to the conditions shown in each example, and each condition described in the above embodiment may be adopted. is there. For example, in Example 1, the sol-gel method is used as the method for forming the ferroelectric film, but the MOCVD method or the sputtering method may be used.

  In Example 2, the MOCVD method is used as the method for forming the ferroelectric film, but a sol-gel method or a sputtering method may be used. Further, the material of the upper electrode or the lower electrode may be appropriately changed within the range disclosed in the above embodiment.

Here, the following supplementary notes are disclosed regarding the embodiment of the present invention including Example 1 and Example 2.
To (Supplementary Note 1) tetragonal _{Pb (Zr x Ti 1-x} ) O 3, a material having the tetragonal _{Pb (Zr x Ti 1-x} ) c -axis / a-axis ratio than _{O 3} is large tetragonal perovskite structure A ferroelectric capacitor comprising: a ferroelectric film added with (111) preferential orientation; and a lower electrode and an upper electrode sandwiching the ferroelectric film.
(Supplementary Note 2) A material having a tetragonal perovskite structure having a c-axis / a-axis ratio larger than that of the tetragonal Pb (Zr _x Ti _1-x ) O ₃ is a part of Pb in Bi and M _y R _{1 The} ferroelectric capacitor as set forth in appendix 1, wherein _-y (where M: Zn, Mg, R: Ti, Zr, Sn, Nb, W).
(Supplementary Note 3) the ferroelectric film, the tetragonal _{Pb (Zr x Ti 1-x} ) O 3 and _{Bi (M y R 1-y} ) O 3 ( where, M: Zn, Mg, R : Ti, 3. The ferroelectric capacitor according to appendix 2, wherein the ferroelectric capacitor is formed of a material having a molar ratio with Zr, Sn, Nb, W) of 98: 2 to 92: 8.
(Supplementary Note 4) The composition ratio y of Bi (M _y R _1-y ) O ₃ (M: Zn, Mg, R: Ti, Zr, Sn, Nb, W) is 0.45 to 0.55. The ferroelectric capacitor as set forth in appendix 3, wherein:
(Supplementary Note 5) ferroelectric according to any one of Supplementary Notes 1 to 4 wherein the tetragonal _{Pb (Zr x Ti 1-x} ) O 3 composition ratio x is equal to or is 0.25 to 0.45 Body capacitor.
(Supplementary note 6) The ferroelectric capacitor according to any one of supplementary notes 1 to 5, wherein the lower electrode is made of a conductive material layer having (111) orientation.
(Supplementary note 7) The ferroelectric capacitor according to supplementary note 6, wherein the conductive material layer is made of any one of Pt, Ir, Ru, or an oxide thereof.
(Supplementary note 8) The ferroelectric capacitor according to supplementary note 6, wherein the conductive material layer is made of SrRuO ₃ or SrTiO ₃ imparted with conductivity.
(Supplementary Note 9) The conductive material layer includes a conductive oxide buffer layer made of SrRuO ₃ or SrTiO ₃ imparted with conductivity, and a conductive layer layer made of Pt, Ir or Ru, or an oxide thereof. The ferroelectric capacitor according to appendix 6, wherein the ferroelectric capacitor has a laminated structure.
(Supplementary Note 10) A semiconductor substrate, a field effect transistor provided on the semiconductor substrate, and an upper layer portion than the field effect transistor, and the tetragonal crystal Pb (Zr _x Ti _1-x ) O ₃ has the tetragonal crystal. A (111) preferentially oriented ferroelectric film is sandwiched by adding a material having a tetragonal perovskite structure having a larger c-axis / a-axis ratio than Pb (Zr _x Ti _1-x ) O _3, and the ferroelectric film sandwiched between A ferroelectric capacitor composed of a lower electrode and an upper electrode; electrically connecting one of a source electrode or a drain electrode of the field effect transistor and one of the upper electrode or the lower electrode; and A ferroelectric memory device, wherein the other of the upper electrode and the lower electrode is connected to a plate line.

DESCRIPTION OF SYMBOLS 1 Base insulating film 2 Lower electrode 3 Ferroelectric film 4 Upper electrode 11 P-type silicon substrate 12 P-type well region 13 Element isolation insulating film 14 Gate insulating film 15 Gate electrode 16 N-type extension region 17 Side wall 18 n ⁺ type drain Region 19 n ⁺ type source regions 20, 31, 51 Interlayer insulating films 21, 22 W plug 23, 26 Pt film 24 Coating film 25, 45 Ferroelectric film 27, 46 Ferroelectric capacitor 28, 47 Lower electrodes 29, 48 Upper electrode 30 Protective film 32, 52 Bit line 33 Plate line 34 Word line 41 SiN film 42 SiO ₂ film 43 RuO ₂ film 44 SrRuO ₃ film 49 Insulating film 50 Local internal wiring

Claims (6)

Tetragonal _{Pb (Zr x Ti 1-x} ) O 3, with the addition of material having the tetragonal _{Pb (Zr x Ti 1-x} ) c -axis / a-axis ratio than _{O 3} is large tetragonal perovskite structure ( 111) a preferentially oriented ferroelectric film;
A ferroelectric capacitor comprising a lower electrode and an upper electrode sandwiching the ferroelectric film. A material having a tetragonal perovskite structure having a c-axis / a-axis ratio larger than that of the tetragonal Pb (Zr _x Ti _1-x ) O ₃ is a part of Pb in Bi and one of Zr _x Ti _1-x . part is _{M y R 1-y} (where, M: Zn, Mg, R : Ti, Zr, Sn, Nb, W) the ferroelectric capacitor according to claim 1, characterized in that a. The ferroelectric film, the said tetragonal _{Pb (Zr x Ti 1-x} ) O 3 Bi (M y R 1-y) O 3 ( where, M: Zn, Mg, R : Ti, Zr, Sn , Nb, W). The ferroelectric capacitor according to claim 2, wherein the ferroelectric capacitor is formed from a raw material having a molar ratio of 98: 2 to 92: 8. The _{Bi (M y R 1-y} ) O 3 ( where, M: Zn, Mg, R : Ti, Zr, Sn, Nb, W) composition ratio y of, that is from 0.45 to 0.55 4. The ferroelectric capacitor according to claim 3, wherein 5. The ferroelectric capacitor according to claim 1, wherein a composition ratio x of the tetragonal Pb (Zr _x Ti _1-x ) O ₃ is 0.25 to 0.45. . A semiconductor substrate;
A field effect transistor provided on the semiconductor substrate;
Is provided on the upper portion than the field-effect transistor, the tetragonal _{Pb (Zr x Ti 1-x} ) O 3 , a large c-axis / a-axis ratio than the tetragonal _{Pb (Zr x Ti 1-x} ) O 3 A ferroelectric film (111) preferentially oriented by adding a material having a tetragonal perovskite structure, and a ferroelectric capacitor including a lower electrode and an upper electrode sandwiching the ferroelectric film,
Electrically connecting one of a source electrode or a drain electrode of the field effect transistor and one of the upper electrode or the lower electrode;
A ferroelectric memory device, wherein the other of the upper electrode and the lower electrode is connected to a plate line.

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