JP2011199071A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that has a plurality of capacitors with different characteristics without exposing a surface of a ferroelectric film to a resist.SOLUTION: The method of manufacturing the semiconductor device includes the processes of: forming an insulating film over a substrate; forming a lower electrode layer over the insulating film; forming the ferroelectric film on the lower electrode layer; forming a first upper electrode layer on the ferroelectric film; forming a first resist covering a first region on the first upper electrode layer; removing the first upper electrode layer in a second region by etching using the first resist as a mask and also shaving the ferroelectric film in the second region; forming a second upper electrode layer on the first upper electrode layer in the first region and on the ferroelectric film not in the first region; forming a second resist in the first region and the second region; and forming a first capacitor and a second capacitor by etching the first upper electrode layer, the second upper electrode layer, the ferroelectric film, and the lower electrode layer through the second resist as a mask.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, with the advancement of digital technology, high-capacity data is processed or stored at high speed. For this reason, high integration and high performance of semiconductor devices used in electronic devices and the like are required. For example, in a semiconductor memory device which is an example of a semiconductor device, DRAM (Dynamic Random Access Memory) is highly integrated. In order to increase the integration density of the DRAM, a ferroelectric material or a high dielectric constant material is used instead of the conventional silicon oxide or silicon nitride as a capacitor insulating film of a capacitor used in the DRAM. Further, a ferroelectric film having spontaneous polarization characteristics is used as a capacitor insulating film in order to realize a nonvolatile RAM capable of writing and reading at a lower voltage and higher speed. Such a semiconductor memory device is called a ferroelectric memory (FeRAM).

  FeRAM stores information using the hysteresis characteristics of ferroelectrics. A ferroelectric capacitor having a ferroelectric film as a capacitor dielectric between a pair of electrodes has a property of causing polarization according to an applied voltage between the electrodes and having spontaneous polarization even when the applied voltage is removed. If the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Information can be read by detecting spontaneous polarization. FeRAM is a non-volatile memory that has features such as high-speed operation, low power consumption, and excellent write / read durability, and further development is expected in the future.

  However, in order to improve the low voltage operation and the degree of integration, it is necessary to reduce the capacitor area, reduce the capacitor dielectric film, and lower the polarization inversion voltage of the ferroelectric capacitor. However, if the capacitor dielectric film is simply thinned and the same voltage as the current voltage is applied to the capacitor, the electric field applied to the capacitor dielectric film becomes larger than the current voltage, and the leakage current in the capacitor dielectric film increases. Further, by reducing the thickness of the dielectric film, the amount of inversion charge is reduced, and the fatigue resistance and imprint characteristics are also deteriorated. These problems are common problems in the current development of ferroelectric capacitors.

  On the other hand, the ferroelectric capacitor is used not only as a memory element but also in many applications by utilizing the feature that a large capacity can be realized with a small area. For example, a ferroelectric capacitor is used as a smoothing capacitor for power supply wiring of a logic circuit that drives a memory element.

Conventionally, capacitors of different applications have been manufactured by separate manufacturing processes. This is because capacitors with different applications require different characteristics, and it is difficult to manufacture them by the same process. For example, a capacitor used in a memory element of a ferroelectric memory is required to have a low voltage operation, a large inversion charge amount (Qsw), an excellent retention characteristic, and a good imprint characteristic. A thin ferroelectric film is used as a capacitor dielectric that satisfies these requirements. Since a high breakdown voltage is given priority to the smoothing capacitor, a technique using a SiO ₂ film or a SiN film having a high breakdown voltage as a capacitor dielectric is known. When two types of capacitors incorporated in the same semiconductor device use different dielectrics such as a ferroelectric capacitor and a MIM (metal-insulator-metal) capacitor, they are manufactured in separate manufacturing processes.

In a method of forming the memory element and the smoothing capacitor on the same plane with a simpler manufacturing process, a ferroelectric material is used. Since the dielectric constant of the ferroelectric material is larger than that of a general insulating material, the memory element and the smoothing capacitor can be formed on the same plane with a smaller area. In the manufacturing process of a ferroelectric memory device up to now, a ferroelectric memory device and a smooth ferroelectric capacitor are simultaneously formed on the same plane.

However, in order to improve the low voltage operation and the degree of integration, it is necessary to make the ferroelectric film thin. As the ferroelectric film becomes thinner, the leakage current of the capacitor increases and the capability of high withstand voltage also decreases. If the ferroelectric film is thinned to some extent, the high withstand voltage smoothing capacitor does not satisfy the withstand voltage requirement. In this case, using the MIM capacitor using the SiO ₂ film or the SiN film is one of the selection items. Further, the present invention can also be applied to a case where a capacitor having a thin ferroelectric substance for a memory element and a capacitor having a thick ferroelectric substance having a high withstand voltage coexist. That is, when the ferroelectric film in the ferroelectric capacitor has different film thicknesses, it can be easily dealt with by depositing different ferroelectric films.

  However, in the above-described method, it is necessary to repeat the capacitor manufacturing process by the number of different ferroelectric film thicknesses of each ferroelectric capacitor, and the manufacturing cost increases due to an increase in the manufacturing process. A lower electrode and a ferroelectric film are sequentially stacked on the insulating film, and the ferroelectric film is partially etched using a resist. There is a method of forming a capacitor having a thick ferroelectric film (capacitor for a smooth ferroelectric capacitor) and a capacitor having a thin ferroelectric film (a capacitor for a memory element) by forming an upper electrode.

Japanese Patent Laid-Open No. 53-112686 JP 2007-281373 A

  The problem of a ferroelectric capacitor for FeRAM is to operate at a low voltage so that a necessary amount of inversion charge can be guaranteed even after a predetermined reliability test. In order to operate at a low voltage, it is necessary to reduce the thickness of the ferroelectric film. As the ferroelectric film is made thinner, it is necessary to improve the fatigue resistance, imprint resistance, and retention characteristics of the capacitor.

  As a result of investigating the influence on the capacitor characteristics with respect to various electrodes, the composition and thickness of the ferroelectric film, and the crystallization method of the ferroelectric film, it is found that the fatigue resistance and in- Print characteristics deteriorate. FIG. 30 shows the dependency relationship between the capacitor imprint resistance and the capacitor leakage current. The vertical axis in FIG. 30 shows the rate reduction (Q3-Rate) of the charge amount of the capacitor, and the horizontal axis in FIG. 30 shows the leakage current of the capacitor. When the leakage current of the capacitor increases, the imprint resistance (Q3-Rate) is improved. Therefore, in order to operate the capacitor at a low voltage, it is important to improve the interface between the electrode and the ferroelectric film.

  Therefore, conventionally, processing as described below has been performed. For example, a resist mask having an opening for covering the formation region of the ferroelectric capacitor for memory and covering the formation region of the ferroelectric capacitor for memory is formed on the ferroelectric film. Then, the reactive ferroelectric etching using the resist mask as a mask is used to etch and thin the ferroelectric film exposed on the bottom surface of the opening. Thereafter, an upper electrode is formed. The smoothing ferroelectric capacitor formed by such a method has the following problems.

  (1) When a resist is formed on the surface of the ferroelectric film, the organic substance of the resist destroys the crystallinity of the ferroelectric film, and the ferroelectricity of the ferroelectric film deteriorates. (2) When a resist is formed on the surface of the ferroelectric film, swelling and film peeling occur at the interface between the ferroelectric film coated with the resist and the upper electrode. These bulges and film peeling defects cause defects such as capacitor shape defects and pattern skipping, which in turn reduce the yield of semiconductor devices.

  The object of the present invention is to manufacture a semiconductor device having a plurality of capacitors having different characteristics without exposing the surface of the ferroelectric film to a resist.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device in which a first capacitor and a second capacitor are respectively formed in a first region and a second region on a semiconductor substrate. Forming an insulating film on the substrate or above the semiconductor substrate; forming a lower electrode layer above the insulating film; forming a ferroelectric film on the lower electrode layer; and Forming a first upper electrode layer on the dielectric film; forming a first resist covering the first region on the first upper electrode layer; and Etching as a mask removes the first upper electrode layer in the second region, scrapes the ferroelectric film in the second region, and the first region in the first region. 1 on the upper electrode layer Forming a second upper electrode layer on the ferroelectric film other than the first region; and the first region and the second region above the second upper electrode layer. Forming a second resist on the substrate, etching the first upper electrode layer, the second upper electrode layer, the ferroelectric film and the lower electrode layer using the second resist as a mask, Forming a first capacitor and the second capacitor.

  According to this case, a semiconductor device having a plurality of capacitors having different characteristics can be manufactured without exposing the surface of the ferroelectric film to a resist.

1 is a cross-sectional view (No. 1) of a semiconductor device according to a first embodiment; FIG. 3 is a sectional view (No. 2) of the semiconductor device according to the first embodiment; FIG. 3 is a sectional view of the semiconductor device according to the first embodiment (part 3); FIG. 6 is a sectional view (No. 4) of the semiconductor device according to the first embodiment; FIG. 6 is a sectional view (No. 5) of the semiconductor device according to the first embodiment; FIG. 6 is a sectional view (No. 6) of the semiconductor device according to the first embodiment; FIG. 6 is a sectional view (No. 7) of the semiconductor device according to Example 1; FIG. 8 is a cross-sectional view (No. 8) of the semiconductor device according to the first embodiment; FIG. 9 is a sectional view (No. 9) of the semiconductor device according to Example 1; FIG. 10 is a sectional view (No. 10) of the semiconductor device according to the first embodiment; FIG. 12 is a cross-sectional view (No. 11) of the semiconductor device according to the first embodiment. FIG. 12 is a cross-sectional view of the semiconductor device according to the first embodiment (No. 12). It is a figure which shows the Qtv characteristic of the capacitor about the sample of a cell array. It is a figure which shows the IV characteristic of the capacitor about a discrete sample. It is a figure which shows the fatigue characteristic of the capacitor about the sample of a cell array. It is a figure which shows the loss amount of the switching charge amount (inversion charge amount) of each capacitor. It is a figure which shows the Q3 characteristic of the capacitor about the sample of a cell array. It is a figure which shows Q3-Rate. 7 is a cross-sectional view of a semiconductor device according to a first modification of Example 1. FIG. 7 is a cross-sectional view of a semiconductor device according to a second modification of Example 1. FIG. 7 is a cross-sectional view of a semiconductor device according to a third modification of Example 1. FIG. 7 is a cross-sectional view of a semiconductor device according to a fourth modification of Example 1. FIG. 7 is a cross-sectional view of a semiconductor device according to a fifth modification of Example 1. FIG. 7 is a cross-sectional view of a semiconductor device according to a sixth modification of Example 1. FIG. 10 is a cross-sectional view of a semiconductor device according to a seventh modification example of Example 1. FIG. 6 is a sectional view of a semiconductor device according to a second embodiment (No. 1). FIG. 6 is a sectional view of a semiconductor device according to a second embodiment (No. 2). FIG. FIG. 6 is a cross-sectional view of the semiconductor device according to the second embodiment (No. 3). FIG. 4 is a cross-sectional view of the semiconductor device according to the second embodiment (No. 4). FIG. 6 is a cross-sectional view of the semiconductor device according to the second embodiment (No. 5). FIG. 6 is a cross-sectional view of the semiconductor device according to the second embodiment (No. 6). FIG. 7 is a cross-sectional view of the semiconductor device according to the second embodiment (No. 7). It is a figure which shows the dependence relationship between the imprint-proof characteristic of a capacitor, and the leakage current of a capacitor.

  Hereinafter, a method for manufacturing a semiconductor device according to a mode for carrying out the invention (hereinafter referred to as an embodiment) will be described with reference to the drawings with specific examples.

  A first example of this embodiment will be described. 1 to 12 are sectional views of the semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment is a semiconductor device having a planar type FeRAM, and is manufactured as follows.

First, steps required until a sectional structure shown in FIG. First, an element isolation insulating film 2 is formed by thermally oxidizing the surface of an n-type or p-type silicon (semiconductor) substrate 1, and the element isolation insulating film 2 defines an active region of a transistor. Such an element isolation structure is called LOCOS (Local Oxidation of Silicon), but instead of STI (Shallow
Trench Isolation) may be adopted.

  Next, after introducing p-type impurities, for example, boron into the active region of the silicon substrate 1 to form the p-well 3, the surface of the active region is thermally oxidized to form a thermal oxide film as the gate insulating film 4. Form. The film thickness of the gate insulating film 4 is, for example, 6 to 7 nm.

  Subsequently, an amorphous silicon film having a thickness of about 50 nm and a tungsten silicide film having a thickness of about 150 nm are sequentially formed on the entire upper surface of the silicon substrate 1. The film thickness of the amorphous silicon film is about 50 nm, for example. The film thickness of the tungsten silicide film is, for example, about 150 nm. Note that a polycrystalline silicon film may be formed instead of the amorphous silicon film. Thereafter, these films are patterned by photolithography to form the gate electrode 5 on the silicon substrate 1. The gate electrode 5 becomes a part of the word line.

  Further, for example, phosphorus is introduced as an n-type impurity into the silicon substrate 1 beside the gate electrode 5 by ion implantation using the gate electrode 5 as a mask to form source / drain extensions 6.

  Thereafter, an insulating film is formed on the entire upper surface of the silicon substrate 1, and the insulating film is etched back to form an insulating sidewall 7 next to the gate electrode 5. For example, a silicon oxide film formed by a CVD (Chemical Vapor Deposition) method may be used as the insulating film.

  Subsequently, n-type impurities such as arsenic are ion-implanted again into the silicon substrate 1 using the gate electrode 5 and the insulating sidewalls 7 as a mask, so that source / drain regions ( Impurity diffusion region) 8 is formed.

  Further, a refractory metal film such as a cobalt film is formed on the entire upper surface of the silicon substrate 1 by sputtering. Then, the refractory metal film is heated and reacted with silicon, whereby the refractory metal silicide layer 9 such as a cobalt silicide layer is formed on the upper surface of the gate electrode 5 and the upper surface of the silicon substrate 1 in the source / drain regions 8 respectively. Form. By the heat treatment, the source / drain region 8 is activated and the resistance of the source / drain region 8 is lowered.

  Thereafter, the unreacted refractory metal film on the element isolation insulating film 2 and the like is removed by wet etching.

Through the steps so far, a MOS (Metal Oxide Semiconductor) transistor having the gate insulating film 4, the gate electrode 5, the source / drain region 8 and the like is formed in the active region of the silicon substrate 1.

  Next, a silicon oxynitride (SiON) film is formed as an antioxidant insulating film (cover film) 10 on the upper surface of the silicon substrate 1 by plasma CVD. The film thickness of the antioxidant insulating film 10 is about 200 nm, for example.

Further, a first interlayer insulating film 11 is formed on the silicon substrate 1 or above the silicon substrate 1. In Example 1, a silicon oxide (SiO ₂ ) film is formed as the first interlayer insulating film 11 on the antioxidant insulating film 10 by plasma CVD using TEOS (tetra ethoxy silane) gas. The film thickness of the first interlayer insulating film 11 is, for example, about 1000 nm.

Thereafter, the first interlayer insulating film 11 is polished by CMP (Chemical Mechanical Polishing) to planarize the upper surface of the first interlayer insulating film 11. By the CMP method, the film thickness from the surface of the silicon substrate 1 to the surface of the first interlayer insulating film 11 becomes a predetermined value, for example, about 785 nm.

  Next, the antioxidant insulating film 10 and the first interlayer insulating film 11 are patterned by photolithography and etching to form a contact hole with a diameter of, for example, 0.25 μm on the source / drain region 8.

  A tungsten plug 12 electrically connected to the source / drain region 8 is formed in the contact hole. For example, by filling a tungsten film by a CVD method through an adhesion film (glue film) in which a Ti film having a thickness of 30 nm and a TiN film having a thickness of 20 nm are stacked, and removing an excess tungsten film by a CMP method, A tungsten plug 12 is formed. The tungsten plug 12 has a film thickness of about 300 nm on the flat surface of the first interlayer insulating film 11.

  Next, in order to prevent the tungsten plug 12 from being oxidized by thermal annealing in an oxygen atmosphere, a second interlayer insulating film 20 is formed. The second interlayer insulating film 20 is formed, for example, by depositing a SiON film with a thickness of about 100 nm and further depositing a TEOS film with a thickness of about 130 nm.

  Next, the second interlayer insulating film 20 is degassed by annealing the second interlayer insulating film 20 for 30 minutes in a nitrogen atmosphere at a substrate temperature of 650 ° C.

Further, an alumina (Al ₂ O ₃ ) film is formed on the second interlayer insulating film 20 as the lower electrode adhesion film 21 by sputtering. The film thickness of the lower electrode adhesion film 21 is, for example, about 20 nm. Thereafter, the lower electrode adhesion film 21 is oxidized in an oxygen atmosphere at 650 ° C. by RTA (Rapid Thermal Anneal). The lower electrode adhesion film 21 is formed to improve adhesion between the lower electrode film (lower electrode layer) 22 and the second interlayer insulating film 20.

Next, a platinum film is formed as the lower electrode film 22 on the lower electrode adhesion film 21 by sputtering. The film thickness of the lower electrode film 22 is, for example, about 75 to 150 nm. Instead of the platinum film, a single-layer film of any of an iridium film, a ruthenium film, a ruthenium oxide (RuO ₂ ) film, and a SrRuO ₃ film, or a laminated film thereof may be used as the lower electrode film 22. Since the lower electrode adhesion film 21 is formed before the lower electrode film 22 is formed, the adhesion between the lower electrode film 22 and the second interlayer insulating film 20 is enhanced.

  Next, RTA is performed on the silicon substrate 1 in an inert gas atmosphere at 650 ° C. (for example, in an Ar gas atmosphere) to make the crystallinity of the lower electrode film 22 uniform, The adhesion between the electrode adhesion film 21 and the second interlayer insulating film 20 is improved. Here, an example of performing RTA is shown, but RTA may not be performed.

Next, PZT (Pb (Zr _X , Ti _1-X ) O ₃ (0 ≦ x) is formed on the lower electrode film 22 as the first ferroelectric film 23 by RF (Radio Frequency) sputtering using a PZT target.
≦ 1)) A film is formed. The film thickness of the first ferroelectric film 23 is, for example, about 50 to 150 nm. The temperature of the silicon substrate 1 during film formation is preferably 100 ° C. or lower. For example, the film formation is performed with the temperature of the silicon substrate 1 set to 50 ° C. When the film forming temperature is 100 ° C. or higher, the PZT (101) and (100) plane orientations in the PZT film become large and the (111) plane orientation becomes weak, so that the capacitor characteristics are deteriorated. On the other hand, if the film forming temperature is too low, the temperature of the silicon substrate 1 becomes very unstable, which is disadvantageous for mass production.

The first ferroelectric film 23 is not limited to the PZT film, and a material obtained by adding any of Ca, Sr, La, Nb, Ta, Ir, and W to the PZT film is used as the first ferroelectric film 23. Also good. Furthermore, Bi layered compounds such as (Bi _1-X R _X ) Ti ₃ O ₁₂ (R is a rare earth element 0 <x <1), SrBi ₂ Ta ₂ O ₉ (SBT), and SrBi ₄ Ti ₄ O ₁₅ are used. Alternatively, the first ferroelectric film 23 may be used. Further, the method for forming the first ferroelectric film 23 is not limited to the sputtering method, and the first ferroelectric film 23 may be formed by a sol-gel method or a MOCVD (Metal Organic CVD) method.

  The crystallinity of the ferroelectric film depends on the crystallizing method of the ferroelectric film, but strongly depends on the crystallinity of the lower electrode film 22 and the surface of the lower electrode film 22. Crystals of the ferroelectric film grow from between the crystal grains of the lower electrode film 22. Accordingly, the crystal uniformity of the lower electrode film 22 affects the crystallinity of the ferroelectric film. On the other hand, if the composition of the ferroelectric film shifts to the interface between the lower electrode film 22 and the ferroelectric film, the crystallinity of the ferroelectric film also deteriorates. When a compound such as SRO, LSCO, or LNO having a perovskite structure is formed on the surface of the lower electrode film 22, the ferroelectric film grows as it is.

Further, when a general noble metal oxide film is formed on the lower electrode film 22, since these noble metal oxides are not oriented in the (111) plane, the crystallinity of the ferroelectric film also deteriorates. Generally, a Pt lower electrode is used in a ferroelectric film formed by sputtering or sol-gel method. In a ferroelectric film formed by the MOCVD method, an Ir lower electrode is used. When the oxide lower electrode is used, a ferroelectric film is formed by reducing the noble metal by the oxide. For example, a ferroelectric film is formed by MOCVD using an IrO _X / Ir lower electrode. Actually, immediately before the formation of the ferroelectric film, IrO _X reduces Ir, and the PZT film is attracted and grown on the Ir crystal grains. When the oxide lower electrode is used, oxygen deficiency at the capacitor ferroelectric and electrode interface is reduced, and fatigue characteristics are improved.

  The first ferroelectric film 23 formed by sputtering is not crystallized immediately after the film formation and is in an amorphous state and has poor dielectric properties. Therefore, in order to crystallize the first ferroelectric film 23, the first ferroelectric film 23 is subjected to crystallization annealing. The crystallization annealing is performed by RTA in an oxygen-containing atmosphere, for example, an oxygen and argon atmosphere adjusted to have an oxygen concentration of 2.0%, the substrate temperature is set to 580 to 610 ° C. (for example, 600 ° C.), and the processing is performed. The time is 90 seconds. As a result, the first ferroelectric film 23 is crystallized, and a large number of PZT crystal grains are formed in the film.

  In the case where the first ferroelectric film 23 is formed by the MOCVD method, the first ferroelectric film 23 is crystallized at the time of film formation, so that the above crystallization annealing is not necessary, but the PZT film In order to remove residual moisture on the surface, heat treatment may be performed in an oxygen atmosphere.

  Next, an amorphous PZT film having a thickness of 40 nm or less is formed on the first ferroelectric film 23 as the second ferroelectric film 24 by RF sputtering. Here, an example in which the second ferroelectric film 24 is formed on the first ferroelectric film 23 is shown, but the second ferroelectric film 24 is not formed on the first ferroelectric film 23. You may do it. The temperature of the silicon substrate 1 at the time of forming the second ferroelectric film 24 is preferably 100 ° C. or less. For example, the second ferroelectric film 24 may be formed by setting the temperature of the silicon substrate 1 to 50 ° C.

The second ferroelectric film 24 is not limited to the PZT film, and a material obtained by adding any of Ca, Sr, La, Nb, Ta, Ir, and W to the PZT film is used as the second ferroelectric film 24. Also good. Furthermore, Bi layered compounds such as (Bi _1-X R _X ) Ti ₃ O ₁₂ (R is a rare earth element 0 <x <1), SrBi ₂ Ta ₂ O ₉ (SBT), and SrBi ₄ Ti ₄ O ₁₅ are used. Alternatively, the second ferroelectric film 24 may be used. In this case, the first ferroelectric film 23 and the second ferroelectric film 24 are preferably made of the same material.

  Next, an iridium oxide film is formed as a first upper electrode film (first upper electrode layer) 30 on the second ferroelectric film 24 by sputtering. The film thickness of the first upper electrode film 30 is, for example, about 25 to 50 nm.

There are the following three methods for forming the first upper electrode film 30. (1) When forming at low temperature (100 ° C. or lower), the second ferroelectric film 24 and the first upper electrode film 30 are continuously formed. That is, the second ferroelectric film 24 is formed, and the silicon substrate 1 is transferred to the first upper electrode (IrO _x ) chamber so as not to be exposed to the atmosphere, and the first upper electrode film 30 is formed.

(2) When the second ferroelectric film 24 and the first upper electrode film 30 cannot be continuously formed by low-temperature film formation, the silicon substrate 1 is subjected to heat treatment so as not to be exposed to the atmosphere. An electrode film 30 is formed. For example, in a reduced-pressure atmosphere having a pressure of about 5.0 × 10 ⁻⁶ Pa, the substrate temperature is set to 100 to 350 ° C., for example, 150 ° C., and is performed for 60 seconds. The first upper electrode film 30 is formed by transporting to the first upper electrode chamber so as not to be exposed to the atmosphere.

  (3) When a high temperature film is formed (100 ° C. or higher), the second ferroelectric film 24 is formed, and the first upper electrode film 30 is formed. In this case, the silicon substrate 1 may or may not be exposed to the atmosphere once.

  The three types of formation methods of the first upper electrode film 30 control the interface between the second ferroelectric film 24 and the first upper electrode film 30, and thus have a great influence on the electrical characteristics of the capacitor.

  Next, steps required until a sectional structure shown in FIG. First, for example, a photoresist film is formed on the first upper electrode film 30 by spin coating. Then, the photoresist film is patterned by photolithography and etching to form a first resist 31 that covers a region where the first capacitor is to be formed. The first capacitor is, for example, a smoothing capacitor, a high breakdown voltage capacitor, or a high breakdown voltage smoothing capacitor. In the first embodiment, a region where the first capacitor is formed is also referred to as a first capacitor region.

Etching is performed using the first resist 31 as a mask. Etching conditions include an atmosphere of a mixed gas of Cl ₂ and Ar (for example, a Cl supply flow rate of 12 sccm, an Ar supply flow rate of 48 sccm, Source = 2000 W, Bias = 1500 W, a pressure of 0.7 Pa, and an etching time of 6 to 6 Etching is performed in 10 seconds. For example, when the IrO _X upper electrode is 50 nm, etching may be performed for about 10 seconds.

  By etching, the first upper electrode film 30 other than the first capacitor region is removed, and the second ferroelectric film 24 other than the first capacitor region is shaved. In this case, the second ferroelectric film 24 other than the first capacitor region may be completely removed by etching. Further, the second ferroelectric film 24 may be left outside the first capacitor region by removing the second ferroelectric film 24 other than the first capacitor region by 10 to 20 nm by etching. When the second ferroelectric film 24 is further etched, the above mixed gas ratio may be finely adjusted to extend the etching time. In this embodiment, the second ferroelectric film 24 other than the first capacitor region is completely removed.

  Thereafter, the first resist 31 in the first capacitor region is removed. FIG. 3 is a cross-sectional view of the semiconductor device when the first resist 31 in the first capacitor region is removed.

Next, a second upper electrode film (second upper electrode layer) is formed on the first upper electrode film 30 in the first capacitor region and on the first ferroelectric film 23 other than the first capacitor region by sputtering. An iridium oxide film is formed as 33. The film thickness of the second upper electrode film 33 is, for example, about 15 to 40 nm. The formation of the second upper electrode film 33 is preferably performed by the method (3) of the method for forming the first upper electrode film 30 described above. This is because when the second upper electrode film 33 is formed at a high temperature, impurities on the surface of the silicon substrate 1 can be removed, and the interface between the second upper electrode film 33 and the first ferroelectric film 23 can be improved. For example, as the film formation conditions, the substrate temperature is 300 ° C., the Ar supply flow rate is 140 sccm, the O ₂ supply flow rate is 60 sccm, 1 kW power, 5 to 10 seconds,
An upper electrode film 33 is formed. FIG. 4 is a cross-sectional view of the semiconductor device when the second upper electrode film 33 is formed. Thereafter, in the oxygen-containing atmosphere, the first ferroelectric film 23 and the second ferroelectric film 24 in the first capacitor region. Alternatively, crystallization annealing is performed on the first ferroelectric film 23 in the region where the second capacitor is formed. The second capacitor is, for example, a memory element capacitor. In the first embodiment, a region where the second capacitor is formed is also referred to as a second capacitor region.

  By performing crystallization annealing, the amorphous second ferroelectric film 24 can be crystallized and the crystallinity of the first ferroelectric film 23 can be enhanced. Further, by performing crystallization annealing, the interface between the first ferroelectric film 23 and the second ferroelectric film 24 can be improved. Although the annealing conditions are not particularly limited, in this embodiment, the substrate temperature is 720 ° C. and the processing time is 120 seconds. Further, as an oxygen-containing atmosphere in which annealing is performed, a mixed atmosphere of oxygen gas and argon gas whose oxygen concentration is adjusted to 1% is used.

As described above, the first upper electrode film 30 and the second upper electrode film 33 are formed in the first capacitor region, and the second upper electrode film 33 is formed in the second capacitor region. 2 The ferroelectric film 24 is crystallized. Thereby, iridium oxide as the first upper electrode film 30 and iridium oxide as the second upper electrode film 33 can be prevented from entering the crystal grain boundary of the second ferroelectric film 24. Further, it is possible to suppress the formation of a leak path in the second ferroelectric film 24 due to iridium oxide. Further, by performing crystallization annealing, oxygen is supplied to the second ferroelectric film 24 through the first upper electrode film 30 and the second upper electrode film 33, and oxygen vacancies in the second ferroelectric film 24 are obtained. There is also an advantage that is compensated.

  In order to obtain such an advantage, the film thickness of the first upper electrode film 30 and the second upper electrode film 33 is reduced so that oxygen can easily pass through the first upper electrode film 30 and the second upper electrode film 33. It is preferable. For example, the film thickness of the first upper electrode film 30 and the second upper electrode film 33 is preferably 10 to 100 nm.

  However, if the first upper electrode film 30 and the second upper electrode film 33 are formed thinly on the second ferroelectric film 24, damage in a subsequent etching process or the like, and the first upper electrode film 30 alone can absorb it. Accordingly, the first ferroelectric film 23 and the second dielectric film may be deteriorated. Therefore, in the next step, an iridium oxide film is formed as a third upper electrode film (third upper electrode layer) 34 on the second upper electrode film 33 by sputtering. The film thickness of the third upper electrode film 34 is, for example, about 200 nm. The third upper electrode film 34 functions as a conductive protective film for protecting the first ferroelectric film 23 and the second ferroelectric film 24. FIG. 5 is a cross-sectional view of the semiconductor device when the third upper electrode film 34 is formed.

Then, after performing back surface cleaning, a TiN film is formed as the first protective film 35 on the third upper electrode film 34 by sputtering. The film thickness of the first protective film 35 is, for example, 34 nm. The first protective film 35 functions as a suppression film that suppresses permeation of the reducing substance. For example, the first protective film 35 is formed in a mixed gas atmosphere using a Ti target at a substrate temperature of 200 ° C., an Ar supply amount of 50 sccm, and an N ₂ supply amount of 90 sccm.

The first protective film 35 can also be used as a hard mask for the first upper electrode film 30. The first protective film 35 is not limited to a TiN film. For example, a material selected from TaN, TiON, TiO _X , TaO _X , TaON, TiAlO _X , TaAlO _X , TiAlON, TaAlON, TiSiON, TaSiON, TiSiO _X , TaSiO _X , AlO _X , ZrO _{X and the} like is used as the first protective film. 35 may be used.

  Next, a photoresist film is formed on the first protective film 35 by, eg, spin coating. Then, the photoresist film is patterned by photolithography. In this case, the photoresist film is patterned so that the second resist 36A is formed in the first capacitor region and the second resist 36B is formed in the second capacitor region. FIG. 6 is a cross-sectional view of the semiconductor device when the second resist 36A is formed in the first capacitor region and the second resist 36B is formed in the second capacitor region.

  Then, anisotropic etching is performed on the first upper electrode film 30, the second upper electrode film 33, the third upper electrode film 34, and the first protective film 35 using the second resists 36A and 36B as a mask, The first upper electrode film 30, the second upper electrode film 33, the third upper electrode film 34, and the first protective film 35 are patterned. Since the first protective film 35 functions as a hard mask, the first upper electrode film 30, the second upper electrode film 33, the third upper electrode film 34, and the first protective film 35 are cleaned by controlling the end point. It can be etched.

By etching the first upper electrode film 30, the second upper electrode film 33, the third upper electrode film 34, and the first protective film 35, an upper electrode 37 is formed in the first capacitor region, and the upper portion is formed in the second capacitor region. An electrode 38 is formed. FIG. 7 is a cross-sectional view of the semiconductor device when the upper electrode 37 and the upper electrode 38 are formed. As shown in FIG. 7, the upper electrode 37 includes a first upper electrode film 30, a second upper electrode film 33, and a third upper electrode film 34, and the upper electrode 38 includes a second upper electrode film 33 and a third upper electrode film 34. Since the upper electrode film 34 is provided, the upper electrode 37 and the upper electrode 38 have different heights.

  Thereafter, the second resists 36A and 36B are removed. Then, the first protective film 35 is removed by dry etching. Next, heat treatment is performed on the silicon substrate 1 in an oxygen-containing atmosphere. The temperature of the heat treatment is 600 to 700 ° C. In the first embodiment, heat treatment is performed at 650 ° C. for 40 minutes. Since this heat treatment recovers damage received by the first ferroelectric film 23 and the second ferroelectric film 24 during the process, such heat treatment is also called recovery annealing.

  Next, a photoresist film is formed above the silicon substrate 1 by, eg, spin coating. Then, the photoresist film is patterned by photolithography. In this case, the photoresist film is patterned so that the third resist 39A is formed in the first capacitor region and the third resist 39B is formed in the second capacitor region.

  Next, anisotropic etching is performed on the first ferroelectric film 23 and the second ferroelectric film 24 using the third resists 39A and 39B as a mask, so that the first ferroelectric film 23 and the second ferroelectric film 24 are subjected to anisotropic etching. The dielectric film 24 is patterned. By controlling the end point, it is possible to simultaneously etch the first ferroelectric film 23 and the second ferroelectric film 24 in the first capacitor region and the first ferroelectric film 23 in the second capacitor region. It is. FIG. 8 is a cross-sectional view of the semiconductor device when the first ferroelectric film 23 and the second ferroelectric film 24 in the first capacitor region and the first ferroelectric film 23 in the second capacitor region are etched. is there.

  Thereafter, the third resists 39A and 39B are removed. Then, heat treatment is performed in an oxygen atmosphere, for example, at 300 ° C. to 400 ° C. for 30 minutes to 120 minutes. Next, an aluminum oxide film is formed as the second protective film 40 above the silicon substrate 1 by, for example, sputtering or CVD. The film thickness of the aluminum oxide film is, for example, 20 to 50 nm. Next, heat treatment is performed in an oxygen atmosphere, for example, at 400 to 600 ° C. for 30 to 120 minutes.

  Then, for example, a photoresist film is formed above the silicon substrate 1 by spin coating. Next, the photoresist film is patterned by photolithography. In this case, the photoresist film is patterned so that the fourth resist 41 covering the first capacitor region and the second capacitor region is formed. Subsequently, anisotropic etching is performed on the lower electrode film 22 and the second protective film 40 using the fourth resist 41 as a mask, and the lower electrode film 22 and the second protective film 40 are patterned. By patterning the lower electrode film 22 and the second protective film 40, the lower electrode 42 is formed in the first capacitor region and the second capacitor region. FIG. 9 is a cross-sectional view of the semiconductor device when the lower electrode 42 is formed in the first capacitor region and the second capacitor region.

  A first capacitor having a lower electrode 42, a first ferroelectric film 23, a second ferroelectric film 24, and an upper electrode 37 is formed above the silicon substrate 1. A second capacitor having a lower electrode 42, a first ferroelectric film 23, and an upper electrode 38 is formed above the silicon substrate 1. The second protective film 40 remains on the lower electrode 42 so as to cover the first ferroelectric film 23, the second ferroelectric film 24, the upper electrode 37 and the upper electrode 38.

Thereafter, the fourth resist 41 is removed. Next, heat treatment is performed in an oxygen atmosphere, for example, at 300 ° C. to 400 ° C. for 30 minutes to 120 minutes. Next, an aluminum oxide film is formed as the third protective film 43 above the silicon substrate 1 by, for example, sputtering or CVD.
The film thickness of the third protective film 43 is, for example, 20 nm. FIG. 10 is a cross-sectional view of the semiconductor device when the third protective film 43 is formed.

  Then, heat treatment is performed in an oxygen atmosphere, for example, at 500 ° C. to 700 ° C. for 30 minutes to 120 minutes. As a result, oxygen is supplied to the first ferroelectric film 23 and the second ferroelectric film 24, and the electrical characteristics of the first capacitor and the second capacitor are recovered.

  Next, a silicon oxide film is formed as the third interlayer insulating film 44 on the third protective film 43 by, for example, plasma TEOSCVD. The film thickness of the third interlayer insulating film 44 is 1400 nm, for example. Then, the surface of the third interlayer insulating film 44 is planarized by, eg, CMP.

Next, heat treatment is performed, for example, at 350 ° C. for 2 minutes in a plasma atmosphere generated using N ₂ O gas or N ₂ gas. As a result of the heat treatment, moisture in the third interlayer insulating film 44 is removed, the film quality of the third interlayer insulating film 44 changes, and moisture hardly enters the third interlayer insulating film 44. Further, by this heat treatment, the surface of the third interlayer insulating film 44 is nitrided, and a SiON film is formed on the surface of the third interlayer insulating film 44.

  Then, for example, an aluminum oxide film is formed as the fourth protective film 45 on the third interlayer insulating film 44 by sputtering or CVD. The film thickness of the fourth protective film 45 is, for example, 20 to 50 nm. Next, a silicon oxide film is formed as the fourth interlayer insulating film 46 on the fourth protective film 45 by, for example, plasma TEOSCVD. The film thickness of the fourth interlayer insulating film 46 is, for example, 300 nm.

  Next, a contact hole 50A reaching the upper electrode 37 is formed in the second protective film 40, the third protective film 43, the third interlayer insulating film 44, the fourth protective film 45, and the fourth interlayer insulating film 46 by photolithography and etching. Form. A contact hole 50B reaching the upper electrode 38 is formed in the second protective film 40, the third protective film 43, the third interlayer insulating film 44, the fourth protective film 45, and the fourth interlayer insulating film 46 by photolithography and etching. Form. Further, a contact hole 50C reaching the lower electrode 42 is formed in the second protective film 40, the third protective film 43, the third interlayer insulating film 44, the fourth protective film 45, and the fourth interlayer insulating film 46 by photolithography and etching. Form.

  Then, heat treatment is performed in an oxygen atmosphere, for example, at 400 ° C. to 600 ° C. for 30 minutes to 120 minutes. As a result, oxygen is supplied to the first ferroelectric film 23 and the second ferroelectric film 24, and the electrical characteristics of the first capacitor and the second capacitor are recovered. Note that this heat treatment may be performed not in an oxygen atmosphere but in an ozone atmosphere. Even when heat treatment is performed in an ozone atmosphere, oxygen is supplied to the first ferroelectric film 23 and the second ferroelectric film 24 to restore the electrical characteristics of the first capacitor and the second capacitor. .

  Next, a contact hole 50D reaching the tungsten plug 12 to the second protective film 40, the third protective film 43, the third interlayer insulating film 44, the fourth protective film 45, and the fourth interlayer insulating film 46 by photolithography and etching. Form. FIG. 11 is a cross-sectional view of the semiconductor device when the contact holes 50A, 50B, 50C, and 50D are formed.

  Next, the interlayer insulating film is degassed by performing an annealing process. The annealing process is preferably performed in an inert gas atmosphere or in a vacuum. Then, surface treatment (RF etching) is performed on the inner wall surfaces of the contact holes 50A, 50B, 50C, and 50D.

Next, a TiN film is formed as a conductive barrier film in the contact holes 50A, 50B, 50C and 50D, for example, by sputtering. The film thickness of the TiN film is, for example, 50 to 150 nm. For example, a TiN film is formed at 200 ° C. in a mixed atmosphere of Ar (supply amount 50 sccm) and N ₂ (supply amount 90 sccm) using a Ti target in an ENDURA SIP chamber with good coverage. The conductive barrier film is not limited to the TiN film. TiN, TaN, CrN, HfN, ZrN, TiAlN, TaAlN, TiSiN, TaSiN, CrAlN, HfAlN, ZrAlN, TiON, TaON, CrON, HfON, ZrON, TiAlON, TaAlON, CrAlON, HfArON, ZrAlON, TiSiON, TaSiON, TaSiON At least one film selected from the group consisting of Ru, IrO _X , RuO _X , Ti / TiN, Ti / TaN, Ta / TiN, and Ta / TaN may be used as the conductive barrier film.

  Next, a tungsten film is formed in the contact holes 50A, 50B, 50C, and 50D by, for example, the CVD method. The film thickness of the tungsten film is, for example, 300 nm. Instead of the tungsten film, a copper film may be formed in the contact holes 50A, 50B, 50C and 50D. Alternatively, a glue film may be formed in the contact holes 50A, 50B, 50C, and 50D, tungsten or polysilicon is partially embedded on the glue film, and a copper film may be further laminated.

  Then, for example, the tungsten film and the conductive barrier film are polished by CMP until the surface of the fourth interlayer insulating film 46 is exposed. As a result, the conductor plugs 51A, 51B, 51C and 51D containing tungsten are embedded in the contact holes 50A, 50B, 50C and 50D, respectively. Next, for example, plasma cleaning using argon gas is performed. As a result, the natural oxide film and the like existing on the surfaces of the conductor plugs 51A, 51B, 51C and 51D are removed.

  Next, for example, by sputtering, on the fourth interlayer insulating film 46, for example, a TiN film having a thickness of 50 nm, an AlCu alloy film having a thickness of 550 nm, a Ti film having a thickness of 5 nm, for example, Then, a TiN film having a thickness of 50 nm is sequentially laminated. As a result, a conductor film having a TiN film, an AlCu alloy film, a Ti film, and a TiN film is formed on the fourth interlayer insulating film 46.

  Then, the conductor film is patterned by photolithography and dry etching. As a result, the first metal wiring layer 52 is formed. That is, a wiring electrically connected to the upper electrode 37 via the conductor plug 51A and a wiring electrically connected to the upper electrode 38 via the conductor plug 51B are formed. In addition, a wiring electrically connected to the lower electrode 42 through the conductor plug 51C and a wiring electrically connected to the tungsten plug 12 through the conductor plug 51D are formed. FIG. 12 is a cross-sectional view of the semiconductor device when the conductive plugs 51A, 51B, 51C, 51D and the metal wiring layer 52 are formed.

  Thereafter, the basic structure of the semiconductor device according to the present embodiment is completed when three-layer wiring or five-layer wiring is performed by a film forming method or patterning method substantially the same as the formation of the first metal wiring layer 52. That is, a semiconductor device having a first capacitor and a second capacitor is manufactured.

With respect to the ferroelectric capacitor formed by the above method, the characteristics of the ferroelectric capacitor were measured after the process out. The results of measuring the characteristics of a total of five types of ferroelectric capacitors are shown in FIGS. In the five types of ferroelectric capacitors, the thickness of the first ferroelectric film 23 is 90 nm, and the thickness of the second ferroelectric film 24 is 0 nm, 10 nm, 15 nm, 20 nm, and 30 mm, respectively. In FIG. 13 to FIG. 15, the thickness of the first ferroelectric film 23 is 90 nm and the thickness of the second ferroelectric film 24 is 0 nm (the second ferroelectric film 24 is formed). State). 90 + 10 nm in FIGS. 13 to 15 indicates that the film thickness of the first ferroelectric film 23 is 90 nm and the film thickness of the second ferroelectric film 24 is 10 nm. 90 + 15 nm in FIGS. 13 to 15 indicates that the film thickness of the first ferroelectric film 23 is 90 nm and the film thickness of the second ferroelectric film 24 is 15 nm. 90 + 20 nm in FIGS. 13 to 15 indicates that the film thickness of the first ferroelectric film 23 is 90 nm and the film thickness of the second ferroelectric film 24 is 20 nm. 90 + 30 nm in FIGS. 13 to 15 indicates that the film thickness of the first ferroelectric film 23 is 90 nm and the film thickness of the second ferroelectric film 24 is 30 nm.

  A monitor check was performed after the completion of the 5-layer wiring. In this experiment, two types of samples, a discrete and a cell array, were prepared, the relationship between the switching charge amount (inverted charge amount) Qsw of the cell array and the applied voltage (IV characteristics), the discrete leakage current and the applied voltage. (I-V characteristics), fatigue characteristics of the cell array, and imprint measurement. In discrete samples, discrete ferroelectric capacitors are often used not in memory cells but in logic circuits such as RF circuits and smoothing circuits. In the discrete sample, the planar shape of the ferroelectric capacitor was a square of 50 μm × 50 μm. In the cell array sample, 1736 rectangular ferroelectric capacitors having a planar shape of 1.00 μm × 1.44 μm were arranged.

  FIG. 13A is a diagram illustrating a Qtv characteristic of a capacitor for a sample of a cell array. The horizontal axis in FIG. 13A indicates the applied voltage, and the vertical axis in FIG. 13A indicates the switching charge amount (inversion charge amount). As shown in FIG. 13A, under the condition of 90 + 15 nm (when the thickness of the second ferroelectric film 24 is 15 nm), the rise of Qtv is the fastest and the saturation Qsw is the largest. Further, as shown in FIG. 13A, the rise of Qtv is delayed in the order of the conditions of 90 + 20 nm, 90 + 10 nm, 90 + 30 nm, and 90 + 0 nm. From this result, when used as a memory element for low-voltage operation, it can be said that the condition of 90 + 15 nm, that is, the thickness of the second ferroelectric film 24 is preferably 15 nm.

  FIG. 13B is a diagram illustrating the IV characteristics of a capacitor for a discrete sample. The horizontal axis in FIG. 13B indicates the applied voltage, and the vertical axis in FIG. 13B indicates the leakage current of the capacitor. The film thickness of the second ferroelectric film 24 greatly affects the leakage current of the capacitor. As shown in FIG. 13B, when the second ferroelectric film 24 is thickened, the leakage current of the capacitor can be reduced. As the second ferroelectric film 24 becomes thicker, the leakage current of the capacitor decreases. Therefore, when a high voltage smoothing capacitor is used for the RF circuit or the smoothing circuit, it is preferable to increase the thickness of the second ferroelectric film 24. However, if the thickness of the second ferroelectric film 24 is too thick, the crystallinity of the second ferroelectric film 24 may be deteriorated in the heat treatment after the second upper electrode film 33 is formed. The film thickness of the second ferroelectric film 24 is preferably 40 nm or less.

  FIG. 14A is a diagram showing fatigue characteristics of capacitors for a sample of a cell array. The fatigue characteristic is a phenomenon in which the remanent polarization gradually decreases as the polarization inversion is repeated. The horizontal axis in FIG. 12A indicates the stress cycle, and the vertical axis in FIG. 12A indicates the switching charge amount. The stress cycle is the number of times the stress voltage is applied. Since the number of times the ferroelectric memory is rewritten is limited by a fatigue phenomenon, it is preferable to improve the fatigue resistance characteristics of the capacitor. The measurement conditions are as follows. The measurement temperature was 90 ° C., the stress voltage was 5.25 V, the frequency was 2 MHz, the measurement voltage was 1.8 V, and the stress cycle was up to 1E10 times.

FIG. 14B is a diagram illustrating a loss amount of the switching charge amount (inverted charge amount) of each capacitor after performing a stress cycle of 1E10 times at a stress voltage of 5.25V. According to the results shown in FIGS. 14A and 14B, when the thickness of the second ferroelectric film 24 is increased, the fatigue resistance characteristics of the capacitor are also deteriorated. When the film thickness of the second ferroelectric film 24 is 0 nm (when the second ferroelectric film 24 is not formed), and when the film thickness of the second ferroelectric film 24 is 15 nm Then, the fatigue resistance is at the same level. When the thickness of the second ferroelectric film 24 is 10 nm, the fatigue resistance characteristic of the cell array capacitor is the best.

  Next, the imprint resistance of the cell array capacitor was evaluated. Imprint is a phenomenon in which data written in a memory cell is fixed and difficult to reverse. If the capacitor is left in a state where it is polarized in one direction for a long time, the state becomes stable and polarization inversion hardly occurs. Even if the polarization is reversed in this state, it is greatly depolarized and approaches the original polarization state. As the imprint progresses, the hysteresis loop undergoes a voltage shift. The direction of the shift is opposite to the polarization direction, that is, when it is left after being polarized by a positive voltage, it shifts in the negative voltage direction.

  Imprinting is accelerated by temperature, and the measurement is usually carried out at about 150 ° C. If the remanent polarization becomes small due to the temperature being too high, the imprint depends on the direction of the remanent polarization. Imprinting also proceeds by applying a DC bias or a monopolar continuous pulse. The direction of the voltage shift is opposite to the applied voltage as in the case of heat. The case of accelerating with temperature without applying voltage is called static (thermal) imprint, and the case of applying voltage is called dynamic imprint. The retention characteristic of remanent polarization in the imprinted direction is temporarily improved because the state becomes stable. However, when the voltage shift is increased, the remanent polarization itself is decreased, and the data retention capability is eventually reduced.

  As a method of evaluating the influence of depolarization on memory operation due to imprinting, the measurement procedure and results of the Q123 test will be shown and the influence will be described. In the Q123 test, measurement is performed by simulating the memory operation of the 2T2C method. Measurement is performed using one memory cell in the 2T2C system. Data is written so that the polarization directions of Cap-A and Cap-B are opposite. Cap-A and Cap-B are two adjacent capacitors (Capacitor-A, Capacitor-B). In the Q123 test, a signal difference due to the presence or absence of polarization inversion is measured using two capacitors having different polarization directions.

After writing to Cap-A and Cap-B at + 1.8V and -1.8V, respectively ("0" writing), hold at 150 ° C. for acceleration. During holding, no voltage is applied to the capacitor (open state). After holding at high temperature for 168, 336, 504, and 1008 hours, reading is performed by applying a pulse of +1.8 V to each (“0” reading). The difference between the polarization change amounts of Cap-A and Cap-B is Q2. Cap-A originally has a direction in which the remanent polarization does not reverse, but a polarization change corresponding to the depolarization during holding at high temperature appears at the time of reading. Conversely, the amount of polarization reversal of Cap-B decreases due to depolarization. Q2 indicates how much residual polarization remains without being depolarized during baking and can be used for data reading, that is, a retention characteristic (also referred to as Qss-same state).

Following the measurement of Q2, write data opposite to that before baking ("1" write), that is, apply -1.8V to Cap-A and + 1.8V to Cap-B and leave for 30 seconds. To do. In a state where the imprint has progressed, a large depolarization occurs while the polarization tries to return to the original state. After leaving for 30 seconds, a pulse of +1.8 V is applied again to perform reading (“1” reading), and the difference in polarization change between Cap-A and Cap-B is defined as Q3. Q3 represents how much polarization inverted after imprinting remains after depolarization and can be used for data reading (also referred to as Qos: opposite state). Imprint progresses with bake time, and Q3 decreases. Q3 indicates the imprint characteristic of the capacitor. Further, the slope between Q3 and the high temperature holding time is referred to as Q3-Rate. When Q3-Rate is low, the capacitor has good imprint resistance.

FIG. 15A is a diagram illustrating a Q3 characteristic of a capacitor for a sample of a cell array. FIG.
FIG. 5B is a diagram illustrating Q3-Rate. According to the results shown in FIGS. 15A and 15B, when the thickness of the second ferroelectric film 24 is increased, the deterioration of Q3 is accelerated and Q3-Rate is also increased. When the film thickness of the second ferroelectric film 24 is 0 nm (when the second ferroelectric film 24 is not formed), Q3-Rate is the lowest. From this result, in order to improve the imprint resistance of the memory element capacitor, it is preferable to make the second ferroelectric film 24 thin.

  From the above experimental results, the capacitor has a trade-off between Qtv, IV characteristics, fatigue resistance, and imprint resistance. When used as a capacitor for a memory element, it is preferable that Qtv rises quickly, saturation Qsw is high, fatigue loss is low, and Q3-Rate is low because the influence of the capacitor leakage current is small. Therefore, the film thickness of the second ferroelectric film 24 of the memory element capacitor is preferably 0 to 20 nm.

  When the results shown in FIGS. 13 to 15 are combined, the film thickness of the second ferroelectric film 24 of the memory element capacitor is more preferably 10 to 15 nm. On the other hand, since the high withstand voltage smoothing capacitor of the RF circuit or the smoothing circuit preferably has a low capacitor leakage current (high withstand voltage performance improvement) and a stable capacitance, the film thickness of the second ferroelectric film 24 is It is preferable that it is 20 nm or more. As described above, since the thickness of the second ferroelectric film 24 is preferably 40 nm or less, the thickness of the second ferroelectric film 24 of the high breakdown voltage smoothing capacitor is 20 to 40 nm. Is preferable, and 30 nm is more preferable.

<Modification>
A modification of the first embodiment will be described. The first to seventh modifications described below may be combined as much as possible.

  FIG. 16 is a cross-sectional view of a semiconductor device according to a first modification of the first embodiment. In the first modification, the first capacitor does not include the second ferroelectric film 24. That is, in the first modification, the second ferroelectric film 24 is not formed on the first ferroelectric film 23 of the first capacitor. In the manufacturing process of the semiconductor device in the first modification, after the first ferroelectric film 23 is formed, the first ferroelectric 23 is crystallized by heat treatment to form the first upper electrode film 30, and the first A resist is formed in one capacitor region, etching is performed using the resist as a mask, the first upper electrode film 30 of the second capacitor is completely etched, and the thickness of the first ferroelectric film 23 is reduced.

  Therefore, the film thickness of the first ferroelectric film 23 of the first capacitor is different from the film thickness of the second ferroelectric film 23 of the second capacitor. By controlling the etching time, it is possible to adjust the film thickness of the first ferroelectric film 23 of the second capacitor. In the first modification, the first ferroelectric film 23 is formed with a large thickness, and the first ferroelectric film 23 of the second capacitor is thinned by etching, so that the second The formation of the ferroelectric film 24 is omitted. In the first modification, the first upper electrode film 30 and the second upper electrode film 33 have different film formation conditions.

  FIG. 17 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment. In the second modification, the first capacitor does not include the second ferroelectric film 24. That is, in the second modification, the second ferroelectric film 24 is not formed on the first ferroelectric film 23 of the first capacitor. The difference between the film thickness of the first ferroelectric film 23 of the first capacitor and the film thickness of the second ferroelectric film 23 of the second capacitor is the same as in the first modification.

In the second modification, the first capacitor does not include the second upper electrode film 33. That is, in the second modification, the second upper electrode film 33 is formed on the first upper electrode film 30 of the first capacitor.
Is not formed. In the second modification, the second upper electrode film 33 is formed under the same film formation conditions as the first upper electrode film 30. Therefore, a thick first upper electrode film 30 is formed on the first ferroelectric film 23 of the first capacitor. That is, in the second modification, the first upper electrode film 30 and the second upper electrode film 33 are formed as one electrode film on the first ferroelectric film 23 of the first capacitor. The second upper electrode film 33 is formed on the first upper electrode film 30 in the first capacitor region by forming the second upper electrode film 33 under film formation conditions different from the film formation conditions of the first upper electrode film 30. 33 may be removed.

  FIG. 18 is a cross-sectional view of a semiconductor device according to a third modification of the first embodiment. In the third modification, the second ferroelectric film 24 is not formed on the first ferroelectric film 23. The difference between the film thickness of the first ferroelectric film 23 of the first capacitor and the second ferroelectric film 23 of the second capacitor is the same as in the first modification. In the third modification, the second upper electrode film 33 and the third upper electrode film 34 are not formed on the first upper electrode film 30 of the first capacitor. In the third modification, the third upper electrode film 34 is not formed on the second upper electrode film 33 of the second capacitor. In the third modification, the second upper electrode film 33 on the first upper electrode film 30 of the first capacitor is removed by etching. In the third modification, the step of forming the third upper electrode film 34 is not performed. In the third modification, the first upper electrode film 30 is formed by increasing the thickness of the first upper electrode film 30, and the second upper electrode film 33 is increased by increasing the thickness of the second upper electrode film 33. Is formed. The second protective film 40 may be formed by increasing the thickness of the second protective film 40.

  FIG. 19 is a cross-sectional view of a semiconductor device according to a fourth modification of the first embodiment. The fourth modification is an example in which the first capacitor and the second capacitor are formed as a stack structure. In the fourth modification, a second ferroelectric film 24 is formed on the first ferroelectric film 23 of the second capacitor. That is, in the fourth modification, the second ferroelectric film 24 formed on the first ferroelectric film 23 of the second capacitor is not completely removed by etching, and the first ferroelectric film 24 of the second capacitor is removed. The second ferroelectric film 24 is left on the dielectric film 23. For example, a second ferroelectric film 24 having a thickness of 20 nm may be formed on the first ferroelectric film 23 of the second capacitor. Further, in the fourth modification, the lower electrode 42 is not shared by the first capacitor and the second capacitor. That is, in the fourth modification, the lower electrode 42 of the first capacitor and the lower electrode 42 of the second capacitor are independent from each other. According to the fourth modification, the inversion charge amount of the second capacitor can be improved.

  FIG. 20 is a cross-sectional view of the semiconductor device according to the fifth modification of the first embodiment. In the fifth modification, the first capacitor does not include the second upper electrode film 33. That is, in the fifth modification, the second upper electrode film 33 is not formed on the first upper electrode film 30 of the first capacitor. In the fifth modification, the second upper electrode film 33 is formed under the same film formation conditions as the first upper electrode film 30. Therefore, a thick first upper electrode film 30 is formed on the second ferroelectric film 24 of the first capacitor. That is, in the fifth modification, the first upper electrode film 30 and the second upper electrode film 33 are formed as one electrode film on the second ferroelectric film 24 of the first capacitor. The second upper electrode film 33 is formed on the first upper electrode film 30 in the first capacitor region by forming the second upper electrode film 33 under film formation conditions different from the film formation conditions of the first upper electrode film 30. 33 may be removed.

FIG. 21 is a cross-sectional view of a semiconductor device according to a sixth modification of the first embodiment. In the sixth modification, the second upper electrode film 33 and the third upper electrode film 34 are not formed on the first upper electrode film 30 of the first capacitor. In the sixth modification, the third upper electrode film 34 is not formed on the second upper electrode film 33 of the second capacitor. In the sixth modification, the first upper electrode film 30 is formed by increasing the film thickness of the first upper electrode film 30, and the second upper electrode film 33 is formed by increasing the film thickness of the second upper electrode film 33. Is formed. The second protective film 40 may be formed by increasing the thickness of the second protective film 40.

  FIG. 22 is a cross-sectional view of a semiconductor device according to a seventh modification of the first embodiment. The seventh modification is an example in which the first capacitor and the second capacitor are formed as a stack structure. In the seventh modified example, the lower electrode 42 is not shared by the first capacitor and the second capacitor. That is, in the seventh modification, the lower electrode 42 of the first capacitor and the lower electrode 42 of the second capacitor are independent from each other.

  When Pt is used for the upper electrodes 37 and 38, the leakage current of the capacitor is lowered, but the rise of Qtv is slow and the fatigue resistance is deteriorated. When PtO is used for the upper electrodes 37 and 38, the leakage current of the capacitor is lowered and the fatigue resistance is improved. Furthermore, when using IrOx for the upper electrodes 37 and 38, the electrical characteristics of the capacitor vary greatly depending on the IrOx film forming conditions. When IrOx is deposited at a low temperature, the leakage current of the capacitor can be lowered by adjusting the oxygen flow rate during deposition (the leakage current does not reach the Pt upper electrode). In addition, when IrOx is deposited at a low temperature, the rise of Qtv is accelerated by adjusting the oxygen flow rate during deposition, and the fatigue resistance and imprint characteristics are further improved. In addition, when IrOx is formed at a high temperature, the leakage current of the capacitor increases, but the rise of Qtv becomes faster, and the saturation Qsw, fatigue resistance and imprint resistance can be greatly improved.

  For high-voltage smoothing capacitors used for RF circuits and smoothing capacitors, it is preferable that the leakage current of the capacitors is low. When reducing the leakage current of the capacitor, it is preferable to use any one of Pt, PtOx, and IrOx as the upper electrodes 37 and 38. When Pt or PtOx is used as the upper electrodes 37 and 38, since the mutual diffusion between Pt and the ferroelectric film is small, the leakage current of the capacitor is low. On the other hand, when using IrOx as the upper electrodes 37 and 38, it is preferable to form IrOx at a low temperature. For the memory element capacitor, it is preferable to use IrOx formed at a high temperature as the upper electrodes 37 and 38 in order to improve low voltage operation, fatigue resistance and imprint characteristics.

  The first capacitor has an element used as a smoothing capacitor (high withstand voltage capacitor), and the second capacitor has a memory element having constant voltage operation, fatigue resistance, imprint resistance, and reliability. According to the first embodiment and its modification, a semiconductor device having a first capacitor and a second capacitor having different characteristics is manufactured by adding an etching process for the first upper electrode film 30 and the second ferroelectric film 24. can do. Therefore, the manufacturing cost of the semiconductor device can be reduced by manufacturing the semiconductor device having the first capacitor and the second capacitor having different characteristics without significantly changing the process.

  According to the first embodiment and its modification, the first ferroelectric in the second capacitor region is formed without forming a resist on the first ferroelectric film 23 and the second ferroelectric film 24 in the first capacitor region. The body film 24 is removed. Further, according to the first embodiment and the modification thereof, the second capacitor region second in the second capacitor region in a state where no resist is formed on the first ferroelectric film 23 and the second ferroelectric film 24 in the first capacitor region. The ferroelectric film 24 is shaved to reduce the thickness of the second ferroelectric film 24 in the second capacitor region. Therefore, according to the first embodiment and the modification thereof, the ferroelectric film of the second capacitor can be thinned while the surface of the first ferroelectric film 24 of the first capacitor is not exposed to the resist. According to the first embodiment and the modification thereof, the semiconductor having the first capacitor and the second capacitor having different thicknesses of the ferroelectric film without exposing the surface of the first ferroelectric film 24 of the first capacitor to the resist. The device can be manufactured. According to the first embodiment and the modification thereof, a semiconductor device having a plurality of capacitors having different characteristics can be manufactured without exposing the surface of the first ferroelectric film 24 of the first capacitor to the resist.

  A second example of this embodiment will be described. The semiconductor device according to the second embodiment is a semiconductor device having a stack structure type FeRAM. The semiconductor device according to Example 2 is manufactured as follows. The same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment.

  The steps required until a sectional structure shown in FIG. FIG. 23 is a cross-sectional view of the semiconductor device according to the second embodiment. First, a trench for STI (Shallow Trench Isolation) that defines an active region of a transistor is formed on the surface of an n-type or p-type silicon (semiconductor) substrate 1. Next, an insulating film such as silicon oxide is embedded in the STI trench, and an element isolation insulating film 2 is formed on the silicon substrate 1. The element isolation structure is not limited to STI, and the element isolation insulating film 2 may be formed by a LOCOS (Local Oxidation of Silicon) method.

  Next, after introducing p-type impurities, for example, boron into the active region of the silicon substrate 1 to form the p-well 3, the surface of the active region is thermally oxidized to form a thermal oxide film as the gate insulating film 4. Form.

  Subsequently, an amorphous or polycrystalline silicon film is formed on the entire upper surface of the silicon substrate 1. Then, the silicon film is patterned by photolithography and etching to form two gate electrodes 5 on the silicon substrate 1. On the p-well 3 of the silicon substrate 1, two gate electrodes 5 are arranged in parallel at an interval, and the two gate electrodes 5 become part of a word line.

  Next, by performing ion implantation using the gate electrode 5 as a mask, for example, phosphorus is introduced as an n-type impurity into the silicon substrate 1 beside the gate electrode 5 to form source / drain extensions 6.

  Next, an insulating film is formed on the entire upper surface of the silicon substrate 1, and the insulating film is etched back to form insulating sidewalls 7 beside the gate electrode 5. For example, a silicon oxide film formed by a CVD method may be used as the insulating film.

  Subsequently, n-type impurities such as arsenic are ion-implanted again into the silicon substrate 1 using the gate electrode 5 and the insulating sidewalls 7 as a mask, so that source / drain regions are formed in the silicon substrate 1 on the side of the gate electrode 5. (Impurity diffusion region) 8 is formed.

  Further, a refractory metal film such as a cobalt film is formed on the entire upper surface of the silicon substrate 1 by sputtering. Then, by heating the refractory metal film to react with silicon, a refractory metal silicide layer 9 such as a cobalt silicide layer is formed on the upper surface of the gate electrode 5 and on the silicon substrate 1 in the source / drain regions 8 respectively. Form. By the heat treatment, the source / drain region 8 is activated and the resistance of the source / drain region 8 is lowered.

  Thereafter, the unreacted refractory metal film on the element isolation film or the like is removed by wet etching. Through the steps so far, a MOS (Metal Oxide Semiconductor) transistor having the gate insulating film 4, the gate electrode 5, the source / drain region 8 and the like is formed in the active region of the silicon substrate 1.

  Next, a silicon oxynitride (SiON) film is formed as an antioxidant insulating film (cover film) 10 on the entire upper surface of the silicon substrate 1 by plasma CVD. The film thickness of the antioxidant insulating film 10 is about 200 nm, for example.

Next, a silicon oxide (SiO ₂ ) film is formed as the first interlayer insulating film 11 on the antioxidant insulating film 10 by plasma CVD using TEOS (tetra ethoxy silane) gas. The film thickness of the first interlayer insulating film 11 is, for example, about 1000 nm.

Subsequently, the first interlayer insulating film 11 is polished by CMP (Chemical Mechanical Polishing) to flatten the upper surface of the first interlayer insulating film 11. By the CMP method, the film thickness from the surface of the silicon substrate 1 to the surface of the first interlayer insulating film 11 becomes a predetermined value, for example, about 700 nm.

  Then, the oxidation-preventing insulating film 10 and the first interlayer insulating film 11 are patterned by photolithography and etching to form contact holes with a diameter of, for example, 0.25 μm on the source / drain regions 8.

  Next, a tungsten plug 12 electrically connected to the source / drain region 8 is formed in the contact hole. For example, by filling a tungsten film by a CVD method through an adhesion film (glue film) in which a Ti film having a thickness of 30 nm and a TiN film having a thickness of 20 nm are stacked, and removing an excess tungsten film by a CMP method, A tungsten plug 12 is formed.

  Next, a silicon oxynitride (SiON) film is formed as the first antioxidant film 60 on the first interlayer insulating film 11 by plasma CVD. The film thickness of the first antioxidant film 60 is, for example, 130 nm. Instead of the silicon oxynitride film, a SiN film or an AlO film may be formed as the first antioxidant film 60. Subsequently, a silicon oxide film is formed as the second interlayer insulating film 61 on the first antioxidant film 60 by plasma CVD using TEOS as a raw material. The film thickness of the second interlayer insulating film 61 is, for example, 300 nm.

  Then, by photolithography and etching, a contact hole penetrating the first antioxidant film 60 and the second interlayer insulating film 61 is formed with a diameter of, for example, 0.25 μm. Next, a tungsten plug 62 electrically connected to the tungsten plug 12 is formed in the contact hole. For example, by filling a tungsten film by a CVD method through an adhesion film (glue film) in which a Ti film having a thickness of 30 nm and a TiN film having a thickness of 20 nm are stacked, and removing an excess tungsten film by a CMP method, A tungsten plug 62 is formed.

In the CMP performed to form the tungsten plug 62, a slurry is used such that the polishing rate for the adhesion film (glue film) and tungsten film to be polished is higher than that of the underlying second interlayer insulating film 61. For example, SSW2000 manufactured by Cabot Microelectronics Corporation may be used. In order not to leave a polishing residue on the second interlayer insulating film 61, the polishing amount of CMP is set to be thicker than the total film thickness of each film. That is, the CMP performed to form the tungsten plug 62 is overpolishing. As a result, the height of the upper surface of the tungsten plug 62 is lower than that of the second interlayer insulating film 61. Therefore, a recess is formed in the second interlayer insulating film 61 around the tungsten plug 62. The depth of the recess formed in the second interlayer insulating film 61 is, for example, 20 to 50 nm, and typically about 50 nm.

Next, the surface of the second interlayer insulating film 61 is treated with ammonia (NH ₃ ) plasma to bond NH groups to oxygen atoms on the surface of the second interlayer insulating film 61. Even if Ti atoms are further deposited on the second interlayer insulating film 61, the deposited Ti atoms are not captured by oxygen atoms, so that the surface of the second interlayer insulating film 61 can be moved freely. As a result, a Ti film self-organized in (002) orientation is formed on the second interlayer insulating film 61. In the ammonia plasma processing, for example, a parallel plate type plasma processing apparatus having a counter electrode is used. The counter electrode is installed at a position separated from the silicon substrate 1 by about 9 mm (350 mils). The processing condition is, for example, 266.
Under a pressure of Pa (2 Torr), ammonia gas is supplied at a flow rate of 350 sccm into a processing vessel in which the substrate temperature is maintained at 400 ° C., and a high frequency of 13.56 MHz is applied to the silicon substrate 1 side at 100.
This is performed by supplying a high frequency of 350 MHz to the counter electrode with a power of W at a power of 55 W for 60 seconds.

  Next, for example, in a sputtering apparatus in which the distance between the silicon substrate 1 and the target is set to 60 mm, a sputtering DC power of 2.6 kW is supplied for 35 seconds at a substrate temperature of 20 ° C. in an Ar atmosphere of 0.15 Pa. Thereby, a Ti film having a strong Ti (002) orientation is formed to a thickness of about 100 nm.

  Next, a base conductive film 63 having a (111) orientation is formed on the second interlayer insulating film 61 by performing a heat treatment for 60 seconds at a substrate temperature of 650 ° C. in a nitrogen atmosphere by the RTA method. The underlying conductive film 63 is, for example, a titanium nitride film (TiN film). The film thickness of the base conductive film 63 is preferably 100 to 300 nm. In this embodiment, the film thickness of the underlying conductive film 63 is about 100 nm.

  Further, the base conductive film 63 is not limited to the titanium nitride film, and any one of a tungsten film, a silicon film, and a copper film may be formed as the base conductive film 63. However, in order to improve crystallinity, a titanium nitride film formed by performing ammonia plasma treatment is preferably used as the base conductive film 63.

Due to the influence of the recess formed around the tungsten plug 62, a recess is formed on the upper surface of the base conductive film 63. However, if a recess is formed on the upper surface of the base conductive film 63, the crystallinity of the ferroelectric film formed above the base conductive film 63 may be deteriorated by a subsequent process. Therefore, in this embodiment, the upper surface of the underlying conductive film 63 is polished and planarized by the CMP method, and the recesses on the upper surface of the underlying conductive film 63 are removed. The slurry used in the CMP is not particularly limited. For example, SSW2000 manufactured by Cabot Microelectronics Corporation may be used.

  The film thickness of the underlying conductive film 63 after CMP varies in the plane of the silicon substrate 1 or between the plurality of silicon substrates 1 due to polishing errors. In consideration of the variation, in this embodiment, by controlling the polishing time, the target value of the film thickness of the underlying conductive film 63 after CMP is set to 50 to 100 nm, more preferably 50 nm.

After CMP is performed on the base conductive film 63, crystals near the upper surface of the base conductive film 63 are in a state distorted by polishing. However, when the lower electrode of the capacitor is formed above the underlying conductive film 63 in which the crystal is distorted, the distortion of the crystal of the underlying conductive film 63 is transmitted to the lower electrode, and the crystallinity of the lower electrode is deteriorated. The ferroelectric characteristics of the ferroelectric film on the electrode may be deteriorated. In order to avoid such an inconvenience, the upper surface of the base conductive film 63 is exposed to NH ₃ plasma so that crystal distortion of the base conductive film 63 is not transmitted to the lower electrode.

Next, a titanium film is formed as a crystalline conductive adhesive film by sputtering on the base conductive film 63 from which crystal distortion has been eliminated by NH ₃ plasma treatment. The film thickness of the crystalline conductive adhesive film is, for example, about 20 nm. Next, a base conductive adhesive film 64 having a (111) orientation is formed on the base conductive film 63 by performing a heat treatment for 60 seconds at a substrate temperature of 650 ° C. in an atmosphere of nitrogen by an RTA method. The underlying conductive adhesion film 64 is, for example, a titanium nitride film (TiN film). The underlying conductive adhesive film 64 has a function of increasing the orientation of the film formed on the underlying conductive adhesive film 64 by the action of the orientation of the underlying conductive adhesive film 64, and the underlying conductive adhesive film 64 serves as an adhesive film. It also has a function. The underlying conductive adhesion film 64 is not limited to a titanium nitride film. For example, the underlying conductive adhesion film 64 may be a noble metal film (Ir film, Pt film, etc.) having a thin film thickness (preferably a film thickness of 20 nm).

  Subsequently, a TiAlN film is formed as the oxygen barrier film 65 on the base conductive adhesion film 64. The oxygen barrier film 65 is formed by reactive sputtering using an alloyed target of Ti and Al. The film thickness of the oxygen barrier film 65 is, for example, 100 nm. The conditions for forming the oxygen barrier film 65 are set to, for example, a substrate temperature of 400 ° C. and a sputtering power of 1.0 kW under a pressure of 253.3 Pa in a mixed atmosphere of Ar 40 sccm and nitrogen 10 sccm.

Then, an Ir film is formed as a lower electrode film (lower electrode layer) 66 on the oxygen barrier film 65. The film thickness of the Ir film is, for example, 100 nm. The formation conditions of the lower electrode film 66 are set to, for example, a substrate temperature of 500 ° C. and a sputtering power of 0.5 kW under a pressure of 0.11 Pa in an Ar atmosphere. In place of the Ir film, a platinum group metal such as Pt or P
A conductive oxide such as tO, IrOx, SrRuO ₃ may be used as the lower electrode film 66. Alternatively, a stacked film of a platinum group metal such as Pt and a conductive oxide such as PtO, IrOx, or SrRuO ₃ may be used as the lower electrode film 66.

Next, a PZT film is formed as a first ferroelectric film 67 on the lower electrode film 66 by MOCVD. More specifically, Pb (DPM) ₂ , Zr (dmhd) ₄ and Ti (O—iOr) ₂ (DPM) ₂ were dissolved in a THF solvent at a concentration of 0.3 mol / l, and Pb, Each liquid raw material of Zr and Ti is formed. Furthermore, each liquid raw material of Pb, Zr and Ti is supplied to the vaporizer of the MOCVD apparatus together with a THF solvent having a flow rate of 0.474 ml / min, 0.326 ml / min, 0.200 ml / min, and 0.200 ml / min, respectively. Supply at a flow rate of minutes. By vaporizing the liquid raw materials of Pb, Zr and Ti, raw material gases of Pb, Zr and Ti are formed.

  Next, Pb, Zr, and Ti source gases are supplied to the MOCVD apparatus for 620 seconds at a substrate temperature of 620 ° C. under a pressure of 665 Pa (5 Torr). Thereby, a desired PZT film is formed on the lower electrode film 66 with a film thickness of, for example, 100 nm.

Subsequently, an amorphous second ferroelectric film 68 is formed on the first ferroelectric film 67 by sputtering, for example. The second ferroelectric film 68 is, for example, a PZT film. The film thickness of the second ferroelectric film 68 is, for example, 1 nm to 40 nm. When the second ferroelectric film 68 is formed by MOCVD, Pb (DPM) ₂ (Pb (C ₁₁ H ₁₉ O ₂ ) ₂ ) is used as an organic source for supplying lead (Pb) in THF (Tetra Hydro Furan: A material dissolved in (C ₄ H ₈ O) solution is used. As an organic source for supplying zirconium (Zr), a material in which Zr (DMHD) ₄ (Zr ((C ₉ H ₁₅ O ₂ ) ₄ ) is dissolved in a THF solution is used.Organic for supplying titanium (Ti) As the source, a material in which Ti (O—iPr) ₂ (DPM) ₂ (Ti (C ₃ H ₇ O) ₂ (C ₁₁ H ₁₉ O ₂ ) ₂ ) is dissolved in a THF solution is used.

Then, a first upper electrode film (first upper electrode layer) 69 is formed on the second ferroelectric film 68. In forming the first upper electrode film 69, first, an iridium oxide film (IrO _X film) having a film thickness of 25 to 50 nm is formed on the second ferroelectric film 68 by sputtering. For example, the deposition temperature is 20 ° C., Ar and O ₂ are used as the deposition gas, the flow rate of Ar is 100 sccm, the flow rate of O ₂ is 50 to 56 sccm, and the sputtering power is about 2 kW.

Next, a photoresist film is formed on the first upper electrode film 69 by, eg, spin coating. Then, the photoresist film is patterned by photolithography and etching to form a first resist 70 that covers a region where the first capacitor is to be formed. The first capacitor is, for example, a smoothing capacitor, a high breakdown voltage capacitor, or a high breakdown voltage smoothing capacitor. In Example 2, the region where the first capacitor is formed is also referred to as a first capacitor region.

  Next, etching is performed using the first resist 70 as a mask to remove the first upper electrode film 69 other than the first capacitor region and the second ferroelectric film 68 other than the first capacitor region. In this case, the second ferroelectric film 68 other than the first capacitor region may be completely removed by etching. Further, the second ferroelectric film 68 other than the first capacitor region may be left about 10 to 20 nm. In this embodiment, the second ferroelectric film 68 other than the first capacitor region is completely removed. FIG. 24 is a cross-sectional view of the semiconductor device when the first upper electrode film 69 and the second ferroelectric film 68 other than the first capacitor region are removed.

Subsequently, the first resist 70 in the first capacitor region is removed. Then, a second upper electrode film (second upper electrode layer) 71 is oxidized above the silicon substrate 1, specifically, on the first upper electrode film 69 and the first ferroelectric film 67, by sputtering. An iridium film (IrO _X film) is formed. The film thickness of the second upper electrode film 71 is, for example, 15 to 50 nm. For example, the deposition temperature is 300 ° C., Ar and O ₂ are used as the deposition gas, the flow rate of Ar is 140 sccm, the flow rate of O ₂ is 60 sccm, and the sputtering power is about 1 kW.

Next, heat treatment is performed by an RTA method in a nitrogen atmosphere at a substrate temperature of 725 ° C., with an O ₂ flow rate of 20 sccm and an Ar flow rate of 2000 sccm, for 60 seconds. By this heat treatment, the second ferroelectric film 68 is completely crystallized, and the plasma damage of the first upper electrode film 69 and the second upper electrode film 71 is recovered, and oxygen vacancies in the first ferroelectric film 67 are recovered. Is compensated.

Next, an iridium oxide film (IrO _Y film) is formed as a third upper electrode film (third upper electrode layer) 72 on the second upper electrode film 71 by sputtering. The film thickness of the third upper electrode film 72 is, for example, 100 nm to 300 nm. For example, when the third upper electrode film 72 is deposited in an Ar atmosphere under a pressure of 0.8 Pa and a sputtering power of 1.0 kW for 79 seconds, the film thickness of the third upper electrode film 72 becomes 200 nm. At this time, if the iridium oxide film has a composition close to the stoichiometric composition of IrO _{2 in} order to suppress the process deterioration, no catalytic action is generated on hydrogen. Therefore, the problem that the second ferroelectric film 68 is reduced by hydrogen radicals is suppressed, and the hydrogen resistance of the capacitor is improved. As the material of the third upper electrode film 72, Ir, Ru, Rh, Re, Os, Pd, oxides thereof, and conductive oxides such as SrRuO ₃ or a laminated structure thereof are used instead of IrO _2. May be.

Subsequently, an Ir film is formed as a hydrogen barrier film 73 on the third upper electrode film 72 by sputtering in order to stabilize the contact resistance to the wiring. The film thickness of the hydrogen barrier film 73 is, for example, 100 nm. The hydrogen barrier film 73 is formed in an Ar atmosphere at a pressure of 1 Pa and a sputtering power of 1.0 kW. Instead of the Ir film, a Pt film or a SrRuO ₃ film may be used as the hydrogen barrier film 73. FIG. 25 is a cross-sectional view of the semiconductor device when the hydrogen barrier film 73 is formed on the third upper electrode film 72.

Then, after performing the back surface cleaning, a hard mask used for patterning each film from the base conductive film 63 to the hydrogen barrier film 73 is formed on the hydrogen barrier film 73. Specifically, first, a titanium nitride film (TiN film) is formed as a first mask material layer on the hydrogen barrier film 73 by sputtering. Instead of the titanium nitride film, a TiAlN film, a TaAlN film, a TaN film, or a laminated film thereof may be used as the first mask material layer. Next, a silicon oxide film is formed as a second mask material layer on the first mask material layer by a CVD method using TEOS gas. Next, the hard mask having the first mask material layer and the second mask material layer is formed by patterning the second mask material layer into an island shape and etching the first mask material layer using the second mask material layer as a mask. Is formed on the hydrogen barrier film 73.

Subsequently, the first capacitor and the second capacitor are formed by dry-etching each film from the lower electrode film 66 to the hydrogen barrier film 73 in a portion not covered with the hard mask. In Example 2, the region where the second capacitor is formed is also referred to as a second capacitor region. The second capacitor is, for example, a memory element capacitor. The dry etching is, for example, plasma etching using a mixed gas of HBr, O ₂ , Ar, and C ₄ H ₈ as an etching gas.

Then, the second mask material layer is removed by dry etching or wet etching. Next, the underlying conductive film 63, the underlying conductive adhesion film 64, and the oxygen barrier film 65 in portions not covered with the first capacitor and the second capacitor are removed by dry etching. Further, the first mask material layer is removed by dry etching. Etching is performed by, for example, down flow plasma etching. As an etching condition, a gas mixture of 5% CH ₄ gas and 95% O ₂ gas is supplied into the chamber as an etching gas, and a high frequency with a frequency of 2.45 GHz and a power of 1400 W is supplied to the upper electrode of the chamber. Electric power is supplied to set the substrate temperature to 200 ° C.

  For example, a photoresist film may be formed on the hydrogen barrier film 73 by spin coating. Then, the photoresist film may be patterned by photolithography and etching to form a resist covering a region where the first capacitor is formed and a resist covering a region where the second capacitor is formed. Furthermore, each film from the base conductive film 63 to the hydrogen barrier film 73 may be etched using a resist covering the region where the first capacitor is formed and a resist covering the region where the second capacitor is formed as a mask.

  FIG. 26 is a cross-sectional view of the semiconductor device when the first capacitor and the second capacitor are formed. The first capacitor includes a lower electrode film 66, a ferroelectric film 75 and an upper electrode 76. The ferroelectric film 75 includes a first ferroelectric film 67 and a second ferroelectric film 68. The upper electrode 76 includes a first upper electrode film 69, a second upper electrode film 71, and a third upper electrode film 72. The second capacitor includes a lower electrode film 66, a second ferroelectric film 68 and an upper electrode 77. The upper electrode 77 has a second upper electrode film 71 and a third upper electrode film 72.

Next, an Al ₂ O ₃ film is formed as the first protective film 80 by sputtering so as to cover the first capacitor and the second capacitor. The film thickness of the first protective film 80 is, for example, 20 nm. Further, instead of the Al ₂ O ₃ film, an AlO film may be formed as the first protective film 80 by the MOCVD method. The film thickness of the AlO film is, for example, 2 to 5 nm.

  In order to recover damage to the first ferroelectric film 67 and the second ferroelectric film 68, recovery annealing is performed on the first ferroelectric film 67 and the second ferroelectric film 68 in an oxygen-containing atmosphere. . The conditions for the recovery annealing are not particularly limited. For example, the recovery annealing is performed by setting the substrate temperature in the furnace to 550 ° C. to 700 ° C. When the first ferroelectric film 67 and the second ferroelectric film 68 are PZT films, it is preferable to perform a recovery annealing for 60 seconds in an oxygen atmosphere at 600 ° C.

Subsequently, an Al ₂ O ₃ film is formed as the second protective film 81 by the CVD method so as to cover the first protective film 80. The film thickness of the second protective film 81 is, for example, about 38 nm. The aluminum oxide film included in the first protective film 80 and the second protective film 81 has an excellent function of blocking the transmission of a reducing substance such as hydrogen or moisture, and the ferroelectric film of the capacitor is reduced by the reducing substance. It plays a role of preventing deterioration of its ferroelectric properties due to reduction.

  In order to prevent the first protective film 80 and the second protective film 81 from peeling off, annealing may be performed in a furnace containing oxygen before the first protective film 80 and the second protective film 81 are formed. . Annealing is performed, for example, under conditions of a substrate temperature of 350 ° C. and a processing time of 1 hour. Instead of the aluminum oxide film, any of a titanium oxide film, a tantalum oxide film, a zirconium oxide film, an aluminum nitride film, a tantalum nitride film, and an aluminum oxynitride film is used as the first protective film 80 and the second protective film 81. Also good.

  Next, a silicon oxide film is formed as the third interlayer insulating film 82 on the second protective film 81 by, for example, plasma TEOSCVD. The film thickness of the third interlayer insulating film 82 is, for example, 1500 nm. When a silicon oxide film is formed as the third interlayer insulating film 82, for example, a mixed gas of TEOS gas, oxygen gas, and helium gas is used as the source gas. For example, an insulating inorganic film may be formed as the third interlayer insulating film 82. Next, the surface of the third interlayer insulating film 82 is planarized by, eg, CMP.

Subsequently, in a plasma atmosphere generated by using N 2 _O gas or N ₂ gas or the like, for example 350 ° C., a heat treatment is carried out for 2 minutes. As a result of the heat treatment, moisture in the third interlayer insulating film 82 is removed, the film quality of the third interlayer insulating film 82 changes, and moisture hardly enters the third interlayer insulating film 82. Further, by this heat treatment, the surface of the third interlayer insulating film 82 is nitrided, and a SiON film is formed on the surface of the third interlayer insulating film 82.

  Then, for example, an aluminum oxide film is formed as the barrier film 83 on the third interlayer insulating film 82 by sputtering or CVD. The film thickness of the barrier film 83 is, for example, 20 to 100 nm. Since the barrier film 83 is formed on the planarized third interlayer insulating film 82, the barrier film 83 becomes flat.

  Next, a silicon oxide film is formed as the fourth interlayer insulating film 84 on the barrier film 83 by, for example, plasma TEOSCVD. The film thickness of the fourth interlayer insulating film 84 is, for example, 800 to 1000 nm. Instead of the silicon oxide film, a SiON film, a silicon nitride film, or the like may be formed as the fourth interlayer insulating film 84. Next, the surface of the fourth interlayer insulating film 84 is planarized by, eg, CMP. FIG. 27 is a cross-sectional view of the semiconductor device when the fourth interlayer insulating film 84 is formed on the barrier film 83.

  Next, contacts reaching the upper electrode 76 to the hydrogen barrier film 73, the first protective film 80, the second protective film 81, the third interlayer insulating film 82, the barrier film 83, and the fourth interlayer insulating film 84 by photolithography and etching. A hole 85A is formed. Further, the contact reaching the upper electrode 77 to the hydrogen barrier film 73, the first protective film 80, the second protective film 81, the third interlayer insulating film 82, the barrier film 83, and the fourth interlayer insulating film 84 by photolithography and etching. Hole 85B is formed. Further, the first antioxidant film 60, the second interlayer insulating film 61, the first protective film 80, the second protective film 81, the third interlayer insulating film 82, the barrier film 83, and the fourth interlayer insulating film are formed by photolithography and etching. In 84, a contact hole 85C reaching the tungsten plug 12 is formed. FIG. 28 is a cross-sectional view of the semiconductor device when the contact holes 85A, 85B, and 85C are formed.

  When the contact holes 85A and 85B are formed, the hydrogen barrier film 73 is exposed, and then heat treatment is performed in an oxygen atmosphere at 450 ° C., and the first ferroelectric film 67 generated along with the formation of the contact holes 85A and 85B. And the oxygen deficiency of the second ferroelectric film 68 is recovered.

Subsequently, moisture in the interlayer insulating film is removed by performing an annealing process. The annealing process is preferably performed in an inert gas atmosphere or in a vacuum. Then, surface treatment (RF etching) is performed on the inner wall surfaces of the contact holes 85A, 85B, and 85C.

Then, for example, a TiN film is formed as a conductive barrier film in the contact holes 85A, 85B, and 85C by sputtering. The film thickness of the TiN film is, for example, 50 to 150 nm. For example, in a ENDURA SIP chamber with good coverage, a TiN film is formed at 200 ° C. in a mixed atmosphere of Ar (supply amount 50 Sccm) and N ₂ (supply amount 90 Sccm) using a Ti target. The conductive barrier film is not limited to the TiN film. TiN, TaN, CrN, HfN, ZrN, TiAlN, TaAlN, TiSiN, TaSiN, CrAlN, HfAlN, ZrAlN, TiON, TaON, CrON, HfON, ZrON, TiAlON, TaAlON, CrAlON, HfArON, ZrAlON, TiSiON, TaSiON, TaSiON At least one film selected from the group consisting of Ru, IrO _X , RuO _X , Ti / TiN, Ti / TaN, Ta / TiN, and Ta / TaN may be used as the conductive barrier film.

  Next, a tungsten film is formed in the contact holes 85A, 85B, and 85C by, for example, the CVD method. The film thickness of the tungsten film is, for example, 300 nm. Instead of the tungsten film, a copper film may be formed in the contact holes 85A, 85B and 85C. Alternatively, a glue film may be formed in the contact holes 85A, 85B, and 85C, tungsten or polysilicon may be partially embedded on the glue film, and a copper film may be further laminated.

  Then, for example, the tungsten film and the conductive barrier film are polished by CMP until the surface of the fourth interlayer insulating film 84 is exposed. As a result, conductor plugs 90A, 90B and 90C containing tungsten are buried in the contact holes 85A, 85B and 85C, respectively. Next, for example, plasma cleaning using argon gas is performed. As a result, the natural oxide film and the like existing on the surfaces of the conductor plugs 90A, 90B and 90C are removed.

  Next, for example, by sputtering, over the entire upper surface of the fourth interlayer insulating film 84, for example, a 50 nm thick TiN film, for example, a 550 nm thick AlCu alloy film, for example, a 5 nm thick Ti film, For example, a TiN film having a thickness of 50 nm is sequentially stacked. As a result, a conductor film having a TiN film, an AlCu alloy film, a Ti film, and a TiN film is formed on the fourth interlayer insulating film 84.

  Then, the conductor film is patterned by photolithography and dry etching. As a result, the first metal wiring layer 91 is formed. That is, the metal wiring layer 91 electrically connected to the upper electrodes 76 and 77 via the conductor plugs 90A and 90B and the metal wiring layer 91 electrically connected to the tungsten plug 12 via the conductor plug 90C are provided. It is formed. FIG. 29 is a cross-sectional view of the semiconductor device when the conductor plugs 90A, 90B and 90C and the metal wiring layer 91 are formed.

  Thereafter, when a three-layer wiring or a five-layer wiring is performed by a film forming method or patterning method substantially the same as the formation of the first metal wiring layer, the basic structure of the semiconductor device according to the present embodiment is completed. That is, a semiconductor device having a first capacitor and a second capacitor is manufactured.

As shown in FIG. 29, the first capacitor and the second capacitor are formed on the stack structure. The first capacitor has an element used as a smoothing capacitor (high withstand voltage capacitor), and the second capacitor has a memory element having constant voltage operation, fatigue resistance, imprint resistance, and reliability. According to the second embodiment, by adding an etching process for the first upper electrode film 69 and the second ferroelectric film 68, a semiconductor device having a first capacitor and a second capacitor having different characteristics is manufactured. Can do. Therefore, the manufacturing cost of the semiconductor device can be reduced by manufacturing the semiconductor device having the first capacitor and the second capacitor having different characteristics without changing the process significantly.

  According to the second embodiment, the second ferroelectric film 68 in the second capacitor region is formed in a state where no resist is formed on the first ferroelectric film 67 and the second ferroelectric film 68 in the first capacitor region. It has been removed. Further, according to the second embodiment, the second ferroelectric film in the second capacitor region is formed without forming a resist on the first ferroelectric film 67 and the second ferroelectric film 68 in the first capacitor region. 68 is removed to reduce the thickness of the second ferroelectric film 68 in the second capacitor region. Therefore, according to the second embodiment, the ferroelectric film of the second capacitor can be thinned while the surface of the ferroelectric film 75 of the first capacitor is not exposed to the resist. According to the second embodiment, a semiconductor device having a first capacitor and a second capacitor having different thicknesses of the ferroelectric film can be manufactured without exposing the surface of the ferroelectric film 75 of the first capacitor to the resist. it can. According to the second embodiment, a semiconductor device having a plurality of capacitors having different characteristics can be manufactured without exposing the surface of the ferroelectric film 75 of the first capacitor to the resist.

As a method of forming the first ferroelectric film 67 and the second ferroelectric film 68, in addition to the sputtering method and the MOCVD method, a sol-gel method, an organometallic decomposition (MOD) method, a CSD (Chemical Solution Deposition) method, Examples include chemical vapor deposition (CVD) and epitaxial growth. Further, as the first ferroelectric film 67 and the second ferroelectric film 68, for example, a film having a Bi layer structure or a perovskite structure may be formed by heat treatment. As a film having a Bi-layered structure or a perovskite structure in crystal structure, in addition to a PZT film, PZT, SBT, BLT and Bi-based layered compounds in which one or more kinds such as La, Ca, Sr and Si are slightly doped A film represented by the formula ABO ₃ may be mentioned.

  When forming the first upper electrode film 69, for example, sputtering using a target containing Pt or Ir may be performed under conditions where oxidation of Pt or Ir occurs. In the case where an iridium oxide film is formed as the third upper electrode film 72, the film forming temperature is preferably set to 20 ° C. to 400 ° C., for example, 300 ° C. Moreover, it is preferable that the partial pressure of the oxygen gas with respect to the pressure of the oxygen gas and the inert gas contained in the sputtering gas is 10% to 60%. The film thickness of the iridium oxide film is preferably 10 nm to 75 nm.

  The heat treatment temperature after forming the first upper electrode film 69 is preferably 650 ° C. to 750 ° C., for example, 700 ° C., and the heat treatment atmosphere preferably has an oxygen content of 1% to 50%.

The first upper electrode film 69 and the second upper electrode film 71 are not limited to IrO _X films. As the first upper electrode film 69 and the second upper electrode film 71, a metal film containing one or more kinds of noble metal elements such as Pt, Ir, Ru, Rh, Re, Os and Pd may be formed. These oxide films, for example, SrRuO ₃ films may be formed. Alternatively, a film having a two-layer structure or more may be formed as the conductive film.

  The semiconductor device manufacturing method described in the first to sixth modifications of the first embodiment may be applied to the semiconductor device manufacturing method described in the second embodiment. Further, the semiconductor device manufacturing methods described in the first to sixth modifications of the first embodiment may be combined as much as possible and applied to the semiconductor device manufacturing method described in the second embodiment.

  With respect to the embodiment including the first example, the modified example, and the second example, the following additional notes are disclosed.

(Appendix 1)
In a method for manufacturing a semiconductor device in which a first capacitor and a second capacitor are respectively formed in a first region and a second region on a semiconductor substrate,
Forming an insulating film on or over the semiconductor substrate;
Forming a lower electrode layer above the insulating film;
Forming a ferroelectric film on the lower electrode layer;
Forming a first upper electrode layer on the ferroelectric film;
Forming a first resist covering the first region on the first upper electrode layer;
Etching the first resist as a mask to remove the first upper electrode layer in the second region and scraping the ferroelectric film in the second region;
Forming a second upper electrode layer on the first upper electrode layer in the first region and on the ferroelectric film other than the first region;
Forming a second resist above the second upper electrode layer and in the first region and the second region;
Using the second resist as a mask, the first upper electrode layer, the second upper electrode layer, the ferroelectric film and the lower electrode layer are etched, and the first capacitor and the second capacitor are etched. Forming, and
A method for manufacturing a semiconductor device, comprising:

(Appendix 2)
The method for manufacturing a semiconductor device according to appendix 1, further comprising a step of heat-treating the ferroelectric film.

(Appendix 3)
The first capacitor includes the first upper electrode layer, the second upper electrode layer, the ferroelectric film, and the lower electrode layer,
The second capacitor includes the second upper electrode layer, the ferroelectric film, and the lower electrode layer,
3. The semiconductor device according to appendix 1 or 2, wherein a film thickness of the ferroelectric film included in the second capacitor is smaller than a film thickness of the ferroelectric film included in the first capacitor. Production method.

(Appendix 4)
The method for manufacturing a semiconductor device according to any one of appendices 1 to 3, further comprising a step of heat-treating the second upper electrode layer.

(Appendix 5)
The method for manufacturing a semiconductor device according to any one of appendices 1 to 4, further comprising a step of forming a third upper electrode layer on the second upper electrode layer.

(Appendix 6)
An insulating film formed on or over the semiconductor substrate;
A first capacitor formed in a first region on the insulating film, wherein a first lower electrode, a first ferroelectric film, and a first upper electrode are sequentially stacked;
A second lower electrode, a second ferroelectric film having a thickness smaller than that of the first ferroelectric film, and the second upper electrode are sequentially stacked in the second region on the insulating film. A second capacitor,
A semiconductor device comprising:

(Appendix 7)
The semiconductor device according to appendix 6, wherein the film thickness of the second upper electrode is smaller than the film thickness of the first upper electrode.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 11 1st interlayer insulation film 20, 61 2nd interlayer insulation film 22, 66 Lower electrode film 23, 67 1st ferroelectric film 24, 68 2nd ferroelectric film 30, 69 1st upper electrode film 31 70 First resist 33, 71 Second upper electrode film 34, 72 Third upper electrode film 36A, B Second resist 37, 38, 76, 77 Upper electrode 39A, B Third resist 41 Fourth resist 42 Lower electrode

Claims (5)

In a method for manufacturing a semiconductor device in which a first capacitor and a second capacitor are respectively formed in a first region and a second region on a semiconductor substrate,
Forming an insulating film on or over the semiconductor substrate;
Forming a lower electrode layer above the insulating film;
Forming a ferroelectric film on the lower electrode layer;
Forming a first upper electrode layer on the ferroelectric film;
Forming a first resist covering the first region on the first upper electrode layer;
Etching the first resist as a mask to remove the first upper electrode layer in the second region and scraping the ferroelectric film in the second region;
Forming a second upper electrode layer on the first upper electrode layer in the first region and on the ferroelectric film other than the first region;
Forming a second resist above the second upper electrode layer and in the first region and the second region;
Using the second resist as a mask, the first upper electrode layer, the second upper electrode layer, the ferroelectric film and the lower electrode layer are etched, and the first capacitor and the second capacitor are etched. Forming, and
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 1, further comprising a step of heat-treating the ferroelectric film. The first capacitor includes the first upper electrode layer, the second upper electrode layer, the ferroelectric film, and the lower electrode layer,
The second capacitor includes the second upper electrode layer, the ferroelectric film, and the lower electrode layer,
3. The semiconductor device according to claim 1, wherein a film thickness of the ferroelectric film included in the second capacitor is smaller than a film thickness of the ferroelectric film included in the first capacitor. Manufacturing method. An insulating film formed on or over the semiconductor substrate;
A first capacitor formed in a first region on the insulating film, wherein a first lower electrode, a first ferroelectric film, and a first upper electrode are sequentially stacked;
A second lower electrode, a second ferroelectric film having a thickness smaller than that of the first ferroelectric film, and the second upper electrode are sequentially stacked in the second region on the insulating film. A second capacitor,
A semiconductor device comprising:   The semiconductor device according to claim 4, wherein a film thickness of the second upper electrode is thinner than a film thickness of the first upper electrode.

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