JP5338800B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To maintain a low voltage operation and enhance its operation speed remarkably, even if a capacitor film is continually thinned. <P>SOLUTION: A capacitor having a ferroelectric film (capacitor film) 302 that is formed above a semiconductor substrate and is sandwiched between an upper electrode 303 and a lower electrode 301, wherein a conductive oxide film 303a, which is crystallized at deposition, is provided on an interface between the upper electrode 303 and the ferroelectric film 302, thus evading the formation of an interface layer with coarsened crystal grains in the interface between the upper electrode 303 and the ferroelectric film 302. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device having a capacitor structure and a method for manufacturing the same, and more particularly to a semiconductor device including a ferroelectric as a dielectric and a method for manufacturing the same.

  In recent years, with the progress of digital technology, there is an increasing tendency to process or store a large amount of data at high speed. For this reason, high integration and high performance of semiconductor devices used in electronic devices are required.

  Therefore, with respect to semiconductor memory devices, for example, in order to realize high integration of DRAM, it replaces the conventionally used silicon oxide and silicon nitride as a capacitor insulating film of a capacitor element (capacitor) constituting the DRAM. The technology using ferroelectric materials and high dielectric constant materials has been widely researched and developed.

  In addition, in order to realize a non-volatile RAM that can perform a write operation and a read operation at a lower voltage and at a higher speed, a technique using a ferroelectric having spontaneous polarization characteristics as a capacitor insulating film has been actively researched and developed. Yes. Such a semiconductor memory device is called a ferroelectric memory (FeRAM: Ferroelectric Random Access Memory).

  A ferroelectric memory includes a ferroelectric capacitor configured by sandwiching a ferroelectric film as a capacitive insulating film between a pair of electrodes. In the ferroelectric memory, information is stored using the hysteresis characteristic of the ferroelectric film.

  This ferroelectric film is polarized according to the applied voltage between the electrodes, and has a spontaneous polarization characteristic even when the applied voltage is removed. Further, if the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization of the ferroelectric film is also reversed. Therefore, information can be read out by detecting this spontaneous polarization. A ferroelectric memory operates at a lower voltage than a flash memory, and can perform power saving and high-speed writing operation.

  When manufacturing a ferroelectric capacitor, it is necessary to perform heat treatment in an oxygen atmosphere a plurality of times in order to recover damage and defects generated in the ferroelectric film. For this reason, as the material of the upper electrode of the ferroelectric capacitor, a metal that is not easily oxidized even in an oxygen atmosphere such as Pt, or a conductive oxide such as IrOx or RuOx is used.

Non-Patent Document 1 (APPL. Phys. Lett. 65, P.19 (1994)) sandwiches a ferroelectric film made of lead zirconate titanate (PZT: (Pb (Zr, Ti) O ₃ )). It is described that by using iridium oxide (IrO ₂ ) as a material for the upper electrode and the lower electrode, so-called fatigue of the ferroelectric capacitor can be suppressed and good capacitance characteristics can be secured. Similarly, Patent Document 1 below describes that iridium oxide (IrO ₂ ) is used as a material for the upper electrode on a ferroelectric film made of PZT.

However, when iridium oxide (IrO ₂ ) is used as the electrode, it is known that giant crystals of IrO ₂ abnormally grown on the surface of the electrode are likely to be formed (for example, paragraph [ 0010]). Such a giant crystal forms a defect and degrades the electrical characteristics of the ferroelectric capacitor, which in turn reduces the yield of the semiconductor device.

In order to solve this problem, in Patent Document 2, when forming an upper electrode on a ferroelectric film, a thin iridium oxide having a thickness of 100 nm or less is formed by sputtering with a low power (low power) of about 1 kW. It is disclosed to suppress the formation of giant crystals growing from the iridium oxide film by forming an (IrO ₂ ) film.

JP 2000-91270 A JP 2001-127262 A JP 2005-183842 A

APPL. Phys. Lett. 65, P.19 (1994)

However, in the ferroelectric memory manufactured by the manufacturing method of Patent Document 2 described above, there are not a few giant crystals grown from the iridium oxide film of the upper electrode between the ferroelectric film. Recently, like other semiconductor devices, ferroelectric memories have been required to be miniaturized and operated at a low voltage. As the ferroelectric film becomes thinner, the ferroelectric memory has been requested. The influence of the giant crystals formed between the body membranes becomes larger. Specifically, when a giant crystal is formed, the inversion charge amount (switching charge amount) _QSW of the ferroelectric capacitor is significantly reduced, and the coercive voltage Vc is difficult to decrease. When the inversion charge amount Q _SW of the ferroelectric capacitor decreases, it becomes difficult to operate the ferroelectric memory at a low voltage, and when the coercive voltage Vc becomes difficult to decrease, the polarity reversal speed in the ferroelectric capacitor increases. It becomes difficult to improve.

  That is, the conventional semiconductor device having a capacitor structure has a problem that it becomes difficult to operate at a low voltage as the capacitor film becomes thinner, and the operation speed cannot be remarkably improved.

  The present invention has been made in view of the above-described problems. Even when the capacitor film is made thinner, the operation at a low voltage is maintained and the operation speed is remarkably improved. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same.

The method for manufacturing a semiconductor device of the present invention includes a step of forming a lower electrode above a semiconductor substrate, a step of forming a first ferroelectric film on the lower electrode, and a step of forming on the first ferroelectric film. And a step of forming a second ferroelectric film in an amorphous state in a film formation state, and a crystallized state on the interface of the second ferroelectric film on the second ferroelectric film. Forming a first upper electrode including a conductive oxide film; forming a second upper electrode including an IrO _Y film on the first upper electrode; and on the second upper electrode. Forming a third upper electrode containing Ir .

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a capacitor structure, the step of forming a lower electrode of the capacitor structure above a semiconductor substrate, and forming a capacitor film on the lower electrode a step of, on the capacitor film, at least, a step of forming a first conductive film is a conductive oxide film of the crystalline state in the film forming time, after forming the first conductive film, oxide A step of performing a heat treatment in an atmosphere containing a reactive gas ; a step of forming a second conductive film including an IrO _Y film on the first conductive film after performing the heat treatment; and the second conductive film. above, forming the Ir film, the first conductive film, the second conductive film, and patterning the Ir film, which have a forming an upper electrode.

  According to the present invention, even when the thickness of the capacitor film is reduced, it is possible to maintain the operation at a low voltage and remarkably improve the operation speed.

It is a characteristic view of the ferroelectric capacitor in the ferroelectric memory produced using the conventional manufacturing method. It is a schematic diagram which shows the ferroelectric capacitor in the conventional ferroelectric memory. It is a schematic diagram which shows the ferroelectric capacitor in the ferroelectric memory of this invention. FIG. 3 is a cross-sectional view showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the first embodiment in the order of steps. FIG. 5 is a cross-sectional view showing the manufacturing method of the ferroelectric memory according to the first embodiment in the order of steps, following FIG. 4. FIG. 6 is a cross-sectional view showing the method of manufacturing the ferroelectric memory according to the first embodiment in the order of steps, following FIG. 5. FIG. 7 is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory according to the first embodiment in the order of processes, following FIG. 6. FIG. 8 is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory according to the first embodiment in the order of steps, following FIG. 7. It is a figure which shows orientation of the crystal plane of the upper electrode located in an interface with a ferroelectric film by X-ray diffraction. It is sectional drawing which shows the manufacturing method of the ferroelectric memory (semiconductor device) which concerns on 2nd Embodiment to process order. FIG. 11 is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory according to the second embodiment in order of processes following FIG. 10. FIG. 12 is a cross-sectional view illustrating the method of manufacturing the ferroelectric memory according to the second embodiment in order of processes following FIG. 11. FIG. 13 is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory according to the second embodiment in order of processes following FIG. 12. FIG. 14 is a cross-sectional view showing the method of manufacturing the ferroelectric memory according to the second embodiment in order of processes following FIG. 13. FIG. 6 is a characteristic diagram showing a first test result obtained by measuring an inversion charge amount of a ferroelectric capacitor in the ferroelectric memory. FIG. 11 is a characteristic diagram showing a second test result obtained by measuring the inversion charge amount of the ferroelectric capacitor in the ferroelectric memory. It is a characteristic view showing the 3rd test result which measured the coercive voltage of the ferroelectric capacitor in a ferroelectric memory. It is a characteristic view showing the 4th test result which measured the relation between the applied voltage of a ferroelectric capacitor and the amount of inversion charges in a ferroelectric memory. It is a characteristic view which shows the 5th test result which measured the fatigue loss of the ferroelectric capacitor in a ferroelectric memory. It is a characteristic view showing the 6th test result which measured the imprint characteristic of the ferroelectric capacitor in a ferroelectric memory. The seventh test result is shown, and in the manufacturing method according to the first embodiment, the oxygen flow rate in the deposition gas when forming the IrO _x film crystallized at the time of deposition on the ferroelectric film. It is a characteristic view of the inversion charge amount of the ferroelectric capacitor with respect to each ratio. The seventh test result is shown, and in the manufacturing method according to the first embodiment, the oxygen flow rate in the deposition gas when forming the IrO _x film crystallized at the time of deposition on the ferroelectric film. It is a characteristic view of the inversion charge amount of the ferroelectric capacitor with respect to each ratio. The seventh test result is shown, and in the manufacturing method according to the first embodiment, the oxygen flow rate in the deposition gas when forming the IrO _x film crystallized at the time of deposition on the ferroelectric film. It is a characteristic view of the coercive voltage of the ferroelectric capacitor for each ratio. The seventh test result is shown, and in the manufacturing method according to the first embodiment, the oxygen flow rate in the deposition gas when forming the IrO _x film crystallized at the time of deposition on the ferroelectric film. It is a characteristic view which shows the relationship between the applied voltage of a ferroelectric capacitor and the amount of inversion charges with respect to each ratio. The seventh test result is shown, and in the manufacturing method according to the present invention, each ratio of the oxygen flow rate in the film forming gas when forming the IrO _x film crystallized at the time of film formation on the ferroelectric film FIG. 5 is a characteristic diagram of a leakage current value of a ferroelectric capacitor with respect to FIG. The seventh test result is shown, and in the manufacturing method according to the present invention, each ratio of the oxygen flow rate in the film forming gas when forming the IrO _x film crystallized at the time of film formation on the ferroelectric film FIG. 5 is a characteristic diagram of a leakage current value of a ferroelectric capacitor with respect to FIG. Shows an eighth test results, in the manufacturing method according to the first embodiment, the strength on the dielectric film, a ferroelectric capacitor with respect to the thickness for forming the IrO _x film is crystallized at the time of film formation It is a characteristic view of the inversion charge amount _QSW . Shows an eighth test results, in the manufacturing method according to the first embodiment, the strength on the dielectric film, a ferroelectric capacitor with respect to the thickness for forming the IrO _x film is crystallized at the time of film formation It is a characteristic view of the inversion charge amount _QSW . Shows an eighth test results, in the manufacturing method according to the first embodiment, the strength on the dielectric film, a ferroelectric capacitor with respect to the thickness for forming the IrO _x film is crystallized at the time of film formation It is a characteristic view of the leakage current value. FIG. 9 shows a ninth test result. In the manufacturing method according to the second embodiment, an oxygen flow rate in a film forming gas when forming an IrO _x film crystallized at the time of film formation on a ferroelectric film. It is a characteristic view of the inversion charge amount of the ferroelectric capacitor with respect to the ratio. FIG. 9 shows a ninth test result. In the manufacturing method according to the second embodiment, an oxygen flow rate in a film forming gas when forming an IrO _x film crystallized at the time of film formation on a ferroelectric film. It is a characteristic view of the leakage current value of the ferroelectric capacitor with respect to the ratio. 10 shows the test results, in the manufacturing method according to the second embodiment, the strength on the dielectric film, a ferroelectric capacitor for annealing temperature after forming the IrO _x film is crystallized at the time of film formation FIG. 10 shows the test results, in the manufacturing method according to the second embodiment, the strength on the dielectric film, a ferroelectric capacitor for annealing temperature after forming the IrO _x film is crystallized at the time of film formation It is a characteristic view of the leakage current value. 11 shows a result of an eleventh test, and in the manufacturing method according to the second embodiment, a ferroelectric capacitor with respect to a film thickness when an IrO _x film crystallized at the time of film formation is formed on the ferroelectric film. It is a characteristic view of the inversion charge amount _QSW . 11 shows a result of an eleventh test, and in the manufacturing method according to the second embodiment, a ferroelectric capacitor with respect to a film thickness when an IrO _x film crystallized at the time of film formation is formed on the ferroelectric film. It is a characteristic view of the leakage current value. It is a figure which shows the hysteresis loop which shows the relationship between the applied voltage of a ferroelectric capacitor, and the amount of polarization.

-Outline of the present invention-
In order to realize low voltage operation and increase the operation speed in the ferroelectric memory, the present inventor firstly determines the thickness of the ferroelectric film in the conventional ferroelectric memory and the inversion charge amount Q of the ferroelectric capacitor. _We decided to investigate the relationship between _SW and its coercive voltage Vc.

The inventor actually manufactured a ferroelectric capacitor using a conventional manufacturing method (the manufacturing method described in Patent Document 2), and measured the inversion charge amount _QSW and the coercive voltage Vc. FIG. 1 shows the measurement results. FIG. 1A is a characteristic diagram showing the relationship between the thickness of the ferroelectric film and the inversion charge amount Q _SW, and FIG. 1B shows the relationship between the thickness of the ferroelectric film and the coercive voltage Vc. FIG.

In FIG. 1A, Q _SW1 (“◆”) and Q _SW2 (“▲”) indicate the results of a ferroelectric capacitor whose planar shape is a square having a length of 50 μm, and Q _SW3 (“■”). “)” Shows the result of the ferroelectric capacitor whose planar shape is a rectangle having a long side length of 1.60 μm and a short side length of 1.15 μm. Q _SW2 (“▲”) and Q _SW3 (“■”) indicate the results of measurements performed after the wiring was formed on the upper electrode, and Q _SW1 (“◆”) represents the upper electrode. Fig. 6 shows the results of measurement performed before forming the wiring. FIG. 1A shows the average data of 1428 pieces.

In measuring the coercive voltage Vc in FIG. 1B, a hysteresis loop indicating the relationship between the applied voltage and the polarization amount of the ferroelectric capacitor shown in FIG. 36 is obtained, and the change in the polarization amount with respect to the change in the predetermined applied voltage is obtained. The applied voltage with the largest ratio was defined as the coercive voltage Vc. In FIG. 1B, Vc (−) (“♦”) indicates the coercive voltage when the polarization amount change is negative, and Vc (+) (“▲”) indicates the case where the polarization amount change is positive. Indicates coercive voltage. Further, the inversion charge amount Q _SW in FIG. 1A is a value obtained by the following formula 1 using values P, U, N, and D obtained from the hysteresis loop shown in FIG. Here, P is the value of the maximum polarization inversion amount of the capacitor when a voltage is applied in the positive direction, U is the value of the polarization non-inversion amount of the capacitor when a voltage is applied in the positive direction, and N is the voltage in the reverse direction. The value of the maximum polarization reversal amount of the capacitor when applied, and D is the value of the polarization non-reversal amount of the capacitor when a voltage is applied in the reverse direction.

From the results shown in FIG. 1 (a), it was confirmed that the inversion charge amount _QSW significantly decreased as the thickness of the ferroelectric film made of PZT was reduced. Further, from the result shown in FIG. 1B, it was confirmed that the rate of decrease in the coercive voltage Vc decreases as the thickness of the ferroelectric film decreases.

As a result of intensive studies on this cause, the present inventor paid attention to the laminated portion of the ferroelectric film and the upper electrode formed thereon in the conventional ferroelectric capacitor. When the electrode is formed, iridium oxide (IrO ₂ ), which is the material of the upper electrode, reacts with the upper part of the ferroelectric film made of PZT, and as a result, the ferroelectric characteristics of the ferroelectric film are deteriorated. I found out.

FIG. 2 is a schematic diagram showing a ferroelectric capacitor in a conventional ferroelectric memory.
As shown in FIG. 2, in the conventional manufacturing method, even if the ferroelectric film 202 made of PZT is formed with a thickness d on the lower electrode 201 made of Pt or the like, the upper part made of iridium oxide (IrO ₂ ). A mutual reaction between the ferroelectric film 202 and the upper electrode 203 occurs due to heat treatment after the electrode 203 is formed, and an interface layer 204 is formed between the ferroelectric film 202 and the upper electrode 203. understood. Due to this interaction, the portion of the thickness d ₁ of the thickness d of the ferroelectric film 202 cannot sufficiently function as a ferroelectric.

In the conventional manufacturing method, it was found that the upper electrode 203 formed on the ferroelectric film 202 was in an amorphous state at the time of film formation, and columnar crystals existed thereon. Since the amorphous portion appears as large crystal grains by heat treatment such as recovery annealing, the interface layer 204 is formed relatively thick, and the thickness d _{1 of the} portion that does not sufficiently function as a ferroelectric is also obtained. growing.

The present inventors, as a result of the thickness d ₁ is increased, with decreasing the polarization inversion amount Q _SW occurs, becomes loose rise of the hysteresis loop showing a change in the polarization inversion amount Q _SW with respect to the applied voltage, the coercive voltage Vc I thought that it would be difficult to make it smaller. The inventor believes that the thickness d ₁ is almost independent of the thickness d of the ferroelectric film. Therefore, as the thickness d of the ferroelectric film 202 decreases, the thickness d 1 increases. The ratio of the thickness d ₁ of the portion that does not sufficiently function as a dielectric increases, and as a result, the above-described problem in the ferroelectric characteristics is considered to be remarkable.

  The present inventor also conceived another mechanism in which the ferroelectric characteristics deteriorate due to the amorphous state of the upper electrode 203 being formed into large crystal grains by heat treatment.

  The present inventor has found that the crystal vacancies increase with the coarsening of the crystal grains, and hydrogen generated during the formation of the wiring layer or the like enters the ferroelectric film 202 through the diffusion path 205 via the crystal vacancies. As a result, it was considered that the characteristics of the ferroelectric film 202 deteriorated.

  For example, when the upper electrode 203 includes a metal film such as Pt or Ir, hydrogen used when forming an interlayer insulating film in a multilayer wiring structure enters the metal film, and the catalyst that these metals have It is activated by action. Then, the present inventor finds that when the activated hydrogen enters the ferroelectric film 202 through the diffusion path 205 and the ferroelectric film 202 is reduced, the characteristic deterioration of the ferroelectric film 202 occurs. Thought. In this case, the increase in crystal vacancies in the interface layer 204 results in the presence of many hydrogen diffusion paths 205, so that it is considered that the characteristic deterioration of the ferroelectric film 202 becomes more remarkable. Further, it is considered that the deterioration of the characteristics of the ferroelectric film 202 becomes conspicuous even when the number of times of processing in a reducing atmosphere or a non-oxidizing atmosphere is increased in order to form a multilayer wiring structure.

  That is, the present inventor avoids the formation of the interface layer 204 with coarse crystal grains between the ferroelectric film and the formation of the upper electrode. Improved implementation and operating speed.

FIG. 3 is a schematic diagram showing a ferroelectric capacitor in the ferroelectric memory of the present invention.
As shown in FIG. 3, the present inventor, when forming the upper electrode 303 on the ferroelectric film 302 formed on the lower electrode 301, the conductive state in the crystallized state is directly above the ferroelectric film 302. It was conceived that the oxide film 303a is formed, that is, the conductive oxide film 303a crystallized at the time of film formation is provided at the interface with the ferroelectric film 302. Then, a conductive film 303b is formed on the conductive oxide film 303a to form an upper electrode 303.

Then, the present inventor reduces the interaction with the ferroelectric film 202 by providing a conductive oxide film 303a such as IrO _x crystallized at the time of film formation on the ferroelectric film 302. In addition, coarsening of crystal grains due to subsequent heat treatment or the like was suppressed. Incidentally, Patent Document 3, the ferroelectric film, a conductive oxide film as iridium oxide _{(IrO X: 0 <x <} 2) are described to form a film, at the time of film formation There is no disclosure or suggestion about depositing what is crystallized, and this is different from the present invention.

As a result, the portion (d−d ₂ ; d ₂ <d ₁ ) functioning as the ferroelectric film 302 can be made wider than the conventional ferroelectric capacitor shown in FIG. Intrusion hydrogen can be suppressed, and the low-voltage operation and the operation speed can be improved in the ferroelectric memory.

-Specific embodiment of the present invention-
Next, embodiments of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
The first embodiment of the present invention will be described below.
In the first embodiment, a planar type ferroelectric memory in which an upper electrode and a lower electrode of a ferroelectric capacitor are electrically connected from above will be described. However, here, for the sake of convenience, the sectional structure of the ferroelectric memory will be described together with its manufacturing method.

4 to 8 are cross-sectional views showing the method of manufacturing the ferroelectric memory (semiconductor device) according to the first embodiment in the order of steps.
In the first embodiment, first, as shown in FIG. 4A, the element isolation insulating film 2 and, for example, the p-well 21 are formed on the semiconductor substrate 1, and the MOSFET 100 is further formed on the semiconductor substrate 1. At the same time, a silicon oxynitride film 7, a silicon oxide film 8a, an Al ₂ O ₃ film 8b, and a lower electrode film 9a are sequentially formed on the MOSFET 100.

Specifically, first, an element isolation insulating film 2 is formed in an element isolation region of a semiconductor substrate 1 such as a Si substrate by, for example, a LOCOS (Local Oxidation of Silicon) method to define an element formation region. Subsequently, boron (B), for example, is ion-implanted into the surface of the element formation region of the semiconductor substrate 1 under the conditions of an energy of 300 keV and a dose of 3.0 × 10 ¹³ cm ⁻² to form a p-well 21. To do. Subsequently, a silicon oxide film having a thickness of about 3 nm is formed on the semiconductor substrate 1 by, eg, thermal oxidation. Subsequently, a polycrystalline silicon film having a thickness of about 180 nm is formed on the silicon oxide film by a CVD method. Subsequently, patterning is performed to leave the polycrystalline silicon film and the silicon oxide film only in the element formation region, thereby forming the gate insulating film 3 made of the silicon oxide film and the gate electrode 4 made of the polycrystalline silicon film.

Subsequently, using the gate electrode 4 as a mask, for example, phosphorus (P) is ion-implanted into the surface of the semiconductor substrate 1 under the conditions of an energy of 20 keV and a dose of 4.0 × 10 ¹³ cm ⁻² , for example, n ^−. A low concentration diffusion layer 22 of the mold is formed. Subsequently, after a SiO ₂ film having a thickness of about 300 nm is formed on the entire surface by CVD, anisotropic etching is performed to leave the SiO ₂ film only on the side wall of the gate electrode 4 to form the side wall 6. Form.

Subsequently, for example, arsenic (As) is ion-implanted into the surface of the semiconductor substrate 1 using the gate electrode 4 and the sidewalls 6 as a mask, for example, under conditions of an energy of 10 keV and a dose of 5.0 × 10 ¹³ cm ^−2. Thus, the n ⁺ -type high concentration diffusion layer 23 is formed.

  Subsequently, for example, a Ti film is deposited on the entire surface by sputtering. Thereafter, a heat treatment at a temperature of 400 ° C. to 900 ° C. is performed to cause a silicide reaction between the polycrystalline silicon film of the gate electrode 4 and the Ti film, and a silicide layer 5 is formed on the upper surface of the gate electrode 4. Thereafter, the unreacted Ti film is removed using hydrofluoric acid or the like. As a result, the MOSFET 100 including the gate insulating film 3, the gate electrode 4, the silicide layer 5, the sidewall 6, and the source / drain diffusion layer including the low concentration diffusion layer 22 and the high concentration diffusion layer 23 on the semiconductor substrate 1 is formed. It is formed. In the present embodiment, the description has been given by taking the formation of an n-channel MOSFET as an example, but a p-channel MOSFET may be formed.

Subsequently, a silicon oxynitride film 7 having a thickness of about 200 nm is formed by CVD to cover the MOSFET 100. Subsequently, a silicon oxide film 8a having a thickness of about 700 nm is formed on the silicon oxynitride film 7 by a CVD method. Thereafter, the silicon oxide film 8a is degassed by performing an annealing process at a temperature of 650 ° C. for about 30 minutes in an N ₂ atmosphere. The silicon oxynitride film 7 is formed to prevent hydrogen deterioration of the gate insulating film 3 and the like when the silicon oxide film 8a is formed.

Subsequently, an Al ₂ O ₃ film 8b having a thickness of about 20 nm is formed on the silicon oxide film 8a as a lower electrode adhesion film by, eg, sputtering. Note that a Ti film or a TiO _x film having a thickness of about 20 nm may be formed as the lower electrode adhesion layer. Subsequently, a lower electrode film 9a is formed on the Al ₂ O ₃ film 8b. As the lower electrode film 9a, for example, a Pt film having a thickness of about 150 nm is formed by sputtering. When the lower electrode adhesion film is a Ti film having a thickness of about 20 nm, a laminate of the lower electrode adhesion film made of the Ti film and the lower electrode film 9a made of a Pt film having a thickness of about 180 nm is formed. Also good. In this case, for example, the Ti film is formed at a temperature of about 150 ° C., and the Pt film is formed at a temperature of 100 ° C. to 350 ° C.

Next, as shown in FIG. 4B, a ferroelectric film 10a to be a capacitor film is formed in an amorphous state on the lower electrode film 9a. As the ferroelectric film 10a, for example, a LaZ-doped PZT (PLZT: (Pb, La) (Zr, Ti) O ₃ ) target is used, and a PLZT film having a thickness of 100 nm to 200 nm is formed by RF sputtering. . Thereafter, heat treatment (RTA) at 650 ° C. or lower is performed in an atmosphere containing Ar and O ₂ , and further RTA is performed at about 750 ° C. in an oxygen atmosphere. As a result, the ferroelectric film 10a is completely crystallized, the Pt film constituting the lower electrode film 9a is densified, and Pt and O in the vicinity of the interface between the lower electrode film 9a and the ferroelectric film 10a Diffusion is suppressed.

  In this embodiment, the ferroelectric film 10a is formed by the sputtering method, but is not limited to this. For example, the sol-gel method, the organometallic decomposition method, the CSD method, the chemical method is used. It can also be formed by vapor deposition, epitaxial growth, or MO-CVD.

Next, as shown in FIG. 4C, the IrO _x film 11a in a crystallized state is formed on the ferroelectric film 10a with a thickness of about 50 nm by sputtering using iridium (Ir) as a target. . The IrO _x film 11a functions as a lower layer film of the upper electrode. At this time, the value of X is in a range of 1.1 <X <2.0. As sputtering conditions at this time, under conditions where oxidation of iridium (Ir) occurs, for example, a film forming temperature is set to about 300 ° C., and Ar and O ₂ are used as film forming gases, and these are all supplied at a flow rate of about 100 sccm. In addition, the power during sputtering is set to about 1 kW to 2 kW.

In the present embodiment, an example in which an IrO _x film made of iridium oxide is applied as a film crystallized at the time of film formation is shown, but the present invention is not limited to this. For example, a film composed of at least one oxide selected from the group consisting of platinum oxide, ruthenium oxide, rhodium oxide, rhenium oxide, osmium oxide and palladium oxide may be applied. Is possible. In this case, a target including at least one noble metal element selected from the group consisting of platinum (Pt), ruthenium (Ru), rhodium (Rh), rhenium (Re), osmium (Os), and palladium (Pd) is used. The sputtering is performed under conditions where oxidation of the noble metal element occurs.

Next, as shown in FIG. 5A, an IrO _Y film 11b, which is a conductive film, is formed on the IrO _x film 11a by sputtering to a thickness of about 200 nm. Here, the IrO _Y film 11b does not need to be crystallized at the time of film formation. For example, the value of Y is in the range of 1.8 <Y <2.2. The IrO _x film 11a functions as an upper layer film of the upper electrode.

In the present embodiment, an example in which an IrO _Y film made of iridium oxide is applied as the conductive film formed on the IrO _x film 11a is shown. However, the present invention is not limited to this. For example, at least one noble metal selected from the group consisting of iridium (Ir), platinum (Pt), ruthenium (Ru), rhodium (Rh), rhenium (Re), osmium (Os) and palladium (Pd) It is also possible to apply a metal film containing an element, a conductive oxide film containing these noble metal elements, or a conductive oxide such as SrRuO ₃ .

Then, after the back washing of the semiconductor substrate 1 by patterning the IrO _x film 11a and IrO _Y film 11b, as shown in FIG. 5 (b), the upper consisting of IrO _x film 11a and IrO _Y film 11b The electrode 11 is formed. Thereafter, recovery annealing is performed in an O ₂ atmosphere at a temperature of about 650 ° C. for about 60 minutes. This heat treatment is for recovering physical damage or the like received by the ferroelectric film 10a when the upper electrode 11 is formed.

Next, as shown in FIG. 5C, the ferroelectric film 10a is patterned to form the ferroelectric film 10 that becomes the capacitor film of the ferroelectric capacitor. Thereafter, oxygen annealing for preventing peeling of an Al ₂ O ₃ film to be formed later is performed.

Next, as shown in FIG. 6A, an Al ₂ O ₃ film 12 is formed on the entire surface as a protective film by sputtering. Thereafter, oxygen annealing is performed in order to reduce damage caused by sputtering. The Al ₂ O ₃ film 12 prevents hydrogen from entering the ferroelectric capacitor from the outside.

Next, as shown in FIG. 6B, the lower electrode 9 is formed by patterning the Al ₂ O ₃ film 12 and the lower electrode film 9a. Thereafter, oxygen annealing for preventing peeling of an Al ₂ O ₃ film to be formed later is performed.

Next, as shown in FIG. 6C, an Al ₂ O ₃ film 13 is formed on the entire surface by a sputtering method as a protective film. Thereafter, oxygen annealing is performed to reduce capacitor leakage.

  Next, as shown in FIG. 7A, an interlayer insulating film 14 is formed on the entire surface by HDP-CVD (high density plasma CVD). The thickness of the interlayer insulating film 14 is, for example, about 1.5 μm.

Next, as shown in FIG. 7B, the interlayer insulating film 14 is planarized by a CMP (Chemical Mechanical Polishing) method. Thereafter, plasma treatment using N ₂ O gas is performed. As a result, the surface layer portion of the interlayer insulating film 14 is slightly nitrided, making it difficult for moisture to enter the inside. This plasma treatment is effective if performed using a gas containing at least one of N and O. Subsequently, a via hole 15z reaching the high concentration diffusion layer 23 of the MOSFET 100 is formed in the interlayer insulating film 14, the Al ₂ O ₃ film 13, the Al ₂ O ₃ film 8b, the silicon oxide film 8a, and the silicon oxynitride film 7. . Thereafter, a Ti film and a TiN film are successively stacked in the via hole 15z by sputtering, thereby forming a glue film 15a on the inner wall of the via hole 15z. Subsequently, after depositing a W film having a thickness sufficient to fill the via hole 15z by the CVD method, the W film is planarized until the surface of the interlayer insulating film 14 is exposed by the CMP method. A W plug 15 is formed in the hole 15z.

  Next, as shown in FIG. 7C, a SiON film 16 is formed as an antioxidant film for the W plug 15 by, for example, a plasma enhanced CVD method.

Next, as shown in FIG. 8A, by etching, the via hole 17y reaching the upper electrode 11 and the via hole 17z reaching the lower electrode 9 are formed into the SiON film 16, the interlayer insulating film 14, and the Al. _{A 2} O ₃ film 13 and an Al ₂ O ₃ film 12 are formed. Thereafter, oxygen annealing is performed in order to recover the damage of the ferroelectric film 10 due to the influence of the etching.

  Next, as shown in FIG. 8B, first, the surface of the W plug 15 is exposed by removing the SiON film 16 over the entire surface by etch back. Subsequently, a Ti film and a TiN film are successively laminated in the via hole 17y and the via hole 17z by a sputtering method, thereby forming a glue film 17a on the inner wall of each via hole. Subsequently, after depositing a W film having a thickness sufficient to fill the via holes 17y and 17z by CVD, the W film is planarized by CMP until the surface of the interlayer insulating film 14 is exposed. Thus, the W plug 17 is formed in the via hole 17y and the via hole 17z.

Next, as shown in FIG. 8C, a metal wiring layer composed of the glue film 18a, the wiring film 18 and the glue film 18b is formed.
Specifically, first, a Ti film having a thickness of approximately 60 nm, a TiN film having a thickness of approximately 30 nm, an AlCu alloy film having a thickness of approximately 360 nm, a Ti film having a thickness of approximately 5 nm, and a thickness are formed on the front surface by, for example, sputtering. A TiN film having a thickness of about 70 nm is sequentially stacked. Subsequently, the laminated film is patterned into a predetermined shape using a photolithography technique, and a glue film 18a made of a Ti film and a TiN film and a wiring film 18 made of an AlCu alloy film are formed on the W plugs 15 and 17, respectively. Then, a metal wiring layer made of the Ti film and the glue film 18b made of the TiN film is formed. At this time, the metal wiring layer connected to the W plug 15 and the metal wiring layer connected to the upper electrode 11 or the metal wiring layer connected to the lower electrode 9 are connected to each other at a part of the wiring film 18.

  Thereafter, further formation of an interlayer insulating film, formation of contact plugs, formation of wiring from the second layer onward, and the like are performed. Then, for example, a strong film according to this embodiment having a ferroelectric capacitor including the lower electrode 9, the ferroelectric film 10, and the lower electrode 11 is formed by forming a cover film made of a TEOS (tetraethyl orthosilicate) oxide film and a SiN film. A dielectric memory is completed.

In the present embodiment, as described above, when the upper electrode 11 is formed, the crystallized IrO _x film 11a is formed on the ferroelectric film 10, so that the upper layer of the ferroelectric film 10 is It is difficult to react with the IrO _x film 11a, and the formation of the interface layer is suppressed. Accordingly, since many portions functioning as ferroelectrics remain in the ferroelectric film 10, a sufficient amount of inversion polarization Q _SW can be obtained. Further, since the IrO _x film 11a is crystallized at the time of film formation, the crystal growth can be suppressed even when heat treatment such as recovery annealing is performed thereafter. As a result, even during a heat treatment in a subsequent reducing atmosphere, hydrogen does not easily diffuse into the ferroelectric film 10, and good ferroelectric characteristics can be obtained.

That is, according to the present embodiment, the interface between the upper electrode 11 and the ferroelectric film 10 can be improved, and the yield in the manufacturing process can be improved. As a result, the inversion charge amount _QSW can be improved and the coercive voltage Vc can be remarkably reduced, and fatigue resistance and imprint resistance can be improved as compared with the conventional ferroelectric memory. Such a ferroelectric capacitor is extremely suitable for a ferroelectric memory that operates at a next-generation low voltage.

FIG. 9 is a diagram showing the orientation of the crystal plane of the upper electrode located at the interface with the ferroelectric film by X-ray diffraction. The solid line in FIG. 9 indicates the orientation of the crystal plane of the IrO _x film 11a, and the dotted line indicates the orientation of the crystal plane in the initial layer of the upper electrode formed by the conventional manufacturing method.

As shown in FIG. 9, the initial layer of the upper electrode formed by the conventional manufacturing method has a crystal plane slightly oriented to the (110) plane, but the IrO _x film 11a has its crystal It can be seen that the plane is strongly oriented in the (110) plane and the (200) plane. Thus, there is a great difference in the orientation of crystal planes in the initial layer of the upper electrode between the conventional manufacturing method and the manufacturing method according to the present invention.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
In the first embodiment, the planar type ferroelectric memory has been described. However, in the second embodiment, the upper electrode of the ferroelectric capacitor is electrically connected from above, and the lower electrode of the ferroelectric capacitor is electrically connected. A stack-type ferroelectric memory that has a general connection from below will be described. However, here, the cross-sectional structure of the ferroelectric memory will be described together with its manufacturing method.

10 to 14 are cross-sectional views showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the second embodiment in the order of steps.
In the second embodiment, first, as shown in FIG. 10A, an element isolation insulating film 62 and, for example, a p-well 91 are formed on a semiconductor substrate 61, and MOSFETs 101 and 102 are further formed on the semiconductor substrate 61. And an SiON film 67 covering each MOSFET is formed.

Specifically, first, an element isolation insulating film 62 is formed in an element isolation region of a semiconductor substrate 61 such as a Si substrate by, for example, an STI (Shallow Trench Isolation) method to define an element formation region. Subsequently, boron (B), for example, is ion-implanted into the surface of the element formation region of the semiconductor substrate 61 under the conditions of an energy of 300 keV and a dose of 3.0 × 10 ¹³ cm ⁻² to form a p-well 91. To do. Subsequently, a silicon oxide film having a thickness of about 3 nm is formed on the semiconductor substrate 61 by, eg, thermal oxidation. Subsequently, a polycrystalline silicon film having a thickness of about 180 nm is formed on the silicon oxide film by a CVD method. Subsequently, patterning is performed to leave the polycrystalline silicon film and the silicon oxide film only in the element formation region, thereby forming a gate insulating film 63 made of a silicon oxide film and a gate electrode 64 made of a polycrystalline silicon film.

Subsequently, the gate electrode 64 as a mask, the surface of the semiconductor substrate 61, for example, phosphorus (P), for example, energy 13 keV, and ion implantation with a dose of ^{5.0 × 10 14 cm -2, n} - A low concentration diffusion layer 92 of the mold is formed. Subsequently, after a SiO ₂ film having a thickness of about 300 nm is formed on the entire surface by CVD, anisotropic etching is performed to leave the SiO ₂ film only on the side wall of the gate electrode 64, thereby forming the sidewall 66. Form.

Subsequently, for example, arsenic (As) is ion-implanted into the surface of the semiconductor substrate 61 using the gate electrode 64 and the sidewalls 66 as a mask under the conditions of an energy of 10 keV and a dose of 5.0 × 10 ¹⁴ cm ⁻² . An n ⁺ type high concentration diffusion layer 93 is formed.

  Subsequently, for example, a Ti film is deposited on the entire surface by sputtering. Thereafter, by performing a heat treatment at a temperature of 400 ° C. to 900 ° C., the polysilicon film of the gate electrode 64 and the Ti film undergo a silicide reaction, and a silicide layer 65 is formed on the upper surface of the gate electrode 64. Thereafter, the unreacted Ti film is removed using hydrofluoric acid or the like. As a result, the MOSFET 101 having the gate insulating film 63, the gate electrode 64, the silicide layer 65, the sidewall 66, and the source / drain diffusion layer including the low concentration diffusion layer 92 and the high concentration diffusion layer 93 on the semiconductor substrate 61, 102 is formed. In the present embodiment, the description has been given by taking the formation of an n-channel MOSFET as an example, but a p-channel MOSFET may be formed. Subsequently, a SiON film 67 having a thickness of about 200 nm is formed on the front surface by plasma CVD.

  Next, as shown in FIG. 10B, a silicon oxide film having a thickness of about 1000 nm is deposited on the SiON film 67 by the plasma CVD method, and then planarized by the CMP method to be made of a silicon oxide film. An interlayer insulating film 68 is formed with a thickness of about 700 nm. Subsequently, a via hole 69z reaching the high concentration diffusion layer 93 of each MOSFET is formed in the interlayer insulating film 68 and the SiON film 67 with a diameter of, for example, about 0.25 μm. Thereafter, a glue film 69a is formed in the via hole 69z by successively laminating a Ti film with a thickness of about 30 nm and a TiN film with a thickness of about 20 nm by sputtering. Subsequently, a W film having a thickness sufficient to fill each via hole 69z is deposited by CVD, and then the W film is planarized by CMP until the surface of the interlayer insulating film 68 is exposed. Thus, W plugs 69b and 69c are formed in the via hole 69z. Here, the W plug 69b is connected to one of the source / drain diffusion layers of each MOSFET, and the W plug 69c is connected to the other.

  Next, as shown in FIG. 10C, a SiON film 70 serving as an antioxidant film having a thickness of about 130 nm is formed on the front surface by plasma CVD. Subsequently, an interlayer insulating film 71 made of a silicon oxide film having a thickness of about 300 nm is formed on the SiON film 70 by plasma CVD using TEOS as a raw material. Subsequently, a via hole 72z exposing the surface of the W plug 69b is formed in the interlayer insulating film 71 and the SiON film 70 with a diameter of, for example, about 0.25 μm. Thereafter, a glue film 72a is formed in the via hole 72z by continuously laminating a Ti film with a thickness of about 30 nm and a TiN film with a thickness of about 20 nm by sputtering. Subsequently, after depositing a W film having a thickness sufficient to fill each via hole 72z by CVD, the W film is planarized by CMP until the surface of the interlayer insulating film 71 is exposed. Thus, the W plug 72b is formed in the via hole 72z.

Thereafter, the surface of the interlayer insulating film 71 is treated with NH ₃ (ammonia) plasma to bond NH groups to oxygen atoms on the surface of the interlayer insulating film 71. This ammonia plasma treatment is performed using, for example, a parallel plate type plasma treatment apparatus having a counter electrode at a position separated from the semiconductor substrate 61 by about 9 mm (350 mils), a pressure of about 266 Pa (2 Torr), and a substrate temperature of about 400 ° C. Is supplied at a flow rate of about 350 sccm, a high frequency of about 13.56 MHz is supplied to the semiconductor substrate 61 with a power of about 100 W, and a high frequency of about 350 kHz is supplied to the counter electrode with a power of about 55 W, respectively. It is performed by supplying in about 60 seconds.

Next, as shown in FIG. 11A, a TiN film 73 is formed on the interlayer insulating film 71 and the W plug 72b.
Specifically, first, on the front surface, for example, using a sputtering apparatus in which the distance between the semiconductor substrate 61 and the target is set to about 60 mm, the substrate temperature is about 20 ° C. in an Ar atmosphere at a pressure of about 0.15 Pa. A Ti film is formed by sputtering which supplies DC power of about 2.6 kW for about 7 seconds. Since this Ti film is formed on the interlayer insulating film 71 that has been subjected to the ammonia plasma treatment, the Ti atoms are freely captured on the surface of the interlayer insulating film 71 without being captured by the oxygen atoms of the interlayer insulating film 71. As a result, a self-organized Ti film having a crystal plane oriented in the (002) plane is obtained. Subsequently, the TiN film 73 is formed by performing an RTA process on the Ti film in a nitrogen atmosphere at a temperature of about 650 ° C. for about 60 seconds. Here, the TiN film 73 has a crystal plane oriented in the (111) plane.

Next, as shown in FIG. 11B, a TiAlN film 74a having a thickness of about 100 nm is formed on the TiN film 73 by a reactive sputtering method using a target obtained by alloying Ti and Al. This TiAlN film 74a is formed, for example, by sputtering under conditions of a pressure of about 253.3 Pa, a substrate temperature of about 400 ° C., and a power of about 1.0 kW in a mixed atmosphere where Ar is about 40 sccm and nitrogen is about 10 sccm. It is formed. This TiAlN film 74a functions as a lower layer film of the lower electrode. Subsequently, an Ir film 74b having a thickness of about 100 nm is formed on the TiAlN film 74a by, for example, sputtering in an Ar atmosphere under conditions of a pressure of about 0.11 Pa, a substrate temperature of about 500 ° C., and a power of about 0.5 kW. To do. This Ir film 74b functions as an upper film of the lower electrode. In place of the Ir film 74b, a metal such as Pt or a conductive oxide such as PtO, IrO _x , SrRuO ₃ can also be used. Further, the film constituting the lower electrode may be a laminated film of metal or metal oxide.

  Next, as shown in FIG. 11C, a ferroelectric film 75 serving as a capacitor film is formed on the Ir film 74b by MO-CVD. Specifically, the ferroelectric film 75 of this embodiment is formed of a PZT film (a first PZT film 75a and a second PZT film 75b) having a two-layer structure.

More specifically, first, Pb (DPM) ₂ , Zr (dmhd) ₄ and Ti (O—iOr) ₂ (DPM) ₂ are each added to a THF (Tetra Hydro Furan: C ₄ H ₈ O) solvent. Is dissolved at a concentration of about 0.3 mol / l to form liquid materials of Pb, Zr and Ti. Further, these liquid raw materials are supplied to the vaporizer of the MO-CVD apparatus together with a THF solvent having a flow rate of about 0.474 ml / min, about 0.326 ml / min, about 0.200 ml / min, and about 0.200 ml / min, respectively. Pb, Zr and Ti source gases are formed by supplying and vaporizing at a flow rate of. Then, in the MO-CVD apparatus, by supplying Pb, Zr and Ti source gases for about 620 seconds under conditions of a pressure of about 665 Pa (5 Torr) and a substrate temperature of about 620 ° C., the thickness is increased on the Ir film 74b. A first PZT film 75a having a thickness of about 100 nm is formed.

Subsequently, an amorphous second PZT film 75b having a thickness of 1 nm to 30 nm, in this embodiment, about 20 nm is formed on the entire surface by, eg, sputtering. Further, when the second PZT film 75b is formed by the MO-CVD method, Pb (DPM) ₂ (Pb (C ₁₁ H ₁₉ O ₂ ) ₂ ) is used as an organic source for supplying lead (Pb) in a THF solution. A material dissolved in is used. Further, as an organic source for supplying zirconium (Zr), a material in which Zr (DMHD) ₄ (Zr ((C ₉ H ₁₅ O ₂ ) ₄ ) is dissolved in a THF solution is used. As the organic source, a material in which Ti (O—iPr) ₂ (DPM) ₂ (Ti (C ₃ H ₇ O) ₂ (C ₁₁ H ₁₉ O ₂ ) ₂ ) is dissolved in a THF solution is used.

  In the present embodiment, the ferroelectric film 75 is formed by the MO-CVD method and the sputtering method. However, the present invention is not limited to this. For example, the sol-gel method, the organometallic decomposition is performed. It can also be formed by a method, a CSD method, a chemical vapor deposition method or an epitaxial growth method.

Next, as shown in FIG. 12A, a crystallized IrO _x film 76a having a thickness of about 50 nm is formed on the second PZT film 75b by sputtering using iridium as a target. The IrO _x film 76a functions as a lower layer film of the upper electrode. At this time, the value of X is in the range of 1.0 <X <2.0. As sputtering conditions at this time, for example, a film forming temperature is set to about 300 ° C., and Ar and O ₂ are used as film forming gases at a flow rate of about 100 sccm. Further, the power during sputtering is set to about 1 kW to 2 kW. Thereafter, RTA heat treatment is performed for about 60 seconds in an atmosphere at a temperature of about 725 ° C., an oxygen flow rate of about 20 sccm, and an Ar flow rate of about 1980 sccm. This heat treatment completely crystallizes the ferroelectric film 75 (second PZT film 75b) to form a Bi layer structure or a perovskite structure, and at the same time, restores plasma damage of the IrO _x film.

In this embodiment, the film formation temperature when forming the crystallized IrO _x film 76a is about 300 ° C., but the film formation temperature for obtaining the effect of the present invention is 20 ° C. to 400 ° C. It can be a range. That this is caused inconveniently IrO _x the film formation temperature is less than 20 ° C. becomes amorphous, also, IrO _x of crystalline state and the film forming temperature exceeds 400 ° C. tends to abnormal growth This is because a defect occurs. In the present embodiment, the content of the oxidizing gas in the atmosphere (O ₂ flow rate / (Ar flow rate + O ₂ flow rate)) is set to about 1% in the heat treatment of RTA, but the effect of the present invention is obtained. The content of oxidizing gas during RTA can be in the range of 0.1% to 50%. This is because when the content of the oxidizing gas is less than 0.1%, a non-uniform atmosphere is likely to occur, and there is a possibility that the annealing effect may be reduced, and the content of the oxidizing gas is 50%. This is because if it exceeds, the surface of the IrO _x film 76a grows abnormally, causing a problem that the characteristics of the ferroelectric capacitor are deteriorated.

In this embodiment, an example in which an IrO _x film made of iridium oxide is applied as a film crystallized at the time of film formation is shown, but the present invention is not limited to this. For example, a film composed of at least one oxide selected from the group consisting of platinum oxide, ruthenium oxide, rhodium oxide, rhenium oxide, osmium oxide and palladium oxide may be applied. Is possible. In this case, a target including at least one noble metal element selected from the group consisting of platinum (Pt), ruthenium (Ru), rhodium (Rh), rhenium (Re), osmium (Os), and palladium (Pd) is used. The sputtering is performed under conditions where oxidation of the noble metal element occurs.

Next, as shown in FIG. 12B, on the IrO _x film 76a, for example, in an Ar atmosphere, by a sputtering method under conditions of a pressure of about 0.8 Pa, a power of about 1.0 kW, and a deposition time of about 79 seconds. An IrO _Y film 76b, which is a conductive film, is formed with a thickness of about 100 nm. The IrO _Y film 76b functions as an upper layer film of the upper electrode. For example, the value of Y is in the range of 1.8 <Y <2.2. In the present embodiment, the IrO _Y film 76b has a composition close to the stoichiometric composition of IrO _{2 in} order to suppress deterioration in the process, thereby avoiding a catalytic action against hydrogen. Thereby, the problem that the ferroelectric film 75 is reduced by hydrogen radicals is suppressed, and the hydrogen resistance of the ferroelectric capacitor is improved.

In the present embodiment, an example in which an IrO _Y film made of iridium oxide is applied as the conductive film formed on the IrO _x film 76a is shown, but the present invention is not limited to this. For example, at least one noble metal selected from the group consisting of iridium (Ir), platinum (Pt), ruthenium (Ru), rhodium (Rh), rhenium (Re), osmium (Os) and palladium (Pd) It is also possible to apply a metal film containing an element, a conductive oxide film containing these noble metal elements, or a conductive oxide such as SrRuO ₃ .

Next, as shown in FIG. 12C, an Ir film having a thickness of about 100 nm is formed on the IrO _Y film 76b by, for example, sputtering in an Ar atmosphere under a pressure of about 1.0 Pa and a power of about 1.0 kW. A film 77 is formed. The Ir film 77 functions as a hydrogen barrier film that prevents hydrogen generated during formation of a wiring layer or the like from entering the ferroelectric film 75. In addition, as the hydrogen barrier film, a Pt film or a SrRuO ₃ film can also be used. Subsequently, after the back surface of the semiconductor substrate 61 is cleaned, a hard mask (not shown) that covers only the ferroelectric capacitor forming region on the Ir film 77 is formed. Here, as the hard mask, for example, a titanium nitride film having a thickness of about 200 nm under a temperature condition of about 200 ° C. and a silicon oxide film using TEOS having a thickness of about 390 nm under a condition of a temperature of about 390 ° C. are sequentially formed. These are formed by patterning. Subsequently, the Ir film 77, the IrO _Y film 76b, the IrO _x film 76a, the second PZT film 75b, the first PZT film 75a, Ir in regions other than the ferroelectric capacitor formation region are etched by using a hard mask. The film 74b, the TiAlN film 74a, and the TiN film 73 are removed. Thereby, in the ferroelectric capacitor formation region, the lower electrode 74 made of the TiAlN film 74a and the Ir film 74b, the ferroelectric film 75 made of the first PZT film 75a and the second PZT film 75b, and the IrO _x A ferroelectric capacitor including the film 76a and the upper electrode 76 made of the IrO _Y film 76b is formed. Thereafter, after removing the hard mask, heat treatment is performed in an oxygen atmosphere at a temperature of 300 ° C. to 500 ° C. for a time of 30 minutes to 120 minutes, for example.

Next, as shown in FIG. 13A, an Al ₂ O ₃ film 78 is formed so as to cover the ferroelectric capacitor and the interlayer insulating film 71, and an interlayer insulating film 79 is formed on the Al ₂ O ₃ film 78. Form.

Specifically, first, an Al ₂ O ₃ film having a thickness of about 20 nm is deposited by sputtering, and then heat treatment is performed in an oxygen atmosphere at a temperature of 600 ° C. to generate oxygen vacancies in the ferroelectric capacitor. Do recovery. Subsequently, an Al ₂ O ₃ film having a thickness of about 20 nm is further deposited by CVD to form an Al ₂ O ₃ film 78.

Subsequently, a silicon oxide film having a thickness of about 1500 nm is deposited on the entire surface by, eg, CVD using plasma TEOS, and then the silicon oxide film is planarized by CMP to form an interlayer insulating film 79. Here, when a silicon oxide film is formed as the interlayer insulating film 79, for example, a mixed gas of TEOS gas, oxygen gas, and helium gas is used as the source gas. As the interlayer insulating film 79, for example, an insulating inorganic film or the like may be formed. Thereafter, heat treatment is performed in a plasma atmosphere generated using N ₂ O gas or N ₂ gas. As a result of this heat treatment, moisture in the interlayer insulating film 79 is removed, and the film quality of the interlayer insulating film 79 changes, so that moisture does not easily enter the interlayer insulating film 79.

Next, as shown in FIG. 13B, an Al ₂ O ₃ film 80 serving as a barrier film is formed to a thickness of 20 nm to 100 nm on the entire surface by, eg, sputtering or CVD. Since the Al ₂ O ₃ film 80 is formed on the planarized interlayer insulating film 79, it is formed flat. Subsequently, a silicon oxide film is deposited on the entire surface by, eg, CVD using plasma TEOS, and then the silicon oxide film is planarized by CMP to form an interlayer insulating film 81 having a thickness of 800 nm to 1000 nm. To do. Note that a SiON film, a silicon nitride film, or the like may be formed as the interlayer insulating film 81.

Next, first, via holes 82z that expose the surface of the Ir film 77 that is a hydrogen barrier film in the ferroelectric capacitor are formed in the interlayer insulating film 81, the Al ₂ O ₃ film 80, the interlayer insulating film 79, and the Al ₂ O ₃ film 78. Then, heat treatment is performed in an oxygen atmosphere at a temperature of about 550 ° C. to recover oxygen deficiency generated in the ferroelectric film 75 due to the formation of the via hole. Thereafter, as shown in FIG. 13C, a Ti film is deposited in the via hole 82z by, for example, a sputtering method, and subsequently a TiN film is continuously deposited by the MO-CVD method. A glue film 82a, which is a laminated film of TiN films, is formed. In this case, since it is necessary to remove carbon from the TiN film, a treatment in a mixed gas plasma of nitrogen and hydrogen is necessary. In this embodiment, the Ir film 77 serving as a hydrogen barrier film in the ferroelectric capacitor is used. Therefore, there is no problem that hydrogen enters the ferroelectric film 75 and reduces the ferroelectric film 75.

Subsequently, after depositing a W film having a thickness sufficient to fill the via hole 82z by the CVD method, the W film is planarized until the surface of the interlayer insulating film 81 is exposed by the CMP method. A W plug 82b is formed in 82z. Subsequently, via holes 83z that expose the surface of the W plug 69c are formed in the interlayer insulating film 81, the Al ₂ O ₃ film 80, the interlayer insulating film 79, the Al ₂ O ₃ film 78, the interlayer insulating film 71, and the SiON film 70. Then, a glue film 83a made of a TiN film is formed in the via hole 83z. The glue film 83a is formed by, for example, depositing a Ti film by a sputtering method, and then successively depositing a TiN film by an MO-CVD method to form a laminated film of a Ti film and a TiN film. It is also possible to do. Thereafter, a W film having a thickness sufficient to fill the via hole 83z is deposited, and then the W film is planarized until the surface of the interlayer insulating film 81 is exposed by CMP, so that a W plug is formed in the via hole 83z. 83b is formed.

Next, as shown in FIG. 14, a metal wiring layer 84 is formed.
Specifically, first, a Ti film having a thickness of approximately 60 nm, a TiN film having a thickness of approximately 30 nm, an AlCu alloy film having a thickness of approximately 360 nm, a Ti film having a thickness of approximately 5 nm, and a thickness are formed on the front surface by, for example, sputtering. A TiN film having a thickness of about 70 nm is sequentially stacked. Subsequently, the laminated film is patterned into a predetermined shape using a photolithography technique, and a glue film 84a made of a Ti film and a TiN film and a wiring film 84b made of an AlCu alloy film are formed on the W plugs 82b and 83b. Then, a metal wiring layer 84 made of a glue film 84c made of a Ti film and a TiN film is formed.

  Thereafter, after further formation of an interlayer insulating film and contact plug, a second and subsequent metal wiring layers are formed, and a ferroelectric including the lower electrode 74, the ferroelectric film 75, and the lower electrode 76 is formed. A ferroelectric memory according to this embodiment having a body capacitor is completed.

  Next, the results of tests actually performed by the present inventor will be described.

(First test)
FIG. 15 is a characteristic diagram showing a first test result obtained by measuring the inversion charge amount Q _SW of the ferroelectric capacitor in the ferroelectric memory.
In the first test, two methods of manufacturing a ferroelectric capacitor (discrete) whose planar shape is a square having a length of about 50 μm, the manufacturing method according to the present invention (first embodiment) and the conventional manufacturing method. And the inversion charge amount Q _SW was measured. Here, as the ferroelectric film of the ferroelectric capacitor, two types of PZT films (PLZT films) containing about 1.5 mol% of La, having a thickness of about 120 nm and a thickness of about 150 nm, are produced. did.

In the manufacturing method according to the present invention (first embodiment), in forming the upper electrode, first, a crystal is formed on the ferroelectric film by sputtering at a film forming temperature of about 300 ° C. at the time of film formation. An IrO _x film having a thickness of about 50 nm was formed. Subsequently, two types of IrO _Y films were formed on the IrO _x film by sputtering. Specifically, an IrO _Y film having a thickness of about 75 nm is formed on the IrO _x film by sputtering under conditions of a film formation temperature of about 20 ° C. and a power of about 1 kW. An IrO _Y film having a thickness of about 125 nm was formed by sputtering under conditions of about 2 kW.

In the conventional manufacturing method, when forming the upper electrode, two types of IrO _Y films are formed by sputtering, directly on the PLZT film, without forming the IrO _x film crystallized at the time of film formation. Specifically, an IrO _Y film having a thickness of about 75 nm is formed on the PLZT film by sputtering under conditions of a film formation temperature of about 20 ° C. and a power of about 1 kW, followed by a film formation temperature of about 20 ° C. An IrO _Y film having a thickness of about 125 nm was formed by sputtering under conditions of about 2 kW.

FIG. 15 shows the result of measuring the inversion charge amount Q _SW under the condition that the applied voltage is 3.0 V. Q _SW1-1 (“■”) is the value before the wiring is formed on the upper electrode. The measured reverse charge amount Q _SW , and Q _SW1-2 (“▲”) is the reverse charge amount Q _SW measured after the wiring is formed on the upper electrode. In FIG. 15, W / N indicates a wafer number. That is, wafer numbers 1 and 2 are ferroelectric memories each having a ferroelectric capacitor with a thickness of 150 nm of a ferroelectric film manufactured by a conventional manufacturing method, and wafer numbers 3 and 4 are manufactured according to the present invention. 1 is a ferroelectric memory having a ferroelectric capacitor with a thickness of 150 nm of a ferroelectric film manufactured by the method. Wafer numbers 5 and 6 are those having a thickness of 120 nm of a ferroelectric film manufactured by a conventional manufacturing method. Wafer numbers 7 and 8 are ferroelectric memories having a ferroelectric film having a thickness of 120 nm of a ferroelectric film manufactured by the manufacturing method of the present invention. is there.

  As shown in FIG. 15, when the present invention is compared with the prior art, the change in the inversion charge amount due to the presence or absence of the wiring is smaller in the present invention regardless of the thickness of the ferroelectric film. This indicates that the ferroelectric capacitor formed by the manufacturing method of the present invention is not easily damaged when the wiring is formed.

(Second test)
FIG. 16 is a characteristic diagram showing a second test result obtained by measuring the inversion charge amount Q _SW of the ferroelectric capacitor in the ferroelectric memory.
In the second test, a ferroelectric capacitor (cell capacitor) whose planar shape is a rectangle having a long side length of about 1.60 μm and a short side length of about 1.15 μm is used in the present invention (first implementation). 1428 are produced by the two production methods of the embodiment) and the conventional production method, and the inversion charge amount Q _SW is measured. The manufacturing method of each ferroelectric capacitor is the same as in the first test.

FIG. 16 shows the average value of the inversion charge amount Q _SW by each ferroelectric capacitor after the wiring is formed on the upper electrode. Q _SW2-1 (“■”) indicates the applied voltage as 1 Q _SW2-2 (“▲”) is an applied voltage of about 3.0V. As shown in FIG. 16, comparing the present invention with the prior art, it was found that the present invention can provide a higher inversion charge amount Q _SW regardless of the thickness of the ferroelectric film.

(Third test)
FIG. 17 is a characteristic diagram showing a third test result obtained by measuring the coercive voltage Vc of the ferroelectric capacitor in the ferroelectric memory.
In the third test, the same ferroelectric capacitor (cell capacitor) as in the second test is manufactured by the two manufacturing methods of the present invention (first embodiment) and the conventional manufacturing method. The coercive voltage Vc is measured. Here, the applied voltage having the largest change rate of the polarization amount with respect to the change of the predetermined applied voltage was defined as the coercive voltage Vc.

  In FIG. 17, Vc (+) (“▲”) indicates a coercive voltage when the change in polarization amount is positive, and Vc (−) (“■”) indicates a coercive voltage when the change in polarization amount is negative. Show. As shown in FIG. 17, comparing the present invention with the prior art, it was found that the present invention can provide a lower coercive voltage Vc regardless of the thickness of the ferroelectric film. Further, the thinner the ferroelectric film, the lower coercive voltage Vc was obtained.

(Fourth test)
Figure 18 is a characteristic diagram showing a fourth test result of measuring the relation between the voltage applied to the ferroelectric capacitor in a ferroelectric memory and the polarization inversion amounts Q _SW.
In the fourth test, the same ferroelectric capacitor (cell capacitor) as in the second test is manufactured by the two manufacturing methods of the present invention (first embodiment) and the conventional manufacturing method. The relationship between the applied voltage and the inversion charge amount Q _SW is measured. As shown in FIG. 18, when the present invention is compared with the prior art, the present invention has a higher inversion charge amount Q _SW from the applied voltage to the saturation voltage regardless of the thickness of the ferroelectric film. As can be seen, the gradient is increased. This indicates that the ferroelectric capacitor of the present invention is extremely suitable for a ferroelectric memory operating at a low voltage.

(Fifth test)
FIG. 19 is a characteristic diagram showing a fifth test result obtained by measuring the fatigue loss of the ferroelectric capacitor in the ferroelectric memory.
In the fifth test, the same ferroelectric capacitor (cell capacitor) as in the second test is manufactured by two manufacturing methods of the present invention (first embodiment) and the conventional manufacturing method. The fatigue loss was measured from the dependency of the stress cycle. In the fifth test, the read voltage (applied voltage) was about 3V, and the stress voltage was about 7V.

As shown in FIG. 19, the inversion charge amount Q _SW at a stress cycle of 2 × 10 ⁸ is 342 fC / cell in a ferroelectric capacitor having a ferroelectric film with a thickness of about 150 nm manufactured by the manufacturing method according to the present invention. In a ferroelectric capacitor having a ferroelectric film with a thickness of about 150 nm manufactured by a conventional manufacturing method, it was 232 fC / cell. Further, in a ferroelectric capacitor having a ferroelectric film having a thickness of about 120 nm manufactured by the manufacturing method according to the present invention, the ferroelectric capacitor having a ferroelectric film having a thickness of about 120 nm manufactured by a conventional manufacturing method is used. It was 83 fC / cell for the body capacitor.

  That is, in a ferroelectric capacitor having a ferroelectric film with a thickness of about 150 nm manufactured by the manufacturing method according to the present invention, the fatigue loss based on the initial value is about 22%, and the thickness manufactured by the conventional manufacturing method is In a ferroelectric capacitor having a ferroelectric film of about 150 nm, the fatigue loss based on the initial value was about 41%. Further, in a ferroelectric capacitor having a ferroelectric film having a thickness of about 120 nm manufactured by the manufacturing method according to the present invention, the fatigue loss based on the initial value is about 59%, and the thickness manufactured by the conventional manufacturing method is reduced. In a ferroelectric capacitor having a ferroelectric film of about 120 nm, the fatigue loss based on the initial value was about 74%. This indicates that the ferroelectric capacitor of the present invention has higher fatigue resistance than the conventional ferroelectric capacitor.

(Sixth test)
FIG. 20 is a characteristic diagram showing a sixth test result obtained by measuring the imprint characteristic of the ferroelectric capacitor in the ferroelectric memory.
In the sixth test, the same ferroelectric capacitor (cell capacitor) as in the second test is manufactured by the two manufacturing methods of the present invention (first embodiment) and the conventional manufacturing method. The imprint characteristics are measured. In the sixth test, imprint characteristics were measured by OS_RATE. This OS_Rate indicates that the lower the absolute value, the harder it is to imprint. FIG. 20 shows the worst characteristic values of each ferroelectric capacitor.

  As shown in FIG. 20, when the present invention is compared with the conventional one, the imprint characteristic of the present invention is about 40% better than the conventional one. This indicates that the ferroelectric capacitor of the present invention has higher imprint resistance than the conventional ferroelectric capacitor.

(Seventh test)
In the seventh test, oxygen in the film forming gas when forming the IrO _x film crystallized at the time of film formation on the ferroelectric film in the manufacturing method according to the first embodiment of the present invention. Various characteristics with respect to each ratio of the flow rate are measured.

FIG. 21 shows the ratio of the oxygen flow rate in the film forming gas when forming the IrO _x film crystallized at the time of film formation on the ferroelectric film in the manufacturing method according to the first embodiment. strength is a characteristic diagram of the polarization inversion amount Q _SW of the ferroelectric capacitor. Here, the ferroelectric capacitor in FIG. 21 was a ferroelectric capacitor having a planar shape of a square having a length of about 50 μm, as in the first test. As the ferroelectric film, a PZT film (PLZT film) containing about 2.0 mol% of La was formed with a thickness of about 150 nm. Then, when forming an IrO _x film crystallized at the time of film formation on the PLZT film, the film formation temperature is set to about 300 ° C., and the ratio of oxygen flow rate in the film formation gas (O ₂ flow rate / ( The measurement was performed at an Ar flow rate + O ₂ flow rate)) of about 20%, about 30%, about 40%, and about 50%. In FIG. 21, Q _SW3-1 (“▲”) is the inversion charge amount after formation of the ferroelectric capacitor, and Q _SW3-2 (“■”) is the first wiring layer on the ferroelectric capacitor. Q _SW3-3 (“●”) is the inversion charge amount after the three wiring layers are formed on the ferroelectric capacitor.

  As shown in FIG. 21, after the ferroelectric capacitor is formed, the inversion charge amount of each ferroelectric capacitor after the first wiring layer is formed on the ferroelectric capacitor and after the three wiring layers are formed on the ferroelectric capacitor. There was little change. This indicates that in the manufacturing method according to the first embodiment of the present invention, the characteristics of the ferroelectric capacitor do not deteriorate even after the wiring layer is formed. Further, as shown in the trend of FIG. 21, it can be seen that when the proportion of the oxygen flow rate in the deposition gas is reduced, a higher inversion charge amount can be obtained.

FIG. 22 shows the ratio of oxygen flow rate in the film forming gas when forming the IrO _x film crystallized at the time of film formation on the ferroelectric film in the manufacturing method according to the first embodiment. strength is a characteristic diagram of the polarization inversion amount Q _SW of the ferroelectric capacitor. Here, as the ferroelectric capacitor in FIG. 22, the same one as in the second test is used, and when the IrO _x film crystallized at the time of film formation is formed on the PLZT film, The film forming temperature is set to about 300 ° C., and the ratio of the oxygen flow rate in the film forming gas (O ₂ flow rate / (Ar flow rate + O ₂ flow rate)) is set to about 20%, about 30%, about 40%, and about 50%. It was. In FIG. 22, Q _SW4-1 (“♦”) is an inversion charge amount when an applied voltage of about 3.0 V is applied to the ferroelectric capacitor in which the first wiring layer is formed, Q _SW4-2 ( “●”) represents the inversion charge when an applied voltage of about 3.0 V is applied to a ferroelectric capacitor having three wiring layers, and Q _SW4-3 (“▲”) represents the first wiring layer. Q _SW4-4 (“■”) indicates the amount of inversion charge when an applied voltage of about 1.8 V is applied to a ferroelectric capacitor in which a layer is formed. This is the amount of inversion charge when an applied voltage of about 1.8 V is applied.

As shown in FIG. 22, the inversion charge amount when a low voltage (applied voltage of about 1.8 V) is supplied to the ferroelectric capacitor is the inversion charge amount Q of the ferroelectric capacitor in which three wiring layers are formed. _SW4-4 is slightly lower than the inversion charge amount _QSW4-3 of the ferroelectric capacitor in which the first wiring layer is formed. However, the inversion charge amount when the saturation applied voltage (applied voltage of about 3 V) is supplied is the inversion charge amount Q _SW4-2 of the ferroelectric capacitor in which the three wiring layers are formed and the first wiring layer. In the manufacturing method according to the first embodiment of the present invention, the ferroelectric capacitor has characteristics even after the wiring layer is formed because the inverted charge amount Q _SW4-1 of the ferroelectric capacitor formed with It is thought that it does not deteriorate. Further, as shown in the tendency of FIG. 22, it can be seen that when the proportion of the oxygen flow rate in the deposition gas is reduced, a higher inversion charge amount can be obtained.

FIG. 23 shows the ratio of the oxygen flow rate in the deposition gas when forming the IrO _x film crystallized at the time of deposition on the ferroelectric film in the manufacturing method according to the first embodiment. It is a characteristic view of the coercive voltage Vc of the ferroelectric capacitor. Here, the ferroelectric capacitor in FIG. 23 is the same as that in the second test. In FIG. 23, Vc (+) (“▲”) indicates a coercive voltage when the change in polarization amount is positive, and Vc (−) (“■”) indicates a coercive voltage when the change in polarization amount is negative. Show.

  As shown in FIG. 23, it was found that the coercive voltage Vc decreases as the oxygen flow rate decreases. This means that a small proportion of the oxygen flow rate is extremely suitable for a ferroelectric memory operating at a low voltage.

FIG. 24 shows the ratio of oxygen flow rate in the deposition gas when forming the IrO _x film crystallized at the time of deposition on the ferroelectric film in the manufacturing method according to the first embodiment. FIG. 6 is a characteristic diagram showing a relationship between an applied voltage of a ferroelectric capacitor and an inversion charge amount _QSW .

As shown in FIG. 24, it was found that when the proportion of the oxygen flow rate is reduced, a high inversion charge amount Q _SW is obtained from the low voltage to the saturation voltage, and the gradient thereof is increased. This means that a small proportion of the oxygen flow rate is extremely suitable for a ferroelectric memory operating at a low voltage.

FIG. 25 and FIG. 26 show the ratio of oxygen flow rate in the film forming gas when forming the IrO _x film crystallized at the time of film formation on the ferroelectric film in the manufacturing method according to the present invention. It is a characteristic view of the leakage current value of a ferroelectric capacitor. FIG. 25 shows a leakage current value in a ferroelectric capacitor (discrete) similar to that in the first test, and L _1-1 (“▲”) is obtained when the potential of the lower electrode is set to about +5 V with respect to the upper electrode. , L _1-2 (“■”) is a leakage current value when the potential of the lower electrode is set to about −5 V with respect to the upper electrode. FIG. 26 shows the leakage current value in a ferroelectric capacitor (cell capacitor) similar to that in the second test, and L _2-1 (“▲”) represents the potential of the lower electrode about +5 V with respect to the upper electrode. L _2-2 (“■”) is a leakage current value when the potential of the lower electrode is set to about −5 V with respect to the upper electrode. The applied voltage in the measurement of the leakage current value was set such that the potential of the lower electrode was ± 5 V with respect to the upper electrode.

As shown in FIG. 25 and FIG. 26, when the ratio of the oxygen flow rate in the film-forming gas when forming the IrO _x film crystallized at the time of film formation is small, the leak current value is slightly reduced, There is no change. This indicates that there is almost no influence on the characteristics of the leakage current value even if the film forming conditions are changed.

(Eighth test)
The eighth test is a manufacturing method according to the first embodiment of the present invention, in which various characteristics with respect to the film thickness when an IrO _x film crystallized at the time of film formation is formed on the ferroelectric film. Is measured.

27 and 28 show the ferroelectric capacitor relative to the film thickness when the IrO _x film crystallized at the time of film formation is formed on the ferroelectric film in the manufacturing method according to the first embodiment. It is a characteristic view of inversion charge amount _QSW .

The ferroelectric capacitor in FIG. 27 is the same ferroelectric capacitor (discrete) as in the first test, and the measurement target is a ferroelectric capacitor in which three wiring layers are formed. The ferroelectric capacitor in FIG. 28 is the same ferroelectric capacitor (cell capacitor) as in the second test, and the measurement target is a ferroelectric capacitor in which three wiring layers are formed. is there. In FIG. 28, Q _SW5-1 (“◆”) is the inversion charge amount when the applied voltage is 1.8 V, and Q _SW5-2 (“▲”) is the applied voltage of 3.0 V. Is the amount of inversion charge.

FIG. 29 shows the leakage current value of the ferroelectric capacitor with respect to the film thickness when the IrO _x film crystallized at the time of film formation is formed on the ferroelectric film in the manufacturing method according to the first embodiment. FIG. A measurement object is a ferroelectric capacitor in which three wiring layers are formed. L _3-1 (“◆”) and L _3-2 (“▲”) are leakage current values in the same ferroelectric capacitor (discrete) as in the first test, and L _3-1 represents the upper electrode. A leak current value when the potential of the lower electrode is about +5 V as a reference, and L _3-2 is a leak current value when the potential of the lower electrode is about −5 V with respect to the upper electrode. L _3-3 (“■”) and L _3-4 (“●”) are leakage current values in the same ferroelectric capacitor (cell capacitor) as in the second test, and L _3-3 is the upper part. The leakage current value when the potential of the lower electrode is about + 5V with respect to the electrode, and L _3-4 is the leakage current value when the potential of the lower electrode is about -5V with respect to the upper electrode.

Further, in the ferroelectric capacitors of FIGS. 27, 28 and 29, the film formation temperature when forming the IrO _x film crystallized at the time of film formation is set to about 300 ° C., and oxygen in the film formation gas is used. The flow rate ratio (O ₂ flow rate / (Ar flow rate + O ₂ flow rate)) was set to about 30%. Then, the inversion charge amount Q _SW of the ferroelectric capacitor was measured when the film thickness of the IrO _x film crystallized at the time of film formation was about 50 nm, about 38 nm, and about 25 nm.

As shown in FIGS. 27 and 28, even if the film thickness of the IrO _x film crystallized at the time of film formation changes in the range of 25 nm to 50 nm, the characteristics of the inversion charge amount Q _SW of the ferroelectric capacitor. Was not affected. Further, as shown in FIG. 29, even if the film thickness of the IrO _x film crystallized at the time of film formation changes in the range of 25 nm to 50 nm, the characteristics of the leakage current value of the ferroelectric capacitor are affected. Was not seen.

(9th test)
FIG. 30 is a graph showing the strength against the ratio of the oxygen flow rate in the film forming gas when forming the IrO _x film crystallized at the time of film formation on the ferroelectric film in the manufacturing method according to the second embodiment. it is a characteristic diagram of the polarization inversion amount Q _SW of the ferroelectric capacitor. FIG. 31 shows the ratio of the oxygen flow rate in the film forming gas when forming the IrO _x film crystallized at the time of film formation on the ferroelectric film in the manufacturing method according to the second embodiment. FIG. 5 is a characteristic diagram of a leakage current value of a ferroelectric capacitor with respect to FIG.

The ninth test is a measurement of a ferroelectric capacitor manufactured by the manufacturing method according to the second embodiment.
Specifically, a crystallized first PZT film 75a having a thickness of about 100 nm is formed on the lower electrode 74 by MO-CVD, and a thickness of the first PZT film 75a is increased by sputtering. A second PZT film 75b in an amorphous state with a thickness of about 20 nm was formed. Then, an IrO _x film 76a crystallized at the time of film formation was formed on the second PZT film 75b by a sputtering method in which the temperature (film formation temperature) of the semiconductor substrate 61 was about 300 ° C. Three types of strong gases having a ratio of oxygen flow rate (O ₂ flow rate / (Ar flow rate + O ₂ flow rate)) in the film forming gas at the time of forming the IrO _x film 76a to about 10%, about 30%, and about 40%. A dielectric capacitor was fabricated. Further, these were subjected to RTA for about 60 seconds in an atmosphere of a temperature of about 675 ° C. and an O ₂ flow rate / (Ar flow rate + O ₂ flow rate) = 1%. Thereafter, the first wiring layer was formed by the manufacturing method according to the second embodiment.

In FIG. 30, Q _SW6-1 (“♦”) is an inversion charge amount of a ferroelectric capacitor (discrete) similar to that in the first test with an applied voltage of about 1.8 V, and Q _SW6-2 (“●”) is an inversion charge amount of a ferroelectric capacitor (cell capacitor) similar to that in the second test with an applied voltage of about 1.8V. In FIG. 31, L _4-1 (“♦”) is a leakage current value when the potential of the lower electrode is about +1.8 V with respect to the upper electrode, and L _4-2 (“●”) is This is a leakage current value when the potential of the lower electrode is about −1.8 V with respect to the upper electrode.

As shown in FIG. 30, when the ratio of the oxygen flow rate is about 20% to about 40%, compared with the case where the ratio of the oxygen flow rate in the film forming gas when forming the IrO _x film 76a is about 10%. As shown in FIG. 31, when the rate of oxygen flow is about 10%, the rate of oxygen flow is about 20% to 40%. Compared with the above case, the leakage current value is slightly lower, which is advantageous for the operation of the ferroelectric memory. That is, in order to obtain a higher inversion charge amount of the ferroelectric capacitor, it is desirable that the ratio of the oxygen flow rate is about 20% to 40%. In order to obtain a lower leakage current value, it is desirable that the proportion of the oxygen flow rate is about 10%.

Here, in the manufacturing method according to the second embodiment of the present invention, when the ratio of the oxygen flow rate in the film forming gas during the formation of the IrO _x film 76a is 10% to 40%, the crystal of the IrO _x film 76a. It is thought that the electrical characteristics of the ferroelectric capacitor do not change so much because it is considered that it does not have a great influence on the characteristics. In the annealing step after the formation of the IrO _x film 76a, the amorphous second PZT film 75b is completely crystallized, and at the same time, the plasma damage of the IrO _x film 76a can be recovered. It also compensates for oxygen deficiency. Further, in order to make the interface layer between the upper electrode 76 and the ferroelectric film 75 thinner, it is desirable that the crystal grains of the IrO _x film 76a be smaller.

Considering the ninth test result and the above-described seventh test result, the ratio of the oxygen flow rate in the IrO _x film forming gas for obtaining the effect of the present invention is in the range of 10% to 60%. It can be. This is because when the ratio of the oxygen flow rate in the film forming gas is less than 10%, the inversion charge amount of the ferroelectric capacitor becomes small as shown in the tendency of the ninth test result. If a malfunction occurs that interferes with the voltage operation, and if the proportion of the oxygen flow rate in the deposition gas exceeds 60%, the inversion charge amount of the ferroelectric capacitor can be seen from the tendency of the seventh test result, etc. This is because the coercive voltage Vc is increased and the coercive voltage Vc is increased, which causes a problem that the low voltage operation of the ferroelectric memory is hindered.

(Tenth test)
FIG. 32 shows the inversion charge amount of the ferroelectric capacitor with respect to the annealing temperature after forming the IrO _x film crystallized at the time of film formation on the ferroelectric film in the manufacturing method according to the second embodiment. It is a characteristic figure of _QSW . FIG. 33 shows the leakage current value of the ferroelectric capacitor with respect to the annealing temperature after forming the IrO _x film crystallized at the time of film formation on the ferroelectric film in the manufacturing method according to the second embodiment. FIG.

The tenth test is a measurement of the ferroelectric capacitor produced by the manufacturing method according to the second embodiment, as in the ninth test.
Specifically, the temperature of the semiconductor substrate 61 (deposition temperature) is about 300 ° C. on the second PZT film 75b in an amorphous state, and the ratio of oxygen flow rate in the deposition gas (O ₂ flow rate / (Ar flow rate + O _2). After forming the IrO _x film 76a having a thickness of about 50 nm by sputtering under the condition that the flow rate)) is about 20%, in an atmosphere of O ₂ flow rate / (Ar flow rate + O ₂ flow rate) = 1%, Three types of ferroelectric capacitors were manufactured by performing RTA for about 60 seconds at temperatures of about 675 ° C., about 700 ° C., and about 725 ° C., respectively. The temperature in this RTA is an extremely important parameter because the interface between the upper electrode 76 and the ferroelectric film 75 is formed at the same time when the second PZT film 75b is crystallized.

In FIG. 32, Q _SW7-1 (“♦”) is an inversion charge amount of a ferroelectric capacitor (discrete) similar to that in the first test with an applied voltage of about 1.8 V, and Q _SW7-2 (“●”) is an inversion charge amount of a ferroelectric capacitor (cell capacitor) similar to that in the second test with an applied voltage of about 1.8V. In FIG. 33, L _5-1 (“♦”) is a leakage current value when the potential of the lower electrode is about +1.8 V with respect to the upper electrode, and L _5-2 (“●”) is This is a leakage current value when the potential of the lower electrode is about −1.8 V with respect to the upper electrode.

It is known that the annealing temperature after the formation of the IrO _x film 76a affects the characteristics of the ferroelectric capacitor. As shown in FIG. 32, when the annealing temperature is about 675 ° C., the inversion charge amount of the ferroelectric capacitor is slightly lower than when the annealing temperature is about 700 ° C. and about 725 ° C. An annealing temperature of about 700 ° C. to 725 ° C. is optimal for obtaining a higher inversion charge amount of the ferroelectric capacitor. However, even when the annealing temperature is about 675 ° C., the inversion charge amount at these annealing temperatures is not much. Since there is no great difference, it is considered that the level has not reached a level that hinders the operation of the ferroelectric memory.

  As shown in FIG. 33, when the annealing temperature is about 725 ° C., the leakage current value is slightly higher than when the annealing temperature is about 675 ° C. and about 700 ° C. In order to obtain a lower leakage current value, the annealing temperature is optimally about 675 ° C. to 700 ° C. However, even when the annealing temperature is about 725 ° C., there is not much difference from the leakage current value at these annealing temperatures. It is considered that the level has not been reached to hinder the operation of the ferroelectric memory.

Considering the tenth test result and the like, the annealing temperature after forming the IrO _x film 76a for obtaining the effect of the present invention can be set in the range of 600 ° C. to 800 ° C. This is because when the annealing temperature is less than 600 ° C., the inversion charge amount of the ferroelectric capacitor is reduced, which causes a problem in that the low voltage operation of the ferroelectric memory is hindered. This is because if it exceeds, the leakage current value becomes high, which causes a problem that the low voltage operation of the ferroelectric memory is hindered.

(Eleventh test)
FIG. 34 shows the inversion charge amount of the ferroelectric capacitor with respect to the film thickness when forming the IrO _x film crystallized at the time of film formation on the ferroelectric film in the manufacturing method according to the second embodiment. It is a characteristic figure of _QSW . FIG. 35 shows a leakage current value of a ferroelectric capacitor with respect to a film thickness when an IrO _x film crystallized at the time of film formation is formed on the ferroelectric film in the manufacturing method according to the second embodiment. FIG.

As in the ninth test, the eleventh test is a measurement of a ferroelectric capacitor manufactured by the manufacturing method according to the second embodiment.
Specifically, the temperature of the semiconductor substrate 61 (deposition temperature) is about 300 ° C. on the second PZT film 75b in an amorphous state, and the ratio of oxygen flow rate in the deposition gas (O ₂ flow rate / (Ar flow rate + O _2). When the IrO _x film 76a was formed by sputtering under the condition that the flow rate was about 20%, three types of ferroelectric capacitors having a film thickness of about 25 nm, about 50 nm, and about 75 nm were fabricated. Further, these were subjected to RTA for about 60 seconds in an atmosphere of a temperature of about 725 ° C. and an O ₂ flow rate / (Ar flow rate + O ₂ flow rate) = 1%. Thereafter, the first wiring layer was formed by the manufacturing method according to the second embodiment.

In FIG. 34, Q _SW8-1 (“◆”) is an inversion charge amount of a ferroelectric capacitor (discrete) similar to that in the first test with an applied voltage of about 1.8 V, and Q _SW8-2 (“●”) is an inversion charge amount of a ferroelectric capacitor (cell capacitor) similar to that in the second test with an applied voltage of about 1.8V. In FIG. 35, L _6-1 (“◆”) is a leakage current value when the potential of the lower electrode is about +1.8 V with respect to the upper electrode, and L _6-2 (“●”) is This is a leakage current value when the potential of the lower electrode is about −1.8 V with respect to the upper electrode.

As shown in FIG. 34, when the film thickness of the IrO _x film 76a is about 75 nm, the inversion charge amount of the ferroelectric capacitor is slightly larger than when the film thickness of the IrO _x film 76a is about 25 nm and about 50 nm. It is low. As described above, when the thickness of the IrO _x film 76a is increased, the inversion charge amount of the capacitor is decreased because the heat treatment after the film formation makes it difficult for oxygen to diffuse into the ferroelectric film 75, and the upper electrode This is probably because the damage at the time of film formation 76 is difficult to recover. In order to obtain a higher inversion charge amount of the ferroelectric capacitor, the film thickness of the IrO _x film 76a is optimally about 25 nm to 50 nm. However, even when the film thickness of the IrO _x film 76a is about 75 nm, these films Since there is not much difference from the inversion charge amount in thickness, it is considered that the level has not reached the level that hinders the operation of the ferroelectric memory.

On the other hand, as shown in FIG. 35, with respect to the characteristics of the leakage current value, a result with no significant difference was obtained when the thickness of the IrO _x film 76a was in the range of 25 nm to 75 nm.

Considering the eleventh test result and the eighth test result described above, the optimum film thickness of the IrO _x film for obtaining the effect of the present invention can be in the range of 10 nm to 100 nm. This is because the thickness of the IrO _x film exceeds 100 nm, is smaller inversion charge amount of the ferroelectric capacitor, resulting disadvantageously hindered low-voltage operation of the ferroelectric memory, also formed IrO _x This is because if the film thickness is less than 10 nm, the ferroelectric film 75 is damaged when the IrO _Y film 76b is formed, and the characteristics of the ferroelectric capacitor are deteriorated.

As the ferroelectric film of the ferroelectric capacitor, for example, the crystal structure is a Bi layer structure (for example, (Bi _1-x R _x ) Ti ₃ O ₁₂ (R is a rare earth element: 0 <x <1 ), SrBi ₂ Ta ₂ O ₉ and SrBi ₄ Ti ₄ O ₁₅ ) or a film having a perovskite structure. Examples of such a film include a film represented by the general formula ABO ₃ such as PZT film, PZT film, SBT film, BLT film, and Bi layer compound in which at least one of La, Ca, Sr, and Si is doped in addition to the PZT film. It is done.

  According to the embodiment of the present invention, since the interface between the ferroelectric film and the upper electrode can be made in a good state, even when the thinning of the ferroelectric film is advanced, the low voltage can be used. This operation can be maintained and the operation speed can be remarkably improved. Furthermore, a ferroelectric capacitor having high fatigue resistance and high imprint resistance can be obtained.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1) a semiconductor substrate;
A capacitor structure formed above the semiconductor substrate and having a capacitor film sandwiched between an upper electrode and a lower electrode;
The semiconductor device according to claim 1, wherein the upper electrode includes a conductive oxide film that is crystallized at the time of film formation at an interface with the capacitor film.

(Appendix 2)
The conductive oxide film is composed of at least one oxide selected from the group consisting of iridium oxide, platinum oxide, ruthenium oxide, rhodium oxide, rhenium oxide, osmium oxide, and palladium oxide. 2. The semiconductor device according to appendix 1, wherein the semiconductor device is a formed film.

(Appendix 3)
The semiconductor device according to appendix 1 or 2, wherein the conductive oxide film is a film whose crystal plane is oriented in a (110) plane and a (200) plane.

(Appendix 4)
The semiconductor device according to any one of appendices 1 to 3, wherein the upper electrode further includes a conductive film formed on the conductive oxide film.

(Appendix 5)
The conductive film is a metal film or a conductive oxide film containing at least one noble metal element selected from the group consisting of iridium, platinum, ruthenium, rhodium, rhenium, osmium and palladium. 5. The semiconductor device according to 4.

(Appendix 6)
6. The semiconductor device according to any one of appendices 1 to 5, wherein the capacitor film is a ferroelectric film.

(Appendix 7)
A method of manufacturing a semiconductor device having a capacitor structure,
Forming a lower electrode of the capacitor structure above a semiconductor substrate;
Forming a capacitor film on the lower electrode;
Forming a crystallized conductive oxide film on at least a part of the upper electrode of the capacitor structure on the capacitor film.

(Appendix 8)
8. The method of manufacturing a semiconductor device according to appendix 7, further comprising a step of performing a heat treatment in an atmosphere containing an oxidizing gas after forming the conductive oxide film.

(Appendix 9)
9. The method of manufacturing a semiconductor device according to appendix 7 or 8, further comprising forming a conductive film forming the upper electrode on the conductive oxide film.

(Appendix 10)
The step of forming the conductive oxide film includes sputtering using a target containing at least one noble metal element selected from the group consisting of iridium, platinum, ruthenium, rhodium, rhenium, osmium, and palladium. 10. The method for manufacturing a semiconductor device according to any one of appendices 7 to 9, further comprising a step of performing under conditions in which oxidation of the semiconductor occurs.

(Appendix 11)
11. The manufacturing method of a semiconductor device according to any one of appendices 7 to 10, wherein the conductive oxide film is a film whose crystal plane is oriented in a (110) plane and a (200) plane. Method.

(Appendix 12)
12. The method of manufacturing a semiconductor device according to appendix 11, wherein, in the step of forming the conductive oxide film, the film formation temperature is controlled to form the conductive oxide film oriented in the crystal plane. Method.

(Appendix 13)
13. The method of manufacturing a semiconductor device according to appendix 12, wherein the film forming temperature is 20 ° C. to 400 ° C.

(Appendix 14)
In the step of forming the conductive oxide film, the partial pressure of oxygen gas in a gas used for sputtering is controlled to form the conductive oxide film oriented in the crystal plane. A method for manufacturing a semiconductor device according to attachment 11.

(Appendix 15)
15. The semiconductor device according to appendix 14, wherein a partial pressure of the oxygen gas is set to 10% to 60% with respect to a pressure of an oxygen gas and an inert gas constituting a gas used in the sputtering. Production method.

(Appendix 16)
16. The method for manufacturing a semiconductor device according to any one of appendices 7 to 15, wherein the conductive oxide film has a thickness of 10 nm to 100 nm.

(Appendix 17)
9. The method of manufacturing a semiconductor device according to appendix 8, wherein the step of performing the heat treatment is performed in an atmosphere containing 0.1% to 50% of the oxidizing gas.

(Appendix 18)
9. The method of manufacturing a semiconductor device according to appendix 8, wherein the heat treatment is performed at a temperature of 600 ° C. to 800 ° C.

(Appendix 19)
The conductive film is a metal film or a conductive oxide film containing at least one noble metal element selected from the group consisting of iridium, platinum, ruthenium, rhodium, rhenium, osmium and palladium. A method for manufacturing a semiconductor device according to claim 9.

(Appendix 20)
20. The method for manufacturing a semiconductor device according to any one of appendices 7 to 19, wherein the capacitor film is a ferroelectric film.

DESCRIPTION OF SYMBOLS 1, 61 Semiconductor substrate 2, 62 Element isolation insulating film 3, 63 Gate insulating film 4, 64 Gate electrode 5, 65 Silicide layer 6, 66 Side wall 7 Silicon oxynitride film 8a Silicon oxide film 8b, 12, 13, 78, 80 Al ₂ O ₃ films 9, 74 Lower electrode 9a Lower electrode films 10a, 10, 75 Ferroelectric films 11, 76 Upper electrodes 11a, 76a IrO _x films 11b, 76b IrO _Y films 14, 68, 71, 79, 81 Interlayer insulating films 15, 17, 69b, 69c, 72b, 82b, 83b W plugs 15a, 17a, 18a, 18b, 69a, 72a, 82a, 83a, 84a, 84c Glue films 15z, 17y, 17z, 69z, 72z, 82z 83z Via hole 16, 67, 70 SiON film 18, 84b Wiring film 21, 91 p-well 22, 92 Low concentration diffusion layer 23, 3 high-concentration diffusion layer 73 TiN film 74a TiAlN film 74b Ir film 75a, 75b PZT film 77 Ir film 84 metal wiring layers 101 and 102 MOSFET
205 Hydrogen diffusion path 301 Lower electrode 302 Ferroelectric film 303 Upper electrode 303a Conductive oxide film 303b Conductive film

Claims (9)

Forming a lower electrode above the semiconductor substrate;
Forming a first ferroelectric film on the lower electrode;
Forming an amorphous second ferroelectric film on the first ferroelectric film; and
Forming a first upper electrode including a conductive oxide film in a crystallized state on an interface with the second ferroelectric film on the second ferroelectric film ;
Forming a second upper electrode including an IrO _Y film on the first upper electrode;
The method of manufacturing a semiconductor device according to the on the second upper electrode, characterized in that organic and forming a third upper electrode including an Ir film. The conductive oxide film is composed of at least one oxide selected from the group consisting of iridium oxide, platinum oxide, ruthenium oxide, rhodium oxide, rhenium oxide, osmium oxide, and palladium oxide. The method of manufacturing a semiconductor device according to claim 1, wherein the film is a formed film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive oxide film is a film whose crystal plane is oriented in a (110) plane and a (200) plane. 4. 4. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a hydrogen barrier film formed on the third upper electrode. 5. A method of manufacturing a semiconductor device having a capacitor structure,
Forming a lower electrode of the capacitor structure above a semiconductor substrate;
Forming a capacitor film on the lower electrode;
On the capacitor film, at least, a step of forming a first conductive film is a conductive oxide film of the crystalline state at the deposition point,
Performing a heat treatment in an atmosphere containing an oxidizing gas after forming the first conductive film;
Forming a second conductive film including an IrO _Y film on the first conductive film after performing the heat treatment ;
Forming an Ir film on the second conductive film;
The first conductive layer, the second conductive film, and patterning the Ir film, a method of manufacturing a semiconductor device, which comprises organic and forming an upper electrode.   The step of forming the conductive oxide film includes sputtering using a target containing at least one noble metal element selected from the group consisting of iridium, platinum, ruthenium, rhodium, rhenium, osmium and palladium. 6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of performing under conditions where oxidation of the semiconductor occurs.   The method for manufacturing a semiconductor device according to claim 5, wherein the conductive oxide film is a film whose crystal plane is oriented in a (110) plane and a (200) plane.   8. The step of forming the conductive oxide film controls the film formation temperature at 20 to 400 ° C. to form the conductive oxide film oriented in the crystal plane. The manufacturing method of the semiconductor device as described in 2.   In the step of forming the conductive oxide film, the partial pressure of oxygen gas in the gas used for sputtering is 10% of the pressure of oxygen gas and inert gas constituting the gas used for sputtering. The method for manufacturing a semiconductor device according to claim 8, wherein the conductive oxide film oriented in the crystal plane is formed by being controlled by 60% to 60%.

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