JP4671194B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device suitable for a ferroelectric memory.

  The nonvolatile random access memory (RAM) has, for example, a feature that it can hold the immediately preceding memory even when the power is turned off, a feature that random access is possible, and the like. Therefore, it is promising as a device that forms the foundation of a ubiquitous society.

  One of nonvolatile RAMs is a ferroelectric memory. A ferroelectric memory includes a ferroelectric capacitor using a ferroelectric film having spontaneous polarization as a capacitive insulating film. Ferroelectric memories are expected as next-generation memories in the mobile field because of their low power consumption.

  In a ferroelectric memory that is currently in practical use, one memory cell is provided with one transistor and one ferroelectric capacitor, and such a structure is called 1T1C type. In such a structure, it is inevitable that the ferroelectric capacitor occupies a certain size in the memory cell. On the other hand, the amount of charge stored in the ferroelectric capacitor is proportional to the area. Accordingly, the amount of charge that can be accumulated with the miniaturization decreases, and the charge necessary for storing and holding cannot be accumulated. That is, there is a limit to the increase in capacity.

For example, the case of manufacturing the ferroelectric memory in the process of 150nm rule, the area of the memory cell when a 0.27 [mu] m ^2, the area of the ferroelectric capacitor in a non-patent document 1 to be 0.11 .mu.m ² Are listed.

Considering the reading ability of a sense amplifier manufactured by the current CMOS process, when the area of the ferroelectric capacitor is about 0.11 μm ² , the minimum residual polarization quantity Q _SW necessary for the memory holding operation is 30. Estimated to be 1 μC / cm ² .

On the other hand, the ferroelectric materials currently in practical use are mainly PbZr _1-X Ti _X O ₃ and SrBi ₂ Ta ₂ O ₉ . The residual polarization quantity Q _SW of PbZr _1-X Ti _X O ₃ is about 30 μC / cm ^{2 at the} maximum at the thickness used for the ferroelectric capacitor, and the residual polarization quantity Q of SrBi ₂ Ta ₂ O _{9. SW} is about 10 μC / cm ^{2 at the} maximum at a thickness used for a ferroelectric capacitor. Therefore, if PbZr _1-X Ti _X O ₃ is used as the ferroelectric material, the minimum residual polarization quantity Q _SW necessary for the memory holding operation can be secured.

  However, judging the commerciality from the chip area, the maximum memory capacity per chip of this generation (150 nm rule) is considered to be 64 Mbit. For this reason, it is difficult to further miniaturize and increase the capacity with the conventional technology.

Patent Document 1 describes a technique for forming a ferroelectric layer made of BiFeO ₃ . For example, the structure and formation method of a base (electrode) for forming a tetragonal (001) -oriented ferroelectric (BiFeO ₃ ) layer is described. A method for forming the ferroelectric layer itself is also described. However, even with these technologies, sufficient capacity cannot be ensured in generations after the 150 nm rule. For example, the amount of residual polarization is not sufficient, and the leakage current cannot be sufficiently suppressed. Specifically, the leakage current of BiFeO ₃ at room temperature is 10 ⁻² A / cm ² or more and cannot be used for a ferroelectric memory as it is.

  Patent Document 2 describes that when a ferroelectric layer (perovskite oxide thin film) is subjected to heat treatment in a nitrogen atmosphere, the leakage current of the ferroelectric layer is reduced. However, Patent Document 2 does not describe a specific material for the perovskite oxide thin film. Moreover, there is no detailed description regarding the specific method and effect of heat processing.

  Patent Document 3 describes a technique for forming various metal oxide thin films by a sol-gel method. However, Patent Document 3 does not disclose a specific method for improving the electrical characteristics of the metal oxide thin film.

  Thus, although an effective technique for increasing the capacitance of the ferroelectric capacitor has been conventionally demanded, there is no sufficient one.

JP 2005-11931 A JP 2000-49285 A JP 2000-327311 A '2005 International Conference on Solid State Devices and Materials' Extended Abstract pp. 1026-1027

  An object of the present invention is to provide a semiconductor device that can obtain a high remanent polarization amount while obtaining good electrical characteristics, and a manufacturing method thereof.

  As a result of intensive studies to solve the above problems, the inventors of the present application have come up with various aspects of the invention shown below.

The semiconductor device according to the present invention includes a first electrode, a capacitor insulating film formed on the first electrode, and a second electrode formed on the capacitor insulating film. . A ferroelectric film represented by BiFe _1-X Cr _X O ₃ ( 0.03 ≦ X ≦ 0.08) is formed as the capacitive insulating film.

In the method for manufacturing a semiconductor device according to the present invention, a first conductive film is formed above a substrate, and then a ferroelectric film is formed on the first conductive film. Next, a second conductive film is formed on the ferroelectric film. As the ferroelectric film, a film represented by BiFe _1-X Cr _X O ₃ ( 0.03 ≦ X ≦ 0.08) is formed.

According to the present invention, since the film represented by BiFe _1-X Cr _X O ₃ ( 0.03 ≦ X ≦ 0.08) is used as the ferroelectric film, the leakage current is reduced as described later. A high remanent polarization amount can be obtained while achieving the above.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

(First embodiment)
First, a first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view showing a ferroelectric capacitor according to the first embodiment of the present invention.

  A ferroelectric capacitor 5 is formed on an insulating film 1 formed on or above a silicon substrate or the like. The ferroelectric capacitor 5 is provided with a lower electrode 2 formed on the insulating film 1, a capacitive insulating film 3 formed thereon, and an upper electrode 4 formed thereon.

As the upper electrode 4 and the lower electrode 2, for example, a noble metal film such as a Pt film, an Ir film, or a Ru film, or a conductive oxide film such as an IrO ₂ film, a SrRuO ₃ film, a YBCO film, or an LSCO film is formed. Yes.

Further, as the capacitive insulating film 3, a BiFe _1-x Cr _x O ₃ film is formed. This BiFe _1-X Cr _X O ₃ film is a film containing BiFeO ₃ as a main component, and the Cr content is more than 0 mol% and not more than 8 mol%, preferably 3 mol% to 8 mol%. That is, 1 mol of BiFe _1-X Cr _X O ₃ contains more than 0 mol and 0.08 mol or less, preferably 0.03 mol to 0.08 mol of Cr.

In the ferroelectric capacitor having such a structure, the residual polarization quantity Q _SW is 70 μC / cm ² or more, and the coercive electric field E _C is 0.3 MV / cm or less. In addition, the leak current I _leak is 1 × 10 ⁻³ A / cm ² or less when the applied electric field is within a range of 3 times the coercive electric field. That is, the leakage current I _leak can be kept low while obtaining a high residual polarization quantity Q _SW .

Further, when the frequency of the applied electric field is in the range of 1 × 10 ³ Hz to 1 × 10 ⁶ Hz, the relative dielectric constant ε _r is about 70 to 140.

  The reason why the electric characteristics of the ferroelectric capacitor according to the present embodiment are good is considered as follows.

For example, in the case of a capacitive insulating film made of BiFeO ₃ not added with Cr, when the electric field strength applied thereto is increased, the leak current increases remarkably when a predetermined electric field strength is exceeded. It was found. In this phenomenon, when the electric field strength applied to the ferroelectric increases, the hopping conduction of electrons occurs while changing the charge of Fe ions between divalent (Fe ²⁺ ) and trivalent (Fe ³⁺ ). It may be due to the mechanism.

Here, it is considered that the above-mentioned hopping conduction is suppressed by adding an appropriate amount (8 mol% or less, preferably 3 mol% to 8 mol%) of Cr to BiFeO ₃ . For example, Cr can be a divalent ion, a trivalent ion, or a tetravalent ion. For this reason, a model is considered in which electrons that are separated (hopped) from Fe ions are fixed by Cr (ions), while the charge changes on the Cr side.

  Further, it is considered that the leakage current may be suppressed by changing the abundance ratio of trivalent ions and divalent ions of Fe by addition of Cr.

  Next, a method for manufacturing the ferroelectric capacitor 5 will be described. FIG. 2 is a flowchart showing a method of manufacturing the ferroelectric capacitor 5, and FIG. 3 is a flowchart showing details of step S2 in FIG.

First, in step S1, a lower electrode film, which is a film serving as a base of the lower electrode 2, is formed on an insulating film 1 formed on or above a silicon substrate or the like. As the lower electrode film, for example, a noble metal film such as a Pt film or a conductive oxide film such as an IrO ₂ film is formed by, for example, a sputtering method, a CVD method, an epitaxial growth method, or the like.

Next, in step S <b> 2, a ferroelectric film serving as the source of the capacitive insulating film 3 is formed on the lower electrode film. Here, as the ferroelectric film, a BiFe _1-X Cr _X O ₃ film containing 8 mol% or less, preferably 3 mol% to 8 mol% of Cr is formed by a sol-gel method.

In forming the BiFe _1-X Cr _X O ₃ film, as shown in FIG. 3, first, in step S21, a sol-gel solution is applied onto the lower electrode film by, eg, spin coating. Then, a coating film having an appropriate thickness is formed. Here, for example, the rotation speed of the spinner is 2000 rpm to 3500 rpm, and the coating time is 10 seconds to 60 seconds. The thickness of the coating film is preferably 30 nm or less, for example, about 20 nm to 25 nm. In the conventional method, when the ferroelectric film is formed by spin coating, the thickness of the coating film is about 40 nm to 50 nm.

  Next, in step S22, the coating film is temporarily baked so that another film can be laminated thereon. In this temporary baking, first, drying is performed by heating at 150 ° C. to 250 ° C. for 1 minute to 10 minutes, and then heating is performed at 300 ° C. to 400 ° C. for 5 minutes to 20 minutes. In addition, these series of temporary baking are performed in air | atmosphere, for example.

  If the thickness of the ferroelectric film after the pre-baking does not reach the desired thickness, the process returns to step S21, and a coating film is formed again on the ferroelectric film after the pre-baking. Pre-baking is performed. Such a process is repeated until a ferroelectric film having a desired thickness (for example, 200 nm to 300 nm) is obtained. The standard of the number of repetitions is about 2 to 30 times.

  After the ferroelectric film having a desired thickness is obtained, in step S3, the ferroelectric film is subjected to main baking at 450 ° C. to 600 ° C. in an inert gas. The firing time is, for example, 5 minutes to 30 minutes.

Next, in step S4, an upper electrode film, which is a film serving as the base of the upper electrode 4, is formed on the ferroelectric film. As the upper electrode film, for example, a noble metal film such as a Pt film or a conductive oxide film such as an IrO ₂ film is formed by, for example, a sputtering method, a CVD method, an epitaxial growth method, or the like.

  Subsequently, in step S5, the upper electrode film, the ferroelectric film, and the lower electrode film are patterned. As a result, the upper electrode 4, the capacitor insulating film 3 and the lower electrode 2 are formed, and accordingly, the ferroelectric capacitor 5 is completed. These films may be patterned in a lump or may be individually patterned.

  The reason why the firing in step S3 is performed in an inert gas atmosphere is to realize a model for reducing the leakage current. For example, when firing in the atmosphere, the function of fixing hopped electrons by Cr does not work sufficiently due to the influence of oxygen present in the atmosphere, reducing the leakage current of the fired ferroelectric film It becomes difficult to do. For this reason, it is preferable to perform baking of step S3 in inert gas atmosphere. A gas that does not react with the ferroelectric film (for example, a rare gas or a nitrogen gas) may be used.

  The reason why the firing in step S3 is performed at 600 ° C. or less is to prevent the deterioration of the silicide that constitutes the gate contact of the cell selection transistor connected to the ferroelectric capacitor and the transistor used in the logic circuit. is there. That is, W silicide, Ti silicide, Co silicide, Ni silicide, or the like is used as the silicide, and the treatment is performed at a temperature lower than these heat resistant temperatures (about 600 ° C.). In addition, when the gate of the transistor is made of a material other than polycrystalline silicon, for example, in the case of a metal gate, it is necessary to perform the treatment at or below the heat resistant temperature.

(Second Embodiment)
Next, a manufacturing method of the stack type ferroelectric memory (semiconductor device) according to the second embodiment of the present invention will be described. 4A to 4G are cross-sectional views showing a method of manufacturing a ferroelectric memory according to the second embodiment of the present invention in the order of steps.

  First, as shown in FIG. 4A, an element isolation region 12 is formed on the surface of a semiconductor substrate 11 such as a silicon substrate by, for example, STI (shallow trench isolation). Next, a well 13 is formed on the surface of the semiconductor substrate 11 in the element active region partitioned by the element isolation region 12. Subsequently, the MOS transistor 14 is formed by forming the gate insulating film 17, the gate electrode 18, the low concentration impurity diffusion layer 16, the sidewall 20, the high concentration impurity diffusion layer 15, and the silicide layer 19 on the surface of the well 13. . One set of the low concentration impurity diffusion layer 16 and the high concentration impurity diffusion layer 15 constitutes one source / drain region. Each MOS transistor 14 is formed with two source / drain regions, one of which is shared between the two MOS transistors 14.

  Next, a silicon oxynitride film 21 is formed on the entire surface so as to cover the MOS transistor 14, and a silicon oxide film 22 is further formed on the entire surface by, for example, an organic CVD method. The silicon oxynitride film 21 is formed in order to prevent hydrogen deterioration of the gate insulating film 17 and the like when the silicon oxide film 22 is formed.

Thereafter, as shown in FIG. 4B, contact holes reaching the source / drain regions are formed in the silicon oxide film 22 and the silicon oxynitride film 21, thereby opening the plug contact portion. Then, after forming a laminated film made of a 50 nm TiN film and a 30 nm Ti film as the glue film 23 in the contact hole, a W film is buried by, for example, a CVD method and flattened by CMP (chemical mechanical polishing). As a result, the W plug 24 is formed. After the planarization is completed, the surface of the silicon oxide film 22 (interlayer insulating film) is slightly nitrided with plasma using NH ₃ gas.

Next, as shown in FIG. 4C, a lower electrode film 25, a ferroelectric film 26, and an upper electrode film 27 are sequentially formed on the entire surface (steps S1 to S4). As the ferroelectric film 26, a BiFe _1-x Cr _x O ₃ film is formed as in the first embodiment.

  Subsequently, the upper electrode film 27, the ferroelectric film 26, and the lower electrode film 25 are processed using patterning and etching techniques, so that the upper electrode film 27 becomes the upper electrode, the lower electrode film 25 becomes the lower electrode, A stack type ferroelectric capacitor is formed using the ferroelectric film 26 as a capacitive insulating film (step S5). In this processing, for example, a laminated film (not shown) of a plasma TEOS (tetraethyl orthosilicate) film and a TiN film is used as a hard mask, and the upper electrode film 27, the ferroelectric film 26, and the lower electrode film 25 are batched. And etch.

Next, an alumina protective film 28 covering the ferroelectric capacitor is formed on the entire surface. The alumina protective film 28 is formed by, for example, a CVD method, and the thickness thereof is, for example, 5 to 20 nm, and in this embodiment, 10 nm. The step coverage of the alumina protective film 28 is good. Subsequently, in-furnace annealing in an O ₂ atmosphere at 550 ° C. is performed for 60 minutes, thereby recovering etching damage generated in the ferroelectric film 26.

  Next, as shown in FIG. 4D, after an interlayer insulating film 29 is formed on the entire surface, it is planarized by CMP. As the interlayer insulating film 29, for example, a silicon oxide film is formed. The remaining film thickness after CMP is, for example, 400 nm on the upper electrode 27.

Subsequently, as shown in FIG. 4E, the W plug 24 connected to the source / drain region shared by the two MOS transistors 14 is formed on the interlayer insulating film 29 and the alumina protective film 28 using patterning and etching techniques. A contact hole reaching up to is formed. Next, after forming, for example, a 50 nm TiN film as a glue film 30 in the contact hole, a W film is buried by, for example, a CVD method, and planarized by CMP to form a W plug 31. Thereafter, the surface of the interlayer insulating film 29 and the W plug 31 is exposed to N ₂ plasma at 350 ° C., for example. The plasma processing time is, for example, 120 seconds.

Next, a W antioxidant film (not shown) is formed on the entire surface. As the W antioxidant film, for example, a SiON film can be used, and its thickness is, for example, about 100 nm. Then, using patterning and etching techniques, as shown in FIG. 4F, contact holes reaching the upper electrode film 27 and contact holes reaching the lower electrode film 25 (see FIG. 4F). (Not shown). Subsequently, annealing is performed to recover damage caused by hydrogen during etching of the interlayer insulating film 29 and damage caused by etching. This annealing may be, for example, in-furnace annealing at 550 ° C. in an O ₂ atmosphere, and the time is, for example, 60 minutes. After this annealing, the W antioxidant film is removed by etch back.

  Next, a glue film, a wiring material film, and a glue film are sequentially deposited. As the lower glue film, for example, a laminated film of a TiN film having a thickness of 70 nm and a Ti film having a thickness of 5 nm is formed, and as the wiring material film, for example, an Al—Cu alloy film having a thickness of 400 nm is formed. As the glue film, for example, a laminated film of a 30 nm thick TiN film and a 60 nm Ti film is formed.

  Next, an antireflection film (not shown) is formed on the upper glue film by coating, and a resist is further applied. Subsequently, the resist film is processed to match the wiring pattern, and the antireflection film, the upper glue film, the wiring material film, and the lower glue film are etched using the processed resist film as a mask. As the antireflection film, for example, a SiON film is formed, and the thickness thereof is, for example, about 30 nm. By such etching, as shown in FIG. 2F, the glue film 32, the wiring 33, and the glue film 34 that are electrically connected to the W plug 31 and / or the upper electrode film 27 are formed.

  Thereafter, as shown in FIG. 4G, an interlayer insulating film 35 is formed on the entire surface, and then planarized by CMP. For example, a silicon oxide film is formed as the interlayer insulating film 35. Subsequently, a contact hole reaching the glue film 34 is formed in the interlayer insulating film 35 using patterning and etching techniques. Next, after forming, for example, a 50 nm TiN film as a glue film 36 in the contact hole, a W film is buried by, for example, a CVD method, and planarized by CMP to form a W plug 37.

  Thereafter, further upper wirings, interlayer insulating films and the like are formed. Then, for example, a cover film made of a TEOS oxide film and a SiN film is formed to complete a ferroelectric memory having a ferroelectric capacitor. In forming the upper layer wiring, for example, the wiring 33 connected to the upper electrode film 27 is connected to the plate line, and the wiring connected to the source / drain region shared by the two MOS transistors 14 is used. 33 is connected to the bit line. The gate electrode 18 itself may be a word line, or the gate electrode 18 may be connected to the word line in the upper layer wiring.

  The ferroelectric memory manufactured as described above includes a ferroelectric capacitor similar to the ferroelectric capacitor according to the first embodiment. Therefore, the same effect as the first embodiment can be obtained. For example, it is possible to cope with further miniaturization, and when applied to a 65 nm rule process, the maximum memory capacity can be set to about 256 Mbit.

  The present invention can be applied to other than stacked ferroelectric capacitors, and can also be applied to memories having various three-dimensional structures. In this case, the memory capacity can be further increased. Further, the present invention may be applied to a semiconductor device other than a nonvolatile memory.

  Hereinafter, the contents and results of the tests conducted by the inventors will be described.

(First test)
In the first test, the relationship between the composition of the capacitive insulating film and the shape of the hysteresis loop (polarization-electric field curve) was verified. The sample was produced in the same manner as in the first embodiment. However, the value of X in the BiFe _1-X Cr _X O ₃ film was set to three types of 0, 0.03, and 0.06. The frequency of the applied electric field was 100 kHz, and the maximum electric field strength was ± 750 kV / cm. The result is shown in FIG. The broken line in FIG. 5 shows the hysteresis loop when X = 0, the solid line shows the hysteresis loop when X = 0.03, and the dotted line shows the hysteresis loop when X = 0.06.

As shown in FIG. 5, in the sample to which Cr was not added (X = 0), the slope of the hysteresis loop was gentle and the residual polarization amount was low. On the other hand, in the sample to which Cr was added (X = 0.03, 0.06), the slope of the hysteresis loop was steep and the residual polarization amount was high. For example, when X = 0.03, the residual polarization amount was 100 μC / cm ² . The coercive electric field was 258 kV / cm.

(Second test)
In the second test, the relationship between the composition of the capacitive insulating film and the leakage current was verified. The sample was produced in the same manner as in the first embodiment. However, the value of X in the BiFe _1-X Cr _X O ₃ film was set to three types of 0, 0.03, and 0.06. The result is shown in FIG. The solid line in FIG. 6 shows the change in leak current when X = 0, the broken line shows the change in leak current when X = 0.03, and the dotted line shows the change in leak current when X = 0.06 Is shown.

  As shown in FIG. 6, in the sample to which Cr was not added (X = 0), when the electric field exceeded about 30 kV / cm, the leakage current increased rapidly. On the other hand, in the sample to which Cr was added (X = 0.03, 0.06), the leakage current gradually increased with the increase of the electric field, but no rapid increase occurred.

(Third test)
In the third test, the relationship between the composition of the capacitive insulating film and the frequency dependence of the relative dielectric constant ε _r was verified. The sample was produced in the same manner as in the first embodiment. However, the value of X in the BiFe _1-X Cr _X O ₃ film was set to three types of 0, 0.03, and 0.06. The result is shown in FIG. The solid line in FIG. 7 shows the change in leak current when X = 0, the broken line shows the change in leak current when X = 0.03, and the dotted line shows the change in leak current when X = 0.06. Is shown.

As shown in FIG. 7, the relative dielectric constant ε _r was low in all samples. Incidentally, conventionally, the dielectric constant epsilon _r of PbZr _1-X Ti X O ₃ used is about 500, the dielectric constant epsilon _r of SrBi ₂ Ta ₂ O ₉ is approximately 200 to 300.

(Fourth test)
In the fourth test, the relationship between the composition and thickness of the capacitive insulating film and the orientation was verified. The sample was created in the same manner as in the first embodiment. However, six values of 0, 0.03, 0.06, 0.08, 0.1, and 0.2 were used for the value of X in the BiFe _1-X Cr _X O ₃ film. The thickness of the capacitive insulating film was set to four types of 200 nm, 300 nm, 400 nm, and 500 nm. The results are shown in FIGS. 8A to 8D. 8A shows the result of a sample having a thickness of 200 nm, FIG. 8B shows the result of a sample having a thickness of 300 nm, FIG. 8C shows the result of a sample having a thickness of 400 nm, and FIG. 8D shows the thickness of the sample. The result of a sample having a thickness of 500 nm is shown.

  As shown in FIGS. 8A to 8D, good orientation was obtained when the capacitance insulating film was approximately 200 nm or 300 nm thick and the value of X was 0.03 to 0.08. As shown in FIGS. 8A to 8D, the capacitive insulating film is mainly formed of (111), (012), (110), (024), (116), and (300) oriented. It has sex. That is, it can be said that the capacitor insulating film is not preferentially oriented in a specific plane orientation, but is composed of a randomly oriented polycrystal. The capacitor insulating film may be an epitaxial film that inherits the orientation of the lower electrode film.

1 is a cross-sectional view showing a ferroelectric capacitor according to a first embodiment of the present invention. 3 is a flowchart showing a method for manufacturing a ferroelectric capacitor 5; It is a flowchart which shows the detail of step S2 in FIG. It is sectional drawing which shows the manufacturing method of the ferroelectric memory which concerns on the 2nd Embodiment of this invention. FIG. 4B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 4A. FIG. 4B is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 4B. FIG. 4D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 4C. FIG. 4D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 4D. FIG. 4E is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 4E. FIG. 4F is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory, following FIG. 4F. It is a graph which shows the result of a 1st test. It is a graph which shows the result of the 2nd test. It is a graph which shows the result of a 3rd test. It is a graph which shows the result of a 4th test (film thickness: 200 nm). It is a graph which shows the result of the 4th test (film thickness: 300 nm). It is a graph which shows the result of a 4th test (film thickness: 400 nm). It is a graph which shows the result of the 4th test (film thickness: 500 nm).

Explanation of symbols

1: Insulating film 2: Lower electrode 3: Capacitive insulating film 4: Upper electrode 5: Ferroelectric capacitor 25: Lower electrode film 26: Ferroelectric film 27: Upper electrode film

Claims (10)

A first electrode;
A capacitive insulating film formed on the first electrode;
A second electrode formed on the capacitive insulating film;
Have
A semiconductor device, wherein a ferroelectric film represented by BiFe _1-X Cr _X O ₃ ( 0.03 ≦ X ≦ 0.08) is formed as the capacitive insulating film.   The semiconductor device according to claim 1, wherein a coercive electric field of the capacitive insulating film is 0.3 MV / cm or less. The leakage current between the first electrode and the second electrode is 10 ⁻³ A / cm ² or less when the electric field strength is −0.9 MV / cm to 0.9 MV / cm. The semiconductor device according to claim 1, wherein the semiconductor device is characterized. The relative dielectric constant of the capacitive insulating film is 70 to 140 when an electric field of 1 × 10 ³ Hz to 1 × 10 ⁶ Hz is applied between the first electrode and the second electrode. The semiconductor device according to claim 1, wherein:   5. The semiconductor device according to claim 1, wherein the capacitor insulating film has a thickness of 300 nm or less. Forming a first conductive film above the substrate;
Forming a ferroelectric film on the first conductive film;
Forming a second conductive film on the ferroelectric film;
Have
A method of manufacturing a semiconductor device, comprising forming a film represented by BiFe _1-X Cr _X O ₃ ( 0.03 ≦ X ≦ 0.08) as the ferroelectric film.   The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming the ferroelectric film is performed at 600 ° C. or lower. The step of forming the ferroelectric film includes
A step of repeating the formation of a coating film made of a sol-gel solution and the temporary baking of the coating film;
A step of performing main baking for the plurality of coating films after the preliminary baking;
The method of manufacturing a semiconductor device according to claim 6, wherein:   9. The method of manufacturing a semiconductor device according to claim 8, wherein the thickness of the coating film is 30 nm or less.   The method of manufacturing a semiconductor device according to claim 6, wherein a thickness of the ferroelectric film is 300 nm or less.

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