JP2011029507A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a gate current in driving in a semiconductor device including a normally-off-type transistor using a nitride semiconductor. <P>SOLUTION: The semiconductor device includes: a substrate 101; a first nitride semiconductor layer 104S made of a plurality of nitride semiconductor layers stacked on the substrate 101 and including a channel region; a second semiconductor layer 105 that is formed on the first nitride semiconductor layer 104S and is of the opposite conductivity type from the channel region; a third semiconductor layer 106 that is formed on the second semiconductor layer 105 and is of the same conductivity type as the channel region; a gate electrode 107 formed on the third semiconductor layer 106; and a source electrode 108 and a drain electrode 109 formed at both the sides of the second semiconductor layer 105. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a transistor using a nitride semiconductor that can be applied to a power transistor used in a power supply circuit of a consumer device.

  The group III nitride semiconductor is, for example, a wide gap semiconductor in which gallium nitride (GaN) and aluminum nitride (AlN) have large forbidden band widths at 3.4 eV and 6.2 eV, respectively. Group III nitride semiconductors are characterized by a large breakdown electric field and a higher electron saturation speed than arsenic semiconductors such as gallium arsenide (GaAs) and semiconductors such as silicon (Si). Therefore, research and development of field effect transistors (FETs) using GaN-based nitride semiconductors are actively conducted as high-frequency electronic devices or high-power electronic devices.

  Since GaN-based nitride semiconductors can obtain various mixed crystals with AlN or indium nitride (InN), it is possible to form heterojunctions as in the case of conventional arsenic semiconductors such as GaAs. Heterostructures using GaN-based nitride semiconductors, for example, AlGaN / GaN heterostructures, have the feature that high-concentration carriers are generated at the heterointerface due to spontaneous polarization and piezopolarization even when impurities are not doped. . For this reason, an FET using a GaN-based nitride semiconductor is likely to be a depletion type (normally on type) FET, and is unlikely to be an enhancement type (normally off type) FET. However, many of the devices currently used in the power electronics field are normally-off devices, and there is a strong demand for normally-off devices even in devices using GaN-based nitride semiconductors.

  The following structure has been reported as a structure for realizing a normally-off transistor. First, for example, in an AlGaN / GaN heterostructure, a so-called recess structure in which only a portion located under the gate electrode in the AlGaN layer is thinned to reduce the concentration of the two-dimensional electron gas (2DEG), thereby reducing the transistor Is shifted to a positive value. Thus, a normally-off transistor is realized. Secondly, for example, a GaN layer having a {11-20} plane is grown on the main surface of the sapphire substrate having a {10-12} plane orientation of the principal plane, and with respect to the principal plane of the sapphire substrate. The polarization electric field should not be generated in the vertical direction. Thus, a normally-off transistor is realized. Here, the minus sign attached to the Miller index of the plane orientation represents the inversion of one index following the minus sign for convenience.

  As a promising structure for realizing a normally-off type FET, a junction field effect transistor (JFET) in which a p-type AlGaN layer is provided in a gate electrode formation portion has been proposed. In this JFET, the potential energy of the AlGaN barrier layer and the GaN channel layer is increased by connecting the p-type AlGaN layer to a barrier layer made of AlGaN. Thereby, since the concentration of the two-dimensional electron gas formed under the gate electrode forming portion can be reduced, the JFET can be normally off.

JP 2006-339561 A

  However, the conventional JFET using a nitride semiconductor has a problem that the gate current increases when a large voltage is applied to the pn junction in the gate region.

  In the normally-off type FET using a nitride semiconductor, the following FET has been proposed for the purpose of obtaining a sufficiently large current density (see, for example, Patent Document 1). In this FET, an AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer, and a high-concentration p-type GaN layer are sequentially formed on a substrate. The gate electrode is in ohmic contact with the high-concentration p-type GaN layer. As a result, a pn junction generated by the two-dimensional electron gas generated at the interface between the undoped GaN layer and the undoped AlGaN layer and the p-type GaN layer is formed in the gate region. For this reason, even if a large gate voltage is applied, a gate leakage current hardly flows and a large drain current can be obtained.

  In view of the conventional problem, an object of the present invention is to reduce a gate current during driving in a semiconductor device including a normally-off transistor using a nitride semiconductor.

  In order to achieve the above object, according to the present invention, in a semiconductor device, a plurality of pn junctions are provided in gate regions in a plurality of stacked semiconductor layers.

  Specifically, in order to achieve the above object, a semiconductor device according to the present invention includes a substrate and a first nitride including a plurality of nitride semiconductor layers stacked on the substrate and including a channel region. Formed on the semiconductor layer and the first nitride semiconductor layer and having the same conductivity type as that of the channel region, formed on the second semiconductor layer of the opposite conductivity type to the channel region, and on the second semiconductor layer; The semiconductor device includes a third semiconductor layer, a gate electrode formed on the third semiconductor layer, and a source electrode and a drain electrode formed on both sides of the second semiconductor layer.

  According to the semiconductor device of the present invention, a diffusion potential (built-in potential) is formed between the second semiconductor layer having a conductivity type opposite to that of the channel region and the third semiconductor layer having the same conductivity type as that of the channel region. Therefore, the gate current can be reduced.

  In addition, since the second semiconductor layer has a conductivity type opposite to that of the channel region, the transistor can be normally off. Furthermore, it is possible to generate a high-concentration two-dimensional carrier gas at the interface between the carrier traveling layer and the carrier supply layer included in the first nitride semiconductor layer, and the transistor can be driven with a large current.

  Therefore, low on-resistance, large current drive, and normally-off operation are possible while reducing the gate current.

  In the semiconductor device according to the present invention, the carrier in the channel region is an electron, the conductivity type of the second semiconductor layer is preferably p-type, and the conductivity type of the third semiconductor layer is preferably n-type. .

  In this manner, a diffusion potential is formed between the p-type second semiconductor layer and the n-type third semiconductor layer, so that the gate current can be reduced.

  In the semiconductor device according to the present invention, it is preferable that the second semiconductor layer and the third semiconductor layer are alternately and repeatedly formed on the first nitride semiconductor layer.

  In this way, a diffusion potential is alternately and repeatedly formed between the second semiconductor layer and the third semiconductor layer, and between the third semiconductor layer and the second semiconductor layer. Can be further reduced.

  In the semiconductor device according to the present invention, the carrier in the channel region is an electron, the conductivity type of the second semiconductor layer is preferably p-type, and the conductivity type of the third semiconductor layer is preferably n-type. .

  In this case, alternating between the p-type second semiconductor layer and the n-type third semiconductor layer and between the n-type third semiconductor layer and the p-type second semiconductor layer. Since the diffusion potential is repeatedly formed, the gate current can be further reduced.

  In the semiconductor device according to the present invention, the first nitride semiconductor layer preferably includes a carrier travel layer and a carrier supply layer, and the carrier travel layer preferably has a smaller band gap than the carrier supply layer.

  In this way, it is possible to generate a high-concentration two-dimensional carrier gas at the interface between the carrier traveling layer and the carrier supply layer, and the transistor can be driven with a large current.

  In the semiconductor device according to the present invention, it is preferable that the third semiconductor layer has a larger band gap than the second semiconductor layer.

  In this case, the energy band of the second semiconductor layer and the energy band of the third semiconductor layer are discontinuous, so that the flow of electrons and holes can be reduced, and the gate current is reduced. It becomes possible to do.

  According to the semiconductor device of the present invention, the third semiconductor layer having the same conductivity type as the channel region is formed on the second semiconductor layer having the opposite conductivity type to the channel region. Thereby, the gate current can be reduced. Furthermore, low on-resistance, large current drive, and normally-off operation are possible while reducing the gate current.

1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
The semiconductor device according to the first embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to the first embodiment of the present invention.

  As shown in FIG. 1, for example, on the main surface of a substrate 101 made of sapphire having a (0001) plane orientation of the main surface, for example, a buffer layer 102 made of aluminum nitride (AlN) having a film thickness of 100 nm, for example, An undoped gallium nitride (GaN) layer 103 having a thickness of 2 μm, an undoped aluminum gallium nitride (AlGaN) layer 104 having a thickness of, for example, 25 nm, a p-type GaN layer 105 having a thickness of, for example, 150 nm, and a thickness of, for example, The n-type AlGaN layer 106 having a thickness of 30 nm is sequentially formed by epitaxial growth. Here, “undoped” means that impurities are not intentionally introduced.

Al _x Ga _1-x N (where x is 0 ≦ x ≦ 1) is used as the material of the undoped GaN layer 103, and Al _y Ga _1-y N (where x is 0 ≦ x ≦ 1) y is 0 <y ≦ 1, y> x), and Al _z Ga _1-z N (where z is 0 ≦ z ≦ 1) is used as the material of the p-type GaN layer 105. As the material of the n-type AlGaN layer 106, In _w Al _v Ga _{1 -wv} N (where w is 0 ≦ w ≦ 1, v is 0 ≦ v ≦ 1, and w and v are 0 ≦ w + v ≦ 1) may be used. In the present embodiment, for example, GaN (that is, x = 0) is used as the material of the undoped GaN layer 103, and Al _0.2 Ga _0.8 N (that is, y = 0.2) is used as the material of the undoped AlGaN layer 104, for example. For example, GaN (that is, z = 0) is used as the material of the p-type GaN layer 105, and Al _0.2 Ga _0.8 N (that is, w = 0, for example) is used as the material of the n-type AlGaN layer 106. v = 0.2).

The carrier concentration of the p-type GaN layer 105 may be any concentration that can deplete the channel region located under the p-type GaN layer 105, and specifically, for example, 1 × 10 ¹⁶ cm ⁻³ or more. preferable.

  A gate electrode 107 made of, for example, titanium (Ti) / aluminum (Al) is formed so as to be in contact with the n-type AlGaN layer 106. A source electrode 108 and a drain electrode 109 made of, for example, Ti / Al are formed on both sides of the p-type GaN layer 105 so as to be in contact with the undoped AlGaN layer 104.

  On the undoped AlGaN layer 104, the upper surfaces of the gate electrode 107, the source electrode 108, and the drain electrode 109 are exposed, and the silicon nitride having a thickness of, for example, 100 nm is covered so as to cover the p-type GaN layer 105 and the n-type AlGaN layer 106. An insulator layer 110 made of (SiN) is formed.

  In a region outside the region including the gate electrode 107, the source electrode 108, and the drain electrode 109, for example, non-conductive impurities such as argon (Ar) penetrate through the undoped AlGaN layer 104 and reach the upper portion of the undoped GaN layer 103. Thus, an ion-implanted region 111 that has been ion-implanted and increased in resistance (that is, made insulating or non-conductive), in other words, a non-conductive impurity-containing region containing a non-conductive impurity is formed.

  As described above, the first nitride semiconductor layer 104S in which the AlN buffer layer 102, the undoped GaN layer 103, and the undoped AlGaN layer 104 are sequentially stacked is formed on the substrate 101.

  The first nitride semiconductor layer 104S is located under the p-type GaN layer 105 and includes an n-type channel region (two-dimensional electron gas layer) in which electrons are used as carriers. A p-type GaN layer (second semiconductor layer) 105 having a conductivity type opposite to that of the n-type channel region is formed on the first nitride semiconductor layer 104S. On the p-type GaN layer 105, an n-type AlGaN layer 106 having the same conductivity type as that of the n-type channel region is formed.

  A first nitride semiconductor layer 104S including an n-type channel region, a p-type GaN layer 105, and an n-type AlGaN layer 106 are sequentially formed. The semiconductor device according to this embodiment includes a plurality of ( 2) including a pn junction.

  The first nitride semiconductor layer 104S includes a carrier travel layer (ie, undoped GaN layer 103) and a carrier supply layer (ie, undoped AlGaN layer 104). The undoped GaN layer 103 has a smaller band gap than the undoped AlGaN layer 104.

  The n-type AlGaN layer 106 has a larger band gap than the p-type GaN layer 105.

  According to the present embodiment, the built-in potential generated by the connection of the p-type GaN layer 105 (that is, the built-in formed between the first nitride semiconductor layer 104S including the n-type channel region and the p-type GaN layer 105). Potential) can reduce the electron current toward the gate electrode 107. In addition, due to the built-in potential generated by the connection of the n-type AlGaN layer 106 (that is, the built-in potential formed between the p-type GaN layer 105 and the n-type AlGaN layer 106), the gate electrode 107 changes to the undoped GaN layer 103. The heading hole current can be reduced, and the gate current can be reduced.

  In addition, since the p-type GaN layer 105 has a conductivity type opposite to that of the channel region, the transistor can be normally off. Furthermore, a high-concentration two-dimensional electron gas can be generated at the interface between the undoped GaN layer 103 and the undoped AlGaN layer 104, and the transistor can be driven with a large current.

  Therefore, low on-resistance, large current drive, and normally-off operation are possible while reducing the gate current.

  In the present embodiment, as shown in FIG. 1, the case where the p-type GaN layer 105 and the n-type AlGaN layer 106 are in direct contact with each other has been described as a specific example, but the present invention is limited to this. For example, between the p-type GaN layer and the n-type AlGaN layer, an undoped semiconductor layer (for example, an undoped InGaN layer or an undoped InAlGaN layer), another n-type semiconductor layer (for example, an n-type InGaN layer or One or more n-type InAlGaN layers) or other p-type semiconductor layers (for example, p-type InGaN layers or p-type InAlGaN layers) may be interposed. In the present embodiment, as shown in FIG. 1, the case where the n-type AlGaN layer 106 and the gate electrode 107 are in direct contact with each other has been described as a specific example. However, the present invention is not limited to this. For example, an undoped semiconductor layer (for example, an undoped InGaN layer or an undoped InAlGaN layer) or another n-type semiconductor layer (for example, an n-type InGaN layer or an n-type InAlGaN layer) between the n-type AlGaN layer and the gate electrode ) Or another p-type semiconductor layer (for example, a p-type InGaN layer or a p-type InAlGaN layer) may be interposed.

(Modification of the first embodiment)
A semiconductor device according to a modification of the first embodiment of the present invention will be described below with reference to FIG. FIG. 2 is a cross-sectional view showing a configuration of a semiconductor device according to a modification of the first embodiment of the present invention. In FIG. 2, the same reference numerals as those shown in FIG. 1 are given to the same constituent elements as those in the first embodiment. Therefore, in this modification, the description similar to that of the first embodiment is omitted as appropriate.

  The characteristic points of this modification are the following points. In this modification, as shown in FIG. 2, a recess 112 is formed in the gate region of the undoped AlGaN layer 104, and a p-type GaN layer 205 is formed so as to fill the recess 112.

  According to this modification, the same effect as that of the first embodiment can be obtained.

  In addition, by providing the recess 112 in the gate region of the undoped AlGaN layer 104, it is possible to reduce the concentration of the two-dimensional electron gas and shift the threshold voltage of the transistor to a positive value.

  Furthermore, by providing the recess 112 in the gate region of the undoped AlGaN layer 104, it is possible to increase the thickness of the region other than the gate region in the undoped AlGaN layer 104. For this reason, the two-dimensional electron gas layer located under the undoped AlGaN layer 104 (in other words, generated at the interface between the undoped GaN layer 103 and the undoped AlGaN layer 104) in the undoped AlGaN layer 104 other than the gate region. Since the distance to the two-dimensional electron gas layer can be increased, current collapse (here, “current collapse” means that electrons are trapped at the surface level between the gate and the source or between the gate and the drain. It is possible to suppress the occurrence of a phenomenon that the current decreases due to

(Second Embodiment)
A semiconductor device according to the second embodiment of the present invention will be described below with reference to FIG. FIG. 3 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention. In FIG. 3, the same reference numerals as those shown in FIG. 1 are given to the same constituent elements as those in the first embodiment. Therefore, in this embodiment, the same description as that of the first embodiment is omitted as appropriate.

  As shown in FIG. 3, on the main surface of a substrate 101 made of sapphire whose main surface has a plane orientation of (0001), for example, an AlN buffer layer 102 with a film thickness of 100 nm and an undoped film with a film thickness of 2 μm, for example. A GaN layer 103 and an undoped AlGaN layer 104 having a thickness of, for example, 25 nm are sequentially formed by epitaxial growth. Here, as described above, “undoped” means that impurities are not intentionally introduced.

Al _x Ga _1-x N (where x is 0 ≦ x ≦ 1) is used as the material of the undoped GaN layer 103, and Al _y Ga _1-y N (where x is 0 ≦ x ≦ 1) y may be 0 <y ≦ 1, y> x). In the present embodiment, for example, GaN (that is, x = 0) is used as the material of the undoped GaN layer 103, and Al _0.2 Ga _0.8 N (that is, y = 0.2) is used as the material of the undoped AlGaN layer 104, for example. Is used).

  On the undoped AlGaN layer 104, for example, a p-type NiO layer 305 having a thickness of 150 nm and an n-type ZnO layer 306 having a thickness of 50 nm, for example, are sequentially formed.

The carrier concentration of the p-type NiO layer 305 may be any concentration that can deplete the channel region located under the p-type NiO layer 305, and is preferably 1 × 10 ¹⁶ cm ⁻³ or more.

  A gate electrode 107 made of, for example, Ti / Al is formed so as to be in contact with the n-type ZnO layer 306. A source electrode 108 and a drain electrode 109 made of, for example, Ti / Al are formed on both sides of the p-type NiO layer 305 so as to be in contact with the undoped AlGaN layer 104.

  On the undoped AlGaN layer 104, the upper surfaces of the gate electrode 107, the source electrode 108, and the drain electrode 109 are exposed, and the p-type NiO layer 305 and the n-type ZnO layer 306 are covered with, for example, SiN having a thickness of 200 nm. An insulating layer 110 is formed.

  In a region outside the region including the gate electrode 107, the source electrode 108, and the drain electrode 109, a non-conductive impurity such as Ar penetrates the undoped AlGaN layer 104 and reaches the upper portion of the undoped GaN layer 103. An ion-implanted region 111 is formed by ion implantation and high resistance.

  Thus, on the substrate 101, the first nitride semiconductor layer 104S in which the AlN buffer layer 102, the undoped GaN layer 103, and the undoped AlGaN layer 104 are sequentially stacked is formed.

  The first nitride semiconductor layer 104S is located under the p-type NiO layer 305 and includes an n-type channel region (two-dimensional electron gas layer) in which electrons are used as carriers. A p-type NiO layer 305 having a conductivity type opposite to that of the n-type channel region is formed on the first nitride semiconductor layer 104S. On the p-type NiO layer 305, an n-type ZnO layer 306 having the same conductivity type as that of the n-type channel region is formed.

  A first nitride semiconductor layer 104S including an n-type channel region, a p-type NiO layer 305, and an n-type ZnO layer 306 are sequentially formed. The semiconductor device according to the present embodiment includes a plurality of ( 2) pn junction.

  According to the present embodiment, the electron current toward the gate electrode 107 can be reduced by the built-in potential generated by the connection of the p-type NiO layer 305. In addition, the built-in potential generated by the connection of the n-type ZnO layer 306 can reduce the hole current from the gate electrode 107 toward the undoped GaN layer 103, thereby reducing the gate current.

  In addition, since the p-type NiO layer 305 has a conductivity type opposite to that of the channel region, the transistor can be normally off. Furthermore, a high-concentration two-dimensional electron gas can be generated at the interface between the undoped GaN layer 103 and the undoped AlGaN layer 104, and the transistor can be driven with a large current.

  Therefore, low on-resistance, large current drive, and normally-off operation are possible while reducing the gate current.

In this embodiment, instead of the p-type NiO layer, for example, a p-type copper aluminum oxide (CuAl ₂ O ₂ ) layer, a p-type strontium copper oxide (SrCu ₂ O ₂ ) layer, a p-type lanthanum copper oxide P-type semiconductor layers such as p-type lanthanum copper selenium oxide (LaCuOSe) layers or p-type lanthanum copper sulfide (LaCuS) layers may be used. For example, an n-type ZnCdMgO layer may be used instead of the n-type ZnO layer. N-type semiconductor layers may be used.

(Third embodiment)
The semiconductor device according to the third embodiment of the present invention will be described below with reference to FIG. FIG. 4 is a cross-sectional view showing a configuration of a semiconductor device according to the third embodiment of the present invention. In FIG. 4, the same reference numerals as those shown in FIG. 1 are attached to the same constituent elements as those in the first embodiment. Therefore, in this embodiment, the same description as that of the first embodiment is omitted as appropriate.

  The difference between the present embodiment and the first embodiment is as follows.

  In the first embodiment, as shown in FIG. 1, a p-type GaN layer 105 having a thickness of, for example, 150 nm and an n-type AlGaN layer 106 having a thickness of, for example, 30 nm are sequentially formed on the undoped AlGaN layer 104. Has been. A gate electrode 107 made of, for example, Ti / Al is formed so as to be in contact with the n-type AlGaN layer 106.

  In contrast, in the present embodiment, as shown in FIG. 4, on the undoped AlGaN layer 104, for example, a p-type GaN layer 405 a having a thickness of 150 nm, and an n-type AlGaN layer 406 a having a thickness of 50 nm, for example, For example, a p-type GaN layer 405b having a thickness of 50 nm and an n-type AlGaN layer 406b having a thickness of 30 nm, for example, are sequentially formed. A gate electrode 107 made of, for example, Ti / Al is formed so as to be in contact with the n-type AlGaN layer 406b.

  Thus, in the first embodiment, the p-type GaN layer and the n-type AlGaN layer are alternately formed, whereas in this embodiment, the p-type GaN layer and the n-type AlGaN layer are alternately arranged. It is formed twice.

  According to this embodiment, the same effect as that of the first embodiment can be obtained.

  Furthermore, the number of energy barriers against the electron current going to the gate electrode 107 can be increased. In addition, since the number of energy barriers against the hole current from the gate electrode 107 toward the undoped GaN layer 103 can be increased, the gate current can be further reduced. That is, the built-in between the p-type GaN layer 405a and the n-type AlGaN layer 406a, between the n-type AlGaN layer 406a and the p-type GaN layer 405b, and between the p-type GaN layer 405b and the n-type AlGaN layer 406b. Since the potential is formed, the gate current can be further reduced.

  In the present embodiment, the case where the pair of the p-type GaN layer and the n-type AlGaN layer is formed twice has been described as a specific example, but the present invention is not limited to this. For example, a set of a p-type GaN layer and an n-type AlGaN layer may be repeatedly formed three times or more. As the number of repetitions is increased, the number of energy barriers for each of the electron current and hole current can be increased, so that the gate current can be further reduced.

In this embodiment, instead of the p-type GaN layer, for example, a p-type NiO layer, a p-type copper aluminum oxide (CuAl ₂ O ₂ ) layer, a p-type strontium copper oxide (SrCu ₂ O ₂ ) layer, p A p-type semiconductor layer such as a p-type lanthanum copper oxide layer, a p-type lanthanum copper selenium oxide (LaCuOSe) layer, or a p-type lanthanum copper sulfide (LaCuS) layer may be used. For example, instead of an n-type AlGaN layer, An n-type semiconductor layer such as an n-type ZnO layer or an n-type ZnCdMgO layer may be used.

  Further, in the first embodiment and its modifications, the second embodiment, and the third embodiment, for example, a Si substrate, a SiC substrate, a GaN substrate, or the like may be used instead of the sapphire substrate 101.

  The present invention can reduce a gate current in a semiconductor device including a normally-off type transistor using a nitride semiconductor. Therefore, for example, a transistor applicable to a power transistor used in a power circuit of a consumer device or the like. It is useful for a semiconductor device provided with

DESCRIPTION OF SYMBOLS 101 Substrate 102 AlN buffer layer 103 Undoped GaN layer 104 Undoped AlGaN layer 104S First nitride semiconductor layer 105, 205, 405a, 405b p-type GaN layer 305 p-type NiO layer 106, 306, 406a, 406b n-type AlGaN layer 306 n-type ZnO layer 107 gate electrode 108 source electrode 109 drain electrode 110 insulator layer 110 ion implantation region 112 recess

Claims (6)

A substrate,
A first nitride semiconductor layer comprising a plurality of nitride semiconductor layers stacked on the substrate and including a channel region;
A second semiconductor layer formed on the first nitride semiconductor layer and having a conductivity type opposite to the channel region;
A third semiconductor layer formed on the second semiconductor layer and having the same conductivity type as the channel region;
A gate electrode formed on the third semiconductor layer;
A semiconductor device comprising a source electrode and a drain electrode formed on both sides of the second semiconductor layer. The carriers in the channel region are electrons,
The conductivity type of the second semiconductor layer is p-type,
The semiconductor device according to claim 1, wherein a conductivity type of the third semiconductor layer is an n-type.   The semiconductor device according to claim 1, wherein the second semiconductor layer and the third semiconductor layer are alternately and repeatedly formed on the first nitride semiconductor layer. The carriers in the channel region are electrons,
The conductivity type of the second semiconductor layer is p-type,
The semiconductor device according to claim 3, wherein the conductivity type of the third semiconductor layer is n-type. The first nitride semiconductor layer includes a carrier travel layer and a carrier supply layer,
The semiconductor device according to claim 1, wherein the carrier travel layer has a band gap smaller than that of the carrier supply layer.   The semiconductor device according to claim 1, wherein the third semiconductor layer has a band gap larger than that of the second semiconductor layer.

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