JP2011003792A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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JP2011003792A
JP2011003792A JP2009146698A JP2009146698A JP2011003792A JP 2011003792 A JP2011003792 A JP 2011003792A JP 2009146698 A JP2009146698 A JP 2009146698A JP 2009146698 A JP2009146698 A JP 2009146698A JP 2011003792 A JP2011003792 A JP 2011003792A
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silicon nitride
nitride film
semiconductor substrate
film
element isolation
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Michihiro Ebe
通広 江部
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Lapis Semiconductor Co Ltd
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Oki Semiconductor Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for protecting the backside of a semiconductor substrate, reducing stress caused by a silicon nitride film on the backside, and preventing the semiconductor substrate from remarkably protrusively bending toward the front surface side.SOLUTION: The method of manufacturing the semiconductor device includes, in the following order, steps of: forming silicon nitride films on the front and back sides of a semiconductor substrate; leaving the silicon nitride film on the backside of the semiconductor substrate by reducing the film thickness of the silicon nitride film on the backside relative to the front face of the semiconductor substrate; forming a separation mask opening for selectively exposing the front surface of the semiconductor substrate on the silicon nitride film; forming an element isolation groove on the front face of the semiconductor substrate through the separation mask opening; oxidizing the inner surface of the element isolation groove; filling a silicon oxide film in the element isolation groove at a film thickness exceeding the depth of the element isolation groove; and flattening the silicon oxide film.

Description

本発明は、半導体装置の製造技術に関し、特に、半導体基板上に浅い素子分離溝を形成し、それを絶縁膜で埋め戻して素子分離領域を形成する技術を用いた半導体装置製造方法に関する。   The present invention relates to a semiconductor device manufacturing technique, and more particularly to a semiconductor device manufacturing method using a technique of forming a shallow element isolation trench on a semiconductor substrate and filling it with an insulating film to form an element isolation region.

従来の半導体プロセスにおいて、シリコンなどの半導体基板(ウエハともいう)上の隣接半導体素子間の電気的絶縁を行う素子分離領域はLOCOS(Local Oxidation of Silicon)法と呼ばれる技術によって形成されていた。しかし、LOCOS法では有効である素子形成領域を狭めてしまうために、近年、LSI(半導体集積回路)の微細化が進行するにつれて、最近はSTI(Shallow Trench Isolation)法と呼ばれる、ウエハ上にシリコン窒化膜のようなストッパ膜を付着させ、素子分離溝(トレンチともいう)内にシリコン酸化膜のような絶縁膜を埋め込み、溝の外部の余分な絶縁膜を化学機械研磨(CMP:chemical vapor polishing)を用いて平担化し、ストッパ膜を露出させ、その後ストッパ膜をエッチング除去する方法が採用されている。CMP研磨液(スラリ)は、ストッパ膜に対する絶縁膜の研磨速度選択比が低く、トレンチが密集した部分の研磨がトレンチの疎な部分に比べ進行してしまい、シニングが発生するという問題がある。また、シニングを防ぐためにストッパ膜を厚くすると、ストッパ膜のシリコン窒化膜の残留応力がウエハに影響するようになる。   In a conventional semiconductor process, an element isolation region that performs electrical insulation between adjacent semiconductor elements on a semiconductor substrate (also referred to as a wafer) such as silicon is formed by a technique called a LOCOS (Local Oxidation of Silicon) method. However, in order to narrow the element formation region effective in the LOCOS method, in recent years, as the miniaturization of LSI (semiconductor integrated circuit) has progressed, silicon called on the STI (Shallow Trench Isolation) method has recently been developed. A stopper film such as a nitride film is attached, an insulating film such as a silicon oxide film is embedded in an element isolation groove (also referred to as a trench), and an extra insulating film outside the groove is subjected to chemical mechanical polishing (CMP). ), The stopper film is exposed, and then the stopper film is removed by etching. The CMP polishing liquid (slurry) has a problem that the polishing rate selection ratio of the insulating film to the stopper film is low, and the polishing of the portion where the trenches are densely progresses as compared with the sparse portion of the trenches, resulting in thinning. If the stopper film is thickened to prevent thinning, the residual stress of the silicon nitride film of the stopper film affects the wafer.

従来の一般的な半導体装置のSTI形成方法について、図面を参照しながらその概略を説明する。図1は半導体装置におけるSTIの製造工程を順に示したウエハの概略部分断面図である。   An outline of a conventional general STI forming method of a semiconductor device will be described with reference to the drawings. FIG. 1 is a schematic partial cross-sectional view of a wafer sequentially illustrating STI manufacturing steps in a semiconductor device.

図1に示すように、ウエハ1上に、シリコン酸化膜2,2b、シリコン窒化膜3,3bの順に積層形成し(図1(a))、ウエハ1表面側にてレジストパターン(図示せず)をマスクとして用い、表面(被処理面)側のシリコン窒化膜3、シリコン酸化膜2を順次パターニングし(図1(b))、次いで、両膜の一部が除去され露出したウエハ1の素子分離領域をさらに異方性エッチングし、露出したウエハ1にトレンチTを形成し(図1(c))、CMP法により、トレンチTを絶縁膜4で埋めるようにウエハ1の表面全面に絶縁膜4を形成し(図1(d))、その後、シリコン窒化膜3をストッパとしたCMPによりシリコン窒化膜3上部に形成された絶縁膜4を除去することにより、トレンチT内部にのみ絶縁膜4を残して素子分離構造を形成し(図1(e))、次いで、熱リン酸溶液により、シリコン窒化膜3,3bを除去する(図1(f))。   As shown in FIG. 1, silicon oxide films 2 and 2b and silicon nitride films 3 and 3b are stacked in this order on a wafer 1 (FIG. 1A), and a resist pattern (not shown) is formed on the wafer 1 surface side. ) As a mask, the silicon nitride film 3 and the silicon oxide film 2 on the surface (surface to be processed) side are sequentially patterned (FIG. 1B), and then a part of both films is removed and exposed on the wafer 1 The element isolation region is further anisotropically etched to form a trench T in the exposed wafer 1 (FIG. 1C), and is insulated over the entire surface of the wafer 1 by CMP to fill the trench T with the insulating film 4. A film 4 is formed (FIG. 1D), and then the insulating film 4 formed on the silicon nitride film 3 is removed by CMP using the silicon nitride film 3 as a stopper, so that the insulating film is formed only inside the trench T. 4 leaving element isolation structure To form a (FIG. 1 (e)), followed by hot phosphoric acid solution, to remove the silicon nitride film 3, 3b (FIG. 1 (f)).

しかしながら、上記STI方法では図1(b)に示すパターニングする工程において、部分的に露出したウエハ表面と全面にシリコン窒化膜が形成されている裏面との間で、残留応力に差が生じウエハ1が表面側に大きく凸に反るため、強い応力に起因する結晶欠陥等をウエハの表面側に発生させる原因ともなり、トランジスタ特性や分離特性に悪影響を与えることがある。   However, in the STI method, in the patterning step shown in FIG. 1B, a difference in residual stress occurs between the partially exposed wafer surface and the back surface on which the silicon nitride film is formed on the entire surface. Since the surface warps greatly on the surface side, it may cause crystal defects or the like due to strong stress on the surface side of the wafer, which may adversely affect transistor characteristics and isolation characteristics.

ウエハの表裏面に成膜されたシリコン窒化膜は、シリコン酸化膜よりヤング率が高いため、熱処理等を行う際、シリコン窒化膜に発生した応力はシリコン窒化膜中では緩和されず、ウエハに応力を与えることとなる。そのため、ウエハに歪み、ウエハ表面で転移、結晶欠陥などを発生させる。   Since the silicon nitride film formed on the front and back surfaces of the wafer has a higher Young's modulus than the silicon oxide film, the stress generated in the silicon nitride film is not relaxed in the silicon nitride film during heat treatment or the like, and stress is applied to the wafer. Will be given. For this reason, the wafer is distorted, and transfer, crystal defects, etc. are generated on the wafer surface.

この問題点を解決するために、ウエハ裏面の窒化膜をすべて除去する方法が用いられていた(特許文献1、参照)。   In order to solve this problem, a method of removing all the nitride films on the back surface of the wafer has been used (see Patent Document 1).

特開2005−340734号公報JP 2005-340734 A

しかしながら、従来方法では、ウエハ裏面のシリコン窒化膜をすべて除去するので、ウエハ表面の異方性エッチングによる後のトレンチ形成工程において、表面から裏面にエッチングガスが回り込みによるウエハ裏面の汚染が懸念される。   However, since all of the silicon nitride film on the back surface of the wafer is removed by the conventional method, there is a concern about contamination of the back surface of the wafer due to etching gas flowing from the front surface to the back surface in the subsequent trench formation process by anisotropic etching of the wafer surface. .

そこで、本発明は、ウエハの裏面を汚染から保護するとともに裏面のシリコン窒化膜に起因する応力を軽減し、ウエハが表面側に大きく凸に反るというの不具合を改善した半導体素子の製造方法を提供することを目的としている。   Therefore, the present invention provides a method for manufacturing a semiconductor device that protects the back surface of a wafer from contamination, reduces stress caused by the silicon nitride film on the back surface, and improves the problem of the wafer warping greatly on the front surface side. It is intended to provide.

本発明の半導体装置製造方法は、半導体基板の表裏面上にシリコン窒化膜を形成する工程と、半導体基板の表面よりも裏面のシリコン窒化膜の膜厚を薄くして半導体基板の裏面のシリコン窒化膜を残す工程と、半導体基板の表面を選択的に露出させる分離マスク開口部をシリコン窒化膜に形成する工程と、分離マスク開口部を通して半導体基板の表面に素子分離溝を形成する工程と、素子分離溝の内面を酸化する工程と、素子分離溝の深さを越える膜厚で素子分離溝にシリコン酸化膜を充填する工程と、シリコン酸化膜を平坦化する工程とを、この順序に有することを特徴とする。本発明は、半導体集積回路の中で、特に、素子分離溝(トレンチ)の形成前に、半導体基板裏面に形成されるシリコン窒化膜を薄くすることで、トレンチ形成後の半導体基板の反りを抑制する。   The method of manufacturing a semiconductor device of the present invention includes a step of forming a silicon nitride film on the front and back surfaces of a semiconductor substrate, and a silicon nitride film on the back surface of the semiconductor substrate by reducing the thickness of the silicon nitride film on the back surface of the semiconductor substrate. A step of leaving a film, a step of forming an isolation mask opening for selectively exposing the surface of the semiconductor substrate in the silicon nitride film, a step of forming an element isolation groove on the surface of the semiconductor substrate through the isolation mask opening, and an element A process of oxidizing the inner surface of the isolation groove, a process of filling the element isolation groove with a silicon oxide film with a film thickness exceeding the depth of the element isolation groove, and a process of flattening the silicon oxide film in this order It is characterized by. The present invention suppresses warpage of a semiconductor substrate after forming a trench by thinning a silicon nitride film formed on the back surface of the semiconductor substrate, particularly before forming an element isolation trench (trench) in a semiconductor integrated circuit. To do.

上記半導体装置製造方法のシリコン窒化膜を残す工程においては、半導体基板の裏面のシリコン窒化膜の膜厚は、半導体基板の裏面のシリコン窒化膜の残留応力と分離マスク開口部が形成されたシリコン窒化膜の残留応力とが相殺される膜厚であることとすることができる。本発明は、トレンチ形成前に、裏面に形成されるシリコン窒化膜をトレンチのパターンレシオ(半導体基板の表面に形成されたシリコン窒化膜の面積に対する当該シリコン窒化膜に形成された分離マスク開口部の面積の比率)と同じ比率だけウェットエッチングで除去することで、トレンチ形成後の半導体基板の反りを完全に抑制する。   In the step of leaving the silicon nitride film in the semiconductor device manufacturing method, the film thickness of the silicon nitride film on the back surface of the semiconductor substrate is the same as the silicon nitride film in which the residual stress of the silicon nitride film on the back surface of the semiconductor substrate and the isolation mask opening are formed. It can be a film thickness that cancels out the residual stress of the film. According to the present invention, before forming a trench, a silicon nitride film formed on the back surface is formed with a trench pattern ratio (an isolation mask opening formed in the silicon nitride film with respect to the area of the silicon nitride film formed on the surface of the semiconductor substrate). By removing the same ratio as the area ratio) by wet etching, the warpage of the semiconductor substrate after the trench formation is completely suppressed.

上記半導体装置製造方法においては、半導体基板の裏面のシリコン窒化膜は、トレンチのパターンレシオ以上の膜厚にウェットエッチングで減少されることとすることができる。   In the semiconductor device manufacturing method, the silicon nitride film on the back surface of the semiconductor substrate can be reduced by wet etching to a film thickness equal to or greater than the pattern ratio of the trench.

上記半導体装置製造方法においては、シリコン窒化膜を半導体基板上に直接またはシリコン酸化膜などの他の層を介して形成することとすることができる。   In the semiconductor device manufacturing method, the silicon nitride film can be formed directly on the semiconductor substrate or via another layer such as a silicon oxide film.

本発明の半導体装置製造方法によれば、半導体STI−CMPプロセスにおいて、ウエハの表裏面上にシリコン窒化膜を形成する工程後の分離マスク開口部をシリコン窒化膜に形成する工程の前に、ウエハ裏面に形成されるシリコン窒化膜の膜厚を薄くする、好ましくはトレンチのパターンレシオに応じた膜厚分だけ除去することで、トレンチ形成後のウエハの反りを完全に抑制し、結晶欠陥を抑制することができる。   According to the semiconductor device manufacturing method of the present invention, in the semiconductor STI-CMP process, the wafer is formed before the step of forming the isolation mask opening in the silicon nitride film after the step of forming the silicon nitride film on the front and back surfaces of the wafer. By reducing the thickness of the silicon nitride film formed on the back surface, preferably by the thickness corresponding to the pattern ratio of the trench, the warpage of the wafer after trench formation is completely suppressed and crystal defects are suppressed. can do.

半導体STI−CMPプロセスのウエハを示す概略部分断面図である。It is a schematic fragmentary sectional view which shows the wafer of a semiconductor STI-CMP process. 本発明による実施形態の半導体STI−CMPプロセスを示す概略部分断面図である。1 is a schematic partial cross-sectional view illustrating a semiconductor STI-CMP process according to an embodiment of the present invention.

1 ウエハ
2,2b シリコン酸化膜
3,3b シリコン窒化膜
4 NSG膜
M 分離マスク開口部
T トレンチ
1 Wafer 2, 2b Silicon oxide film 3, 3b Silicon nitride film 4 NSG film M Isolation mask opening T Trench

以下に、本発明による一実施形態の半導体装置製造方法について、図面を用いて説明する。   A semiconductor device manufacturing method according to an embodiment of the present invention will be described below with reference to the drawings.

図2は半導体装置製造方法におけるSTI−CMPプロセスを順に示したウエハの概略部分断面図である。   FIG. 2 is a schematic partial cross-sectional view of a wafer sequentially illustrating an STI-CMP process in the semiconductor device manufacturing method.

まず、図2(a)に示すように、ウエハ1の表裏面上に、シリコン酸化膜2,2b、シリコン窒化膜3,3bを順に積層形成する。例えば、シリコン酸化膜は表面酸化によって形成され、シリコン窒化膜は低圧または常圧の化学気相成長(CVD:Chemical Vapor Deposition)などによって形成される。   First, as shown in FIG. 2A, silicon oxide films 2 and 2 b and silicon nitride films 3 and 3 b are sequentially stacked on the front and back surfaces of the wafer 1. For example, the silicon oxide film is formed by surface oxidation, and the silicon nitride film is formed by low pressure or normal pressure chemical vapor deposition (CVD).

次に、図2(b)に示すように、ウエハ1の裏面に形成されたシリコン窒化膜3bを、後に形成すべきトレンチのパターンレシオ(後述する)と同じ比率だけウェットエッチングで除去し、シリコン窒化膜3b膜厚を減少させる(いわゆるバックエッチング工程)。   Next, as shown in FIG. 2B, the silicon nitride film 3b formed on the back surface of the wafer 1 is removed by wet etching by the same ratio as the pattern ratio (to be described later) of a trench to be formed later. The thickness of the nitride film 3b is reduced (so-called back etching process).

次に、図2(c)に示すように、レジストパターン(図示せず)をマスクとして用い、ウエハ1の表面(被処理面)側のシリコン窒化膜3、シリコン酸化膜2を順次パターニングする。シリコン窒化膜3とシリコン酸化膜2は、フォトリソグラフィー工程のエッチングによって、ウエハ1の所定部分が露出するように分離マスク開口部Mが形成されたマスクとして、形成される。ここで、露出したウエハ表面部分は予定の素子分離領域である。   Next, as shown in FIG. 2C, the silicon nitride film 3 and the silicon oxide film 2 on the surface (surface to be processed) side of the wafer 1 are sequentially patterned using a resist pattern (not shown) as a mask. The silicon nitride film 3 and the silicon oxide film 2 are formed as a mask in which an isolation mask opening M is formed so that a predetermined portion of the wafer 1 is exposed by etching in a photolithography process. Here, the exposed wafer surface portion is a predetermined element isolation region.

次に、図2(d)に示すように、ウエハ1の表面にトレンチTを形成する。分離マスク開口部Mを通して、露出したウエハは所定深さだけ異方性エッチングされてトレンチTが形成される。   Next, as shown in FIG. 2D, a trench T is formed on the surface of the wafer 1. Through the separation mask opening M, the exposed wafer is anisotropically etched by a predetermined depth to form a trench T.

次に、図2(e)に示すように、熱酸化によりトレンチTの内壁に熱シリコン酸化膜Hを形成した後、CVD法により、トレンチTがNSG膜4で埋まるように、すなわち、トレンチTの深さを越える膜厚でウエハ1表面全面にNSG膜4を形成する。ここで、NSG膜4は、例えば、Tetra Ethyl Ortho Silicateを用いたO3−TEOS−CVD装置などにより作製したNSG(None-doped Silicate Glass)、すなわち、不純物を含まないシリコン酸化膜である。ここで、トレンチT部分の上に形成されたNSG膜にトレンチの段差によって凹みが形成される。 Next, as shown in FIG. 2E, after the thermal silicon oxide film H is formed on the inner wall of the trench T by thermal oxidation, the trench T is filled with the NSG film 4 by CVD, that is, the trench T An NSG film 4 is formed on the entire surface of the wafer 1 with a film thickness exceeding the depth of the first wafer. Here, the NSG film 4 is an NSG (None-doped Silicate Glass) produced by, for example, an O 3 -TEOS-CVD apparatus using Tetra Ethyl Ortho Silicate, that is, a silicon oxide film containing no impurities. Here, a recess is formed in the NSG film formed on the trench T portion by the step of the trench.

その後、図2(f)に示すように、シリコン窒化膜3をストッパとしたCMP法によりシリコン窒化膜3上部に形成されたNSG膜4を除去することによりトレンチT内部にのみNSG膜4を残し素子分離領域を形成する。   Thereafter, as shown in FIG. 2F, the NSG film 4 formed on the silicon nitride film 3 is removed by the CMP method using the silicon nitride film 3 as a stopper to leave the NSG film 4 only in the trench T. An element isolation region is formed.

次いで、図2(g)に示すように、熱リン酸処理によりシリコン窒化膜3,3bを除去する。   Next, as shown in FIG. 2G, the silicon nitride films 3 and 3b are removed by hot phosphoric acid treatment.

以上の半導体装置製造方法において、シリコン窒化膜3、シリコン酸化膜2を順次パターニングする工程(図2(c))の前に、図2(b)に示すバックエッチング工程、すなわち、裏面に形成されるシリコン窒化膜を、トレンチTのパターンレシオ(ウエハ1の表面に形成されたシリコン窒化膜3の面積Bに対するシリコン窒化膜3に形成された分離マスク開口部Mの面積Aの比率:A/B)と同じ比率だけ除去する。一例としては、例えば、シリコン窒化膜を1500オングストローム厚で堆積し、トレンチTのパターンレシオが40%の場合、表面にはマスクのパターンレシオ60%のシリコン窒化膜が残るため、シリコン窒化膜が全面に堆積されている裏面と60%堆積されている表面との間で、応力に40%の差が生じる。そのため、トレンチTのパターンレシオ40%である600オングストローム厚の裏面のシリコン窒化膜をウェットエッチングまで除去して、表面のマスクのパターンレシオ60%である900オングストローム厚のシリコン窒化膜を裏面に残す。すなわち、図2(b)に示すシリコン窒化膜を残す工程において、ウエハの裏面のシリコン窒化膜3bの膜厚は、ウエハの裏面のシリコン窒化膜3bの残留応力と分離マスク開口部が形成された表面のシリコン窒化膜3の残留応力とが相殺される膜厚に設定する。   In the above semiconductor device manufacturing method, before the step of sequentially patterning the silicon nitride film 3 and the silicon oxide film 2 (FIG. 2C), the back etching step shown in FIG. The pattern ratio of the trench T (the ratio of the area A of the isolation mask opening M formed in the silicon nitride film 3 to the area B of the silicon nitride film 3 formed on the surface of the wafer 1: A / B ) Is removed at the same rate as). As an example, for example, when a silicon nitride film is deposited with a thickness of 1500 angstroms and the pattern ratio of the trench T is 40%, a silicon nitride film with a mask pattern ratio of 60% remains on the surface. There is a 40% difference in stress between the backside deposited on the surface and the 60% deposited surface. Therefore, the silicon nitride film on the back surface having a thickness of 600 Å having a pattern ratio of 40% of the trench T is removed until wet etching, and a silicon nitride film having a thickness of 900 Å having a pattern ratio of 60% on the front surface is left on the back surface. That is, in the step of leaving the silicon nitride film shown in FIG. 2B, the silicon nitride film 3b on the back surface of the wafer has the residual stress of the silicon nitride film 3b on the back surface of the wafer and the separation mask opening. The film thickness is set so as to cancel out the residual stress of the silicon nitride film 3 on the surface.

上記の実施例によれば、トレンチ形成前にトレンチのパターンレシオと同じ比率だけでなく、トレンチのパターンレシオ以上の膜厚にウェットエッチングで減少することにより、裏面と表面との間で、応力の差が完全に解消され、強いストレスに起因するウエハの表面側の結晶欠陥等を抑制することができる。   According to the above embodiment, not only the same ratio as the trench pattern ratio but also the thickness of the trench pattern ratio or more is reduced by wet etching before the trench formation, so that stress is reduced between the back surface and the front surface. The difference is completely eliminated, and crystal defects on the surface side of the wafer caused by strong stress can be suppressed.

上記の実施例の半導体装置製造方法においては、シリコン窒化膜とウエハの間に自然酸化膜などシリコン酸化膜を積層しているが、本発明はこれに限定されず、ウエハ上にシリコン窒化膜を直接して形成することもできる。   In the semiconductor device manufacturing method of the above embodiment, a silicon oxide film such as a natural oxide film is laminated between the silicon nitride film and the wafer. However, the present invention is not limited to this, and the silicon nitride film is formed on the wafer. It can also be formed directly.

更に、上記の実施例では半導体基板としてシリコン基板を対象としたが、本発明は必ずしもシリコンバルクのプロセスに限定するものではなく、例えば、シリコンカーバイド(SiC)基板や、EPI層を有したシリコン基板、SOI(Silicon-on-Insulator)基板にも適用可能である。   Furthermore, in the above embodiment, a silicon substrate is targeted as a semiconductor substrate. However, the present invention is not necessarily limited to a silicon bulk process. For example, a silicon carbide (SiC) substrate or a silicon substrate having an EPI layer is used. It can also be applied to SOI (Silicon-on-Insulator) substrates.

Claims (4)

半導体基板の表裏面上にシリコン窒化膜を形成する工程と、
前記半導体基板の表面よりも裏面の前記シリコン窒化膜の膜厚を薄くして前記半導体基板の裏面の前記シリコン窒化膜を残す工程と、
前記半導体基板の表面を選択的に露出させる分離マスク開口部を前記シリコン窒化膜に形成する工程と、
前記分離マスク開口部を通して前記半導体基板の表面に素子分離溝を形成する工程と、
前記素子分離溝の内面を酸化する工程と、
前記素子分離溝の深さを越える膜厚で前記素子分離溝にシリコン酸化膜を充填する工程と、
前記シリコン酸化膜を平坦化する工程とを、この順序に有することを特徴とする半導体装置製造方法。
Forming a silicon nitride film on the front and back surfaces of the semiconductor substrate;
Reducing the thickness of the silicon nitride film on the back surface of the semiconductor substrate to leave the silicon nitride film on the back surface of the semiconductor substrate;
Forming a separation mask opening in the silicon nitride film to selectively expose the surface of the semiconductor substrate;
Forming an element isolation trench on the surface of the semiconductor substrate through the isolation mask opening;
Oxidizing the inner surface of the element isolation trench;
Filling the element isolation trench with a silicon oxide film with a film thickness exceeding the depth of the element isolation trench;
And a step of planarizing the silicon oxide film in this order.
前記シリコン窒化膜を残す工程において、前記半導体基板の裏面の前記シリコン窒化膜の膜厚は、前記半導体基板の裏面の前記シリコン窒化膜の残留応力と前記分離マスク開口部が形成された前記シリコン窒化膜の残留応力とが相殺される膜厚であることを特徴とする請求項1記載の半導体装置製造方法。   In the step of leaving the silicon nitride film, the film thickness of the silicon nitride film on the back surface of the semiconductor substrate is such that the residual stress of the silicon nitride film on the back surface of the semiconductor substrate and the silicon nitride film in which the isolation mask opening is formed. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the film thickness cancels out the residual stress of the film. 前記シリコン窒化膜を残す工程において、前記半導体基板の裏面の前記シリコン窒化膜は、前記半導体基板の表面に形成された前記シリコン窒化膜の面積に対する前記シリコン窒化膜に形成された前記分離マスク開口部の面積の比率以上の膜厚に減少されることを特徴とする請求項1又は2記載の半導体装置製造方法。   In the step of leaving the silicon nitride film, the silicon nitride film on the back surface of the semiconductor substrate has the isolation mask opening formed in the silicon nitride film with respect to the area of the silicon nitride film formed on the surface of the semiconductor substrate. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the film thickness is reduced to a thickness equal to or greater than the ratio of the area. 前記シリコン窒化膜を半導体基板上に直接または他の層を介して形成することを特徴とする請求項1乃至3のいずれか1記載の半導体装置製造方法。   4. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon nitride film is formed directly on the semiconductor substrate or via another layer.
JP2009146698A 2009-06-19 2009-06-19 Method of manufacturing semiconductor device Pending JP2011003792A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104282549A (en) * 2013-07-03 2015-01-14 无锡华润上华半导体有限公司 Back structure protecting method
CN106033706A (en) * 2015-03-11 2016-10-19 旺宏电子股份有限公司 Semiconductor element and manufacturing method thereof
CN112635477A (en) * 2020-12-07 2021-04-09 华虹半导体(无锡)有限公司 Method for manufacturing flash memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104282549A (en) * 2013-07-03 2015-01-14 无锡华润上华半导体有限公司 Back structure protecting method
CN106033706A (en) * 2015-03-11 2016-10-19 旺宏电子股份有限公司 Semiconductor element and manufacturing method thereof
CN112635477A (en) * 2020-12-07 2021-04-09 华虹半导体(无锡)有限公司 Method for manufacturing flash memory device

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