JP2010534938A - Multijunction solar cell and method and apparatus for forming multijunction solar cell - Google Patents

Abstract

Embodiments of the present invention generally relate to solar cells and methods and apparatus for forming solar cells. More particularly, embodiments of the invention relate to thin film multijunction solar cells and methods and apparatus for forming thin film multijunction solar cells. Embodiments of the present invention also include improved thin film silicon solar cells and methods and apparatus for forming improved thin film silicon solar cells, wherein one or more of the layers in the solar cell are improved electrical It comprises at least one amorphous silicon layer that has mechanical characteristics and mechanical properties and can be deposited at a rate that is many times faster than conventional amorphous silicon deposition processes.
[Selection] Figure 1

Description

Background of the Invention

Field of Invention
[0001] Embodiments of the present invention generally relate to solar cells and methods and apparatus for forming solar cells. More particularly, embodiments of the invention relate to thin film multijunction solar cells and methods and apparatus for forming thin film multijunction solar cells.

Details of related technology
[0002] Solar cells convert solar radiation and other light into usable electrical energy. Energy conversion occurs as a result of the photovoltaic effect. Solar cells may be formed from crystalline or amorphous materials or microcrystalline materials. In general, there are two main types of solar cells that are mass-produced today: crystalline silicon solar cells and thin film solar cells. Crystalline silicon solar cells typically use either a single crystal substrate (ie, a single crystal substrate of pure silicon) or a multiple crystal silicon substrate (ie, polycrystal or polysilicon). Additional film layers are deposited on the silicon substrate to improve light capture, form an electrical circuit and protect the device. Thin film solar cells use a thin layer of material deposited on a suitable substrate to form one or more pn junctions. Suitable substrates include glass, metal and polymer substrates. It has been found that the properties of thin film solar cells degrade over time when exposed to light, which can reduce the stability of the device than desired. Typical solar cell characteristics that can degrade are fill factor (FF), short circuit current, and open circuit voltage (Voc).

  [0003] Problems with current thin film solar cells include low efficiency and high cost. Accordingly, there is a need for improved thin film solar cells and methods and apparatus for forming improved thin film solar cells in a factory environment. There is also a need for a process for making high stability pin solar cells with high fill factor, high short circuit current, high open circuit voltage and good device stability.

  [0004] Embodiments of the invention relate to thin film multijunction solar cells and methods and apparatus for forming thin film multijunction solar cells. In one embodiment, a method of forming a thin film multi-junction solar cell on a substrate includes forming a first pin junction and forming a second pin on the first pin junction. forming a p-i-n junction. Forming the first pin junction includes forming a p-type amorphous silicon layer, forming an intrinsic type amorphous silicon layer on the p-type amorphous silicon layer, and Forming an n-type microcrystalline silicon layer on the intrinsic type amorphous silicon layer. Forming the second pin junction includes forming a p-type microcrystalline silicon layer, and forming an intrinsic microcrystalline silicon layer on the p-type microcrystalline silicon layer. Forming an n-type amorphous silicon layer on the intrinsic microcrystalline layer. In one embodiment, an apparatus for forming a thin film multi-junction solar cell includes at least one first system configured to form a first pin junction and a first pin. At least one second system configured to form a second pin junction over the -n junction. The first system is configured to deposit one p-type chamber configured to deposit a p-type amorphous silicon layer and an intrinsic type amorphous silicon layer and an n-type microcrystalline silicon layer, respectively. A plurality of i / n chambers. The second system is configured to deposit one p-type chamber configured to deposit a p-type microcrystalline silicon layer and an intrinsic microcrystalline silicon layer and an n-type amorphous silicon layer, respectively. A plurality of i / n chambers.

  [0005] An embodiment of the present invention is a method of forming a thin film multi-junction solar cell on a substrate, the method comprising: forming a first photovoltaic junction on the substrate; and Forming a second photovoltaic junction thereon, forming a p-type microcrystalline silicon layer, and forming an intrinsic microcrystalline silicon layer on the p-type microcrystalline silicon layer And when the intrinsic type microcrystalline silicon layer is formed, one or more process variables control the crystal fraction at two or more points within the thickness of the intrinsic type microcrystalline silicon layer. There may be further provided a method comprising adjusting to do so and forming an n-type amorphous silicon layer on the intrinsic microcrystalline layer.

  [0006] An embodiment of the present invention is a method of forming a thin film multi-junction solar cell on a substrate, comprising forming a first photovoltaic junction on the substrate, a p-type amorphous silicon layer And forming an intrinsic type amorphous silicon layer on the p type amorphous silicon layer, wherein the intrinsic type amorphous silicon layer is a pi buffer intrinsic type amorphous silicon layer. And forming an n-type microcrystalline silicon layer on the intrinsic amorphous silicon layer and a second photovoltaic layer on the first photovoltaic junction. Forming a power junction; forming a p-type microcrystalline silicon layer; forming an intrinsic microcrystalline silicon layer on the p-type microcrystalline silicon layer; and Forming an n-type amorphous silicon layer on the crystalline layer.

  [0007] An embodiment of the present invention is a tandem junction photovoltaic device comprising a first photovoltaic junction and a second photovoltaic junction, wherein the second photovoltaic junction is a p-doped microelectrode. Comprising an amorphous silicon layer, an intrinsic type microcrystalline silicon layer, wherein the intrinsic type microcrystalline silicon layer is formed by a multi-step deposition process, each deposition step having a gas mixture having a different ratio of hydrogen to silane; A different film crystal fraction is formed in each deposition step, and the n-doped amorphous silicon layer may further provide a device adjacent to the intrinsic type microcrystalline silicon layer. In one embodiment, the different ratios of hydrogen to silane control the crystalline fraction that is uniformly formed over the entire thickness of the intrinsic type microcrystalline silicon layer.

  [0008] In order to provide a thorough understanding of the above-described features of the invention, a more detailed description of the invention, briefly outlined above, may be had by reference to embodiments. Some of the embodiments are illustrated in the accompanying drawings.

  [0019] However, the accompanying drawings only illustrate exemplary embodiments of the invention, and thus the invention may recognize other equally effective embodiments, so that the scope of the invention It should be noted that should not be considered limiting.

  [0020] To facilitate understanding, identical reference numerals have been used, where possible, to represent identical elements that are common to the drawings.

Detailed form

  [0021] Embodiments of the present invention include improved thin film multi-junction solar cells and methods and apparatus for forming improved thin film multi-junction solar cells. FIG. 1 is a schematic diagram of an embodiment of a multi-junction solar cell 100 directed to light or solar radiation 101. The solar cell 100 comprises a substrate 102 such as a glass substrate, polymer substrate, metal substrate or other suitable substrate using a thin film formed on the substrate. The solar cell 100 includes a first transparent conductive oxide (TCO) layer 110 formed on the substrate 102 and a first pin junction 120 formed on the first TCO layer 110. A second pin junction 130 formed on the first pin junction 120 and a second TCO formed on the second pin junction 130. Further comprising a layer 140 and a metal backing layer 150 formed on the second TCO layer 140. In order to improve light absorption by enhancing light capture, one or more of the substrate and / or thin film formed on the substrate may be a wet process, plasma process, ion process and / or mechanical It may be arbitrarily organized according to the process. For example, in the embodiment of FIG. 1, the first TCO layer 110 may have a tissue configuration such that the next thin film deposited on the first TCO layer 110 generally follows the topography of the surface below the thin film. Is done.

  [0022] The first TCO layer 110 and the second TCO layer 140 may each comprise tin oxide, zinc oxide, indium tin oxide, cadmium stannate, combinations thereof, or other suitable materials. It will be appreciated that the TCO material may also include additional dopants and components. For example, the zinc oxide may further include a dopant such as aluminum, gallium, boron, and other suitable dopants. The zinc oxide preferably comprises 5 atomic percent or less of the dopant, and more preferably comprises 2.5 atomic percent or less aluminum. In certain cases, the substrate 102 may be provided by a glass manufacturer using the first TCO layer 110 already provided.

  [0023] The first pin junction 120 includes a p-type amorphous silicon layer 122, an intrinsic amorphous silicon layer 124 formed on the p-type amorphous silicon layer 122, and an intrinsic non-layer. An n-type microcrystalline silicon layer 126 formed on the crystalline silicon layer 124 may be provided. In certain embodiments, the p-type amorphous silicon layer 122 may be formed to a thickness between about 60 inches and about 300 inches. In certain embodiments, intrinsic type amorphous silicon layer 124 may be formed to a thickness between about 1,500 and about 3,500 inches. In certain embodiments, the n-type microcrystalline semiconductor layer 126 may be formed to a thickness between about 100 inches and about 400 inches.

  [0024] The second pin junction 130 includes a p-type microcrystalline silicon layer 132, an intrinsic microcrystalline silicon layer 134 formed on the p-type microcrystalline silicon layer 132, an intrinsic micro An n-type amorphous silicon layer 136 formed on the crystalline silicon layer 134 may be provided. In certain embodiments, the p-type microcrystalline silicon layer 132 may be formed to a thickness between about 100 inches and about 400 inches. In certain embodiments, the intrinsic type microcrystalline silicon layer 134 may be formed to a thickness between about 10,000 to about 30,000 inches. In certain embodiments, the n-type amorphous silicon layer 136 may be formed to a thickness between about 100 inches and about 500 inches.

  [0025] The metal backing layer 150 may include, but is not limited to, a material selected from the group consisting of Al, Ag, Ti, Cr, Au, Cu, Pt, alloys thereof, or combinations thereof. Do not mean. The solar cell 100 may be formed by performing other processes such as a laser scribing process. Other films, materials, substrates and / or packaging may be provided on the metal backing layer 150 to complete the solar cell. The solar cells may be interconnected to form a module, which can then be connected to form an array.

  [0026] Solar radiation 101 is absorbed by the intrinsic layers of pin junctions 120, 130 and converted to electron-hole pairs. The electric field formed between the p-type layer and the n-type layer extending across the intrinsic layer causes electrons to flow toward the n-type layer and holes to flow toward the p-type layer, creating a current. To do. Because amorphous silicon and microcrystalline silicon absorb different wavelengths of solar radiation 101, the first pin junction 120 comprises an intrinsic type amorphous silicon layer 124 and a second p The −i−n junction 130 includes an intrinsic type microcrystalline silicon layer 134. Thus, the solar cell 100 is more efficient for capturing a larger portion of the solar radiation spectrum. Since amorphous silicon has a larger band gap than microcrystalline silicon, the intrinsic layer of amorphous silicon and the intrinsic layer of microcrystalline silicon first hit solar radiation 101 against the intrinsic type amorphous silicon layer 124. Next, it is laminated so as to hit the intrinsic type microcrystalline silicon layer 134. Solar radiation not absorbed by the first pin junction 120 continues to the second pin junction 130. Surprisingly, the thicknesses disclosed herein of the p-i-n layers of the first pin junction 120 and the second pin junction 130 provided for the solar cell are: It has been found to use improved efficiency and reduced cost to fabricate solar cells. Unless explicitly stated in the claims, we do not want to be bound by theory, while thicker intrinsic layers 124, 134 are beneficial to absorb a greater amount of solar radiation spectrum, while Thus, it is believed that if intrinsic layers 124, 134 and / or pin junctions 120, 130 are too thick, the flow of electrons through them is impeded.

  [0027] In one aspect, the solar cell 100 need not utilize a metal tunnel layer between the first pin junction 120 and the second pin junction 130. The n-type microcrystalline silicon layer 126 and the p-type microcrystalline silicon layer 132 of the first pin junction 120 are connected from the first pin junction 120 to the second pin junction. In order to allow electrons to flow through 130, it is sufficiently conductive to provide a tunnel junction.

  [0028] In one aspect, the n-type amorphous silicon layer 136 of the second pin junction 130 is more resistant to attack from oxygen, such as oxygen in the air, so enhanced solar It is believed to provide battery efficiency. Oxygen can attack the silicon film, thus forming impurities and reducing the ability of the film to participate in electron / hole transport therein. The lower electrical resistivity of the amorphous silicon layer versus the crystalline silicon layer forming the solar cell structure / device reduces the effect of undesirable shunting on power generation at the second pin junction 130 formed. It is also considered that it has improved electrical characteristics. A shunt that extends generally vertically through the formed p-i-n layer degrades solar cell performance by shorting local lateral regions of the formed solar cell device. Therefore, the lateral resistance of the amorphous n-type layer (ie, orthogonal to the vertical direction) is much higher than that of the crystalline layer, so the effect on the remaining portion of the solar cell where the short-circuit defects are formed is even smaller. . Reduction of the effects of short circuit defects improves the device performance of solar cells.

  [0029] FIG. 2 shows the multijunction solar of FIG. 1 further comprising an n-type amorphous silicon buffer layer 125 formed between the intrinsic-type amorphous silicon layer 124 and the n-type microcrystalline silicon layer 126. 1 is a schematic view of a battery 100. FIG. In certain embodiments, the n-type amorphous silicon buffer layer 125 may be formed to a thickness between about 10 inches and about 200 inches. The n-type amorphous silicon buffer layer 125 is considered to help fill a band gap offset that is considered to exist between the intrinsic-type amorphous silicon layer 124 and the n-type microcrystalline silicon layer 126. Therefore, solar cell efficiency is believed to be improved due to enhanced current collection.

  FIG. 3 shows the multi-junction solar cell 100 of FIG. 1 further comprising a p-type microcrystalline silicon contact layer 121 formed between the first TCO layer 110 and the p-type amorphous silicon layer 122. FIG. In certain embodiments, the p-type microcrystalline silicon contact layer 121 may be formed to a thickness between about 20 inches and about 200 inches. The p-type microcrystalline silicon contact layer 121 is believed to help achieve a low resistance contact with the TCO layer. Therefore, it is believed that the solar cell efficiency is improved because the current between the intrinsic type amorphous silicon layer 122 and the zinc oxide first TCO layer 110 is improved. Since a large amount of hydrogen is used to form the contact layer, the p-type microcrystalline silicon contact layer 121 is used with a TCO layer comprising a material that is resistant to hydrogen plasma, such as zinc oxide. It is preferable. Since tin oxide is chemically reduced by hydrogen plasma, it has been found that tin oxide is not suitable for use with p-type microcrystalline silicon contact layers. As shown in FIG. 2, solar cell 100 further includes an optional n-type amorphous silicon buffer layer formed between intrinsic type amorphous silicon layer 124 and n-type microcrystalline semiconductor layer 126. It is further understood that it may be.

  [0031] FIG. 4 illustrates a plasma enhanced chemical vapor deposition (PECVD) chamber 400 in which one or more films of a solar cell, such as the solar cell 100 of FIG. 1, 2, or 3, may be deposited. It is a schematic sectional drawing of one Embodiment. One suitable plasma enhanced chemical vapor deposition chamber is Applied Materials, Inc., located in Santa Clara, California. Is available from It is contemplated that other deposition chambers may be utilized to implement the present invention, including chambers from other manufacturers.

  [0032] The chamber 400 generally includes a wall 402, a lower portion 404, a showerhead 410, and a substrate support 430 to define a process volume 406. The process volume is accessed through valve 408 such that a substrate, such as substrate 100, may be transferred into or out of chamber 400. The substrate support 430 includes a substrate receiving surface 432 for supporting the substrate and a stem 434 coupled to a lift system 436 for raising and lowering the substrate support 430. A shadow from 433 may optionally be disposed around the substrate 100. The lift pins 438 are arranged to be movable through the substrate support 430 and move the substrate to the substrate receiving surface 432 and move the substrate from the substrate receiving surface 432. The substrate support 430 may also include heating and / or cooling elements 439 to maintain the substrate support 430 at a desired temperature. The substrate support 430 may also include a ground strap 431 to provide RF ground around the substrate support 430. Examples of ground straps can be found in US Pat. No. 6,024,044 issued to Law et al., Published February 15, 2000, and US Patent Application No. 11 issued to Park et al., Filed December 20, 2006. No./613,934, which is hereby incorporated by reference in its entirety as long as it is not inconsistent with the present disclosure.

  [0033] The showerhead 410 is coupled to the backing plate 412 around the showerhead 410 by a suspension device 414. The showerhead 410 is also coupled to the backing plate by one or more central supports 416 to help prevent sagging of the showerhead 410 and / or control the straightness / curvature of the showerhead 410. Also good. A gas source 420 is coupled to the backing plate 412 and supplies gas to the substrate receiving surface 432 through the backing plate 412, through the showerhead 410. A vacuum pump 409 is coupled to the chamber 400 and controls the process volume 406 at the desired pressure. An RF power source 422 is coupled to the backing plate 412 and / or the showerhead 410 to provide RF power to the showerhead 410 so that an electric field is created between the showerhead and the substrate support so that the plasma is It may be generated from gas between the shower head 410 and the substrate support 430. Various RF frequencies may be used, such as frequencies from about 0.3 MHz to about 200 MHz. In one embodiment, the RF power source is provided at a frequency of 13.56 MHz. Examples of showerheads are disclosed in US Pat. No. 6,477,980 issued to White et al., Issued November 12, 2002, US Pat. Appl. No. 20050251990, issued to Choi et al., Published November 17, 2006. And U.S. Patent Publication 2006/0060138, issued to Keller et al., Published March 23, 2006, which are hereby incorporated by reference in their entirety as long as they are not inconsistent with the present disclosure.

[0034] A remote plasma source 424, such as an inductively coupled remote plasma source, may also be coupled between the gas source and the backing plate. Between the processing substrates, a cleaning gas may be provided to the remote plasma source 424 so that a remote plasma is generated and provided to clean the chamber components. The cleaning gas may be further excited by an RF power source 422 provided to the showerhead. Suitable cleaning gases include, but are not limited to, NF ₃ , F ₂ and SF ₆ . An example of a remote plasma source is disclosed in US Pat. No. 5,788,778 issued to Shang et al., Published Aug. 4, 1998, and is hereby incorporated by reference in its entirety, unless inconsistent with the present disclosure. Embedded in the book.

[0035] The method of depositing one or more silicon layers, such as one or more of the silicon layers of the solar cell 100 of FIG. 1, FIG. 2, or FIG. The following deposition parameters in a separate chamber may be included. 10,000 cm ² or more, preferably 40,000 cm ² or more, more preferably a substrate having a 55,000 cm ² or more surface area is provided to the chamber. It will be appreciated that after processing, the substrate may be cut to form smaller solar cells.

  [0036] In one embodiment, the heating and / or cooling element 439 is about 400 ° C. or less, preferably about 100 ° C. to about 400 ° C., more preferably about 150 ° C. to about 300 ° C., such as about It may be set to provide a substrate support temperature such as 200 ° C.

  [0037] The spacing during deposition between the upper surface of the substrate arranged on the substrate receiving surface 432 and the showerhead 410 may be from 400 mils to about 1,200 mils, preferably from 400 mils to About 800 mils.

[0038] In the case of silicon film deposition, a silicon-based gas and a hydrogen-based gas are provided. Suitable silicon-based gases are silane (SiH ₄ ), disilane (Si ₂ H ₆ ), silicon tetrafluoride (SiF ₄ ), silicon tetrachloride (SiCl ₄ ), dichlorosilane (SiH ₂ Cl ₂ ) and these Including, but not limited to, combinations. Suitable hydrogen-based gases include, but are not limited to, hydrogen gas (H ₂ ). Each p-type dopant in the p-type silicon layer may comprise a group III element such as boron or aluminum. Preferably boron is used as the p-type dopant. Examples of sources containing boron are trimethylboron ((TMB) (or B (CH ₃ ) H ₃ )), diborane (B ₂ H ₆ ), BF ₃ , B (C ₂ H ₅ ) ₃ and similar Contains compounds. Preferably, TMB is used as a p-type dopant. Each n-type dopant in the n-type silicon layer may comprise a group V element such as phosphorus, arsenic or antimony. Preferably, phosphorus is used as the n-type dopant. Examples of sources containing phosphorus include phosphine and similar compounds. The dopant is typically provided with a carrier gas such as hydrogen, argon, helium and other suitable compounds. In the processing mold disclosed herein, the total flow rate of hydrogen gas is provided. Thus, when hydrogen gas is provided as a carrier gas, as in the case of a dopant, the carrier gas flow rate is determined by the hydrogen gas flow to determine how much additional hydrogen gas should be provided to the chamber. Should be subtracted from the total flow.

[0039] Certain embodiments of depositing a p-type microcrystalline silicon contact layer, such as contact layer 121 of FIG. 3, comprise providing a gas mixture of hydrogen gas to silane gas at a ratio of about 200: 1 or greater. Also good. Silane gas may be provided at a flow rate between about 0.1 sccm / L and about 0.8 sccm / L. Hydrogen gas may be provided at a flow rate between about 60 sccm / L and about 500 sccm / L. Trimethylboron may be provided at a flow rate between about 0.0002 sccm / L and about 0.0016 sccm / L. In other words, when trimethylboron is provided at 0.5% molar or volume concentration of the carrier gas, the dopant / carrier gas mixture has a flow rate between about 0.04 sccm / L and about 0.32 sccm / L. May be provided in The flow rate in this disclosure is expressed as sccm per internal chamber volume. The internal chamber volume is defined as the volume inside the chamber that can be occupied by a gas. For example, the internal chamber volume of the chamber 400 is derived from the volume defined by the backing plate 412 and the chamber walls 402 and lower portion 404 from the showerhead assembly (ie, including the showerhead 410, suspension 414, center support 415) and substrate. Subtract the volume occupied by the support assembly (ie, including substrate support 430, ground strap 431). RF power of about 50 mW / cm ² ~ about 700 mW / cm ² may be provided to the showerhead. RF power in this disclosure is expressed as W (watts) supplied to the electrodes per substrate area. For example, in the case of 10,385 W of RF power supplied to the showerhead to process a substrate having dimensions of 220 cm × 260 cm, the RF power is 10,385 W / (220 cm × 260 cm) = 180 mW / cm ^2. It is. The chamber pressure may be maintained from about 1 Torr to about 100 Torr, preferably from about 3 Torr to about 20 Torr, more preferably from 4 Torr to about 12 Torr. The deposition rate of the p-type microcrystalline silicon contact layer may be about 10 liters / minute or more. The p-type microcrystalline silicon contact layer has a crystal fraction of about 20% to about 80%, preferably 50% to about 70%.

[0040] Certain embodiments of depositing a p-type amorphous silicon layer, such as the silicon layer 122 of FIG. 1, FIG. 2, or FIG. 3, provide a gas mixture of hydrogen gas to silane gas in a ratio of about 20: 1 or less. You may prepare to do. Silane gas may be provided at a flow rate between about 1 sccm / L and about 10 sccm / L. Hydrogen gas may be provided at a flow rate between about 5 sccm / L and about 60 sccm / L. Trimethylboron may be provided at a flow rate between about 0.005 sccm / L and about 0.05 sccm / L. In other words, when trimethylboron is provided at 0.5% molar or volume concentration of the carrier gas, the dopant / carrier gas mixture is provided at a flow rate between about 1 sccm / L and about 10 sccm / L. Also good. Methane may be provided at a flow rate between about 1 sccm / L and about 15 sccm / L. An RF power of about 15 mW / cm ² to about 200 mW / cm ² may be provided to the showerhead. The chamber pressure is maintained from about 0.1 Torr to 20 Torr, preferably from about 1 Torr to about 4 Torr. The deposition rate of the p-type amorphous silicon layer may be about 100 Å / min or more. Methane or other carbon-containing compounds such as C ₃ H ₈ , C ₄ H ₁₀ , C ₂ H ₂ are used to improve the window properties of the p-type amorphous silicon layer (eg, reduce solar radiation absorption) Can). Therefore, an increased amount of solar radiation may be absorbed through the intrinsic layer, thus improving solar cell efficiency. In embodiments where trimethylboron is used to provide a boron dopant in the p-type amorphous silicon layer 122, the boron dopant concentration is about 1 × 10 ¹⁸ atoms / cm ² to about 1 × 10 ²⁰ atoms / cm ^2. Maintained. In embodiments where methane gas is used to provide a p-type layer as a silicon carbide layer, the carbon dopant concentration is controlled to about 10 atomic percent to about 20 atomic percent of the layer.

[0041] Certain embodiments of depositing an intrinsic type amorphous silicon layer, such as the silicon layer 124 of FIG. 1, FIG. 2, or FIG. 3, provide a gas mixture of hydrogen gas to silane gas in a ratio of about 20: 1 or less. Prepare to do. Silane gas may be provided at a flow rate between about 0.5 sccm / L and about 7 sccm / L. Hydrogen gas may be provided at a flow rate between about 5 sccm / L and about 60 sccm / L. An RF power of about 15 mW / cm ² to about 250 mW / cm ² may be provided to the showerhead. The chamber pressure may be maintained from about 0.1 Torr to 20 Torr, preferably from about 0.5 Torr to about 5 Torr. The deposition rate of the intrinsic type amorphous silicon layer may be about 100 Å / min or more. In the illustrated embodiment, the intrinsic type amorphous silicon layer is deposited at a hydrogen to silane ratio of about 12.5: 1.

  [0042] In one embodiment, the deposition of an intrinsic type amorphous silicon layer, such as silicon layer 124 of FIG. 1, FIG. 2, or FIG. 3, may include two or more steps, such as a multi-step deposition process. For example, prior to the bulk intrinsic type amorphous silicon layer deposition process, a pi buffered intrinsic type amorphous silicon layer (PIB layer) 904 as depicted in FIG. May be deposited. A detailed description of the PIB layer 904 is described in further detail below in connection with FIG. The pi buffered intrinsic type amorphous silicon layer (PIB layer) and the bulk i type amorphous silicon layer 124 smoothly change process parameters during deposition to form layers using different desired film properties. May be deposited in one chamber. The p-i buffered intrinsic type amorphous silicon layer (PIB layer) is deposited in such a way as to use relatively low RF power to minimize damage to the underlying p-type amorphous silicon layer. The Moreover, since the underlying p-type amorphous silicon layer and bulk i-type amorphous silicon layer 124 each have different film transparency and characteristics, the buffered i-type amorphous silicon layer has film characteristics in each layer. Of the optical band gap (OBG) to a minimum, thus providing a wider band gap and providing an open circuit voltage of about 20 meV to 50 meV. Improve.

[0043] In one embodiment, the pi buffered intrinsic type amorphous silicon layer (PIB layer) is about 40: 1 or less, such as less than about 30: 1, such as from about 20: 1 to about 30: 1. For example, it may be deposited by providing a gas mixture of hydrogen gas to silane gas in a ratio such as 25. Silane gas may be provided at a flow rate between about 0.5 sccm / L and about 5 sccm / L, such as about 2.28 sccm / L. Hydrogen gas may be provided at a flow rate between about 5 sccm / L and about 80 sccm / L, such as about 20 sccm / L to about 65 sccm / L, such as about 57 sccm / L. RF power from 15 mW / cm ² to about 250 mW / cm ^2, such as about 30 mW / cm ² , may be provided to the showerhead. The chamber pressure may be maintained from about 0.5 Torr to about 5 Torr, such as about 0.1 Torr to 20 Torr, preferably about 3 Torr. The deposition rate of the pi buffer intrinsic type amorphous silicon layer (PIB layer) may be about 100 Å / min or more. The thickness of the pi buffer intrinsic type amorphous silicon layer (PIB layer) is about 0 to about 500 mm, such as about 0 to about 200 mm, such as about 0 to about 200 mm. The p-i buffered intrinsic type amorphous silicon layer (PIB layer) and the bulk intrinsic type amorphous silicon layer 124 may be deposited integrally in one chamber or individually deposited in separate chambers. It should be noted that

[0044] When the pi buffered intrinsic type amorphous silicon layer (PIB layer) reaches the desired thickness, the gas mixture supplied for the buffered intrinsic type amorphous silicon layer 124 is: It may be variable to deposit the bulk intrinsic type amorphous silicon layer 124. During the transition to the deposition of the pi buffered intrinsic type amorphous silicon layer (PIB layer) on the bulk intrinsic type amorphous silicon layer 124, the hydrogen gas supplied to the gas mixture is gradually reduced and the silane gas is reduced. It may still be the same or gradually increased. In one embodiment, the ratio of hydrogen gas to silane gas in the gas mixture varies from 25: 1 to about 12.5: 1 and the deposition of the pi buffer intrinsic type amorphous silicon layer (PIB layer) is bulk intrinsic. The process proceeds to the deposition of the type amorphous silicon layer 124. RF power is gradually increased to about 50 mW / cm ² in the case of p-i buffer intrinsic type amorphous silicon layer (PIB layer) of about 30 mW / cm ² from the bulk intrinsic type amorphous silicon layer deposition in the case of deposition May be. The process pressure may be maintained to be substantially the same or gradually adjusted from about 3 Torr to about 2.5 Torr.

[0045] Certain embodiments of depositing an n-type amorphous silicon buffer layer, such as the silicon layer 125 of FIG. 2, comprise providing a gas mixture of hydrogen gas to silane gas in a ratio of about 20: 1 or less. Silane gas may be provided at a flow rate between about 1 sccm / L and about 10 sccm / L. Hydrogen gas may be provided at a flow rate between about 4 sccm / L and about 50 sccm / L. Phosphine may be provided at a flow rate between about 0.0005 sccm / L and about 0.0075 sccm / L. In other words, when the phosphine is provided at 0.5% molar or volume concentration of the carrier gas, the dopant / carrier gas mixture is at a flow rate between about 0.1 sccm / L and about 1.5 sccm / L. May be provided. An RF power of about 15 mW / cm ² to about 250 mW / cm ² may be provided to the showerhead. The chamber pressure may be maintained from about 0.1 Torr to 20 Torr, preferably from about 0.5 Torr to about 4 Torr. The deposition rate of the n-type amorphous silicon buffer layer may be about 200 liters / minute or more. In embodiments where phosphine is used to provide a phosphorus dopant in the n-type amorphous silicon layer, the phosphorus dopant concentration is from about 1 × 10 ¹⁸ atoms / cm ² to about 1 × 10 ²⁰ atoms / cm ² . Maintained.

[0046] Certain embodiments of depositing an n-type microcrystalline silicon layer, such as the silicon layer 126 of FIG. 1, FIG. 2, or FIG. 3, provide a gas mixture of hydrogen gas to silane gas in a ratio of about 100: 1 or greater. You may prepare to do. Silane gas may be provided at a flow rate between about 0.1 sccm / L and about 0.8 sccm / L, such as about 0.35 sccm / L. Hydrogen gas may be provided at a flow rate between about 30 sccm / L and about 250 sccm / L, such as about 71.43 sccm / L. Phosphine may be provided at a flow rate between about 0.0005 sccm / L and about 0.006 sccm / L. In other words, when the phosphine is provided at 0.5% molar or volume concentration of the carrier gas, the dopant / carrier gas is provided at a flow rate between about 0.1 sccm / L and about 1.2 sccm / L. May be. RF power of about 100 mW / cm ² ~ about 900 mW / cm ² may be provided to the showerhead. The chamber pressure may be maintained from about 1 Torr to about 100 Torr, preferably from about 3 Torr to about 20 Torr, more preferably from 4 Torr to about 12 Torr. The deposition rate of the n-type microcrystalline silicon layer may be about 50 liters / minute or more. The n-type microcrystalline silicon layer has a crystal fraction of about 20% to about 80%, preferably 50% to about 70%. In embodiments where phosphine is used to provide a phosphorus dopant in the n-type microcrystalline silicon layer, the phosphorus dopant concentration is from about 1 × 10 ¹⁸ atoms / cm ² to about 1 × 10 ²⁰ atoms / cm ² . Maintained.

[0047] In another embodiment of depositing an n-type microcrystalline silicon layer, such as the silicon layer 126 of FIG. 1, FIG. 2, or FIG. 3, the deposition process is about 500, such as about 100: 1 to about 400: 1. Providing a gas mixture of hydrogen gas to silane gas in a ratio of 1: 1 or less, for example about 304: 1 or about 203: 1. Silane gas may be provided at a flow rate between about 0.1 sccm / L and about 0.8 sccm / L, such as between about 0.32 sccm / L and about 0.45 sccm / L. Hydrogen gas may be provided at a flow rate between about 30 sccm / L and about 250 sccm / L, such as between about 68 sccm / L and about 142.85 sccm / L. The phosphine may be provided at a flow rate of about 0.0005 sccm / L to about 0.0025 sccm / L, such as about 0.005 sccm / L, such as about 0.0025 sccm / L to about 0.015 sccm / L. In other words, if the phosphine is provided at 0.5% molar or volume concentration of the carrier gas, the dopant / carrier gas is about 0.5 sccm / L to about 3 sccm / L, about 0.9 sccm / L. May be provided at a flow rate between about 0.1 sccm / L and about 5 sccm / L, such as about 1.088 sccm / L. About 370 mW / cm ² RF power of about 100 mW / cm ² ~ about 900 mW / cm ^2, such as may be provided to the showerhead. The chamber pressure may be maintained at about 1 Torr to 100 Torr, preferably about 3 Torr to about 20 Torr, more preferably 4 Torr to about 12 Torr, such as about 6 Torr or about 9 Torr. The deposition rate of the n-type microcrystalline silicon layer may be about 150 liters / minute or more.

[0048] Certain embodiments of depositing a p-type microcrystalline silicon layer, such as the silicon layer 132 of FIG. 1, FIG. 2, or FIG. 3, provide a gas mixture of hydrogen gas to silane gas in a ratio of about 200: 1 or greater. Prepare to do. Silane gas may be provided at a flow rate between about 0.1 sccm / L and about 0.8 sccm / L. Hydrogen gas may be provided at a flow rate between about 60 sccm / L and about 500 sccm / L. Trimethylboron may be provided at a flow rate between about 0.0002 sccm / L and about 0.0016 sccm / L. In other words, when trimethylboron is provided at 0.5% molar or volume concentration of the carrier gas, the dopant / carrier gas mixture has a flow rate between about 0.04 sccm / L and about 0.32 sccm / L. May be provided in RF power of about 50 mW / cm ² ~ about 700 mW / cm ² may be provided to the showerhead. The chamber pressure may be maintained from about 1 Torr to about 100 Torr, preferably from about 3 Torr to about 20 Torr, more preferably from 4 Torr to about 12 Torr. The deposition rate of the p-type microcrystalline silicon layer may be about 10 liters / minute or more. The p-type microcrystalline silicon contact layer has a crystal fraction of about 20% to about 80%, preferably 50% to about 70%. In embodiments where trimethylboron is used to provide a boron dopant in the p-type microcrystalline silicon layer, the boron dopant concentration is about 1 × 10 ¹⁸ atoms / cm ² to about 1 × 10 ²⁰ atoms / cm ^2. Maintained.

[0049] In yet another embodiment of depositing a p-type microcrystalline silicon layer, such as the silicon layer 132 of FIG. 1, FIG. 2, or FIG. 3, the deposition process is about 200: 1 to about 800: 1. Providing a gas mixture of hydrogen gas to silane gas at a ratio of 1000: 1 or less, such as about 601: 1 or about 401: 1 may be provided. Silane gas may be provided at a flow rate between about 0.1 sccm / L and about 0.8 sccm / L, such as about 0.2 sccm / L, about 0.38 sccm / L. Hydrogen gas may be provided at a flow rate between about 60 sccm / L and about 500 sccm / L, such as about 142.85 sccm / L. Trimethylboron may be provided at a flow rate between about 0.0002 sccm / L and about 0.0016 sccm / L, such as about 0.00115 sccm / L. In other words, when trimethylboron is provided at 0.5% molar or volume concentration of the carrier gas, the dopant / carrier gas mixture is about 0.04 sccm / L, such as about 0.23 sccm / L. It may be provided at a flow rate of about 0.32 sccm / L. About RF power 290 mW / cm ² ~ about 440mW / cm ² to about 50 mW / cm ² ~ about 700 mW / cm ^2, such as may be provided to the showerhead. The chamber pressure may be maintained from about 1 Torr to about 100 Torr, preferably from about 3 Torr to about 20 Torr, more preferably from 4 Torr to about 12 Torr, such as about 9 Torr or about 7 Torr. The deposition rate of the p-type microcrystalline silicon layer may be about 143 Å / min or more.

[0050] Certain embodiments of depositing an intrinsic type microcrystalline silicon layer, such as the silicon layer 134 of FIG. 1, FIG. 2, or FIG. 3, are a gas mixture of silane gas to hydrogen gas in a ratio of 1:20 to 1: 200. May be provided. Silane gas may be provided at a flow rate between about 0.5 sccm / L and about 5 sccm / L. Hydrogen gas may be provided at a flow rate between about 40 sccm / L and about 400 sccm / L. In certain embodiments, the silane flow rate may be increased from a first flow rate to a second flow rate during deposition. In certain embodiments, the hydrogen flow rate may be reduced from a first flow rate to a second flow rate during deposition. RF power of about 300 mW / cm ² or more, preferably about 600 mW / cm ² or more may be provided to the showerhead. In certain embodiments, the power density may be reduced from a first power density to a second power density during deposition. The chamber pressure is maintained at about 1 Torr to about 100 Torr, preferably about 3 Torr to about 20 Torr, more preferably about 4 Torr to about 12 Torr. The deposition rate of the intrinsic type microcrystalline silicon layer may be about 200 kg / min or more, preferably 500 kg / min. A method and apparatus for depositing a microcrystalline intrinsic layer is described in US Patent Application No. 11 / No. 42, entitled “Methods and Apparatus for Deposition of Microcrystalline Silicon Film for Photovoltaic Device”, filed Jun. 23, 2006, US Pat. The disclosure is incorporated herein by reference in its entirety as long as it is disclosed and is not inconsistent with the present disclosure. The microcrystalline silicon intrinsic layer has a crystal fraction of about 20% to about 80%, preferably 55% to about 75%. Surprisingly, it has been found that a microcrystalline silicon intrinsic layer having a crystal fraction of about 70% or less provides an increase in open circuit voltage, resulting in higher solar cell efficiency.

  [0051] In yet another embodiment of depositing an intrinsic type microcrystalline silicon layer, such as the silicon layer 134 of FIG. 1, FIG. 2, or FIG. 3, the intrinsic type microcrystalline silicon layer comprises one or more steps, For example, it may be deposited by multiple deposition steps. Since the crystal fraction may change with an increase in the thickness of the deposited film, the gas ratio supplied during the deposition will maintain the crystal fraction of the entire intrinsic type microcrystalline silicon layer. It may change. As a result, the deposition may be performed in multiple steps using different process parameters or process variables to form different crystal fractions in the resulting film. Multiple deposition steps allow the intrinsic type microcrystalline silicon layer to be formed as a gradient film having different desired film properties at different thickness levels within the film. In one embodiment, process parameters or process variables that may be variable at each deposition step include RF power, deposition time, ratio of hydrogen gas to silane gas supplied in the gas mixture, gas species supplied in the gas mixture, Including process pressure, gas flow rate, spacing, RF frequency and / or other suitable process parameters. In one embodiment, the process variables of hydrogen gas to silane gas ratio, process pressure, RF power or deposition time are used to control the crystalline fractions formed at different sites of the intrinsic type microcrystalline silicon layer that is formed. It may be variable. In another embodiment, the process variable of the ratio of hydrogen gas to silane gas is variable at each deposition step and controls the crystal fractions formed at different sites of the intrinsic type microcrystalline silicon layer that is formed.

  [0052] In one embodiment, the number of steps performed in the deposition process may be determined by the desired thickness of the intrinsic type microcrystalline silicon layer. For example, if it is desired that the intrinsic type microcrystalline silicon layer be deposited using a relatively large thickness of over 5000 mm, the entire process can be performed to maintain a uniform crystal fraction of the film. May be divided into more steps. In contrast, if it is desired that the intrinsic type microcrystalline silicon layer be deposited using a thinner thickness, the number of steps in the deposition process may be controlled within an appropriate range.

  [0053] In an exemplary embodiment where the intrinsic type microcrystalline silicon layer is formed using a thickness of about 17000 mm, the deposition process is divided into four steps, each of which includes hydrogen in the gas mixture. Different ratios of gas to silane gas are used. The thickness formed in each step may be controlled to be substantially equal to about 4250 mm (eg, 17000 mm total thickness / 4 deposition steps = 4250 mm per step) in each step. During deposition, the gas ratio of hydrogen gas to silane gas is gradually reduced in each successive step to efficiently maintain the overall crystal fraction of the deposited film within a predetermined range and to reduce the overall film thickness. The total crystal fraction of the film does not increase as the increases. A low ratio of hydrogen gas to silane gas may be achieved by reducing the amount of hydrogen gas supplied to the gas mixture and / or by increasing the amount of silane gas provided to the gas mixture. The ratio as described herein is a flow ratio (eg, volume ratio) supplied to the processing chamber. In one particular embodiment, the gas ratio of hydrogen gas to silane gas is about 100: 1 in the first step of the deposition process, 95: 1 in the second step, and 90: 1 in the third step. In the fourth / last step, it may be controlled at 85: 1. It should be noted that the gas ratio of hydrogen gas to silane gas may be adjusted from about 20: 1 to about 200: 1, as desired to be suitable for different process types. In one embodiment, when adjusting the gas flow during deposition, the silane gas flow is maintained constant while the hydrogen flow supplied in the gas mixture is gradually reduced, resulting in a gas mixture. This results in a low ratio of hydrogen gas to silane gas, reducing the crystal fraction formed in the intrinsic type microcrystalline silicon layer, or vice versa. Other process parameters such as gas pressure, substrate temperature, RF power, etc. may be maintained substantially the same during each deposition step.

[0054] In one embodiment, the silane gas may be provided at a flow rate between about 0.1 sccm / L and about 5 sccm / L, such as about 0.97 sccm / L. Hydrogen gas may be provided at a flow rate between about 10 sccm / L and about 200 sccm / L, such as between about 80 sccm / L and about 105 sccm / L. In an exemplary embodiment where the deposition has multiple steps, such as four steps, the hydrogen gas stream is configured at about 97 sccm / L in the first step and individually 92 sccm / L, 87.5 sccm in the next process step. / L and may be gradually reduced to 82.6 sccm / L. About 300 mW / cm ² or more RF power, such as about 490mW / cm ² may be provided to the showerhead. The chamber pressure is maintained at about 4 Torr to about 12 Torr, such as about 1 Torr to about 100 Torr, such as about 3 Torr to about 20 Torr, such as about 9 Torr. The deposition rate of the intrinsic type microcrystalline silicon layer may be about 200 Å / min or more, such as 400 Å / min.

[0055] Certain embodiments of a method for depositing an n-type amorphous silicon layer, such as the silicon layer 136 of FIG. 1, FIG. 2, or FIG. 3, may include any first n-type amorphous at a first silane flow rate. And depositing a second n-type amorphous silicon layer on the first arbitrary n-type amorphous silicon layer at a second silane flow rate less than the first silane flow rate. And may be provided. The first optional n-type amorphous silicon layer may comprise providing a gas mixture of hydrogen gas to silane gas at a ratio of about 20: 1 or less, such as about 5.5: 1. Silane gas may be provided at a flow rate between about 1 sccm / L and about 10 sccm / L, such as about 5.5 sccm / L. Hydrogen gas may be provided at a flow rate between about 4 sccm / L and about 40 sccm / L, such as about 27 sccm / L. The phosphine may be provided at a flow rate between about 0.0005 sccm / L and about 0.0015 sccm / L, such as about 0.0095 sccm / L. In other words, if the phosphine is provided at 0.5% molar or volume concentration of the carrier gas, the dopant / carrier gas mixture is about 0.1 sccm / L to about 0.1 sccm / L, such as about 1.9 sccm / L. It may be provided at a flow rate of 3 sccm / L. RF power from 25 mW / cm ² to about 250 mW / cm ^2, such as about 80 mW / cm ² , may be provided to the showerhead. The chamber pressure may be maintained from about 0.5 Torr to about 4 Torr, such as about 0.1 Torr to about 20 Torr, preferably about 1.5 Torr. The deposition rate of the first n-type amorphous silicon layer may be about 200 Å / min or higher, such as about 561 Å / min. In embodiments where phosphine is used to provide a phosphorus dopant in the n-type amorphous silicon layer, the phosphorus dopant concentration is from about 1 × 10 ¹⁸ atoms / cm ² to about 1 × 10 ²⁰ atoms / cm ² . Maintained.

[0056] The second n-type amorphous silicon layer deposition may comprise providing a gas mixture of hydrogen gas to silane gas at a ratio of about 20: 1 or less, such as about 7.8: 1. Silane gas may be provided at a flow rate between about 0.1 sccm / L and about 5 sccm / L, such as about 1.4 sccm / L, such as about 0.5 sccm / L to about 3 sccm / L. Hydrogen gas may be provided at a flow rate between about 1 sccm / L and about 10 sccm / L, such as about 6.42 sccm / L. The phosphine may be provided at a flow rate between 0.01 sccm / L and about 0.075 sccm / L, such as about 0.015 sccm / L to about 0.03 sccm / L, such as about 0.023 sccm / L. In other words, when the phosphine is provided at 0.5% molar or volume concentration of the carrier gas, the dopant / carrier gas mixture is about 2 sccm / L, such as about 3 sccm / L to about 6 sccm / L. It may be provided at a flow rate of about 15 sccm / L, for example about 4.71 sccm / L. RF power from 25 mW / cm ² to about 250 mW / cm ^2, such as about 60 mW / cm ² , may be provided to the showerhead. The chamber pressure may be maintained at about 0.5 Torr to about 4 Torr, such as about 0.1 Torr to about 20 Torr, such as about 1.5 Torr. The deposition rate of the second n-type amorphous silicon layer may be about 100 Å / min or higher, such as about 300 Å / min. The thickness of the second n-type amorphous silicon layer is less than 300 mm, such as about 20 mm and about 150 mm, for example about 80 mm. The second n-type amorphous silicon layer is heavily doped and has a resistivity of about 500 Ω-cm or less. It is believed that amorphous silicon that is heavily n-type doped (eg, degenerately) provides improved ohmic contact with a TCO layer, such as layer TCO layer 140. Therefore, the solar cell efficiency is improved. An optional first n-type amorphous silicon is used to increase the deposition rate of the entire n-type amorphous silicon layer. An n-type amorphous silicon layer is formed without any first n-type amorphous silicon and mainly from a second n-type amorphous layer that is heavily (eg, degenerately) doped. It is understood that it may be formed.

[0057] It should be noted that an optional hydrogen or argon plasma gas treatment process may be performed prior to each deposition of layers including n-type, intrinsic and p-type silicon-containing layers. The hydrogen treatment process may be performed to treat the underlying layer to suppress surface contamination. In addition, because surface defects may be removed or eliminated during the treatment process, the plasma treatment process can also improve the electrical properties at the boundary. In one embodiment, the plasma treatment process may be performed by supplying hydrogen gas or argon gas to the processing chamber. The gas flow for supplying hydrogen gas or argon gas is from about 10 sccm / L to about 45 sccm / L, such as from about 15 sccm / L to about 40 sccm / L, for example, about 20 sccm / L and about 36 sccm / L. In one example, hydrogen gas may be supplied at about 21.42 sccm / L, or argon gas may be supplied at about 35.7 sccm / L. RF power supplied to perform the treatment process may be controlled by the 25 mW / cm ² ~ about 250 mW / cm ^2, such as about 60 mW / cm ^2, in the case of the hydrogen treatment to about 80 mW / cm ^2, argon may be provided to the shower head was about ^{25mW / cm 2 10mW / cm 2} ~ about 250 mW / cm ^2, such as in the case of the treatment.

  [0058] In one embodiment, the argon treatment process is performed prior to the deposition of the p-type amorphous silicon layer. In one embodiment, the hydrogen treatment process, where useful, is intrinsic type amorphous silicon layer, n type microcrystalline silicon layer, p type microcrystalline silicon layer and intrinsic type microcrystalline silicon layer and others. May be performed prior to the deposition of each of the layers.

  [0059] FIGS. 8A-8C schematically illustrate various embodiments of solar cells. Although the embodiments depicted in FIGS. 8A-8C illustrate single-junction solar cells, the depicted layers are polysilicon, amorphous silicon, made by the methods described herein, It should be noted that it may be part of a tandem, three or more junction solar cells formed using different materials, including but not limited to microcrystalline silicon, or any combination thereof. is there.

  [0060] FIG. 8A depicts a substrate 102 having solar cells 850 arranged on a TCO layer 110. FIG. Solar cell 850 has p-type amorphous silicon layer 122, intrinsic-type amorphous silicon layer 124, and n-type amorphous silicon layer 804. A preliminary p-type amorphous silicon layer 802 may be formed on the substrate 102 before the p-type amorphous silicon layer 122 is deposited. The preliminary p-type amorphous silicon layer 802 is formed by controlling the silane flow rate during the p-type amorphous silicon layer deposition process. During deposition, a first silane flow rate may be provided to deposit a spare p-type amorphous silicon layer 802 and a second silane flow rate is applied to the spare p-type amorphous silicon layer 802. It may be provided to deposit a p-type amorphous silicon layer 122 thereon. The second silane flow rate may be controlled at a higher flow rate than the first silane flow rate.

[0061] The resulting preliminary p-type amorphous silicon layer 802 is a p-type amorphous silicon layer that is heavily (eg, degenerately) doped and has a resistance of about 10 ⁵ Ω-cm or less. Have a rate. Preliminary p-type amorphous silicon layer 802 that is heavily (eg, degenerately) doped is believed to provide improved ohmic contact with a TCO layer, such as TCO layer 110. The heavily doped spare p-type amorphous silicon layer 802 provides a reduced width depletion region (eg, a potential barrier between the TCO layer 110 and the solar cell 850) and is therefore effective. This facilitates the tunneling phenomenon of current transport. In addition, the high amount of acceptor-like elements present in the heavily doped spare p-type amorphous silicon layer 802 also lowers the potential barrier at the TCO layer 110 and solar cell 850 boundary. As a result, the p-type amorphous silicon layer 122 acts as a wide band gap layer. Therefore, solar cell efficiency is improved. The p-type amorphous silicon layer 122 is used to increase the deposition rate for the overall p-type silicon formation process. It will be appreciated that the p-type amorphous silicon layer 122 may also be formed from a pre-doped amorphous silicon 802 material that is also heavily doped.

[0062] The heavily doped preliminary p-type amorphous silicon layer 802 deposition process may comprise providing a gas mixture of hydrogen gas to silane gas at a ratio of about 20: 1 or less. Silane gas may be provided at a flow rate between about 0.5 sccm / L and about 5 sccm / L. Hydrogen gas may be provided at a flow rate between about 1 sccm / L and about 5 sccm / L. Trimethylboron may be provided at a flow rate between 0.0025 sccm / L and about 0.15 sccm / L. In other words, when trimethylboron is provided at 0.5% molar or volume concentration of the carrier gas, the dopant / carrier gas mixture is provided at a flow rate between about 0.5 sccm / L and about 30 sccm / L. May be. An RF power of 15 mW / cm ² to about 250 mW / cm ² may be provided to the showerhead. The chamber pressure may be maintained at about 0.1 Torr to about 20 Torr, such as about 0.5 Torr to about 4 Torr. The deposition rate of the preliminary p-type amorphous silicon layer 802 may be about 100 liters / minute or more. In one embodiment, the heavily doped p-type amorphous silicon layer 802 has a dopant concentration of about 10 ²⁰ atoms per cubic centimeter to about 10 ²¹ atoms per cubic centimeter.

  [0063] In one embodiment, the p-type amorphous silicon layer 122 may be fabricated in a manner similar to that described with reference to FIGS.

[0064] Similarly, in the case of an n-type amorphous silicon layer 804 deposition process, the process deposits an n-type amorphous silicon layer 804 along with a densely doped amorphous silicon layer 806. May include a two-step deposition process. The two-step deposition process is similar to the n-type amorphous silicon layer 136 deposition process described with reference to FIGS. Alternatively, the n-type amorphous silicon layer 804 may be initially formed as a heavily doped n-type amorphous silicon layer 806 to provide improved ohmic contact with a TCO layer, such as the TCO layer 140. Good. In one embodiment, the heavily doped n-type amorphous silicon layer 806 has a dopant concentration of about 10 ²⁰ atoms per cubic centimeter to about 10 ²¹ atoms per cubic centimeter.

  [0065] In one embodiment, the p-type amorphous silicon layer 122 has a thickness of about 50 to about 200 and the heavily doped p-type amorphous silicon layer 802 has about 10 to about 200. It has a thickness of 50 mm. The n-type amorphous silicon layer 804 has a thickness of about 100 to about 400 and the heavily doped n-type amorphous silicon layer 806 has a thickness of about 50 to about 200.

  [0066] FIG. 8B depicts another embodiment of a solar cell 852 arranged on a substrate 102. FIG. Similar to the solar cell 850 of FIG. 8A, the solar cell 852 includes a p-type amorphous silicon layer 802, a p-type amorphous silicon layer 122, and an intrinsic amorphous material, as shown in FIG. 8A. A silicon layer 124, an n-type amorphous silicon buffer layer 820, and an n-type microcrystalline silicon layer 808 are included. The n-type amorphous silicon buffer layer 820 is a layer similar to the buffer layer 125 of FIG. 2 and may be formed between the intrinsic type amorphous silicon layer 124 and the n-type microcrystalline silicon layer 808. . The n-type amorphous silicon buffer layer 820 serves to fill a band gap offset that may occur between the intrinsic silicon layer 124 and the n-type silicon layer 808. Therefore, solar cell efficiency is believed to be improved due to enhanced current collection. These layers 802, 122, 124, 808 may be made by any suitable process, such as those described above.

  [0067] FIG. 8C depicts yet another embodiment of a solar cell 854 arranged on the substrate 102. FIG. Similar to the battery structure described above, the solar cell 854 includes a p-type microcrystalline silicon layer 810, an intrinsic microcrystalline silicon layer 812, an n-type amorphous silicon barrier layer 821, and an n-type microcrystalline silicon layer. 814. The n-type amorphous silicon barrier layer 821 functions as a barrier layer formed between the intrinsic microcrystalline silicon layer 812 and the n-type microcrystalline silicon layer 814. The n-type amorphous silicon barrier layer 821 assists in increasing the lateral resistivity of the film and avoiding the problem of ambient current. In one embodiment, the n-type amorphous silicon barrier layer 821 may be deposited in a manner similar to the deposition manner of the n-type amorphous silicon buffer layer 820 of FIG. 8B and the buffer layer 125 of FIG. The n-type amorphous silicon barrier layer 821 may be manufactured by a method having film components similar to the buffer layers 820 and 125. The barrier layer 821 is formed of a microcrystalline-based silicon film (for example, an intrinsic microcrystalline silicon layer 812 and an n-type microcrystalline silicon layer instead of the amorphous silicon film in contact with the buffer layers 820 and 125). 814), the barrier layer 821 acts to increase the lateral resistivity of the film and to avoid ambient current problems.

  [0068] In embodiments where one or more junctions, eg, multiple junctions, are desired, the solar cell 850 of FIG. 8A may be configured as an upper cell in contact with the substrate, and the solar cell of FIG. 8C. 854 may be configured as a lower battery arranged on top of the upper solar cell 850. If the upper cell is desired to provide a higher band gap, the intrinsic type amorphous silicon layer 124 of the solar cell 850 has a higher band gap than the intrinsic type microcrystalline silicon layer 812 in the solar cell 854. May be provided. Alternatively, battery placement may be configured in any suitable manner to achieve the desired battery performance.

  [0069] FIG. 9 depicts another exemplary embodiment of a multi-junction solar cell 900 comprising a number of different contact, buffer or interface layers arranged within the cell 900. FIG. The battery 900 includes a first junction 910 and a second junction 920 arranged on the substrate 102 having a TCO layer 110 arranged on the substrate 102. An interface layer 908 may be deposited between the first bond 910 and the second bond 920. The interface layer 908 is deposited to improve the interface contact resistance and conductivity and provide a wider optical band gap. Moreover, the material of the interface layer 908 is selected such that the reflectivity (RI) and light absorption of the layer 908 may be tuned to provide light capture efficiency for different electrical properties and different device requirements. The In one embodiment, suitable materials for forming the interface layer 908 include SiON, SiN, SiC, SiO, SiOC, SiCN and other suitable carbon, oxygen or nitrogen containing silicon based materials or silicon alloys. Including. In one embodiment, the interface layer 908 is a silicon carbon (SiC) layer, a silicon oxide (SiO) layer, or a silicon oxynitride (SiON) layer. The reflectivity (RI) of the interface layer 908 may be adjusted by changing the gas mixture supplied to deposit the layer 908 during deposition. When the gas mixture supplied for deposition changes, the carbon or nitrogen dopant formed in the deposited interface layer 908 may also be different, so that the resulting film has a desired film band. It may have a gap, light absorption rate and crystal fraction. When the band gap and light absorption rate of the film are improved, the battery conversion efficiency is consequently increased. Further, the interface layer 908 may also be used at any boundary when the bond is in contact with the TCO layer, metal backing plate and / or substrate.

  [0070] In the embodiment depicted in FIG. 9, the interface layer 908 is arranged between the first junction 910 and the second junction 920. The first junction includes a first upper interface layer 902, a p-type amorphous silicon layer 122, a PIB layer 904, an i-type amorphous silicon layer 124, an n-type amorphous silicon buffer layer 906, and an n-type microcrystal. A quality silicon layer 126 is provided. In one embodiment, the first upper interface layer 902 may have film properties similar to the interface layer 908 described above. Alternatively, the first upper interface layer 902 can be a p-type microcrystalline silicon contact layer 121, a preliminary p-type amorphous silicon layer 802 that is heavily (eg, degenerately) doped, p-type microcrystalline. It may be similar to a silicon layer 810 or a p-type amorphous silicon layer as described above with reference to FIGS. 1-3 and 8A-8C. In another embodiment, the PIB layer 904 may be similar to a pi buffered intrinsic amorphous silicon layer (PIB layer) as described above. The n-type amorphous silicon buffer layer 906 may be similar to the amorphous silicon buffer layers 820, 821 or the buffer layer 125 referenced in FIGS. 8B-8C and FIG.

  [0071] The second junction 920 includes a p-type microcrystalline silicon layer 132, an optional PIB layer 912, an intrinsic microcrystalline silicon layer 914, an n-type amorphous silicon layer 916, and a second lower interface layer 918. including. The second lower interface layer 918 may be similar to the interface layer 908 described above. Alternatively, the second lower interface layer 918 may be the densely doped (eg, degenerate) amorphous silicon layer 806 or n-type microcrystalline silicon layer 814 referenced in FIGS. 8B-8C, or as described above. It may be similar to other similar n-type contact layers. The p-type microcrystalline silicon layer 132 has been described above with reference to FIGS. The optional PIB layer 912 may be similar to a pi buffered intrinsic type amorphous silicon layer (PIB layer) as described above. Alternatively, since PIB layer 912 is in contact with a p-type microcrystalline silicon layer (eg, p-type microcrystalline silicon layer 132), any PIB layer 912 can be microcrystalline silicon-based as desired. Or as an amorphous silicon based material. The deposition process for depositing any PIB layer 912 that may be deposited as a microcrystalline silicon-based material or an amorphous silicon-based material is selected from any intrinsic type silicon-based deposition process, as described above. May be. The intrinsic type microcrystalline silicon layer 914 may be deposited as a single step or multiple steps as described above. In one specific embodiment, intrinsic type microcrystalline silicon layer 914 is deposited using a four step process by gradually adjusting the ratio of hydrogen to silane in the gas mixture, as described above. Provide a uniform crystal fraction formed in the resulting film. The n-type amorphous silicon layer 916 may be similar to the n-type amorphous silicon layers 136, 804 as described above with reference to FIGS. 1-3 and 8A.

  [0072] The second TCO layer 140 and the backing electrode layer 150 may then be arranged over the second junction 920 to complete the junction formation process.

  [0073] FIG. 5 is an illustration of one embodiment of a process system 500 having a plurality of process chambers 531-537, such as a PECVD chamber such as chamber 400 of FIG. 4 or other suitable chamber capable of depositing a silicon film. FIG. Process system 500 includes a load lock chamber 510 and a transfer chamber 520 coupled to process chambers 531-537. The load lock chamber 510 allows substrates to be transferred between the ambient environment outside the system and the vacuum environment within the transfer chamber 520 and process chambers 531-537. The load lock chamber 510 includes one or more evacuable regions that hold one or more substrates. The evacuable area is evacuated by a pump during loading of the substrate into the system 500 and vented during ejection of the substrate from the system 500. Transfer chamber 520 has at least one vacuum robot 522 arranged in transfer chamber 520 adapted to transfer substrates between load lock chamber 510 and process chambers 531-537. Seven process chambers are shown in FIG. However, the system may have any suitable number of process chambers.

  [0074] In certain embodiments of the present invention, one system 500 comprises a first p-i comprising an intrinsic type amorphous silicon layer of a multi-junction solar cell, such as a first p-i-n junction 120. Configured to deposit -n junctions. One of the process chambers 531 to 537 is configured to deposit a p-type silicon layer of the first pin junction, while the remaining process chambers 531 to 537 are each intrinsic type amorphous. It is configured to deposit both a porous silicon layer and an n-type silicon layer. The intrinsic type amorphous silicon layer and the n-type silicon layer of the first pin junction may be deposited in the same chamber without reporting a passivation process during the deposition step. Therefore, the substrate enters the system through the load lock chamber 510 and is transferred by the vacuum robot to a dedicated process chamber configured to deposit the p-type silicon layer, and the vacuum robot converts the intrinsic silicon layer and Transferred to one of the remaining process chambers configured to deposit an n-type silicon layer and transferred back to the load lock chamber 510 by a vacuum robot. In certain embodiments, the time for processing a substrate using a process chamber to form a p-type silicon layer is to form an intrinsic amorphous silicon layer and an n-type silicon layer in one chamber. Is about 4 times or more, for example, 6 times or more faster than Thus, in certain embodiments of the system for depositing the first pin junction, the ratio of p chamber to i / n chamber is greater than 1: 4, preferably greater than 1: 6. The throughput of the system including time to provide plasma cleaning of the process chamber may be about 10 substrates / hour or more, preferably 20 substrates / hour or more.

  [0075] In certain embodiments of the present invention, one system 500 includes a second p-i comprising an intrinsic type microcrystalline silicon layer of a multi-junction solar cell, such as a second pin junction 130. Configured to deposit -n junctions. One of the process chambers 531 to 537 is configured to deposit a p-type silicon layer of the first pin junction, while the remaining process chambers 531 to 537 are each intrinsic type microcrystals. It is configured to deposit both a porous silicon layer and an n-type silicon layer. The intrinsic pinned microcrystalline silicon layer and the n-type silicon layer of the second pin junction may be deposited in the same chamber without reporting a passivation process during the deposition step. In certain embodiments, the time for processing a substrate using a process chamber to form a p-type silicon layer is to form an intrinsic microcrystalline silicon layer and an n-type silicon layer in one chamber. It is about 4 times faster than this time. Thus, in certain embodiments of the system for depositing the second pin junction, the ratio of p chamber to i / n chamber is 1: 4 or greater, such as about 1: 6 or greater. The throughput of the system, including time to provide plasma cleaning of the process chamber, may be about 3 substrates / hour or more, such as about 5 substrates / hour or more.

  [0076] In certain embodiments, a first pin comprising an intrinsic type amorphous silicon layer because the thickness of the intrinsic type microcrystalline silicon layer is thicker than the intrinsic type amorphous silicon layer. The throughput of the system 500 for depositing a junction is about twice or more that of the system 500 for depositing a second pin junction comprising an intrinsic type microcrystalline silicon layer. Accordingly, one system 500 adapted to deposit a first pin junction comprising an intrinsic type amorphous silicon layer comprises a second pin comprising an intrinsic type microcrystalline silicon layer. It can be compared to two or more systems 500 that are adapted to deposit n-junctions. Once the first pin junction is formed on one substrate in one system, the substrate is exposed to the ambient environment (ie, vacuum break) and transferred to the second system. Also good. Wet or dry cleaning of the substrate between the first system for depositing the first pin junction and the second system for depositing the second pin junction is not necessary.

Example
[0077] The examples disclosed herein are exemplary in nature and are not intended to limit the scope of the invention unless explicitly recited in the claims.

[0078] A substrate having a surface area of 4,320 cm ² is available from AKT America, Inc. of Santa Clara, California. And processed by an AKT 4300 PECVD System having an internal chamber volume of 130 liters. Layer 1 was deposited in the first chamber of the PECVD system. Layers 2-4 were deposited in the second chamber of the PECVD system. Layer 5 was deposited in the third chamber of the PECVD system. Layers 6 through 11 were deposited in the fourth chamber of the PECVD system. The spacing during deposition of layers 1 to 11 was set to 550 mils, and the temperature of the substrate support was set to 200 ° C. In order to form a tandem pin junction solar cell, the deposition parameters are set forth in FIG. Phosphine was provided at 0.5% mixing in hydrogen carrier gas. Trimethylboron was provided at 0.5% mixing in the hydrogen carrier gas. The hydrogen gas flow rate in FIG. 6 indicates the hydrogen gas flow rate separated from the dopant carrier gas. The solar cell had the following characteristics described in FIG.

Amorphous deposition process
[0079] One aspect of the invention includes an improved thin film silicon solar cell and a method and apparatus for forming an improved thin film silicon solar cell, wherein one or more of the layers in the solar cell are improved It comprises at least one amorphous silicon layer that has improved electrical and mechanical properties and can be deposited at a rate that is many times faster than conventional amorphous silicon deposition processes. The improved deposition rate achieved using the methods described herein can significantly improve substrate throughput with solar cell substrate processing systems. In one embodiment, the process described herein is used to form an amorphous intrinsic type layer in a thin film pin solar cell, where the deposition rate of the amorphous intrinsic type layer is: Faster than about 60 km / min. In one embodiment, the deposition rate of the amorphous intrinsic type layer is from about 150 Å / min to about 400 Å / min for a substrate at least 2200 mm x 260 mm in size.

  [0080] Surprisingly, the methods described herein have been found to improve the photostability of the formed thin film solar cells. The reason is that the use of high pressure during the amorphous silicon deposition process is likely to reduce the ion bombardment of the growing film surface by lowering the ion energy and electron temperature in the generated plasma. is there. In addition, the use of higher ratios of hydrogen gas to silane gas during processing also produces higher order silane related species that have been shown to adversely affect the light stability of the resulting solar cell device Is considered to be suppressed. The following description generally describes a method of forming a single junction solar cell, but the one or more process steps described below are one or more of the steps already described. This configuration is not intended to limit the scope of the present invention since it may be used in combination. In one embodiment, the barrier layer deposition process step, the intrinsic layer deposition step, the power ramp step, the temperature stabilization step, and the plasma cleaning step comprise one or more of the steps described above with respect to FIGS. Used with.

[0081] FIG. 10 illustrates an example of a solar cell 1000 formed using the process described herein. Solar cell 1000 includes a substrate 102, such as a glass substrate, polymer substrate, or other suitable substrate using a thin film formed on the substrate. The solar cell 1000 includes a first transparent conductive oxide (TCO) layer 110 formed on the substrate 102, a pin junction 1020 formed on the first TCO layer 110, p A second TCO layer 1032 formed on the −i−n junction 1020 and a metal backing layer 1034 formed on the second TCO layer 1032 may further be provided. As described above, in order to improve light absorption by increasing light capture, one or more of the substrate and / or thin film formed on the substrate may be a wet process, a plasma process, an ion It may be arbitrarily organized by a process and / or a mechanical process. For example, the first TCO layer 110 in the solar cell 1000 is organized so that the next thin film deposited over the first TCO layer 110 generally follows the topographical features of the surface below the thin film. The first TCO layer 110 and the second TCO layer 1032 are respectively tin oxide (Sn _x O _y ), zinc oxide (Zn _x O _y ), indium tin oxide (In _x Sn _y O _z ), cadmium stannate, Combinations or other suitable materials may be provided and may further include additional dopants and components as described above.

[0082] The p-i-n junction 1020 includes a p-type amorphous silicon layer 1022, an intrinsic type amorphous silicon layer 1024 formed on the p-type amorphous silicon layer 1022, and an intrinsic type amorphous silicon. An n-type amorphous silicon layer 1026 formed over the layer 1024 may be provided. In certain embodiments, the p-type amorphous silicon layer 1022 may be formed to a thickness between about 60 angstroms (Å) and about 200 Å. In certain embodiments, the intrinsic type amorphous silicon layer 1024 may be formed to a thickness between about 1,500 and about 5,000 inches. In certain embodiments, the n-type amorphous semiconductor layer 1026 may be formed to a thickness between about 100 inches and about 400 inches. In certain embodiments, as shown in FIG. 10, the p-i-n junction 1020 may also be formed in a degenerate (e.g., high density) configuration that may be formed to a thickness between about 50 inches and about 150 inches. N) An n ⁺⁺ type amorphous semiconductor layer 1027 may be provided.

  [0083] The metal backing layer 1034 may include, but is not limited to, a material selected from the group consisting of Al, Ag, Ti, Cr, Au, Cu, Pt, alloys thereof, or combinations thereof. is not. The solar cell 1000 may be formed by performing other processes such as a laser scribing process. Other films, materials, substrates and / or packaging may be provided on the metal backing layer 1034 to complete the solar cell.

  [0084] Referring to FIG. 4, a single chamber is illustrated, but a system 500 as illustrated in FIG. 5 may contain a plurality of chambers disposed around a substrate handling robot 522. . In such systems, if additional layers are deposited, the one or more amorphous silicon layers may be deposited in one chamber before the substrate is transferred to another chamber. Typically, when i-type and n-type layers are deposited on a substrate, a p-type layer is deposited on the substrate in a first chamber, and then the substrate is moved to another chamber. The

  [0085] In one embodiment, the heating and / or cooling element 439 may be set to provide a substrate support temperature of about 250 ° C. or less during deposition. In one embodiment, the substrate support is maintained at a temperature of about 150 ° C to about 250 ° C. In one embodiment, the substrate support is maintained at a temperature of about 200 ° C. The spacing during the various deposition steps between the upper surface of the substrate 102 arranged on the substrate receiving surface 432 of the substrate support 430 and the showerhead 410 (ie, the RF electrode) is between 600 mils and about 6,000. It may be a mill. A typical thickness of a glass substrate for solar cell applications is about 40 mils to 200 mils.

  [0086] In one embodiment, the pin amorphous silicon solar cell is formed using the following steps described below. The process values and examples described below are not intended to limit the scope of the invention described herein, and in some cases have a chamber volume of about 2900 liters. And a 60 k processing system adapted to process 2200 mm × 2600 mm substrates. First, a substrate having a TCO layer 110 arranged on at least one substrate is inserted into the PECVD chamber 400 and placed on a substrate support 430 so that the TCO 110 is p-i-n. One or more of the layers contained in the bond 1020 can be accommodated.

  [0087] In one embodiment, prior to depositing one or more of the layers in the pin junction 1020, the temperature of the substrate may be about 3 to about 3 gases, such as argon, hydrogen, or helium. Stabilized by flowing through the processing chamber for a period of 5 minutes, allowing the temperature of a typical 3 mm to 5 mm thick glass substrate to be raised to a desired temperature, such as about 200 ° C. . In one example, the temperature stabilization step comprises providing argon gas at a flow rate of about 25.8 sccm / L (eg, 75,000 sccm), and a chamber pressure of about 2.0 to about 2.5 Torr. Achieving and stabilizing the temperature of the substrate positioned about 640 mils from the showerhead 410 at a desired level within about 5 minutes. In this case, the substrate support can be maintained at a temperature of about 200 ° C.

  [0088] In the next step or plasma cleaning step, plasma is generated in the process volume 406 and argon, hydrogen or helium gas is dispensed through the chamber to clean the surface of the TCO layer 110 and Improve the electrical properties of layer 110. In one embodiment, the gas flowing through the processing volume includes argon because the hydrogen-containing plasma can actively react with a TCO layer, such as a TCO layer containing tin oxide. In one embodiment, it is desirable to perform the plasma cleaning step using a cleaning gas comprising hydrogen gas for a TCO layer comprising zinc oxide.

[0089] In the next step, typically after cleaning the surface of the TCO layer 110, a p-type doped amorphous layer is deposited over the TCO surface. In one embodiment, the p-type doped amorphous layer is deposited in two stages, and the first stage process may utilize a hydrogen to silane dilution ratio of about 0 to about 6.0. This low hydrogen dilution ratio is exploited to prevent damage to the TCO layer that may occur due to the interaction of the TCO layer and the generated plasma. In one embodiment, the first p-type doped amorphous layer is a degenerate (eg, densely) doped p ^++- type amorphous silicon layer of about 2 to about 2.5 Torr. The TMB precursor has a doping concentration corresponding to a layer formed using a TMB: silane precursor gas mixture in a ratio of about 2: 1 to about 6: 1 at pressure, and the TMB precursor has 0.5% TMB. Prepare. In one embodiment, the first p-type doped amorphous layer is formed by plasma power of about 45mW ^/ cm 2 (2400W) ~ about 91mW ^/ cm 2 (4800W). In one example, the first stage of the p-type amorphous silicon layer, such as a portion of the layer 1022 illustrated in FIG. 10, is about 2.1 sccm / L (eg, 6000 sccm) to about 3.1 sccm / L. Providing silane at a flow rate (eg, 9000 sccm), providing hydrogen gas at a flow rate such that the mixing ratio of hydrogen gas to silane gas is about 6.0, and 6: 1 0.5% TMB gas to silane gas It may be formed by providing a doping precursor at a flow rate corresponding to the mixing ratio, while the substrate support temperature is maintained at about 200 ° C. and the plasma power is controlled at 57 mW / cm ² (3287 W). The chamber pressure is maintained at about 2.5 Torr for about 2-10 seconds to form a film of about 10-50 inches. In this example, the substrate can be positioned about 640 mils from the showerhead 410. An amorphous p-type doped silicon layer formed at this doping concentration is believed to improve hole transport in silicon solar cells.

[0090] After deposition of the first p-type doped amorphous layer, a second p-type doped amorphous layer can then be deposited. The second p-type doped amorphous layer may have a thickness of about 80-150 mm, has a TMB: silane precursor mix ratio of about 1: 1 to about 2: 3, and about 5 to about 10. Typically deposited using a doping concentration corresponding to the layer formed using the hydrogen silane dilution ratio. In one embodiment, the second p-type doped amorphous layer is formed by plasma power of about 45mW ^/ cm 2 (2400W) ~ about 91mW ^/ cm 2 (4800W). Also, in one embodiment, during a second amorphous silicon p-type doped layer deposition process, a carbon-containing precursor gas, such as methane (CH ₄ ), is treated to increase the conductivity of the deposited film. It is desirable to provide an amount of carbon for the deposited film by partitioning into the regions. In one embodiment, the ratio of pure methane to silane is varied from about 1: 1 to about 2: 3 (methane: silane) and the silane flow rate is from about 2.1 sccm / L (6000 sccm) to about 3.1 sccm / It may be changed by L (9000 sccm). In one embodiment, the second stage of the p-type amorphous silicon layer provides silane at a flow rate of about 2.3 sccm / L (6702 sccm) and the mixing ratio of hydrogen gas to silane gas is about 10.0. Hydrogen gas is provided at such a flow rate, and a doping precursor is provided at a flow rate corresponding to a mixing ratio of 0.5% TMB gas to silane gas of 5.8: 1, and the mixing ratio of methane gas to silane gas is about 1: 1. At the same time, the substrate support temperature is maintained at about 200 ° C., the plasma power is controlled at about 56 mW / cm ² (3217 W), and the chamber The pressure is maintained at about 2.5 Torr for about 21 seconds to form 120 kg. In this example, the substrate can be positioned about 640 mils from the showerhead 410. The use of the second p-type doped amorphous layer immediately after the first p-type doped amorphous layer is the use of a thin dense (eg, degenerate) doped first p-type layer and more It is thought to be useful for reducing the light absorption loss due to the use of the second wide p-type amorphous layer material having a wide band gap.

[0091] During one or more of the PECVD deposition steps, such as during a p-type layer deposition step, an electrostatic charge can be accumulated on the substrate. The electrostatic charge may be large enough to cause damage to the substrate when it is forcibly removed from the substrate receiving surface 432 by a mechanical substrate lift mechanism. A hydrogen plasma is created in the chamber to eliminate static charges while the spacing between the top surface of the substrate and the showerhead may be variable. Thus, in one embodiment, the process is performed because some of the deposition steps used to form the solar cell device are performed in different chambers (eg, p-type deposition step, i-type deposition step, n-type deposition step). Prior to transferring the substrate from the chamber, an optional plasma processing step or power up step is used to help separate the substrate 102 from the substrate support 430. The generated plasma allows the charge collected on the dielectric substrate during the previous processing step to be discharged. In this step, a plasma is generated in the processing volume 406 and at the same time argon, hydrogen or helium gas passes through the processing chamber for charge trapped in the substrate that is to be lost. Form the path. The substrate support may also be maintained at a desired temperature, such as about 200 ° C. In one embodiment, the power ramp step comprises multiple steps on various substrates for showerhead spacing, such as 6 steps at various spacings, completely eliminating static charge. In one embodiment, the initial hydrogen-containing gas is about 5.2 sccm / L (15,000 sccm) to about 15 at an RF power of about 38 mW / cm ² (1000 W) to about 76 mW / cm ² (4000 W). Distribute through the treatment volume at a flow rate of 5 sccm / L (45000 sccm). In one embodiment, the power ramp step provides hydrogen gas at a flow rate of about 10.3 sccm / L (30,000 sccm) to achieve a chamber pressure of about 2.0 Torr while simultaneously removing the substrate from the showerhead 410. Positioned at about 1400 mils, about 57 mW / cm ² of RF power is distributed for about 3 seconds. In another embodiment, the power ramping step comprises providing hydrogen gas at a flow rate of about 10.3 sccm / L (30,000 sccm) to achieve a chamber pressure of about 2.0 Torr, while at the same time the substrate Is about 1400 mils from the showerhead 410 and about 57 mW / cm ² of RF power is distributed for about 3 seconds and a chamber pressure of about 2.0 Torr is achieved. Second, hydrogen gas is dispensed at a flow rate of 3 sccm / L (30,000 sccm) while the substrate is positioned about 6000 mils from the showerhead 410 and about 57 mW / cm ² of RF power is dispensed for about 5 seconds. These steps are provided.

  [0092] In the next step, optionally, hydrogen gas may be dispensed through the processing chamber for a period of about 20 seconds to allow the substrate to stabilize at a desired temperature, such as about 200 ° C. In some cases, when a substrate is transported in a vacuum environment from one chamber to another in a multi-chamber PECVD system, the substrate with p-type material deposited on the substrate is The time period used to complete this step may be short because it is believed that a substantial amount of temperature will not be lost. In one example, the temperature stabilization step comprises providing argon gas at a flow rate of about 25.9 sccm / L (eg, 75,000 sccm) to achieve a chamber pressure of about 2.5 Torr and about Stabilizes the temperature of the substrate positioned about 640 mils from the showerhead 410 after 20-60 seconds. The substrate support can be maintained at a temperature of about 200 ° C.

[0093] In the next step or plasma cleaning step, this is typically done on the substrate once it has been loaded into the second processing chamber. In this step, a hydrogen plasma is generated in the processing volume of the second processing chamber in order to properly clean the surface of the deposited p-type layer prior to the deposition of the next material layer, such as a barrier layer. The hydrogen plasma treatment passivates the p-type layer and removes any surface defects that may be formed on the p-type layer, and without the hydrogen plasma treatment step, may be likely to diffuse into the i-type layer. Arbitrary carbon and boron contamination can be suppressed. In one embodiment, the hydrogen plasma cleaning step, a plasma power of about 35mW ^/ cm 2 (2000W) ~ about 136mW ^/ cm 2 (7200W), from about 0 to about 60 seconds, the chamber of from about 2 to about 2.5 Torr Providing sufficient hydrogen gas to achieve the pressure. In one embodiment, the hydrogen plasma cleaning step provides hydrogen gas at a flow rate of about 10.3 sccm / L (30,000 sccm) and a plasma power of 52 mW / cm ² (3000 W), and a chamber of about 2.5 Torr. Simultaneously with achieving the pressure, the substrate comprises being positioned about 640 mils from the showerhead 410 for about 15 seconds.

[0094] It has been found that the barrier layer 1023 at the interface between the p-i layers can improve the electrical performance of the solar cell. In one embodiment, the barrier layer 1023 is similar to the PIB layer described above. In certain embodiments, the barrier layer 1023 is equal to the next i-layer deposition process for about 38 seconds to about 225 seconds, or the next i to form a barrier layer having a thickness of about 50-300 mm. Formed by plasma deposition using a silane precursor diluted in hydrogen at a ratio of about 20 to about 50 at a pressure about 0.5 Torr greater than the layer deposition process. The barrier layer is believed to provide a wide band gap and improve the open circuit voltage of solar cells up to about 50 meV. Since the barrier layer is positioned between the previously deposited layer and the next higher deposition rate intrinsic layer described below, the barrier layer is used to ionize previously deposited layers. Impact may be minimized. In order to minimize the impact of previously deposited layers during the barrier layer deposition step, the deposition process typically uses a low RF plasma deposition power. In one embodiment, the barrier layer is an intrinsic type amorphous material and is a silane gas mixture diluted with hydrogen having a dilution ratio of about 20 to about 50, equal to or more than an i-layer deposition process. It is formed on the substrate using a high chamber pressure and an RF plasma power of about 23 mW / cm ² (1200 W) to about 61 mW / cm ² (3240 W) for a time period of about 18 seconds to about 3600 seconds. In one configuration, the chamber pressure is equal to or about 0.5 Torr greater than the i-layer deposition process. In one embodiment, the barrier layer comprising an intrinsic type amorphous silicon layer provides silane at a flow rate of about 1.5 sccm / L (4235 sccm) such that the mixing ratio of hydrogen gas to silane gas is about 25. At the flow rate, while providing hydrogen gas, the substrate support temperature is maintained at about 200 ° C., the plasma power is controlled at about 27 mW / cm ² (1525 W), and the chamber pressure is about 3.0 seconds for about 3.0 seconds. Formed by being maintained in Toll. In one configuration, due to the properties of the barrier layer film formed using the process described herein, the barrier layer improves blue light absorption in the formed solar cell device, and therefore It is believed that it can be used to help improve solar cell efficiency. Barrier layer deposition at hydrogen to silane dilution ratios of about 20 to about 50 and flow rates in excess of 37.9 sccm / L (110,000 sccm) is an excellent factor for fill factor and other conventionally formed solar cell devices. It is thought to improve electrical characteristics such as stability.

[0095] In the next step, an intrinsic layer 1024 is deposited over the substrate surface. Following the deposition of the buffer layer, a 2000-3000 thick layer of intrinsic type amorphous material is diluted with hydrogen having a dilution ratio of about 8 to about 15 silane gas mixture, about 2 to about 3 Torr. An RF plasma power of about 27 mW / cm ² (1440 W) to about 91 mW / cm ² is formed on the substrate at a chamber pressure and a time period of about 300 to about 1800 seconds. In one embodiment, the 2600 真 intrinsic amorphous layer provides silane at a flow rate of about 9000 sccm and simultaneously provides hydrogen gas at a flow rate such that the mixing ratio of hydrogen gas to silane gas is about 12.5. Formed by maintaining the substrate support temperature at about 200 ° C., controlling the plasma power to about 55 mW / cm ² (3168 W), and maintaining the chamber pressure at about 2.5 Torr for about 736 seconds. May be.

[0096] In the next step, the n-type doped amorphous layer 1026 has a hydrogen to silane dilution ratio of about 5.0 to about 9.0, a dopant: silane ratio of about 1: 1 to about 1: 3. A doping precursor at a flow rate corresponding to a mixing ratio of 0.5% phosphine (PH ₃ ) gas to silane gas, RF plasma power of about 68 (3600 W) to about 114 mW / cm ² (6000 W), and about 24 to about 36 seconds In this time period, a chamber pressure of about 1 to about 3 Torr is utilized to deposit on the surface of i-type intrinsic layer 1024. In one embodiment, the 200-300 n-type n-type amorphous silicon layer provides silane at a flow rate between about 1.0 sccm / L (3000 sccm) and about 3.1 sccm / L (6000 sccm) to provide hydrogen versus silane gas. Providing a hydrogen gas at a flow rate such that a mixing ratio of about 5.0 is a doping precursor at a flow rate corresponding to a mixing ratio of 0.5% phosphine (PH ₃ ) gas to silane gas of about 1: 3. Simultaneously, the substrate support temperature is maintained at about 200 ° C., the plasma power is controlled at about 81 mW / cm ² (4678 W), and the chamber pressure is maintained at about 1.5 Torr for about 25 seconds. Formed by. In this example, the substrate can be positioned about 640 mils from the showerhead 410.

[0097] In the next step, a degenerately doped (eg, n ⁺⁺ ) n-type doped amorphous layer 1027 has a hydrogen to silane dilution ratio of about 5.0 to about 9.0, about 1: 2. A doping precursor at a flow rate corresponding to a mixing ratio of 0.5% phosphine (PH ₃ ) gas to silane gas of about 1: 5 (phosphine: silane ratio), about 68 mW / cm ² (3600 W) to about 113 mW / cm ² (6000 W) RF plasma power and a chamber pressure of about 1 to about 3 Torr for about 8 to about 25 seconds, deposited on the surface of n-type layer 1026 to 50-150 Å A thick layer of is formed. In one example, an 80 ｎ n ⁺⁺ type amorphous silicon layer provides silane at a flow rate between about 0.5 sccm / L (1500 sccm) and about 3.1 sccm / L (6000 sccm) to provide a hydrogen gas to silane gas ratio. The hydrogen gas is provided at a flow rate such that the mixing ratio is about 8.3, and the doping precursor is provided at a flow rate corresponding to a mixing ratio of about 5: 1 phosphine (PH ₃ ) gas to silane gas, while at the same time the substrate. The support temperature is formed at about 200 ° C., the plasma power is controlled at about 72 mW / cm ² (4153 W), and the chamber pressure is maintained at about 1.5 Torr for about 10 seconds. In this example, the substrate can be positioned about 640 mils from the showerhead 410.

[0098] After the n and n + layers are formed, plasma may be generated again in the processing volume to eliminate the electrostatic charge on the substrate, as described above. In one embodiment, this step comprises multiple sub-steps on different substrates for showerhead spacing, such as 6 steps at different spacing, completely eliminating static charge. In one embodiment, the gas flowing through the processing volume includes hydrogen. In one embodiment, a so-called “power ramping step” provides hydrogen gas at a flow rate of about 10.3 sccm / L (30,000 sccm) to achieve a chamber pressure of about 2.0 Torr while the substrate is showered. Positioned about 1400 mils from the head 410 and comprising about 57 mW / cm ² of RF power distributed for about 3 seconds. In another embodiment, the power ramp step provides hydrogen gas at a flow rate of about 10.3 sccm / L (30,000 sccm) to achieve a chamber pressure of about 2.0 Torr while simultaneously the substrate is in the showerhead 410. To about 1400 mils and about 57 mW / cm ² of RF power is distributed for about 3 seconds and about 10.3 sccm / L (about 10.3 sccm / L (to achieve a chamber pressure of about 2.0 Torr) A second step in which hydrogen gas is dispensed at a flow rate of 30,000 sccm, while the substrate is positioned about 6000 mils from the showerhead 410 and about 57 mW / cm ² of RF power is dispensed for about 5 seconds; Is provided.

  [0099] While the foregoing is directed to embodiments of the invention, other and alternative embodiments of the invention may be devised without departing from the basic scope thereof. And the scope of the invention is determined by the following claims. For example, the process chamber of FIG. 4 is shown in a horizontal position. It will be appreciated that in other embodiments of the invention the process chamber may be in a position other than horizontal, such as vertical. For example, an embodiment of the present invention is described with respect to a multi-process chamber cluster tool in FIG. It is understood that embodiments of the present invention may also be implemented in inline systems and hybrid inline / cluster systems. For example, embodiments of the present invention are described with reference to a first system configured to form a first pin junction and a second pin junction. It will be appreciated that in other embodiments of the present invention, the first pin junction and the second pin junction may be formed in one system. For example, embodiments of the present invention are described with respect to a process chamber adapted to deposit both intrinsic and n-type layers. It will be appreciated that in other embodiments of the invention, separate chambers may be adapted to deposit intrinsic and n-type layers. It will be appreciated that in other embodiments of the invention, the process chamber may be adapted to deposit both p-type and intrinsic type layers.

1 is a schematic diagram of an embodiment of a multi-junction solar cell that is directed to light or solar radiation. FIG. FIG. 2 is a schematic diagram of the multijunction solar cell of FIG. 1 further comprising an n-type amorphous silicon buffer layer. FIG. 2 is a schematic view of the multijunction solar cell of FIG. 1 further comprising a p-type microcrystalline silicon contact layer. 1 is a schematic cross-sectional view of one embodiment of a plasma enhanced chemical vapor deposition (PECVD) chamber in which one or more films of a solar cell may be deposited. FIG. 1 is a schematic top view of an embodiment of a process system having a plurality of process chambers. FIG. 1 depicts a set of deposition parameters for forming a tandem pin junction solar cell. 1 depicts the characteristics of a solar cell of one embodiment of the present invention. 1 depicts a schematic diagram of different embodiments of a single junction solar cell. 1 depicts a schematic diagram of different embodiments of a single junction solar cell. 1 depicts a schematic diagram of different embodiments of a single junction solar cell. 1 depicts a schematic diagram of different embodiments of a single junction solar cell. 1 is a schematic view of a single junction solar cell according to an embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Multijunction solar cell or board | substrate, 101 ... Solar radiation, 102 ... Board | substrate, 110 ... 1st transparent conductive oxide (TCO) layer, 120 ... 1st pin junction, 121 ... p-type fine Amorphous silicon contact layer, 122 ... p-type amorphous silicon layer, 124 ... intrinsic amorphous silicon layer, 125 ... n-type amorphous silicon buffer layer, 126 ... n-type microcrystalline silicon layer, 130 ... first 2 p-i-n junctions, 132... P-type microcrystalline silicon layer, 134... Intrinsic type microcrystalline silicon layer, 136... N-type amorphous silicon layer, 140... Second TCO layer, 150. Backing layer, 400 ... plasma enhanced chemical vapor deposition (PECVD) chamber, 402 ... wall, 404 ... bottom, 406 ... process volume, 408 ... valve, 409 ... vacuum pump, 410 ... shower head, 412 ... backing plate, 41 ... Suspension device, 416 ... Center support, 420 ... Gas source, 422 ... RF power source, 424 ... Remote plasma source, 430 ... Substrate support, 431 ... Ground strap, 432 ... Substrate receiving surface, 434 ... Stem, 433 ... Shadow From, 436 ... Lift system, 438 ... Lift pin, 439 ... Heating and / or cooling element, 500 ... Process system, 510 ... Load lock chamber, 520 ... Transfer chamber, 522 ... Vacuum robot, 531-537 ... Process chamber, 802 ... Preliminary p-type amorphous silicon layer, 804... N-type amorphous silicon layer, 806... Densely doped n-type amorphous silicon layer, 808... N-type microcrystalline silicon layer, 810. Microcrystalline silicon layer, 812... Intrinsic type microcrystalline silicon layer, 814... N type microcrystalline silicon layer, 820... N type amorphous Silicon buffer layer, 821 ... n-type amorphous silicon buffer layer, 850 ... solar cell, 852 ... solar cell, 854 ... solar cell, 900 ... multi-junction solar cell, 902 ... first upper interface layer, 904 ... p- i buffer intrinsic type amorphous silicon layer (PIB layer), 906... n type amorphous silicon buffer layer, 908... interface layer, 910... first junction, 912 ... arbitrary PIB layer, 914. , ... n-type amorphous silicon layer, 918 ..., second lower interface layer, 920 ... second junction, 1000 ... solar cell, 1020 ... pin junction, 1022 ... p-type non-layer Amorphous silicon layer, 1023 ... barrier layer, 1024 ... intrinsic type amorphous silicon layer, 1026 ... n type amorphous silicon layer, 1027 ... degenerately doped n ⁺⁺ type amorphous semiconductor layer, 1032 ... first 2 TCO layers, 1034 ... Genus backing layer.

Claims (48)

In a method of forming a thin film multi-junction solar cell on a substrate,
Forming a first photovoltaic junction on a substrate;
Forming a second photovoltaic junction on the first photovoltaic junction, comprising:
forming a p-type microcrystalline silicon layer;
Forming an intrinsic microcrystalline silicon layer on the p-type microcrystalline silicon layer, wherein when the intrinsic microcrystalline silicon layer is formed, one or more process variables are: A step adjusted to control the crystal fraction at two or more points within the thickness of the intrinsic type microcrystalline silicon layer;
Forming an n-type amorphous silicon layer on the intrinsic microcrystalline layer;
Comprising the steps of:
Said method. The first photovoltaic junction is
forming a p-type amorphous silicon layer;
Forming an intrinsic amorphous silicon layer on the p-type amorphous silicon layer;
Forming an n-type microcrystalline silicon layer on the intrinsic amorphous silicon layer;
The forming method according to claim 1, further comprising:   The formation method according to claim 2, further comprising a step of forming a pi buffer intrinsic type amorphous silicon layer between the p type amorphous silicon layer and the intrinsic type amorphous silicon layer.   The forming method according to claim 2, further comprising a step of forming an n-type amorphous silicon buffer layer between the intrinsic type amorphous silicon layer and the n-type microcrystalline silicon layer.   4. The method of claim 3, wherein the pi buffered intrinsic type amorphous silicon layer is deposited by a gas mixture having a hydrogen gas to silane gas ratio of about 20: 1 to about 30: 1. The step of forming the intrinsic type microcrystalline silicon layer comprises:
The method of claim 1, further comprising adjusting a ratio between a first gas and a silane gas during the step of forming the intrinsic type microcrystalline silicon layer, wherein the first gas includes hydrogen. The forming method as described.   The method of claim 6, wherein the ratio of the first gas to the silane gas is controlled from about 20: 1 to about 200: 1.   The method of claim 7, wherein the gas flow of hydrogen gas is reduced during deposition. The step of forming the n-type microcrystalline silicon layer comprises:
The method of claim 2, further comprising providing a gas mixture having a hydrogen to silane gas ratio of about 100: 1 to about 400: 1 to deposit the n-type microcrystalline silicon layer. The step of forming the p-type microcrystalline silicon layer comprises:
The method of claim 1, further comprising providing a gas mixture having a hydrogen to silane gas ratio of about 200: 1 to about 800: 1 to deposit the p-type microcrystalline silicon layer.   The formation according to claim 1, further comprising the step of forming a densely doped n-type amorphous silicon layer on the n-type amorphous silicon layer in the second photovoltaic cell. Method.   The method of claim 11, wherein the heavily doped n-type amorphous silicon layer has a thickness of less than about 300 mm. Performing a hydrogen treatment process on the substrate before forming the p-type microcrystalline silicon layer, the hydrogen treatment comprising:
Distributing a gas containing hydrogen toward the surface of the substrate;
Generating RF plasma on the surface of the substrate;
The forming method according to claim 1, further comprising the step of: Performing a hydrogen treatment process on the substrate before forming the intrinsic microcrystalline silicon layer, the hydrogen treatment comprising:
Distributing a gas containing hydrogen toward the p-type microcrystalline silicon layer arranged on the substrate surface;
Generating RF plasma on the surface of the p-type microcrystalline silicon layer;
The forming method according to claim 1, further comprising the step of: Performing an argon treatment process before depositing the p-type amorphous silicon layer, wherein the argon treatment comprises:
Distributing a gas containing argon toward the surface of the substrate;
Generating RF plasma on the surface of the substrate;
The forming method according to claim 2, further comprising the step of:   The formation method according to claim 1, further comprising forming an interface layer between the first photovoltaic junction and the second photovoltaic junction.   The interface layer is selected from at least one of SiON, SiN, SiC, SiO, SiOC, SiCN, and other suitable carbon, oxygen or nitrogen containing silicon based materials or silicon alloys. 16. The forming method according to 16.   The forming method according to claim 2, further comprising forming a first upper interface layer between the substrate and the p-type amorphous silicon layer.   The first upper interface layer is a densely doped p-type amorphous silicon layer, p-type microcrystalline silicon layer, p-type amorphous silicon layer, SiON, SiN, SiC, SiO, SiOC, SiCN The method of claim 18, wherein the method is at least one of a silicon-based material or a silicon alloy containing carbon, oxygen or nitrogen. The formation method of claim 1, wherein the p-type microcrystalline silicon layer has a boron concentration of about 1 × 10 ¹⁸ atoms / cm ² to about 1 × 10 ²⁰ atoms / cm ² . The step of forming the n-type amorphous silicon layer comprises:
Distributing silane gas at a first flow rate on the surface of the substrate;
Distributing the hydrogen-containing gas such that the dilution ratio of hydrogen to silane is about 5.0 to about 9.0;
Dispensing the doping precursor gas at a flow rate such that the mixing ratio of doping precursor gas to silane gas is from about 1: 1 to about 1: 3;
The method of claim 1, comprising controlling pressure in a processing volume adjacent to the surface of the substrate at about 1 to about 3 Torr. After forming the p-type microcrystalline silicon layer, generating RF plasma on the surface of the substrate, forming the p-type microcrystalline silicon layer and generating the RF plasma But,
Steps performed in the first process chamber;
Transferring the substrate to a second process chamber, and then forming the intrinsic microcrystalline silicon layer and the n-type amorphous silicon layer;
The forming method according to claim 1, further comprising: In a method of forming a thin film multi-junction solar cell on a substrate,
Forming a first photovoltaic junction on a substrate, comprising:
forming a p-type amorphous silicon layer;
Forming an intrinsic type amorphous silicon layer on the p type amorphous silicon layer, wherein the intrinsic type amorphous silicon layer comprises a pi buffer intrinsic type amorphous silicon layer and a bulk intrinsic type; A step including a type amorphous silicon layer;
Forming an n-type microcrystalline silicon layer on the intrinsic type amorphous silicon layer;
Comprising the steps of:
Forming a second photovoltaic junction on the first photovoltaic junction, comprising:
forming a p-type microcrystalline silicon layer;
Forming an intrinsic microcrystalline silicon layer on the p-type microcrystalline silicon layer;
Forming an n-type amorphous silicon layer on the intrinsic microcrystalline silicon layer;
Comprising the steps of:
A forming method. The step of forming the intrinsic amorphous silicon layer comprises:
24. The formation of claim 23, further comprising adjusting a gas mixture supplied to deposit the intrinsic type amorphous silicon layer, wherein the gas mixture further comprises at least a silane gas and a hydrogen gas. Method.   25. The method of claim 24, further comprising the step of reducing the hydrogen gas stream utilized to deposit the bulk intrinsic type amorphous silicon layer.   25. The method of claim 24, wherein the step of adjusting the gas mixture further comprises controlling a hydrogen to silane gas ratio of about 25: 1 to about 12.5: 1.   The formation method according to claim 23, further comprising forming an interface layer between the first photovoltaic junction and the second photovoltaic junction.   The interface layer is selected from at least one of SiON, SiN, SiC, SiO, SiOC, SiCN, and other suitable carbon, oxygen or nitrogen containing silicon based materials or silicon alloys. 28. The forming method according to 27. The step of forming the bulk intrinsic amorphous silicon layer comprises:
Distributing silane gas at a first flow rate to a processing volume adjacent to the surface of the substrate;
Distributing a hydrogen-containing gas to the treatment volume such that a dilution ratio of hydrogen to silane is about 8 to about 15.
Controlling the pressure in the processing volume to a first pressure;
Further comprising
Forming the pi buffer intrinsic type amorphous silicon layer before forming the bulk intrinsic type amorphous silicon layer, wherein the pi buffer intrinsic type amorphous silicon layer is formed; Said step comprises
Distributing silane gas at a second flow rate to the processing volume;
Distributing the hydrogen-containing gas to the processing volume such that a ratio of the flow rate of the hydrogen-containing gas to the second flow rate is from about 20 to about 50;
24. The method of claim 23, further comprising controlling the pressure in the processing volume to a pressure that is greater than or equal to the first pressure. After forming the p-type amorphous silicon layer, generating RF plasma on the surface of the substrate, forming the p-type amorphous silicon layer and generating the RF plasma Step is
Steps performed in the first process chamber;
Transferring the substrate to a second process chamber and then forming the intrinsic type amorphous silicon layer and the n type microcrystalline silicon layer;
The forming method according to claim 23, further comprising: A tandem junction photovoltaic device comprising a first photovoltaic junction and a second photovoltaic junction, wherein the first photovoltaic junction is
a p-type amorphous silicon layer;
a pi buffer intrinsic type amorphous silicon layer;
A bulk intrinsic amorphous silicon layer;
an n-type microcrystalline silicon layer, wherein the second photovoltaic junction is
a p-doped microcrystalline silicon layer;
An intrinsic type microcrystalline silicon layer;
An n-doped amorphous silicon layer adjacent to the intrinsic type microcrystalline silicon layer;
A tandem junction photovoltaic device.   32. The device of claim 31, further comprising an interface layer arranged between the first photovoltaic junction and the second photovoltaic junction.   32. The device of claim 31, further comprising a first upper interface layer arranged between the first photovoltaic junction and a substrate.   The first upper interface layer is a densely doped p-type amorphous silicon layer, p-type microcrystalline silicon layer, p-type amorphous silicon layer, SiON, SiN, SiO, SiC, SiOC, SiCN 35. The device of claim 33, wherein the device is at least one of a silicon-based material or a silicon alloy containing, and other suitable carbon, oxygen or nitrogen.   The method further comprises a second lower interface layer arranged over the second photovoltaic junction in contact with the n-doped amorphous silicon layer adjacent to the intrinsic type microcrystalline silicon layer. 34. The device according to 33.   The second lower interface layer is a densely doped n-type amorphous silicon layer, n-type microcrystalline silicon layer, n-type amorphous silicon layer, SiON, SiN, SiC, SiO, SiOC, SiCN 36. The device of claim 35, wherein the device is at least one of a silicon-based material or a silicon alloy containing, and other suitable carbon, oxygen or nitrogen.   32. The device of claim 31, wherein the intrinsic type microcrystalline silicon layer is formed by a multi-step deposition process, each deposition step having a different hydrogen to silane gas ratio.   38. The device of claim 37, wherein a hydrogen to silane gas ratio is reduced in each successive deposition step used to deposit the intrinsic type microcrystalline silicon layer.   32. The pi buffered intrinsic type amorphous silicon layer and the bulk intrinsic type amorphous silicon layer are deposited in one processing chamber by varying a hydrogen to silane gas ratio. Devices. The step of forming the bulk intrinsic amorphous silicon layer comprises:
Distributing silane gas at a first flow rate to a processing volume adjacent to the surface of the substrate;
Distributing a hydrogen-containing gas to the treatment volume such that a dilution ratio of hydrogen to silane is about 8 to about 15.
Controlling the pressure in the processing volume to a first pressure;
Further comprising
Forming the pi buffer intrinsic type amorphous silicon layer before forming the bulk intrinsic type amorphous silicon layer, wherein the pi buffer intrinsic type amorphous silicon layer is formed; Said step comprises
Distributing silane gas at a second flow rate to the processing volume;
Distributing the hydrogen-containing gas to the processing volume such that a ratio of the flow rate of the hydrogen-containing gas to the second flow rate is from about 20 to about 50;
32. The forming method according to claim 31, further comprising the step of controlling the pressure in the processing volume to a pressure greater than or equal to the first pressure. After forming the p-type amorphous silicon layer, generating RF plasma on the surface of the substrate, forming the p-type amorphous silicon layer and generating the RF plasma Step is
Steps performed in the first process chamber;
Transferring the substrate to a second process chamber and then forming the bulk intrinsic amorphous silicon layer and the n-type microcrystalline silicon layer;
The forming method according to claim 31, further comprising: Performing a hydrogen treatment process on the substrate before depositing the p-type amorphous silicon layer, the hydrogen treatment comprising:
Distributing a gas containing hydrogen toward the surface of the substrate;
Generating RF plasma on the surface of the substrate;
The forming method according to claim 31, further comprising:   Performing a hydrogen treatment process on the substrate before depositing the bulk intrinsic type amorphous silicon layer, wherein the hydrogen treatment is arranged on the substrate surface; 32. The forming method according to claim 31, further comprising: a step of distributing a gas containing hydrogen toward the surface, and a step of generating RF plasma on the p-type amorphous silicon layer. Comprising a first photovoltaic junction and a second photovoltaic junction, the second photovoltaic junction comprising:
a p-doped microcrystalline silicon layer;
An intrinsic type microcrystalline silicon layer, wherein the intrinsic type microcrystalline silicon layer is formed by a multi-step deposition process, each deposition step being different to form a different film crystal fraction in each deposition step An intrinsic type microcrystalline silicon layer having a gas mixture having a ratio of hydrogen to silane;
An n-doped amorphous silicon layer adjacent to the intrinsic type microcrystalline silicon layer;
A tandem junction photovoltaic device.   45. The device of claim 44, wherein the hydrogen to silane gas ratio provided in the gas mixture is from about 20: 1 to about 200: 1.   45. The device of claim 44, wherein the hydrogen to silane gas ratio supplied in the gas mixture is reduced at each deposition step.   The intrinsic type microcrystalline silicon layer is formed by a multi-step deposition process and the ratio of hydrogen to silane supplied for the deposition step is about 100: 1, 95: 1, 90: 1 and 85: 1. 45. The device of claim 44.   An interface layer arranged between the first photovoltaic junction and the second photovoltaic junction, the interface layer comprising SiON, SiN, SiC, SiO, SiOC, SiCN, and other 45. The device of claim 44, wherein the device is at least one of a suitable carbon, oxygen or nitrogen containing silicon based material or silicon alloy.

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