JP2010510591A5 - - Google Patents

Download PDF

Info

Publication number
JP2010510591A5
JP2010510591A5 JP2009537409A JP2009537409A JP2010510591A5 JP 2010510591 A5 JP2010510591 A5 JP 2010510591A5 JP 2009537409 A JP2009537409 A JP 2009537409A JP 2009537409 A JP2009537409 A JP 2009537409A JP 2010510591 A5 JP2010510591 A5 JP 2010510591A5
Authority
JP
Japan
Prior art keywords
solver
parallel
graph
support
merged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009537409A
Other languages
English (en)
Japanese (ja)
Other versions
JP4707760B2 (ja
JP2010510591A (ja
Filing date
Publication date
Priority claimed from US11/602,092 external-priority patent/US7543266B2/en
Application filed filed Critical
Publication of JP2010510591A publication Critical patent/JP2010510591A/ja
Publication of JP2010510591A5 publication Critical patent/JP2010510591A5/ja
Application granted granted Critical
Publication of JP4707760B2 publication Critical patent/JP4707760B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2009537409A 2006-11-20 2007-11-19 並列化制約充足問題ソルバにおけるＬｏｃｋ−ｆｒｅｅ状態併合 Active JP4707760B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/602,092 US7543266B2 (en) 2006-11-20 2006-11-20 Lock-free state merging in parallelized constraint satisfaction problem solvers
US11/602,092 2006-11-20
PCT/US2007/085149 WO2008064185A1 (en) 2006-11-20 2007-11-19 Lock-free state merging in parallelized constraint satisfaction problem solvers

Publications (3)

Publication Number Publication Date
JP2010510591A JP2010510591A (ja) 2010-04-02
JP2010510591A5 true JP2010510591A5 (enExample) 2010-12-02
JP4707760B2 JP4707760B2 (ja) 2011-06-22

Family

ID=39418265

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009537409A Active JP4707760B2 (ja) 2006-11-20 2007-11-19 並列化制約充足問題ソルバにおけるＬｏｃｋ−ｆｒｅｅ状態併合

Country Status (8)

Country Link
US (1) US7543266B2 (enExample)
EP (1) EP2084615B1 (enExample)
JP (1) JP4707760B2 (enExample)
KR (1) KR101432328B1 (enExample)
CN (1) CN101542460B (enExample)
CA (1) CA2668121C (enExample)
IL (1) IL197775A (enExample)
WO (1) WO2008064185A1 (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7987352B2 (en) * 2007-11-30 2011-07-26 Intel Corporation Booting with sub socket partitioning
US20100057647A1 (en) * 2008-09-04 2010-03-04 Microsoft Corporation Accommodating learned clauses in reconfigurable hardware accelerator for boolean satisfiability solver
CN101685408B (zh) * 2008-09-24 2013-10-09 国际商业机器公司 多个线程并行访问共享数据结构的方法及装置
US20100169618A1 (en) * 2008-12-30 2010-07-01 Microsoft Corporation Identifying concurrency control from a sequential proof
US8346704B2 (en) * 2009-05-13 2013-01-01 Microsoft Corporation Controlled constraint sharing in parallel problem solvers
US9031890B2 (en) * 2010-08-04 2015-05-12 Sherwin Han Inverse function method of boolean satisfiability (SAT)
CN102467583B (zh) * 2010-10-29 2014-07-23 国际商业机器公司 追踪不确定信号的方法和装置
US8589327B2 (en) 2011-04-22 2013-11-19 International Business Machines Corporation Efficiently determining boolean satisfiability with lazy constraints
US8413091B2 (en) 2011-04-22 2013-04-02 International Business Machines Corporation Enhancing redundancy removal with early merging
US8874498B2 (en) 2011-09-16 2014-10-28 International Business Machines Corporation Unsupervised, supervised, and reinforced learning via spiking computation
US8738554B2 (en) 2011-09-16 2014-05-27 International Business Machines Corporation Event-driven universal neural network circuit
US8799199B2 (en) * 2011-12-14 2014-08-05 International Business Machines Corporation Universal, online learning in multi-modal perception-action semilattices
US8626684B2 (en) 2011-12-14 2014-01-07 International Business Machines Corporation Multi-modal neural network for universal, online learning
US8676866B2 (en) * 2012-03-19 2014-03-18 Sap Ag Computing canonical hierarchical schemas
WO2014152541A1 (en) 2013-03-15 2014-09-25 Sherwin Han Spatial arithmetic method of sequence alignment
CN105190632B (zh) 2013-04-04 2018-06-05 韩小文 构造非确定性(np)图灵机的多项式方法
US9311429B2 (en) 2013-07-23 2016-04-12 Sap Se Canonical data model for iterative effort reduction in business-to-business schema integration
FI20135946L (fi) * 2013-09-23 2015-03-24 Procomp Solutions Oy Rinnakkainen ratkaisun muodostaminen
US11481468B2 (en) * 2014-06-03 2022-10-25 Qualcomm Technologies, Inc. Systems and methods for solving unrestricted incremental constraint problems
US9418137B2 (en) 2014-08-29 2016-08-16 Sherwin Han Database without structured query language
US9424103B2 (en) * 2014-09-30 2016-08-23 Hong Kong Applied Science and Technology Research Institute Company Limited Adaptive lock for a computing system having multiple runtime environments and multiple processing units
US10540477B2 (en) * 2016-05-02 2020-01-21 Siemens Industry Software Nv Space modeling language for the generation of engineering designs
CN106201988A (zh) * 2016-08-03 2016-12-07 桂林电子科技大学 一种重构高性能目标阵列的方法
KR102820745B1 (ko) * 2018-12-31 2025-06-13 삼성전자주식회사 폴링 시간을 예측하는 뉴럴 네트워크 시스템 및 이를 이용한 뉴럴 네트워크 모델 처리 방법

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4918621A (en) 1986-08-13 1990-04-17 Intellicorp, Inc. Method for representing a directed acyclic graph of worlds using an assumption-based truth maintenance system
JPH0789220B2 (ja) * 1987-05-28 1995-09-27 富士写真フイルム株式会社 版材焼付装置
US5276775A (en) 1990-12-07 1994-01-04 Texas Instruments Inc. System and method for building knowledge-based applications
JPH0785748B2 (ja) * 1991-08-06 1995-09-20 三郎 狩野 ゴルフ場のピンに付設する標示体
US5469367A (en) * 1994-06-06 1995-11-21 University Technologies International Inc. Methodology and apparatus for modular partitioning for the machine design of asynchronous circuits
JPH10275084A (ja) * 1997-03-31 1998-10-13 Toshiba Corp 制約充足問題の解決装置及び解決方法、システム構築装置及び構築方法
US6038392A (en) * 1998-05-27 2000-03-14 Nec Usa, Inc. Implementation of boolean satisfiability with non-chronological backtracking in reconfigurable hardware
US6684359B2 (en) * 2000-11-03 2004-01-27 Verisity Ltd. System and method for test generation with dynamic constraints using static analysis
US7085748B2 (en) * 2001-02-16 2006-08-01 International Business Machines Corporation Hyper-arc consistency in a contraint satisfaction network
US7418369B2 (en) 2001-09-07 2008-08-26 The Trustees Of Princeton University Method and system for efficient implementation of boolean satisfiability
US7203917B2 (en) * 2003-04-07 2007-04-10 Nec Laboratories America, Inc. Efficient distributed SAT and SAT-based distributed bounded model checking
US7089220B2 (en) * 2003-06-24 2006-08-08 Palo Alto Research Center Incorporated Complexity-directed cooperative problem solving
US7171393B2 (en) 2003-07-22 2007-01-30 International Business Machines Corporation Solving constraint satisfaction problems using variable-range hopping
US7194710B2 (en) 2004-03-23 2007-03-20 Fujitsu Limited Scheduling events in a boolean satisfiability (SAT) solver
GB0407260D0 (en) 2004-03-31 2004-05-05 Ibm Accelerated solution of constraint satisfaction problems by partioning of the variable space
US7370296B2 (en) 2004-05-25 2008-05-06 International Business Machines Corporation Modeling language and method for address translation design mechanisms in test generation
JP2008510230A (ja) 2004-08-12 2008-04-03 サンドブリッジ テクノロジーズ インコーポレーテッド 非循環命令パターンの認識の方法

Similar Documents

Publication Publication Date Title
JP2010510591A5 (enExample)
EP2084615B1 (en) Lock-free state merging in parallelized constraint satisfaction problem solvers
Nattaf et al. A hybrid exact method for a scheduling problem with a continuous resource and energy constraints
Kaufman et al. Scaling in critical random Boolean networks
CN113221390B (zh) 一种排产模型的训练方法和装置
Rusinol et al. Multipage document retrieval by textual and visual representations
Zaitsev et al. Solving linear diophantine systems on parallel architectures
Cruz et al. A linear logic programming language for concurrent programming over graph structures
Ahmad et al. Petri net modeling and deadlock analysis of parallel manufacturing processes with shared-resources
Pini et al. Bribery in voting with soft constraints
Meylahn Two-community noisy Kuramoto model
JPWO2019210237A5 (enExample)
CN116596035A (zh) 一种神经网络训练的并行方法
CN103336732A (zh) 一种离散事件系统的复合故障因果链解耦方法
JP6044691B2 (ja) 論理推論システム、計算学習装置および論理推論方法
Stepanov Construction of activation functions for wavelet neural networks
Rushdi et al. Construction of general subsumptive solutions of Boolean equations via complete-sum derivation
Mittermayr et al. Timing analysis of concurrent programs
Szymczak et al. Graph grammar based Petri net controlled direct solver algorithm
Xiao et al. An improved exact algorithm for undirected feedback vertex set
Han et al. State estimation for genetic regulatory networks with time-varying delays and reaction-diffusion terms
Prasad Sistla et al. Parameterized verification of linear networks using automata as invariants
Moghaddam et al. A parallel approach to the fractional time delay model for predicting the spread of COVID-19
JPH03167655A (ja) ニューラルネットワーク
Apt et al. Social network games with obligatory product selection