JP2010501915A - メモリ用モジュールコマンド構造およびメモリシステム - Google Patents

メモリ用モジュールコマンド構造およびメモリシステム Download PDF

Info

Publication number
JP2010501915A
JP2010501915A JP2009524852A JP2009524852A JP2010501915A JP 2010501915 A JP2010501915 A JP 2010501915A JP 2009524852 A JP2009524852 A JP 2009524852A JP 2009524852 A JP2009524852 A JP 2009524852A JP 2010501915 A JP2010501915 A JP 2010501915A
Authority
JP
Japan
Prior art keywords
memory
command
address
identifier
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009524852A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010501915A5 (fr
Inventor
ジン−キ・キム
ハク・ジュン・オー
ホン・ボム・ピョン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Conversant Intellectual Property Management Inc
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Conversant Intellectual Property Management Inc, Mosaid Technologies Inc filed Critical Conversant Intellectual Property Management Inc
Publication of JP2010501915A publication Critical patent/JP2010501915A/ja
Publication of JP2010501915A5 publication Critical patent/JP2010501915A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
JP2009524852A 2006-08-22 2007-08-20 メモリ用モジュールコマンド構造およびメモリシステム Pending JP2010501915A (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US83932906P 2006-08-22 2006-08-22
US90200307P 2007-02-16 2007-02-16
US89270507P 2007-03-02 2007-03-02
PCT/CA2007/001428 WO2008022434A1 (fr) 2006-08-22 2007-08-20 structure de commande modulaire pour une mémoire et un système de mémoire

Publications (2)

Publication Number Publication Date
JP2010501915A true JP2010501915A (ja) 2010-01-21
JP2010501915A5 JP2010501915A5 (fr) 2010-09-24

Family

ID=39106428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009524852A Pending JP2010501915A (ja) 2006-08-22 2007-08-20 メモリ用モジュールコマンド構造およびメモリシステム

Country Status (5)

Country Link
EP (1) EP2074623A4 (fr)
JP (1) JP2010501915A (fr)
KR (2) KR101397229B1 (fr)
TW (1) TW200826104A (fr)
WO (1) WO2008022434A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013525889A (ja) * 2010-04-19 2013-06-20 モサイド・テクノロジーズ・インコーポレーテッド 複数のメモリデバイスを有するシステムの状態表示
JP2015144006A (ja) * 2008-10-14 2015-08-06 コンバーサント・インテレクチュアル・プロパティ・マネジメント・インコーポレイテッドＣｏｎｖｅｒｓａｎｔ Ｉｎｔｅｌｌｅｃｔｕａｌ Ｐｒｏｐｅｒｔｙ Ｍａｎａｇｅｍｅｎｔ Ｉｎｃ． ディスクリートメモリデバイスをシステムに接続するためのブリッジデバイスを有する複合メモリ
JP2016181112A (ja) * 2015-03-24 2016-10-13 株式会社東芝 メモリデバイス、半導体装置および情報処理装置
JP2021068072A (ja) * 2019-10-21 2021-04-30 キオクシア株式会社 メモリシステム及び制御方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7904639B2 (en) 2006-08-22 2011-03-08 Mosaid Technologies Incorporated Modular command structure for memory and memory system
JP5385156B2 (ja) 2007-02-16 2014-01-08 モサイド・テクノロジーズ・インコーポレーテッド 半導体デバイスおよび複数の相互接続デバイスを有するシステムの電力消費を低減するための方法
US8194481B2 (en) 2008-12-18 2012-06-05 Mosaid Technologies Incorporated Semiconductor device with main memory unit and auxiliary memory unit requiring preset operation
CN103559905A (zh) 2008-12-18 2014-02-05 莫塞德技术公司 具有主存储单元和需要预设操作的辅存储单元的半导体设备
US8037235B2 (en) 2008-12-18 2011-10-11 Mosaid Technologies Incorporated Device and method for transferring data to a non-volatile memory device
TWI477966B (zh) 2012-05-31 2015-03-21 Silicon Motion Inc 資料儲存裝置與快閃記憶體操作方法
KR102514388B1 (ko) 2016-03-25 2023-03-28 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
KR102651425B1 (ko) 2016-06-30 2024-03-28 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
US11822793B2 (en) 2022-04-04 2023-11-21 Western Digital Technologies, Inc. Complete and fast protection against CID conflict

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001222472A (ja) * 2000-02-08 2001-08-17 Hitachi Ltd 記憶素子及びそれを用いた記憶装置
JP2005353060A (ja) * 2004-06-11 2005-12-22 Samsung Electronics Co Ltd ハブ、メモリモジュール、及びメモリシステムとこれを通じた読み込み方法及び書き込み方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729683A (en) * 1995-05-18 1998-03-17 Compaq Computer Corporation Programming memory devices through the parallel port of a computer system
US6453365B1 (en) * 1998-02-11 2002-09-17 Globespanvirata, Inc. Direct memory access controller having decode circuit for compact instruction format
US7130958B2 (en) * 2003-12-02 2006-10-31 Super Talent Electronics, Inc. Serial interface to flash-memory chip using PCI-express-like packets and packed data for partial-page writes
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
US20020161941A1 (en) * 2001-04-30 2002-10-31 Sony Corporation And Electronics, Inc System and method for efficiently performing a data transfer operation
US7308524B2 (en) * 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
US7073010B2 (en) * 2003-12-02 2006-07-04 Super Talent Electronics, Inc. USB smart switch with packet re-ordering for interleaving among multiple flash-memory endpoints aggregated as a single virtual USB endpoint
US8375146B2 (en) * 2004-08-09 2013-02-12 SanDisk Technologies, Inc. Ring bus structure and its use in flash memory systems

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001222472A (ja) * 2000-02-08 2001-08-17 Hitachi Ltd 記憶素子及びそれを用いた記憶装置
JP2005353060A (ja) * 2004-06-11 2005-12-22 Samsung Electronics Co Ltd ハブ、メモリモジュール、及びメモリシステムとこれを通じた読み込み方法及び書き込み方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015144006A (ja) * 2008-10-14 2015-08-06 コンバーサント・インテレクチュアル・プロパティ・マネジメント・インコーポレイテッドＣｏｎｖｅｒｓａｎｔ Ｉｎｔｅｌｌｅｃｔｕａｌ Ｐｒｏｐｅｒｔｙ Ｍａｎａｇｅｍｅｎｔ Ｉｎｃ． ディスクリートメモリデバイスをシステムに接続するためのブリッジデバイスを有する複合メモリ
JP2013525889A (ja) * 2010-04-19 2013-06-20 モサイド・テクノロジーズ・インコーポレーテッド 複数のメモリデバイスを有するシステムの状態表示
JP2016181112A (ja) * 2015-03-24 2016-10-13 株式会社東芝 メモリデバイス、半導体装置および情報処理装置
JP2021068072A (ja) * 2019-10-21 2021-04-30 キオクシア株式会社 メモリシステム及び制御方法
JP7458740B2 (ja) 2019-10-21 2024-04-01 キオクシア株式会社 メモリシステム及び制御方法

Also Published As

Publication number Publication date
EP2074623A1 (fr) 2009-07-01
WO2008022434A1 (fr) 2008-02-28
KR20130136004A (ko) 2013-12-11
KR101514171B1 (ko) 2015-04-21
KR20090046944A (ko) 2009-05-11
TW200826104A (en) 2008-06-16
EP2074623A4 (fr) 2010-01-06
KR101397229B1 (ko) 2014-05-20

Similar Documents

Publication Publication Date Title
JP2010501915A (ja) メモリ用モジュールコマンド構造およびメモリシステム
US7904639B2 (en) Modular command structure for memory and memory system
US11151027B2 (en) Methods and apparatuses for requesting ready status information from a memory
US11023167B2 (en) Methods and apparatuses for executing a plurality of queued tasks in a memory
EP2487794A2 (fr) Structure de commande modulaire pour mémoire et système de mémoire
US5381538A (en) DMA controller including a FIFO register and a residual register for data buffering and having different operating modes
US5548786A (en) Dynamic bus sizing of DMA transfers
US6324597B2 (en) Host controller interface descriptor fetching unit
US10552047B2 (en) Memory system
US20040054864A1 (en) Memory controller
KR100634436B1 (ko) 멀티 칩 시스템 및 그것의 부트코드 페치 방법
JP2013251045A (ja) 複数の独立したシリアルリンクメモリ
EP3640944A1 (fr) Lecture continue de page non séquentielle
US10990293B2 (en) Extensible storage system and method
US9304952B2 (en) Memory control device, storage device, and memory control method
KR20200123260A (ko) 캐시 및 다중 독립 어레이를 갖는 메모리용 인터페이스
CN101421705B (zh) 具有高储存容量的多媒体卡
WO1991001021A1 (fr) Procede et circuit de selection de sequences d'elements programmables
US8402233B2 (en) Method and apparatus for high throughput mass storage device interface in a microprocessor for handheld systems
US20130033945A1 (en) System and method for interfacing burst mode devices and page mode devices
KR0174211B1 (ko) 병렬처리 프로그램형 제어기용 데이터 액서스 장치
KR20030049448A (ko) 메모리 버스 확장 장치 및 방법
JPH05257698A (ja) 電子計算機

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100804

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100804

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120830

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120904

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20121130

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20121207

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130205

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130305

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20130621

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20140926

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20141003

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20150129