JP2010287812A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve current characteristics of a MOS field effect transistor. <P>SOLUTION: A semiconductor device has a compressive stress film 300 formed over a semiconductor substrate where a P-channel MOS field effect transistor is formed to cover the P-channel MOS field effect transistor where the compressive stress film 300 is formed with a gap 310 along a channel direction of the P-channel MOS field effect transistor, and the gap 310 divides a part of the compressive stress film 300 which covers a gate electrode 200 of the P-channel MOS field effect transistor in a direction orthogonal to the channel direction. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a MOS (Metal-Oxide-Semiconductor) field effect transistor and a manufacturing method thereof.

  As a configuration for improving the current characteristics of the MOS field effect transistor, it is known to form a stress film that generates stress in the channel region of the MOS field effect transistor so as to cover the MOS field effect transistor on the semiconductor substrate.

  In particular, regarding a P-channel MOS field effect transistor, it is known that a current characteristic is improved by using a compressive stress film as a stress film. Furthermore, it is known that an N channel type MOS field effect transistor improves current characteristics by using a tensile stress film as a stress film.

  Also known is a technique for improving the current characteristics of a MOS field effect transistor by devising a way of generating a stress in a channel region by a stress film.

JP 2004-87640 A JP 2007-27359 A JP 2008-218574 A

  However, when the MOS field effect transistor is further miniaturized, the above-described background art may not be able to sufficiently improve the current characteristics of the MOS field effect transistor.

  This problem occurs in each of the P-channel MOS field effect transistor and the N-channel MOS field effect transistor. In one aspect of the present invention, attention is paid to the problem of the P-channel MOS field effect transistor. Yes.

  According to the semiconductor device of one aspect of the present invention, the compressive stress film is formed on the semiconductor substrate on which the P-channel MOS field effect transistor is formed so as to cover the P-channel MOS field effect transistor. The compressive stress film is provided with a gap along the channel direction of the P-channel MOS field effect transistor, and the gap covers the portion of the compressive stress film covering the gate electrode of the P-channel MOS field effect transistor. It is divided in a direction perpendicular to the channel direction.

  In the disclosed semiconductor device, among the compressive stresses generated in the channel region of the P-channel MOS field effect transistor, the compressive stress in the direction perpendicular to the channel direction is selectively reduced, so that the P-channel MOS field effect transistor The current characteristics can be improved.

1 is a top view of a semiconductor device according to a first embodiment. FIG. 2 is a top view of the compressive stress film in FIG. 1. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. It is a calculation result of compressive stress explaining a 1st embodiment. It is a top view explaining the modification of the semiconductor device concerning a 1st embodiment. FIG. 7 is a top view of the compressive stress film in FIG. 6. It is a top view of the semiconductor device concerning a 2nd embodiment. FIG. 9 is a top view of the compressive stress film in FIG. 8. It is sectional drawing of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing of the semiconductor device which concerns on 2nd Embodiment. It is a top view explaining the modification 1 of the semiconductor device concerning a 2nd embodiment. FIG. 13 is a top view of the compressive stress film in FIG. 12. It is a top view explaining the modification 2 of the semiconductor device concerning a 2nd embodiment. FIG. 15 is a top view of the compressive stress film in FIG. 14. It is a top view explaining the modification 3 of the semiconductor device concerning a 2nd embodiment. FIG. 17 is a top view of the compressive stress film in FIG. 16. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 3rd Embodiment.

First, a first embodiment of a semiconductor device according to the present invention will be described with reference to FIGS.
1 is a top view of an example of the semiconductor device according to the first embodiment, FIG. 3 is a cross-sectional view corresponding to the dotted line AA of the semiconductor device of FIG. 1, and FIG. 4 is the semiconductor device of FIG. It is sectional drawing corresponding to the dashed-dotted line BB.

  As shown in FIGS. 1, 3, and 4, the semiconductor device according to the first embodiment includes a semiconductor substrate 100 including an element formation region 110 and an element isolation region 120 that surrounds the element formation region 110.

For example, a silicon substrate is used as the semiconductor substrate 100, and the element isolation region 120 is formed using an insulating material such as a silicon oxide film (SiO ₂ ).
Furthermore, the semiconductor device according to the first embodiment includes a source region 111, a drain region 112, a channel region 113 formed in the element formation region 110, and a gate formed above the semiconductor substrate 100 with a gate insulating film 130 interposed therebetween. The electrode 200 is provided. With these configurations, a P-channel MOS field effect transistor is configured.

The channel region 113 is located between the source region 111 and the drain region 112, and the gate electrode 200 is formed above the channel region 113.
An n-type well is formed in the element formation region 110, and p-type impurity ions are implanted into the source region 111 and the drain region 112. For example, a polysilicon film is used for the gate electrode 200. For example, a silicon oxide film (SiO ₂ ) is used for the gate insulating film 130. A sidewall insulating film 210 is formed on the sidewall of the gate electrode 200.

  The gate electrode 200 extends continuously from one side of the element formation region 110 toward the opposite side, and both ends in the extending direction of the gate electrode 200 are positioned on the element isolation region 120, respectively.

  For example, the P-channel MOS field effect transistor is arranged such that the channel direction L connecting the source region 111 and the drain region 112 is along the <110> axis of the semiconductor substrate 100.

Here, the channel direction L is a direction perpendicular to the extending direction of the gate electrode 200 and may be referred to as a gate length direction.
Furthermore, the semiconductor device according to the first embodiment includes a compressive stress film 300 formed above the semiconductor substrate 100 so as to cover the P-channel MOS field effect transistor.

The compressive stress film has a property of generating a compressive stress in the channel region of the MOS field effect transistor by covering the MOS field effect transistor.
In the first embodiment, a compressive stress is generated in the channel region 113 of the P-channel MOS field effect transistor by the compressive stress film 300, thereby increasing the current amount of the P-channel MOS field effect transistor. .

For example, a silicon nitride film (SiN) is used for the compressive stress film 300.
The compressive stress film 300 is formed on the element formation region 110 and the element isolation region 120 so as to cover the gate electrode 200.

  Furthermore, in the first embodiment, the compressive stress film 300 is provided with the gap portion 310 along the channel direction L, and the portion of the compressive stress film 300 covering the gate electrode 200 by the gap portion 310 is perpendicular to the channel direction L. It is divided in the direction that intersects.

FIG. 2 is a view showing the upper surface of the compressive stress film 300 of FIG. Here, the direction perpendicular to the channel direction L is the extending direction of the gate electrode 200.
That is, the gap portion 310 is provided so as to be positioned on an intermediate region in the extending direction of the gate electrode 200, and the compressive stress film 300 divided in the extending direction of the gate electrode 200 by the gap portion 310 is respectively connected to the gate electrode 200. 200 is covered. Here, the intermediate region of the gate electrode 200 is a region sandwiched between both ends in the extending direction of the gate electrode 200.

  Further, the gap 310 is located above the element formation region 110. The gap 310 is provided so as to continue from one end in the channel direction L of the element forming region 110 to the other opposite end, and both ends of the gap 310 in the channel direction L are respectively located above the element isolation region 120. Yes.

Here, the compressive stress film 300 is continuously formed so as to surround the gap 310.
In the first embodiment, as described above, the compressive stress film 300 is provided with the gap portion 310 along the channel direction L, and the portion of the compressive stress film 300 covering the gate electrode 200 by the gap portion 310 is the channel direction L. It is divided in the direction that intersects perpendicularly. According to this configuration, the compressive stress generated in the channel region 113 by the compressive stress film 300 can be selectively reduced in the direction perpendicular to the channel direction L.

  That is, in the first embodiment, among the compressive stresses generated in the channel region 113 by the compressive stress film 300, the compressive stress in the direction perpendicular to the channel direction L is reduced while maintaining the compressive stress generated in the channel direction L. It becomes possible to do.

  Here, FIG. 5 shows the current increase rate of the current flowing in the <110> axis direction, the compressive stress generated in the <110> axis direction, and the direction perpendicular to the <110> axis direction in the P-type semiconductor substrate. It is the calculation result which showed the relationship with the compressive stress to do.

  Each value arranged in the vertical direction within the frame of reference numeral 510 in FIG. 5 indicates a compressive stress (Mpa) generated in the <110> axial direction, and the value increases from top to bottom. From 0.0 Mpa to 140.0 Mpa, 20.0 Mpa interval values are listed.

  Each value arranged in the horizontal direction in the frame indicated by reference numeral 520 in FIG. 5 indicates a compressive stress (Mpa) generated in a direction perpendicular to the <110> axial direction, and the value increases from left to right. Yes. Values of 20.0 Mpa interval are described from -140.0 Mpa to 140.0 Mpa.

  Each numerical value in the frame indicated by reference numeral 530 in FIG. 5 indicates an increase in current flowing in the <110> axial direction when a predetermined compressive stress is generated in the <110> axial direction and the direction perpendicular to the <110> axial direction. The rate (%) is shown. The rate of increase is based on the current value when the compressive stress generated in the <110> axial direction and the direction perpendicular to the <110> axial direction is both 0.0 Mpa.

  As is clear from this calculation result, as the compressive stress in the <110> axial direction increases, the current flowing in the <110> direction increases and the compressive stress in the direction perpendicular to the <110> axial direction increases. Accordingly, the current flowing in the <110> direction decreases.

  For example, if the stress generated in the direction perpendicular to the <110> axis direction is 0.0 Mpa, the current increases as the stress generated in the <110> axis direction increases to 20.0 Mpa, 40.0 Mpa, and 60.0 Mpa. The increase rate increases to 1.436, 2.871, 4.307%.

  On the other hand, when the stress generated in the <110> axial direction is 0.0 Mpa, the current generated as the stress generated in the direction perpendicular to the <110> axial direction increases to 20.0 Mpa, 40.0 Mpa, and 60.0 Mpa. The increase rate decreases to -1.326, -2.653, and -3.979%.

  In the first embodiment, the P-channel MOS field effect transistor is arranged so that the channel direction L is along the <110> axis of the semiconductor substrate 100, for example. In that case, the relationship between the current flowing through the channel region 113 in the channel direction L and the compressive stress generated in the channel region 113 is considered to be the same as the above calculation result.

  That is, for the P-channel MOS field effect transistor, the amount of current increases with an increase in the compressive stress in the channel direction L among the compressive stresses generated in the channel region 113, but the compressive stress in the direction perpendicular to the channel direction L It is considered that the amount of current decreases with an increase in. In other words, it is considered that the amount of current increases as the compressive stress in the direction perpendicular to the channel direction L generated in the channel region 113 decreases.

  According to the first embodiment, as described above, among the compressive stresses generated in the channel region 113, the compressive stress in the direction perpendicular to the channel direction L can be selectively reduced. Therefore, in the first embodiment, the amount of current of the P-channel MOS field effect transistor can be increased. As a result, the current characteristics of the P-channel MOS field effect transistor can be improved.

  Furthermore, in the first embodiment, the current characteristics of the P-channel MOS field effect transistor can be realized by devising the position of the gap 310 provided in the compressive stress film 300. Therefore, in the first embodiment, it is possible to provide a semiconductor device with improved characteristics at low cost without using a new material or a complicated configuration.

  Furthermore, in the first embodiment, the tensile stress film 400 is formed above the semiconductor substrate 100 so as to cover the P-channel MOS field effect transistor on which the compressive stress film 300 is formed.

  Specifically, an interlayer insulating film 350 is formed above the semiconductor substrate 100 so as to cover the P-channel MOS field effect transistor on which the compressive stress film 300 is formed, and a tensile stress film 400 is formed above the interlayer insulating film 350. Has been.

For example, a silicon nitride film (SiN) is used for the tensile stress film 400.
The tensile stress film 400 is formed above the element formation region 110 and above the element isolation region 120 and covers the source region 111 and the drain region 112.

Furthermore, in the first embodiment, the tensile stress film 400 is provided with a gap 410 in a direction perpendicular to the channel direction L.
The gate electrode 200 is exposed from the tensile stress film 400 by the gap 410. The tensile stress film 400 is divided in the channel direction L by the gap 410. One divided tensile stress film 401 is located on the source region 111, and the other divided tensile stress film 402 is located on the drain region 112. The divided tensile stress films 401 and 402 are arranged separately from the gate electrode 200.

Here, the case where both end portions of the element formation region 110 in the channel direction L are exposed from the tensile stress film 400 is illustrated.
In the first embodiment, as described above, the tensile stress film 400 is formed above the semiconductor substrate 100 so as to cover the P-channel MOS field effect transistor, and the tensile stress film 400 is perpendicular to the channel direction L. A gap 410 is provided. According to this configuration, it is possible to selectively generate a tensile stress in the element forming region 110 in a direction perpendicular to the channel direction L. Alternatively, the compressive stress generated in the element formation region 110 by the compressive stress film 300 can be selectively reduced in the direction perpendicular to the channel direction L.

For this reason, in the first embodiment, among the compressive stresses generated in the channel region 113, the compressive stress in the direction perpendicular to the channel direction L can be selectively reduced further.
As a result, the current amount of the P-channel MOS field effect transistor can be increased, and the current characteristics of the P-channel MOS field effect transistor can be further improved.

  Here, if the tensile stress film 400 can sufficiently reduce the compressive stress generated in the channel region 113 in the direction perpendicular to the channel direction L, the gap 310 is not necessarily provided in the compressive stress film 300. There is no need to provide it.

FIG. 6 is a top view of a modification of the semiconductor device of the first embodiment, and FIG. 7 is a view showing the top surface of the compressive stress film 300 of FIG.
In the modification, the compressive stress film 300 is divided by the gap portion 310 in a direction perpendicular to the channel direction L.

That is, each compressive stress film 300 divided by the gap portion 310 in the direction perpendicular to the channel direction L is formed as an independent film.
Even with the configuration as in the modified example, it is possible to effectively generate compressive stress in the channel region 113 and improve the current characteristics of the P-channel MOS field effect transistor.

Next, a second embodiment of the semiconductor device will be described with reference to FIGS.
8 is a top view of an example of the semiconductor device according to the second embodiment, FIG. 10 is a cross-sectional view corresponding to the dotted line AA of the semiconductor device of FIG. 8, and FIG. 11 is the semiconductor device of FIG. It is sectional drawing corresponding to the dashed-dotted line BB.

  As shown in FIGS. 8, 10, and 11, the semiconductor device according to the second embodiment includes an element isolation region 120, a first element formation region 110 a that is separated by the element isolation region 120, and a second one. The semiconductor substrate 100 is provided with the element formation region 110b.

  The semiconductor device according to the second embodiment includes a first P-channel MOS field effect transistor formed in the first element formation region 110a and a second P-channel type formed in the second element formation region 110b. And a MOS field effect transistor.

  A source region 111, a drain region 112, and a channel region 113 are provided in each of the first element formation region 110a and the second element formation region 110b, and a gate insulating film 130 is interposed above each channel region 113. A gate electrode 200 is formed.

  The first P-channel MOS field effect transistor and the second P-channel MOS field effect transistor are arranged so that the channel directions L are the same. Further, the first P-channel MOS field effect transistor and the second P-channel MOS field effect transistor are arranged such that each channel direction L is, for example, along the <110> axis of the semiconductor substrate 100. .

  Here, the first element formation region 110a and the second element formation region 110b intersect perpendicularly to the channel direction L of the first P-channel MOS field effect transistor and the second P-channel MOS field effect transistor. Adjacent in the direction.

In the second embodiment, the first P-channel MOS field effect transistor and the second P-channel MOS field effect transistor have a common gate electrode 200.
The gate electrode 200 is continuously formed from the first element formation region 110a through the element isolation region 120 to the second element formation region 110b.

  The semiconductor device according to the second embodiment has a compressive stress film 300 formed above the semiconductor substrate 100 so as to cover the first and second P-channel MOS field effect transistors.

  The compressive stress film 300 is formed above the first element formation region 110a, above the second element formation region 110b, and above the element isolation region 120 so as to cover the gate electrode 200.

Furthermore, in the second embodiment, the compressive stress film 300 is provided with a gap 310 along the channel direction L of the first and second P-channel MOS field effect transistors.
FIG. 9 is a view showing the upper surface of the compressive stress film 300 of FIG.

A portion of the compressive stress film 300 covering the gate electrode 200 is divided by the gap 310 in a direction perpendicular to the channel direction L.
The gap 310 is located above the element isolation region 120 located between the first element formation region 110a and the second element formation region 110b.

  Both end portions of the gap portion 310 in the channel direction L are positioned so as to be further away from the gate electrode 200 in the channel direction L than the end portions of the first and second element formation regions 110a and 110b in the channel direction L. ing.

Here, the compressive stress film 300 is continuously formed so as to surround the gap 310.
In the second embodiment, as described above, the compressive stress film 300 is provided with the gap portion 310 along the channel direction L, and the portion of the compressive stress film 300 that covers the gate electrode 200 by the gap portion 310 is the channel direction L. It is divided in the direction that intersects perpendicularly. According to this configuration, the compressive stress generated in the channel regions 113 of the first and second P-channel MOS field effect transistors by the compressive stress film 300 is selected in the direction perpendicular to the channel direction L. Can be reduced.

  As described in the first embodiment, in the P-channel MOS field effect transistor, the amount of current increases as the stress in the channel direction increases among the compressive stresses generated in the channel region, but in the direction perpendicular to the channel direction. It is considered that the amount of current decreases as the stress increases. In other words, it is considered that the amount of current increases as the compressive stress in the direction perpendicular to the channel direction generated in the channel region decreases.

  Thereby, in the second embodiment, in a semiconductor device having two P-channel MOS field effect transistors having a common gate electrode 200, the current characteristics of each P-channel MOS field effect transistor can be improved. .

  Furthermore, in the second embodiment, the tensile stress film 400 is formed above the semiconductor substrate 100 so as to cover the first and second P-channel MOS field effect transistors on which the compressive stress film 300 is formed.

  Specifically, an interlayer insulating film 350 is formed above the semiconductor substrate 100 so as to cover the first and second P-channel MOS field effect transistors on which the compressive stress film 300 is formed, and the tensile insulating film 350 is pulled over the interlayer insulating film 350. A stress film 400 is formed.

  The tensile stress film 400 is formed on the first and second element formation regions 110a and 110b and above the element isolation region 120, and each of the source regions 111 and each of the first and second P-channel MOS field effect transistors is formed. The drain region 112 is covered above.

Furthermore, in the second embodiment, the tensile stress film 400 is provided with a gap 410 in a direction perpendicular to the channel direction L.
The gate electrode 200 is exposed from the tensile stress film 400 by the gap 410, and the tensile stress film 400 is further divided in the channel direction L. One divided tensile stress film 401 is located on the source region 111, and the other divided tensile stress film 402 is located on the drain region 112. The divided tensile stress films 401 and 402 are arranged separately from the gate electrode 200.

  Here, the case where both end portions in the channel direction L of the first and second element formation regions 110a and 110b are exposed from the tensile stress film 400 is illustrated.

  In the second embodiment, as described above, the tensile stress film 400 is formed above the semiconductor substrate 100 so as to cover the first and second P-channel MOS field effect transistors, and the channel stress L is formed in the tensile stress film 400. A gap portion 410 is provided in a direction perpendicular to each other. According to this configuration, it is possible to selectively generate a tensile stress in a direction perpendicular to the channel direction L in each of the element formation regions 110a and 110b of the first and second P-channel MOS field effect transistors. . Alternatively, among the compressive stresses generated by the compressive stress film 300 in the element forming regions 110a and 110b, the compressive stress in the direction perpendicular to the channel direction L can be selectively reduced.

  Therefore, in the second embodiment, among the compressive stresses generated in the channel regions 113 of the first and second P-channel MOS field effect transistors, the compressive stress in the direction perpendicular to the channel direction L is selectively selected. Further reduction is possible.

  This makes it possible to increase the current amounts of the first and second P-channel MOS field effect transistors, and to further improve the current characteristics of the first and second P-channel MOS field effect transistors. It becomes.

  Here, if the compressive stress in the direction perpendicular to the channel direction L generated in each channel region 113 of each P-channel MOS field effect transistor can be sufficiently reduced by the tensile stress film 400, the compressive stress film There is no need to provide the gap 310 in 300.

FIG. 12 is a top view of Modification 1 of the semiconductor device of the second embodiment, and FIG. 13 is a view showing the top surface of the compressive stress film 300 of FIG.
In the first modification, the compressive stress film 300 is divided by the gap portion 310 in a direction perpendicular to the channel direction L.

That is, each compressive stress film 300 divided by the gap portion 310 in the direction perpendicular to the channel direction L is formed as an independent film.
FIG. 14 is a top view of Modification 2 of the semiconductor device of the second embodiment, and FIG. 15 is a view showing the top surface of the compressive stress film 300 of FIG.

In the second modification, a plurality of gap portions 310 are provided in the compressive stress film 300. Each gap 310 is provided on each of the first and second element formation regions 110a and 110b.
Furthermore, in the second modification, the opposing end portions of the first and second element formation regions 110 a and 110 b are exposed from the compressive stress film 300 by the gap portions 310 individually provided in the compressive stress film 300. is doing.

Furthermore, in Modification 2, both end portions in the extending direction of the gate electrode 200 are exposed from the compressive stress film 300.
FIG. 16 is a top view of Modification 3 of the semiconductor device of the second embodiment, and FIG. 17 is a view showing the top surface of the compressive stress film 300 of FIG.

  In the third modification, a plurality of gaps 310 are provided in the compressive stress film 300. Each gap 310 is provided above the first and second element formation regions 110a and 110b.

  Further, in the third modification, the opposing end portions of the first and second element formation regions 110 a and 110 b are respectively separated from the compressive stress film 300 by the common gap portion 310 provided in the compressive stress film 300. Exposed.

Further, in Modification 3, both end portions in the extending direction of the gate electrode 200 are exposed from the compressive stress film 300.
Even with the configurations as in the first to third modifications, it is possible to effectively generate compressive stress in the channel region 113 and improve the current characteristics of the P-channel MOS field effect transistor.

Next, a method for manufacturing a semiconductor device according to the first and second embodiments will be described as a third embodiment.
18 to 21 are cross-sectional views of the semiconductor device illustrating the third embodiment.

  First, as shown in FIG. 18A, a semiconductor substrate including a source region 111, a drain region 112, and a channel region 113, and a gate electrode 200 formed on the channel region 113 with a gate insulating film 130 interposed therebetween. Prepare 100.

  Here, the source region 111, the drain region 112, the channel region 113, the gate insulating film 130, and the gate electrode 200 constitute a P-channel MOS field effect transistor.

Next, as shown in FIG. 18B, a compressive stress film 300 is formed over the semiconductor substrate 100 so as to cover the P-channel MOS field effect transistor.
In the third embodiment, for example, a silicon nitride film (SiN) is used as the compressive stress film 300, and the compressive stress film 300 is formed by a plasma CVD (plasma-enhanced chemical vapor deposition) method. The compressive stress film 300 can be formed by increasing / decreasing any of the deposition parameters such as the power of the high-frequency power for plasma, the pressure of the deposition atmosphere, and the flow rate of the deposition gas. Here, the thickness of the formed compressive stress film 300 is 50 nm to 100 nm.

  Next, a photoresist mask is formed above the compressive stress film 300, and the compressive stress film 300 is etched using the photoresist mask, so that a gap is formed in the compressive stress film 300 as shown in FIG. A portion 310 is provided. For the etching, a selective etching method is used.

  Next, as shown in FIG. 19B, an interlayer insulating film 350 is formed above the semiconductor substrate 100 on which the compressive stress film 300 is formed. For example, an oxide film is used for the interlayer insulating film 350.

Next, as shown in FIG. 20A, a tensile stress film 400 is formed above the semiconductor substrate 100 on which the interlayer insulating film 350 is formed.
In the third embodiment, for example, a silicon nitride film (SiN) is used as the tensile stress film 400, and the tensile stress film 400 is formed by a plasma CVD (plasma-enhanced chemical vapor deposition) method. The tensile stress film 400 can be formed by increasing / decreasing any of the film formation parameters such as the power of the high frequency power for plasma, the pressure of the film formation atmosphere, and the flow rate of the film formation gas. Here, the film thickness of the formed tensile stress film 400 is 50 nm to 100 nm.

  Next, a photoresist mask is formed above the tensile stress film 400, and the tensile stress film 400 is etched using the photoresist mask, so that a gap is formed in the tensile stress film 400 as shown in FIG. A portion 410 is provided. For the etching, a selective etching method is used.

  Next, as shown in FIG. 21, an interlayer insulating film 360 is formed above the semiconductor substrate 100 on which the tensile stress film 400 is formed. For example, an oxide film is used for the interlayer insulating film 360.

Regarding the embodiment described above, the following additional notes are further disclosed.
(Appendix 1) a semiconductor substrate;
A P-channel MOS electric field comprising a source region and a drain region formed on the semiconductor substrate, a channel region located between the source region and the drain region, and a gate electrode formed above the channel region. An effect transistor;
A compressive stress film formed over the semiconductor substrate so as to cover the P-channel MOS field effect transistor;
The compressive stress film is provided with a gap along the channel direction connecting the source region and the drain region,
A portion of the compressive stress film covering the gate electrode by the gap is divided in a direction perpendicular to the channel direction.

(Supplementary Note 2) The semiconductor substrate includes an element isolation region and an element formation region surrounded by the element isolation region.
The P-channel MOS field effect transistor is formed in the element formation region,
The semiconductor device according to appendix 1, wherein the gap provided in the compressive stress film is located above the element formation region.

(Supplementary note 3) The semiconductor device according to supplementary note 2, wherein the gap portion is provided from one end to the other end in the channel direction of the element formation region.
(Supplementary Note 4) The semiconductor substrate includes an element isolation region, and a first element formation region and a second element formation region which are separated by the element isolation region and are adjacent to each other in a direction perpendicular to the channel direction.
The P-channel MOS field effect transistor includes a first P-channel MOS field effect transistor portion formed in the first element formation region and a second P-channel formed in the second element formation region. Type MOS field effect transistor section,
The semiconductor device according to appendix 1, wherein the gate electrode is continuously formed from the first element formation region to the second element formation region through the element isolation region.

  (Supplementary note 5) The supplementary note 4, wherein the gap is located above the element isolation region located between the first element formation region and the second element formation region. Semiconductor device.

  (Additional remark 6) The said P channel type MOS field effect transistor is arrange | positioned so that the said channel direction may follow the <110> axis | shaft of the said semiconductor substrate, The additional description 1-5 characterized by the above-mentioned. Semiconductor device.

(Appendix 7) A tensile stress film is formed over the semiconductor substrate so as to cover the P-channel MOS field effect transistor on which the compressive stress film is formed,
7. The semiconductor device according to any one of appendices 1 to 6, wherein the tensile stress film is provided with a gap portion in a direction perpendicular to the channel direction.

(Supplementary note 8) The semiconductor device according to supplementary note 7, wherein the tensile stress film is disposed above the source region and above the drain region.
(Additional remark 9) The said gap | interval part provided in the said tensile stress film | membrane is located above the said gate electrode, The semiconductor device of Additional remark 7 or 8 characterized by the above-mentioned.

(Supplementary Note 10) a semiconductor substrate;
A P-channel MOS electric field comprising a source region and a drain region formed on the semiconductor substrate, a channel region located between the source region and the drain region, and a gate electrode formed above the channel region. An effect transistor;
A compressive stress film formed over the semiconductor substrate so as to cover the P-channel MOS field effect transistor;
A tensile stress film is formed over the semiconductor substrate so as to cover the P-channel MOS field effect transistor on which the compressive stress film is formed;
The semiconductor device according to claim 1, wherein a gap is provided in the tensile stress film in a direction perpendicular to a channel direction connecting the source region and the drain region.

(Additional remark 11) The process which forms a source region and a drain region in a semiconductor substrate, forms a gate electrode above the region between the source region and the drain region, and forms a P-channel MOS field effect transistor When,
Forming a compressive stress film over the semiconductor substrate so as to cover the P-channel MOS field effect transistor;
Providing the compressive stress film with a gap along the channel direction connecting the source region and the drain region,
A method of manufacturing a semiconductor device, wherein a portion of the compressive stress film covering the gate electrode is divided by the gap in a direction perpendicular to the channel direction.

(Appendix 12) A step of forming a tensile stress film above the semiconductor substrate so as to cover the P-channel MOS field effect transistor on which the compressive stress film is formed;
12. The method of manufacturing a semiconductor device according to claim 11, further comprising a step of providing a gap in the tensile stress film in a direction perpendicular to the channel direction.

  (Supplementary note 13) The method for manufacturing a semiconductor device according to supplementary note 11 or 12, wherein the P-channel MOS field effect transistor is arranged so that the channel direction is along a <110> axis of the semiconductor substrate.

DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 110, 110a, 110b Element formation area 111 Source area 112 Drain area 113 Channel area 120 Element isolation area 130 Gate insulating film 200 Gate electrode 210 Side wall insulating film 300 Compressive stress film 310, 410 Interspace part 350, 360 Interlayer insulating film 400 Tensile stress film L channel direction

Claims (6)

A semiconductor substrate;
A P-channel MOS electric field comprising a source region and a drain region formed in the semiconductor substrate, a channel region located between the source region and the drain region, and a gate electrode formed above the channel region. An effect transistor;
A compressive stress film formed over the semiconductor substrate so as to cover the P-channel MOS field effect transistor;
The compressive stress film is provided with a gap along the channel direction connecting the source region and the drain region,
A portion of the compressive stress film covering the gate electrode by the gap is divided in a direction perpendicular to the channel direction. The semiconductor substrate includes an element isolation region and an element formation region surrounded by the element isolation region,
The P-channel MOS field effect transistor is formed in the element formation region,
The semiconductor device according to claim 1, wherein the gap provided in the compressive stress film is located above the element formation region. A tensile stress film is formed over the semiconductor substrate so as to cover the P-channel MOS field effect transistor on which the compressive stress film is formed;
The semiconductor device according to claim 1, wherein a gap is provided in the tensile stress film in a direction perpendicular to the channel direction.   The semiconductor device according to claim 3, wherein the tensile stress film is disposed above the source region and above the drain region. Forming a source region and a drain region in a semiconductor substrate, forming a gate electrode above a region between the source region and the drain region, and forming a P-channel MOS field effect transistor;
Forming a compressive stress film over the semiconductor substrate so as to cover the P-channel MOS field effect transistor;
Providing the compressive stress film with a gap along the channel direction connecting the source region and the drain region,
A method of manufacturing a semiconductor device, wherein a portion of the compressive stress film covering the gate electrode is divided by the gap in a direction perpendicular to the channel direction. Forming a tensile stress film above the semiconductor substrate so as to cover the P-channel MOS field effect transistor on which the compressive stress film is formed;
The method of manufacturing a semiconductor device according to claim 5, further comprising a step of providing a gap in the tensile stress film in a direction perpendicular to the channel direction.

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