JP2010281905A - Electro-optical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability and a yield of an electro-optical device by avoiding a break caused by a crack of a substrate. <P>SOLUTION: The electro-optical device has: a substrate (S1); an insulating layer (12) disposed on the substrate (S1) and having a pixel region (A1) and a peripheral region (A2) disposed on an outer periphery of the pixel region (A1); an electro-optic element disposed on the pixel region; drive circuits (DC1, DC2) disposed on the peripheral region (A2) and driving the electro-optic element; external terminals (P) disposed on the peripheral region; and lead-out wires (L1, L2) which are wires disposed on the peripheral region and electrically connecting the external terminals and the drive circuits, wherein at least a portion (L1) of the lead-out wires is disposed between the substrate (S1) and the insulating layer (12). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electro-optical device, and more particularly, to an electro-optical device having a lead wiring in a peripheral region of a substrate.

  An electro-optical device represented by a liquid crystal display (LCD) or the like has a configuration in which an electro-optical material such as liquid crystal is disposed between an active matrix substrate and a counter substrate.

A pixel region is disposed at the center of the active matrix substrate, and a drive circuit and wiring for driving the pixels are disposed around the pixel region.
For example, Patent Document 1 below discloses an electro-optical device having a connection wiring 34 c on the outer periphery of a substrate 20.

JP 2005-215616 A

  The inventor is conducting research and development related to an electro-optical device typified by a liquid crystal display and the like, and is considering improving the device characteristics. In the device in which the wiring is arranged on the outer peripheral portion of the substrate as described above, a physical impact may be applied to the substrate due to a handling mistake or the like during the manufacturing process or the mounting process of the device. Such an impact is often applied to the end portion of the substrate (device), thereby causing chipping or cracking of the substrate. At this time, the wiring arranged around the substrate is torn and causes display failure. Such a crack generated at the end of the device is called chipping failure, which leads to a decrease in manufacturing yield, and also causes a decrease in reliability when the actual device is used.

  Therefore, a specific aspect of the present invention aims to provide a device configuration that can improve the reliability and yield of an electro-optical device.

  One aspect of the electro-optical device according to the invention includes a substrate, an insulating layer that is disposed on the substrate and includes a pixel region and a peripheral region that is located on an outer periphery of the pixel region, and the pixel region. The electro-optic element, the drive circuit arranged in the peripheral area and driving the electro-optic element, the external terminal arranged in the peripheral area, the external terminal arranged in the peripheral area, and the drive circuit And at least a part of the lead wiring is disposed between the substrate and the insulating layer. The lead wiring is used for signal transmission, power supply and the like.

  In another embodiment, the substrate includes a substrate, a pixel region, an insulating layer having a peripheral region located on an outer periphery of the pixel region, a plurality of electro-optic elements arranged in the pixel region, and the peripheral First and second driving circuits arranged in the region and driving the plurality of electro-optic elements, a plurality of first external terminals arranged in the peripheral region, and a plurality of first circuits arranged in the peripheral region. Two external terminals, a first lead wiring that is disposed in the peripheral region and electrically connects the plurality of first external terminals and the first drive circuit, and the peripheral A second wiring that is disposed in a region and is disposed between the substrate and the insulating layer and electrically connects the plurality of second external terminals and the second drive circuit. And at least a part of the first lead wiring is the substrate. Is disposed between the insulating layer, at least a portion of said second lead wire is disposed between the substrate and the insulating layer, characterized in that.

  According to this configuration, the peripheral circuit wiring is embedded in the substrate. Because the lead-out wiring in the peripheral area where chipping defects occur frequently is embedded inside the board, even if a physical impact is applied to the peripheral area of the board and the board is chipped or cracked, it is difficult to reach the internal wiring layer Thus, the reliability of the apparatus can be improved. In addition, the manufacturing yield of the device can be improved.

  For example, in plan view, the distance between the lead-out wiring and the pixel region is larger than the distance between the lead-out wiring and the edge of the substrate. Alternatively, the lead-out wiring is embedded on the substrate end side in the peripheral region of the substrate. As a result, disconnection of the lead-out wiring is less likely to occur, particularly in the substrate edge region where chipping defects occur frequently. Further, by using the substrate end region for the wiring, it is possible to reduce the area of a so-called frame that is a non-display region on the outer periphery of the electro-optic display panel. Here, the plan view means a state in which the substrate is viewed from above in a state where the substrate is placed on a flat surface.

  For example, the substrate is a hard substrate. As the substrate, glass for substrate or hard plastic can be used.

  For example, the lead wiring is formed between the glass substrate and the insulating layer. For example, the insulating layer has an appropriate film thickness of about 500 nm or more corresponding to the depth of cracks that can occur. Thereby, the lead-out wiring can be positioned at a deep position inside from the laminated substrate surface, and cracks and cracks generated on the substrate surface can be prevented from reaching the internal lead-out wiring.

An electronic apparatus according to the present invention includes the above-described electro-optical device. According to such a configuration, the characteristics of the electronic device can be improved.
In the present invention, in order to prevent the occurrence of chipping failure, the wiring of the peripheral circuit is embedded in the substrate. In particular, lead-out wirings in the peripheral region and end region of the display panel (substrate) where chipping defects frequently occur are embedded. Even if a crack due to chipping occurs on the surface of the substrate due to the embedded wiring, if the crack does not reach the wiring inside the substrate, the wiring is not broken, and the reliability of the device is improved.
The present invention is applicable not only to liquid crystal displays but also to all electronic devices that require chipping resistance.

2A and 2B are a plan view and a cross-sectional view illustrating a configuration of a liquid crystal device (electro-optical device) according to an embodiment. It is a circuit diagram which shows the structure of the active matrix substrate of this Embodiment. It is sectional drawing which shows the manufacturing process of the liquid crystal device (electro-optical device) of this Embodiment. It is explanatory drawing which shows the comparative example which comprised the extraction wiring L1 only by the uppermost layer wiring. It is explanatory drawing which shows the effect in the case of this Embodiment which made the extraction wiring L1 the wiring in a board | substrate (buried arrangement). It is a figure which shows the example of the electronic device using an electro-optical apparatus.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same or related code | symbol is attached | subjected to what has the same function, and the repeated description is abbreviate | omitted.

(Configuration of liquid crystal device)
In a display device (electro-optical device) such as a liquid crystal display according to the present application, circuit wiring around or around the substrate is embedded in the substrate. Thereby, the wiring and the device are protected from the physical impact on the substrate, and the reliability of the apparatus is improved.

  1A is a plan view illustrating a structure of the liquid crystal device of this embodiment, FIG. 1B is a cross-sectional view in the BB ′ direction in FIG. 1A, and FIG. It is sectional drawing in CC 'direction of FIG. 1 (A). In addition, the satin area | region of FIG. 1 (A) simplifies and shows the mode of the connection of the some external connection terminal P and the some extraction wiring L1, L2. FIG. 2 is a circuit diagram showing a configuration of an active matrix (active matrix substrate) formed on the substrate of the liquid crystal device of the present embodiment.

  As shown in FIGS. 1A to 1C, the liquid crystal device includes an active matrix substrate (hereinafter also simply referred to as “substrate”) S1 and a counter substrate S2. The substrate S1 and the counter substrate S2 are arranged to face each other, and liquid crystal (not shown) is injected and sealed between the substrates and the sealing material 50. The material and size of the substrates S1 and S2 are not limited. For example, the substrates S1 and S2 are made of a hard substrate such as a glass substrate. As shown in FIG. 1A, for example, the substrate S1 is slightly more than the counter substrate S2. Largely composed.

As shown in FIGS. 1 and 2, the substrate S1 has a pixel region A1 and a peripheral region A2 around the pixel region A1. The peripheral area A2 is also an area on the end side of the four sides of the rectangular substrate S1, but may be an area on the end side of the three sides excluding the side where the plurality of external terminals P are arranged.
In FIGS. 1B and 1C, E2 represents a counter electrode. CP indicates a connection pad, and the counter electrode E2 and a predetermined external connection terminal (for example, ground potential supply terminal) P are connected to the counter substrate S2 via a wiring (not shown) at the corresponding part.

  As shown in FIG. 2, in the pixel region A1, a plurality of pixels are arranged in an array, and each pixel includes a thin film transistor T and a pixel electrode PE. The gate electrode of the thin film transistor T is connected to the scanning line SL, one of the source and drain electrodes is connected to the pixel electrode PE, and the other is connected to the data line DL.

  A peripheral circuit is disposed in the peripheral area A2. This peripheral circuit includes a scanning line driving circuit DC2 and a data line driving circuit DC1. That is, the scanning line drive circuits (circuit blocks) DC2 and DC2 are arranged in the regions on both sides in the x direction of the pixel region A1. These scanning line driving circuits DC2 and DC2 alternately drive the scanning lines SL. Further, the data line DL is connected to and driven by a data line driving circuit (circuit block) DC1 disposed in a lower region in the y direction of the pixel region A1.

  The scanning line driving circuit DC2 and the data line driving circuit DC1 are connected to a plurality of external connection terminals (external terminals) P, and receive drive signals input to the terminals. Further, a predetermined signal is output to the outside via the external connection terminal P.

  Here, the wiring connecting the external connection terminal P, the scanning line driving circuits DC2, DC2 and the data line driving circuit DC1, and the wiring connecting the driving circuits (here, between the scanning line driving circuits DC2) are connected to the peripheral region A2. Are referred to as lead-out lines (lead-out lines) L1 and L2, respectively. The lead wires L1 and L2 are used for signal transmission and power supply.

  Of these lead wires L1 and L2, L1 is disposed along the outer edge of the substrate S1 and inside the substrate S1, as shown in FIGS. 1B and 1C. Preferably, the distance between the lead-out line L1 and the pixel region A1 is larger than the distance between the lead-out line L1 and the end of the substrate S1. The substrate S1 is configured to include, for example, a glass substrate 11 and an insulating layer 12, and the lead-out wiring L1 is disposed between the glass substrate 11 and the insulating layer 12. The lead line L1 is formed, for example, by depositing a metal such as aluminum on a substrate by sputtering or the like and patterning the metal film. The insulating layer 12 is formed, for example, by depositing silicon oxide or silicon nitride to a thickness of about 500 nm by a CVD method or the like. The film thickness of the insulating layer 12 can be set according to the depth of cracks generated by an impact assumed in a manufacturing process or the like.

  Although not shown in FIG. 1C, similarly, the lead-out wiring L1 in the peripheral region A2 on the lower side where the plurality of external connection terminals P of the substrate S1 are arranged is a wiring embedded in the substrate. be able to. In addition, a buried wiring may be employed for the lead-out wiring L2 to prevent disconnection due to a crack.

(Manufacturing process of liquid crystal device)
Hereinafter, with reference to FIG. 3, a process of forming a leader line portion on the substrate performed in the manufacturing process of the liquid crystal device (electro-optical device) of the present embodiment will be schematically described.

  As shown in FIG. 3A, for example, a glass substrate 11 is prepared as the substrate S1. For example, a metal film such as aluminum (Al) is deposited as a conductive film on the entire upper surface of the substrate 11 by sputtering. Thereafter, the extraction wiring L1 is formed in the peripheral area A2 of the substrate by patterning according to the wiring pattern. Specifically, a photoresist film (not shown) is formed on the metal film, and a photoresist film having a desired shape is formed by exposure and development (photolithography). Next, the metal film is etched using the photoresist film as a mask to form the lead wiring L1. The remaining photoresist film is removed (patterning).

  Next, as shown in FIG. 3B, for example, a silicon oxide film (SiO 2) is deposited as the insulating film 12 on the entire surface of the substrate 11 and the lead-out wiring L1 by a CVD method. Note that another inorganic insulating film such as a silicon nitride film (SiN) may be used instead of the silicon oxide film. It is also possible to use an organic insulating film such as polyimide. The thickness of the insulating layer 12 is, for example, about 500 nm, but is not limited thereto. The film thickness of the insulating layer 12 is set in accordance with the depth of cracks that are expected to occur due to an impact assumed in a manufacturing process or the like.

  Next, as shown in FIG. 3C, the contact hole 15 is formed by selectively removing the upper insulating film 12 of the wiring L1 portion.

  Next, as shown in FIG. 3D, a metal film such as aluminum (Al), for example, is deposited as a conductive film on the insulating film 12 including the contact hole 15 by a sputtering method and patterned to lead out wiring. L1 is formed.

  In this way, the thin film transistor T, the source, the drain wiring, the scanning line SL, the data line DL, the pixel electrode PE, and the like are formed on the substrate 11 on which the lead line L1 is formed, and the active matrix substrate S1 is completed.

  The formation of the leader line L1 is not limited to the above example. For example, the lead-out wiring L1 is formed together with an active matrix wiring (scanning line SL, data line DL, etc.) formed of a plurality of wiring layers and a wiring that becomes a suitable depth among transistor wirings. be able to. Further, in the peripheral region A2, an external connection terminal P, an extraction wiring L2 for connecting the external connection terminal P and the data line driving circuit DC1, and the like are appropriately formed.

  Thereafter, the counter substrate S2 formed with a separate process and having the counter electrode E2 formed thereon is bonded to the substrate S1 through a sealing material (sealing film) 50, and liquid crystal is filled from an injection port (not shown). Thereafter, the injection port is closed with resin or the like.

  Further, IC chips constituting the scanning line driving circuit DC2 and the data line driving circuit DC1 are mounted on the peripheral area A2 of the substrate S1 exposed on the outer periphery of the counter substrate S2. At this time, a plurality of external terminals of the IC chip, for example, a plurality of bump electrodes and the respective ends of the lead wires L1 and L2 are aligned and bonded (see FIG. 1).

  The liquid crystal device is substantially completed through the above steps.

  In the above process, the scanning line driving circuit DC2 and the data line driving circuit DC1 are separate chips. However, these circuits may be formed as logic circuits in the peripheral region. For example, a thin film transistor constituting a logic circuit may be formed in the same process as the thin film transistor T. In addition, elements other than the thin film transistor, for example, a capacitor and a resistor can be formed as appropriate, and these may be connected as appropriate to form the scanning line driver circuit DC2 and the data line driver circuit DC1.

  As described above, in the present embodiment, the lead-out wiring L1 disposed in the peripheral area A2 is formed at a deep position in the substrate where cracks from the substrate surface are difficult to reach. Even if partial cracks or cracks occur, electrical connection is ensured.

(Contrast with comparative example)
FIG. 4 is a cross-sectional view showing a comparative example in which the lead-out wiring L1 is configured on the substrate surface, and FIG. 5 is a cross-sectional view showing the effect of the present embodiment in which the lead-out wiring L1 is embedded in the substrate. . Corresponding parts in both figures are given the same reference numerals.

  As shown in FIG. 4, when the lead-out wiring L1 is constituted by the wiring on the substrate surface, a physical impact is applied, and when a crack occurs on the substrate surface, the lead-out line L1 on the surface is disconnected and electrical communication cannot be secured, It becomes defective or breaks down.

  On the other hand, as shown in FIG. 5, in the case of the present embodiment in which the lead wiring L1 is buried, the depth of the lead wiring L1 is determined by the number of cracks generated by an impact that may occur in normal handling of the substrate. It is set at a position deeper than the depth. Even if a crack is generated from the surface of the substrate (peripheral area) toward the inside due to a physical impact, disconnection does not occur unless the lead wire L1 is buried, and electrical communication by the lead wire L1 can be ensured. As a result, the manufacturing yield of the apparatus can be improved and the reliability can be improved.

  In the present embodiment, as shown in FIG. 1A, the entire extraction wiring L1 routed along a side other than the one side where the external connection terminal P of the substantially rectangular substrate S1 is formed is provided. Although the embedded arrangement is used, only a part of the wiring may be used as the embedded arrangement. Further, the lead-out wiring L1 may be embedded in the peripheral area A2 on the four sides of the substrate S1 including one side where the external connection terminal P is formed. As a place to be buried, it is effective to verify in advance a place where the occurrence probability of disconnection is high, and to bury the lead-out wiring L1 in the place. In addition, it is also effective to embed the four corners of the substrate S1, which is easily subjected to an impact during handling.

  Although the liquid crystal device has been described as an example in the above embodiment, the present invention can be applied to various electro-optical devices such as an organic EL device and an electrophoresis device. In such an electro-optical device, in order to secure a large pixel region, wiring is often drawn around the peripheral region, which is preferable to apply the present invention.

(Electronics)
The electro-optical device can be incorporated into various electronic devices. An electronic apparatus in which such an electro-optical device is used will be described. FIG. 6 illustrates an example of an electronic device using an electro-optical device.

  FIG. 6A shows an application example to a mobile phone, and FIG. 6B shows an application example to a video camera. FIG. 6C shows an application example to a television (TV).

  As shown in FIG. 6A, the cellular phone 530 includes an antenna portion 531, an audio output portion 532, an audio input portion 533, an operation portion 534, and an electro-optical device (display portion) 500.

  As shown in FIG. 6B, the video camera 540 includes an image receiving unit 541, an operation unit 542, an audio input unit 543, and an electro-optical device (display unit) 500.

  As shown in FIG. 6C, the television 550 includes an electro-optical device (display unit) 500. A personal computer or the like also includes an electro-optical device.

  In addition to the above, the electronic apparatus having the electro-optical device includes a fax machine with a display function, a digital camera finder, a portable TV, an electronic notebook, an electric bulletin board, a display for advertisements, and the like. The electro-optical device of the present invention can be incorporated in the electro-optical device portion of the electronic apparatus.

  In addition, the examples and application examples described through the above-described embodiment can be used in appropriate combination depending on the application, or can be used with modifications or improvements, and the present invention is limited to the description of the above-described embodiment. Is not to be done.

11 glass substrate, 12 insulating layer, 15 contact hole, 20 substrate, 50 sealing material, A1 pixel region, A2 peripheral region, DC1 data line driving circuit, DC2 scanning line driving circuit, DC2 scanning line driving circuit, DL data line, E2 counter electrode, L1 lead wiring, L2 lead wiring, P external connection terminal, PE pixel electrode, S1 active matrix substrate, S2 counter substrate, SL scanning line, T thin film transistor

Claims (5)

A substrate,
An insulating layer disposed on the substrate and having a pixel region and a peripheral region located on an outer periphery of the pixel region;
An electro-optic element disposed in the pixel region;
A drive circuit disposed in the peripheral region and driving the electro-optic element;
An external terminal disposed in the peripheral region;
A lead-out wiring that is disposed in the peripheral region and electrically connects the external terminal and the drive circuit;
An electro-optical device, wherein at least part of the lead-out wiring is disposed between the substrate and the insulating layer. A substrate,
An insulating layer having a pixel region and a peripheral region located on an outer periphery of the pixel region;
A plurality of electro-optic elements arranged in the pixel region;
First and second drive circuits arranged in the peripheral region and driving the plurality of electro-optic elements;
A plurality of first external terminals arranged in the peripheral region;
A plurality of second external terminals arranged in the peripheral region;
A first lead wire that is a plurality of first wires disposed in the peripheral region and electrically connecting the plurality of first external terminals and the first drive circuit;
A plurality of second wirings disposed in the peripheral region and disposed between the substrate and the insulating layer and electrically connecting the plurality of second external terminals and the second drive circuit; 2 lead wires, and
At least a part of the first lead wiring is disposed between the substrate and the insulating layer, and at least a part of the second lead wiring is disposed between the substrate and the insulating layer; An electro-optical device.   3. The electro-optical device according to claim 1, wherein a distance between the lead-out wiring and the pixel region is larger than a distance between the lead-out wiring and an end portion of the substrate in a plan view.   The electro-optical device according to claim 1, wherein the substrate is a glass substrate.   An electronic apparatus comprising the electro-optical device according to claim 1.

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