JP2010277434A5 - - Google Patents

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Publication number
JP2010277434A5
JP2010277434A5 JP2009130939A JP2009130939A JP2010277434A5 JP 2010277434 A5 JP2010277434 A5 JP 2010277434A5 JP 2009130939 A JP2009130939 A JP 2009130939A JP 2009130939 A JP2009130939 A JP 2009130939A JP 2010277434 A5 JP2010277434 A5 JP 2010277434A5
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JP
Japan
Prior art keywords
processing unit
received packet
external memory
occurrence
packet data
Prior art date
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Application number
JP2009130939A
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English (en)
Japanese (ja)
Other versions
JP5496548B2 (ja
JP2010277434A (ja
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Publication date
Application filed filed Critical
Priority to JP2009130939A priority Critical patent/JP5496548B2/ja
Priority claimed from JP2009130939A external-priority patent/JP5496548B2/ja
Priority to US12/783,320 priority patent/US8238440B2/en
Publication of JP2010277434A publication Critical patent/JP2010277434A/ja
Publication of JP2010277434A5 publication Critical patent/JP2010277434A5/ja
Application granted granted Critical
Publication of JP5496548B2 publication Critical patent/JP5496548B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2009130939A 2009-05-29 2009-05-29 半導体集積回路 Expired - Fee Related JP5496548B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009130939A JP5496548B2 (ja) 2009-05-29 2009-05-29 半導体集積回路
US12/783,320 US8238440B2 (en) 2009-05-29 2010-05-19 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009130939A JP5496548B2 (ja) 2009-05-29 2009-05-29 半導体集積回路

Publications (3)

Publication Number Publication Date
JP2010277434A JP2010277434A (ja) 2010-12-09
JP2010277434A5 true JP2010277434A5 (enExample) 2012-04-12
JP5496548B2 JP5496548B2 (ja) 2014-05-21

Family

ID=43220197

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009130939A Expired - Fee Related JP5496548B2 (ja) 2009-05-29 2009-05-29 半導体集積回路

Country Status (2)

Country Link
US (1) US8238440B2 (enExample)
JP (1) JP5496548B2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8402190B2 (en) 2008-12-02 2013-03-19 International Business Machines Corporation Network adaptor optimization and interrupt reduction
US10592459B2 (en) * 2014-03-07 2020-03-17 Cavium, Llc Method and system for ordering I/O access in a multi-node environment
US9411644B2 (en) 2014-03-07 2016-08-09 Cavium, Inc. Method and system for work scheduling in a multi-chip system
US9372800B2 (en) 2014-03-07 2016-06-21 Cavium, Inc. Inter-chip interconnect protocol for a multi-chip system
US9529532B2 (en) 2014-03-07 2016-12-27 Cavium, Inc. Method and apparatus for memory allocation in a multi-node system
US10199848B2 (en) * 2014-07-28 2019-02-05 Qualcomm Incorporated Apparatuses, methods, and systems for enabling higher current charging of Universal Serial Bus (USB) specification revision 2.0 (USB 2.0) portable electronic devices from USB 3.X hosts

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818539A (en) * 1996-03-29 1998-10-06 Matsushita Electric Corporation Of America System and method for updating a system time constant (STC) counter following a discontinuity in an MPEG-2 transport data stream
US5943479A (en) * 1997-01-02 1999-08-24 Digital Equipment Corporation Method for reducing the rate of interrupts in a high speed I/O controller
JP4541007B2 (ja) * 2004-03-19 2010-09-08 株式会社リコー ネットワーク割り込み制御方法、情報処理装置及び画像形成装置
JP2007201983A (ja) 2006-01-30 2007-08-09 Renesas Technology Corp 放送局同期方法、及び制御装置
KR101381476B1 (ko) * 2006-02-14 2014-04-10 삼성전자주식회사 디지털 방송 시스템에서 방송 서비스 정보를 수신하기 위한방법 및 장치
US8396133B2 (en) * 2009-04-21 2013-03-12 Qualcomm Incorporated Synchronizing video frames without hardware timestamps

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