JP2010272729A - Semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element in which electric field concentration on a gate electrode end is reduced without using a complicated field plate structure. <P>SOLUTION: An MOSFET 10 includes a p-GaN layer 14 formed over a substrate via a buffer layer, a gate insulating film 15, a gate electrode 20, a source electrode, and a drain electrode 17. The gate electrode 20 applies a gate voltage, and includes a first region (gate electrode 1) 21 using polysilicon heavily doped with a dopant, and a second region (gate electrode 2) 22 using polysilicon of high resistance. A resistance gradient portion 23 is present between both the gate electrodes 21 and 22. A potential gradient 30 of gentle potential variation is formed in the second region 22. Consequently, an electric field which is a differential of a voltage becomes small as shown by a peak 32 at the gate electrode end 31 to reduce the electric field concentration on the gate electrode end 31. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor element suitable for use as a high-voltage / high-current electronic device for power supply in vehicles such as automobiles, and more particularly to a semiconductor element using a nitride compound semiconductor.

Wide bandgap semiconductors typified by III-V nitride compound semiconductors have high breakdown voltage, good electron transport properties, and good thermal conductivity, so that they can be used in high temperature, high power, or high frequency semiconductor devices. Expected as a material.
When considering a high breakdown voltage lateral device, for example, a semiconductor element using a group III-V nitride compound semiconductor, a high voltage is applied between the gate electrode and the drain electrode. In many cases, a RESURF structure is employed in this portion for electric field relaxation (see, for example, Patent Document 1).

  When the RESURF structure is adopted and the structure is optimized, the electric field generally concentrates on the gate electrode end. For this reason, an FP (field plate) structure or the like has been proposed in order to alleviate electric field concentration at the gate electrode end (see, for example, Patent Document 2).

2009-4493 2007-88371

However, the FP structure is complicated, and the electric field concentration portion is merely dispersed in either the semiconductor layer or the dielectric film thereon.
7A and 7B are explanatory diagrams showing the relationship between the potential and electric field between the gate electrode and the drain electrode of a conventional MOS field effect transistor (MOSFET). 7A and 7B, reference numeral 101 denotes a semiconductor operation layer made of p-GaN, reference numeral 102 denotes an impurity layer formed in the semiconductor operation layer 101, a resurf layer for reducing electric field concentration, reference numeral Reference numeral 103 denotes a gate insulating film, reference numeral 104 denotes a gate electrode, and reference numeral 105 denotes a drain electrode.
In the conventional MOSFET, as shown in FIGS. 7A and 7B, the gate electrode 104 is a conductor, and there is no electric field distribution in the gate electrode 104. Therefore, the potential suddenly rises from the end portion (gate electrode end) 106 of the gate electrode 104 toward the drain electrode 105.

Since the electric field is a derivative of the potential (voltage), at points 110 and 111 (see FIG. 7A) where the potential changes suddenly, as shown by peaks 112 and 113 in FIG. Thus, the device is destroyed starting from the point of such a high electric field.
As described above, in the conventional MOSFET, when a metal or polysilicon doped with impurities at a high concentration is used for the gate electrode 104, the potential abruptly changes at the opposite ends of the gate electrode 104 and the drain electrode 105. 110 and 111 exist, and these points become electric field concentration points. Therefore, electric field relaxation at the gate electrode end 106 is important.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a semiconductor element that can alleviate electric field concentration at the gate electrode end without using a complicated field plate structure. It is to provide.

In order to solve the above problems, a semiconductor element according to a first aspect of the present invention includes a semiconductor operation layer formed on a substrate, a source electrode and a drain electrode formed on the semiconductor operation layer, and the semiconductor In a semiconductor device comprising: a gate insulating film formed between the source electrode and the drain electrode on the operating layer; and a gate electrode formed on the gate insulating film, the gate electrode includes the gate electrode A first region on the source electrode side and a second region on the drain electrode side and having a higher resistance than the first region are provided.
According to this configuration, the gate electrode includes the first region and the second region, and the second region having a higher resistance than the first region is provided in a part on the drain electrode side. An electric field is distributed in a region having high resistance. For this reason, there is no sudden potential change at the gate electrode end, and the electric field concentration at the gate electrode end is alleviated.

In a semiconductor device according to another aspect of the present invention, the gate electrode is made of polysilicon, and the second region has an impurity concentration lower than that of the first region.
According to this configuration, the first region can function as an original gate electrode for applying a gate voltage, and the potential gradient in which the potential changes gently in the second region (the potential gradient shown in FIG. 2). 30). For this reason, there is no point at which the voltage suddenly changes at the gate electrode end (gate electrode end 31 shown in FIG. 2), and the electric field concentration at the gate electrode end is alleviated.

In the semiconductor element according to another aspect of the present invention, the gate electrode has a high resistance from the first region to the second region between the second region and the first region. It has the resistance gradient part which becomes.
According to this configuration, the electric field concentration between the high resistance region and the low resistance region in the gate electrode can be reduced, and a higher breakdown voltage can be achieved.
The semiconductor device according to another aspect of the present invention is characterized in that the semiconductor operation layer is made of a GaN-based compound semiconductor.

  According to the present invention, electric field concentration at the gate electrode end can be relaxed without using a field plate structure having a complicated structure, and a high breakdown voltage semiconductor device can be realized.

It is sectional drawing which shows schematic structure of MOSFET which concerns on one Embodiment of this invention. It is explanatory drawing which shows the relationship between the electric potential in the MOSFET shown in FIG. 1, and an electric field. (A)-(C) is a figure explaining the manufacturing method of MOSFET shown in FIG. (A)-(C) is a figure explaining the manufacturing method of MOSFET shown in FIG. (A)-(C) is a figure explaining the manufacturing method of MOSFET shown in FIG. It is explanatory drawing which shows the relationship between the electric potential in the MOSFET which concerns on other embodiment of this invention, and an electric field. (A), (B) is explanatory drawing which shows the relationship between the electric potential in a conventional MOSFET, and an electric field.

  The MOSFET according to the present invention will be described below with reference to the drawings.

(One embodiment)
FIG. 1 is a cross-sectional view showing a schematic configuration of a MOSFET 10 according to an embodiment of the present invention. FIG. 2 is an explanatory diagram showing the relationship between the potential and the electric field in the MOSFET 10.
In the MOSFET 10 as a semiconductor element, a substrate 11 made of sapphire, SiC, Si or the like, a buffer layer 13 formed on the substrate 11 by alternately laminating GaN layers and AlN layers, and a p-GaN layer. 14 are formed. A source electrode 16 and a drain electrode 17 are formed on the p-GaN layer 14 at a predetermined interval.
This MOSFET 10 is formed so as to be in contact with ohmic contact layers 18a and 18b formed in regions under the source electrode 16 and the drain electrode 17 on the surface of the p-GaN layer 14, respectively, and an ohmic contact layer 18b on the drain electrode 17 side. And a RESURF layer 19 for the purpose of relaxing the electric field concentration. The p-GaN layer 14, the ohmic contact layers 18 a and 18 b, and the RESURF layer 19 constitute a semiconductor operation layer 40 made of a nitride compound semiconductor that is a main part of the MOSFET 10.

  The MOSFET 10 includes a gate insulating film 15 formed on the p-GaN layer 14 between the source electrode 16 and the drain electrode 17, and a gate electrode 20 formed on the gate insulating film 15.

The MOSFET 10 according to this embodiment is characterized in that it has the following configuration.
(1) The gate electrode 20 is formed of polysilicon, and includes a first region 21 made of polysilicon doped with a dopant such as B (boron) or P (phosphorus) at a high concentration, and the first region 21 than the first region. And a second region 22 made of polysilicon having a low dopant concentration and high resistance.
Thus, in the MOSFET 10 according to the present embodiment, the second region 22 which is a part of the gate electrode 20 on the drain electrode 17 side is formed of polysilicon having a higher resistance than the first region 21.
(2) Further, the gate electrode 20 has a resistance gradient portion 23 in which the resistance increases from the first region 21 toward the second region 22 between the first region 21 and the second region 22. .

(Carrier concentration range of gate electrode)
Here, the dopant concentration of the first region 21 is about 1 × 10 ¹⁹ cm ⁻³ , and the dopant concentration of the second region 22 is 1 × 10 ¹⁶ cm ⁻³ or less. Here, the resistivity of the second region 22 is preferably 10 Ωm or more.
Since the second region 22 needs to distribute the electric field inside, the inside needs to be depleted.
A graph showing the relationship between the Si carrier concentration and the depletion layer thickness can be found in the following references.
G. Gibbons, “Avalanche Breakdown Voltages of Abrupt and Linearly Graded pn Juctions in Ge, Si, GaAs, and GaP,” Appl. Phys. Lett., 8, 111 (1996)
In the present invention, since the length of the second region 22 is several microns, the second region 22 is depleted if the carrier concentration is 1 × 10 ¹⁶ cm ⁻³ or less from the graph in the reference document. it is conceivable that.

Next, a method for manufacturing MOSFET 10 shown in FIG. 1 will be described.
First, as shown in FIG. 3A, a substrate 11 made of Si having a (111) plane as a main surface is set in an MOCVD apparatus, and hydrogen gas having a concentration of 100% is used as a carrier gas to trimethylgallium (TMGa). Then, trimethylaluminum (TMAl) and NH ₃ are introduced, and the AlN layer 12, the buffer layer 13, and the p-GaN layer 14 are sequentially epitaxially grown on the substrate 11 at a growth temperature of 1050 ° C.
The AlN layer 12 is stacked, for example, 100 nm. The buffer layer 13 is formed by stacking eight composite layers of a GaN layer having a thickness of 200 nm and an AlN layer having a thickness of 20 nm. Moreover, the p-GaN layer 14 is laminated | stacked by 500 nm. Note that biscyclopentadienyl magnesium (Cp ₂ Mg) is used as a p-type doping source for the p-GaN layer 14, and the flow rate of Cp ₂ Mg is adjusted so that the Mg concentration is about 1 × 10 ¹⁷ cm ^−3. .

Next, as shown in FIG. 3B, a mask layer 41 made of SiO ₂ is formed on the p-GaN layer 14 by using a plasma enhanced chemical vapor deposition (PCVD) method. Is patterned using photolithography and CF ₄ gas to form an opening 41a in a region where the RESURF layer 19 is to be formed.
Thereafter, a SiO ₂ film having a thickness of 20 nm is formed as a screen layer. In the normal ion implantation method, the impurity concentration is highest at a position slightly deeper than the surface. For this reason, a screen layer is formed in advance and ion implantation is performed, and then the screen layer is removed so that the impurity concentration is highest on the surface.

Next, as shown in FIG. 3C, Si is added to the p-GaN layer 14 formed on the buffer layer 13 by ion implantation (Ion Implantation) from the opening 41a.
Considering the screen layer, the implantation energy is set so that the impurity concentration is the highest on the surface. Then, Si is ion-implanted into the opening 41a so as to be 1 × 10 ¹³ cm ⁻² .

Next, as shown in FIG. 4A, the mask layer 41 shown in FIG. 3C is removed, and a mask layer 42 made of SiO ₂ is formed on the p-GaN layer 14 using the PCVD method. To do. Further, the mask layer 42 is patterned using photolithography and CF ₄ gas to form openings 42a and 42a in regions where the ohmic contact layers 18a and 18b are to be formed.

Next, as shown in FIG. 4B, Si is added to the p-GaN layer 14 by ion implantation from the openings 42a and 42a.
Considering the screen layer, the implantation energy is set so that the impurity concentration is the highest on the surface. Then, Si is ion-implanted into the ohmic contact layers 18a and 18b so as to be 1 × 10 ¹⁶ cm ⁻³ .
Thereafter, activation annealing is performed at a temperature of 1200 ° C. for 1 minute. As a result, the RESURF layer 19 is formed in the region between the portion serving as the gate electrode 2 and the portion serving as the drain electrode 17 on the surface of the p-GaN layer 14, and ohmic contacts are formed in 18A and 18B.

Next, as shown in FIG. 4C, the mask layer 42 shown in FIG. 4B is removed, and an insulating film to be the gate insulating film 15, for example, a SiO ₂ film 43 is formed to a thickness of 60 nm.
Thereafter, as shown in FIG. 4C, an undoped polysilicon 44 to be the gate electrode 20 is formed on the SiO ₂ film 43 by the LP-CVD (Low Pressure-CVD) method. The film forming temperature is 600 ° C., and the thickness of the polysilicon 44 is 500 nm.

Thereafter, as shown in FIG. 4C, an SiO ₂ film 45 is formed on the polysilicon 44 by a PCVD method to a thickness of 300 nm.
Next, as shown in FIG. 5 (A), the SiO ₂ film 45, using photolithography and dry etching, of the polysilicon 44, the opening 45a in a region where the first region 21 of the gate electrode 20 Form.
Thereafter, the resistance of the region to be the first region 21 in the polysilicon 44 is reduced by using a thermal diffusion method, an ion implantation method, or the like. In this case, when the first region 21 is to be n-type, P (phosphorus) is introduced up to about 1 × 10 ¹⁹ cm ⁻³ as a dopant. Further, when the first region 21 is made to be p-type, B (boron) is introduced up to about 1 × 10 ¹⁹ cm ⁻³ as a dopant.

Next, as shown in FIG. 5B, the SiO ₂ film 45 shown in FIG. 5A is removed, and the gate electrode 20 of the polysilicon 44 is further removed using photolithography and dry etching. A portion other than the first region 21 and the second region 22 is removed.
Thus, the first region 21 using polysilicon doped with a dopant such as B (boron) or P (phosphorus) at a high concentration and the second region 22 using high-resistance polysilicon are provided. The gate electrode 20 is formed on the SiO ₂ film (insulating film) 43 that becomes the gate insulating film 15.

Note that, when the resistance of the region that becomes the first region 21 in the polysilicon 44 is reduced using the thermal diffusion method, the resistance gradient portion 23 is provided between the first region 21 and the second region 22. Can be natural.
Further, when the resistance of the region to be the first region 21 in the polysilicon 44 is reduced by using the ion implantation method, the impurities in the polysilicon 44 are diffused by the activation annealing performed thereafter, and the resistance gradient. Part 23 is created.

Next, after masking the region other than the region where the source electrode 16 and the drain electrode 17 are formed, as shown in FIG. 5C, the SiO ₂ film (insulating film) in the region where the source electrode 16 and the drain electrode 17 are formed. ) 43 is removed. As a result, the remaining portion of the SiO ₂ film 43 becomes the gate insulating film 15.

Next, as shown in FIG. 5C, the source electrode 16 and the drain electrode 17 are formed on the ohmic contact layers 18a and 18b from which the SiO ₂ film 43 has been removed, using a lift-off method. The source electrode 16 and the drain electrode 17 are formed in the order of the Ti layer and the Al layer in order from the surface of the ohmic contact layers 18a and 18b. The Ti layer is, for example, 25 nm, and the Al layer is, for example, 300 nm. The Ti layer and the Al layer are formed by sputtering or vacuum deposition. Thereafter, annealing is performed at 600 ° C. for 10 minutes.
Further, an Al pad for measurement is provided in a part of the first region 21.
In this way, the MOSFET 10 shown in FIG. 1 is manufactured.

The MOSFET 10 according to the embodiment described above has the following operational effects.
(1) The gate electrode 20 has a structure including a first region 21 using polysilicon doped with a dopant at a high concentration and a second region 22 using polysilicon having high resistance. In the state where a high voltage is applied between the first electrode 22 and the drain electrode 17, a potential gradient 30 (see FIG. 2) in which the potential (voltage) gradually changes can be formed in the second region 22.
This eliminates the point 110 where the voltage suddenly changes at the gate electrode end 106 as in the prior art shown in FIG. As a result, the electric field that is the differential of the voltage at the gate electrode end 31 becomes small as indicated by the peak 32 in FIG. 2, and the electric field concentration at the gate electrode end 31 can be relaxed. Therefore, electric field concentration at the gate electrode end 31 can be alleviated without using a complicated field plate structure, and a high breakdown voltage semiconductor element can be realized.

(2) The gate voltage is applied to the first region 21 by the structure divided into the first region 21 for applying the gate voltage and the second region 22 using high-resistance polysilicon. Therefore, the second region 22 can alleviate the electric field concentration at the gate electrode end 31.
(3) Since there is the resistance gradient portion 23 between the first region 21 and the second region 22, the potential gradient 30a in which the potential (voltage) gradually changes in the resistance gradient portion 23 (see FIG. 2). Can do. For this reason, there is no electric field concentration between the first region 21 and the second region 22.

(4) The gate electrode 20 to which a high voltage is applied is configured by combining the RESURF layer 19 for reducing the electric field concentration and the second region 22 for reducing the electric field concentration at the gate electrode end 31. And electric field concentration between the drain electrode 17 and the drain electrode 17 can be reduced.
(5) Since the p-GaN layer 14 is used for the semiconductor operation layer 40, in a semiconductor device using GaN for the semiconductor operation layer, an electric field concentration at the gate electrode end without using a complicated field plate structure. Can be relaxed, and a high breakdown voltage can be achieved.

FIG. 6 is an explanatory diagram showing a relationship between a potential and an electric field in MOSFET 10A according to another embodiment of the present invention.
The MOSFET 10A according to the present embodiment differs from the MOSFET 10 according to the one embodiment only in that the resistance gradient portion 23 is not provided.
That is, in the MOSFET 10A shown in FIG. 6, the gate electrode 20A is an electrode for applying a gate voltage, and the first region 21 using polysilicon doped with a dopant such as boron or phosphorus at a high concentration, And a second region 22 using resistive polysilicon.
Even with this MOSFET 10A, electric field concentration at the gate electrode end 31 can be relaxed without using a field plate structure having a complicated structure, and a high breakdown voltage semiconductor element can be realized.

  In each of the above embodiments, the gate electrodes 20 and 20A include a first region 21 using polysilicon doped with a dopant at a high concentration and a second region 22 using high-resistance polysilicon. Although the MOSFET has been described, the present invention is not limited to the semiconductor element having such a configuration. In the present invention, the gate electrode is an electrode for applying a gate voltage, and includes a first region formed using a metal and a second region made of a high-resistance semiconductor, that is, the gate electrode The present invention can be widely applied to a semiconductor element partly made of a high-resistance semiconductor.

10, 10A: MOSFET
11: substrate 12: AlN layer 13: buffer layer 14: p-GaN layer 15: gate insulating film 16: source electrode 17: drain electrode 18a, 18b: ohmic contact layer 19: RESURF layer 20, 20A: gate electrode 21: first 1 region 22: second region 23: resistance gradient portion 40: semiconductor operation layer

Claims (4)

A semiconductor operating layer formed on the substrate; a source electrode and a drain electrode formed on the semiconductor operating layer; and a gate insulation formed on the semiconductor operating layer and between the source electrode and the drain electrode. In a semiconductor device comprising a film and a gate electrode formed on the gate insulating film,
The semiconductor device, wherein the gate electrode includes a first region on the source electrode side and a second region on the drain electrode side and having a higher resistance than the first region.   The semiconductor device according to claim 1, wherein the gate electrode is made of polysilicon, and the second region has an impurity concentration lower than that of the first region.   The gate electrode has a resistance gradient portion in which a resistance increases from the first region toward the second region between the second region and the first region. Item 3. The semiconductor element according to Item 1 or 2.   The semiconductor element according to claim 1, wherein the semiconductor operation layer is made of a GaN-based compound semiconductor.

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