JP2010267804A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device achieving short time formation of an interlayer dielectric with a flat surface and ensuring long-term reliability against contamination of a semiconductor substrate with metal ions without increasing the thickness of the interlayer dielectric, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device 1 includes the semiconductor substrate 2 and the interlayer dielectric 8 formed on the semiconductor substrate 2. The interlayer dielectric 8 has a structure that an HDP (High Density Plasma) layer 10, a gettering layer 12 and an NSG (None-doped Silicate Glass) 11 are laminated in order from the semiconductor substrate 2 side. The gettering layer 12 has a property to capture the metal ions, in particular, movable ions. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

As semiconductor devices are highly integrated, miniaturization of wirings formed on interlayer insulating films and through holes (contact holes, via holes) formed in interlayer insulating films is progressing. For good microfabrication of wiring and the like, a lithography focus margin must be ensured, and the flatness of the surface of the interlayer insulating film is extremely important.
FIG. 4 is a schematic cross-sectional view showing an example of a conventional semiconductor device.

  A semiconductor device 101 shown in FIG. 4 includes a semiconductor substrate 102 made of silicon (Si). A field oxide film 103 is selectively formed on the surface of the semiconductor substrate 102. A capacitor 107 having a structure in which a capacitor film 106 is sandwiched between a lower electrode 104 and an upper electrode 105 made of polysilicon is formed on a predetermined portion of the field oxide film 103.

An interlayer insulating film 108 is stacked on the semiconductor substrate 102. The entire surface of the semiconductor substrate 102 and the capacitor 107 are covered with an interlayer insulating film 108. The interlayer insulating film 108 is sequentially formed from the semiconductor substrate 102 side by a thermal oxide film 109 formed by a thermal oxidation method and an HDP-CVD (High Density Plasma Chemical Vapor Deposition) method. It has a three-layer structure in which an HDP film 110 made of silicon oxide (SiO ₂ ) and a BPSG (Boron Phospho Silicate Glass) film 111 formed by a plasma CVD (Chemical Vapor Deposition) method are stacked. Yes. The surface of the BPSG film 111 is planarized by CMP (Chemical Mechanical Polishing).

A wiring 112 is formed on the surface of the BPSG film 111. The wiring 112 has a structure in which a main wiring layer 113 made of an aluminum (Al) alloy is sandwiched between an antireflection film 114 and a barrier film 115 from above and below.
In the interlayer insulating film 108, a contact hole 116 is formed penetrating in the thickness direction between the active region on the surface of the semiconductor substrate 102 and the wiring 112. A barrier film 117 integral with the barrier film 115 is deposited on the inner surface of the contact hole 116. A contact plug 118 made of tungsten (W) is embedded inside the barrier film 117. The upper end of the contact plug 118 passes through the barrier film 115 and is connected to the main wiring layer 113.

  The BPSG film 111 containing phosphorus (P) at a high concentration has a property of capturing mobile ions such as sodium (Na), lithium (Li), and potassium (K). Since the BPSG film 111 is included in the interlayer insulating film 108, it is possible to prevent the mobile ions from diffusing in the interlayer insulating film 108 when the wiring 112 is formed. Contamination can be prevented. However, since the compatibility between the BPSG film 111 and CMP is not good, the in-plane uniformity of planarization is lowered when the polishing rate is increased. Therefore, the surface of the BPSG film 111 must be planarized at a low polishing rate, and it takes time to planarize.

  An NSG (None-doped Silicate Glass) film is known as an insulating film having good compatibility with CMP. If an NSG film is employed instead of the BPSG film 111, the surface of the NSG film can be satisfactorily planarized at a high polishing rate. However, since the NSG film does not have the property of trapping mobile ions, when the NSG film is employed, contamination of the semiconductor substrate 102 and the like by mobile ions cannot be prevented.

FIG. 5 is a schematic cross-sectional view showing another example of a conventional semiconductor device.
In FIG. 5, parts corresponding to the parts shown in FIG. 4 are denoted by the same reference numerals as those given to the respective parts.
In the semiconductor device 121 shown in FIG. 5, an interlayer insulating film 122 stacked on the semiconductor substrate 102 includes a thermal oxide film 123, an HDP film 124, an NSG film 125, and a PSG (Phospho Silicate Glass) film in this order from the semiconductor substrate 102 side. It has a four-layer structure in which 126 are stacked.

  When forming the interlayer insulating film 122, first, a thermal oxide film 123 is formed on the semiconductor substrate 102 by a thermal oxidation method. Next, an HDP film 124 made of silicon oxide is formed on the thermal oxide film 123 by HDP-CVD. Further, an NSG film 125 is formed on the HDP film 124 by plasma CVD. Then, the surface of the NSG film 125 is planarized by CMP. Thereafter, a PSG film 126 is formed on the NSG film 125 by plasma CVD.

  Since the surface of the NSG film 125 is planarized before the PSG film 126 is formed, the surface of the PSG film 126 becomes a flat surface. Therefore, it is not necessary to planarize the surface of the PSG film 126 after the PSG film 126 is formed. Further, the surface of the NSG film 125 can be satisfactorily planarized in a short time at a high polishing rate. Further, since the PSG film 126 has a property of capturing mobile ions, it is possible to prevent the semiconductor substrate 102 and the like from being contaminated by the mobile ions. Therefore, in the structure shown in FIG. 5, the interlayer insulating film 122 having a flat surface can be formed in a short time, and long-term reliability against contamination of the semiconductor substrate 102 and the like by movable ions can be ensured.

JP 2002-359283 A

  However, since the PSG film 126 is further laminated on the NSG film 125, the entire thickness of the interlayer insulating film 122 is increased. Therefore, the aspect ratio Y / X of the contact hole 116 (X: the opening width of the contact hole 116, Y: the depth of the contact hole 116) increases. As a result, the barrier film 117 may have poor coverage with respect to the inner surface of the contact hole 116.

  It is an object of the present invention to form an interlayer insulating film having a flat surface in a short time, and to provide long-term reliability against contamination of a semiconductor substrate by metal ions without increasing the thickness of the interlayer insulating film. A semiconductor device and a method for manufacturing the same can be provided.

In order to achieve the above object, a semiconductor device according to claim 1 includes a semiconductor substrate and an interlayer insulating film formed on the semiconductor substrate. The interlayer insulating film has a structure in which a silicon oxide film, a gettering layer, and an NSG film are stacked in order from the semiconductor substrate side. The gettering layer has a property of capturing metal ions.
The NSG film has good compatibility with CMP. Therefore, even if the surface of the NSG film is planarized at a high polishing rate by CMP, the surface of the NSG film can be made a surface having excellent flatness. Therefore, an interlayer insulating film having a flat surface can be formed in a short time. In addition, since the gettering layer has a property of capturing metal ions, contamination of the semiconductor substrate by metal ions can be prevented without forming a PSG film or a BPSG film on the NSG film. Therefore, long-term reliability against contamination of the semiconductor substrate by metal ions can be ensured without increasing the thickness of the interlayer insulating film.

According to a second aspect of the present invention, the gettering layer may be formed integrally with the silicon oxide film by doping phosphorus in a surface layer portion of the silicon oxide film. In other words, the surface layer portion of the silicon oxide film may be a gettering layer by doping the surface layer portion of the silicon oxide film with phosphorus.
In the structure in which the gettering layer is formed integrally with the silicon oxide film, the thickness of the interlayer insulating film can be reduced as compared with the structure in which the silicon oxide film and the gettering layer are formed separately. Thereby, when a through hole such as a contact hole is formed in the interlayer insulating film, the aspect ratio of the through hole can be reduced.

In a configuration in which the gettering layer is formed integrally with the silicon oxide film, the gettering layer may have a thickness of 50 to 100 nm.
If the thickness of the gettering layer is 50 nm or more, the gettering layer can exhibit good trapping performance of metal ions.
A semiconductor device having a structure in which the gettering layer is formed integrally with the silicon oxide film can be manufactured by the manufacturing method according to claim 7. The manufacturing method according to claim 7 includes a step of forming a silicon oxide film on a semiconductor substrate by high-density plasma chemical vapor deposition, and gettering by doping phosphorus in a surface layer portion of the silicon oxide film. Forming a layer and forming an NSG film on the gettering layer by chemical vapor deposition.

The gettering layer may be a PSG film or a BPSG film interposed between the silicon oxide film and the NSG film.
In this case, as described in claim 5, the thickness of the gettering layer is preferably 20 to 150 nm.
If the thickness of the gettering layer is 20 nm or more, the gettering layer can exhibit good trapping performance of metal ions. If the thickness of the gettering layer is 150 nm or less, an increase in the thickness of the interlayer insulating film due to an unnecessarily thick gettering layer can be prevented.

The interlayer insulating film may be in contact with a surface of the semiconductor substrate, and the semiconductor device may further include a metal wiring formed on the interlayer insulating film. . That is, the interlayer insulating film may be a PMD (Poly Metal Dielectric) film that insulates and isolates the semiconductor substrate and the metal wiring.
Since the interlayer insulating film includes a gettering layer, metal ions that move through the interlayer insulating film can be prevented from reaching the semiconductor substrate when metal wiring is formed on the interlayer insulating film. The contamination of the semiconductor substrate by ions can be prevented.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention. FIG. 2A is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device shown in FIG. FIG. 2B is a schematic cross-sectional view showing the next step of FIG. 2A. FIG. 2C is a schematic cross-sectional view showing a step subsequent to FIG. 2B. FIG. 2D is a schematic cross-sectional view showing a step subsequent to FIG. 2C. FIG. 2E is a schematic cross-sectional view showing a step subsequent to FIG. 2D. FIG. 3 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention. FIG. 4 is a schematic cross-sectional view showing an example of a conventional semiconductor device. FIG. 5 is a schematic cross-sectional view showing another example of a conventional semiconductor device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention.
The semiconductor device 1 includes a semiconductor substrate 2. At least the surface layer portion of the semiconductor substrate 2 is made of, for example, silicon. A field oxide film 3 is selectively formed on the surface of the semiconductor substrate 2. In the active layer where the field oxide film 3 is not formed, a P-type or N-type impurity diffusion region constituting a transistor or the like is selectively formed in the surface layer portion of the semiconductor substrate 2.

A capacitor 7 having a structure in which a capacitive film 6 is sandwiched between a lower electrode 4 and an upper electrode 5 is formed on a predetermined portion of the field oxide film 3.
The lower electrode 4 and the upper electrode 5 are made of polysilicon, for example. Side walls 4A and 5A are formed on the side surfaces of the lower electrode 4 and the upper electrode 5, respectively. The sidewalls 4A and 5A are made of, for example, silicon oxide. The lower electrode 4 extends to the active region, and may also serve as a gate electrode facing the surface of the semiconductor substrate 2 with a gate insulating film (not shown) interposed therebetween.

The capacitor film 6 is made of, for example, silicon oxide or silicon nitride (SiN).
An interlayer insulating film 8 is laminated on the semiconductor substrate 2. The entire surface of the semiconductor substrate 2 and the capacitor 7 are covered with an interlayer insulating film 8. The interlayer insulating film 8 has a structure in which a thermal oxide film 9, an HDP film 10, and an NSG film 11 are stacked in this order from the semiconductor substrate 2 side.
The thermal oxide film 9 and the HDP film 10 are made of silicon oxide. The thickness of the HDP film 10 is 300 to 600 nm (3000 to 6000 mm). The surface layer portion having a thickness of 50 to 100 nm (500 to 1000 mm) from the surface of the HDP film 10 is a gettering layer 12 having a property of capturing metal ions (particularly, mobile ions) by being doped with phosphorus. Yes. That is, the gettering layer 12 is formed integrally with the HDP film 10 by doping P in the surface layer portion of the HDP film 10.

The surface of the NSG film 11 is planarized. The thickness of the NSG film 11 is, for example, 1000 to 1200 nm (10000 to 12000 mm) on the active region of the semiconductor substrate 2.
A wiring 13 is formed on the surface of the NSG film 11. The wiring 13 has a structure in which a main wiring layer 14 made of an Al alloy is sandwiched between an antireflection film 15 and a barrier film 16 from above and below.

The antireflection film 15 is made of, for example, a titanium nitride (TiN) / titanium (Ti) two-layer structure film.
The barrier film 16 is made of, for example, a three-layer structure film of titanium / titanium nitride / titanium.
In the interlayer insulating film 8, a plurality of contact holes 17 are formed penetrating in the thickness direction between the active region on the surface of the semiconductor substrate 2 and the wiring 13. A barrier film 18 that is integral with the barrier film 16 is deposited on the inner surface of each contact hole 17. A contact plug 19 made of tungsten is embedded inside the barrier film 18. The upper end of the contact plug 19 penetrates the barrier film 16 and is connected to the main wiring layer 14 of the wiring 13.

2A to 2E are schematic cross-sectional views in each manufacturing process of the semiconductor device shown in FIG.
In the manufacturing process of the semiconductor device 1, first, the field oxide film 3 is formed on the surface of the semiconductor substrate 2. The field oxide film 3 can be formed by, for example, a LOCOS (Local Oxidation of Silicon) method. Next, a capacitor 7 is formed on field oxide film 3. The capacitor 7 can be formed by a known method including a patterning process by photolithography and etching.

Thereafter, as shown in FIG. 2A, a thermal oxide film 9 is formed by a thermal oxidation method.
Next, as shown in FIG. 2B, an HDP film 10 is formed on the thermal oxide film 9 by HDP-CVD.
Next, as shown in FIG. 2C, phosphorus is doped in the surface layer portion of the HDP film 10 by ion implantation. The implantation energy at this time is, for example, 30 keV. The dose amount is, for example, 4.0E15 cm−2. By this phosphorus doping, the surface layer portion of the HDP film 10 is changed to the gettering layer 12.

Thereafter, as shown in FIG. 2D, the material of the NSG film 11 is deposited on the gettering layer 12 by the CVD method. The thickness of the deposited layer 21 formed on the gettering layer 12 is, for example, 1500 nm (15000 mm).
After the formation of the deposited layer 21, as shown in FIG. 2E, the surface of the deposited layer 21 is planarized by CMP. CMP is continued until the thickness of the deposition layer 21 on the active region of the semiconductor substrate 2 reaches a predetermined thickness (for example, 1000 to 1200 nm). As a result, the NSG film 11 having a flat surface is obtained on the gettering layer 12.

Then, the contact hole 17, the barrier films 16, 18, the contact plug 19, the main wiring layer 14, and the antireflection film 15 are formed in this order by a known method, and the semiconductor device 1 shown in FIG. 1 is obtained.
As described above, the semiconductor device 1 includes the semiconductor substrate 2 and the interlayer insulating film 8 formed on the semiconductor substrate 2. The interlayer insulating film 8 has a structure in which an HDP film 10, a gettering layer 12, and an NSG film 11 are stacked in this order from the semiconductor substrate 2 side. The gettering layer 12 has a property of capturing metal ions, particularly mobile ions.

  The NSG film 11 has good compatibility with CMP. Therefore, even if the surface of the NSG film 11 is planarized at a high polishing rate by CMP, the surface of the NSG film 11 can be made a surface having excellent flatness. Therefore, the interlayer insulating film 8 having a flat surface can be formed in a short time. Further, since the gettering layer 12 has a property of capturing metal ions, the semiconductor substrate 2 can be prevented from being contaminated by metal ions without forming a PSG film or a BPSG film on the NSG film 11. it can. Therefore, long-term reliability against contamination of the semiconductor substrate 2 by metal ions can be ensured without increasing the thickness of the interlayer insulating film 8.

The gettering layer 12 is formed integrally with the HDP film 10 by doping phosphorus in the surface layer portion of the HDP film 10. In other words, the surface layer portion of the HDP film 10 may be the gettering layer 12 by doping the surface layer portion of the HDP film 10 with phosphorus.
In the structure in which the gettering layer 12 is formed integrally with the HDP film 10, the thickness of the interlayer insulating film 8 is made smaller than in the structure in which the HDP film 10 and the gettering layer 12 are formed separately. Can do. Thereby, the aspect ratio of the contact hole 17 formed in the interlayer insulating film 8 can be reduced.

The gettering layer 12 has a thickness of 50 to 100 nm. If the thickness of the gettering layer 12 is 50 nm or more, the gettering layer 12 can exhibit good trapping performance of metal ions.
FIG. 3 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention.
In FIG. 3, parts corresponding to the parts shown in FIG. 1 are denoted by the same reference numerals as those given to the respective parts. In the following description, only the difference between the structure shown in FIG. 3 and the structure shown in FIG. 1 will be described, and the description of each part given the same reference numeral will be omitted.

In the semiconductor device 31 shown in FIG. 3, an interlayer insulating film 32 stacked on the semiconductor substrate 2 is formed by stacking a thermal oxide film 33, an HDP film 34, a PSG film 35, and an NSG film 36 in this order from the semiconductor substrate 2 side. It has a layer structure.
The thermal oxide film 33 and the HDP film 34 are made of silicon oxide. The thickness of the HDP film 34 is 300 to 600 nm (3000 to 6000 mm).

The thickness of the PSG film 35 is 20 to 150 nm (200 to 1500 mm). The PSG film 35 contains phosphorus at a high concentration of 0.5 to 6 wt%. Thereby, the PSG film 35 functions as a gettering layer having a property of capturing metal ions (particularly, mobile ions).
The surface of the NSG film 36 is planarized. The thickness of the NSG film 36 is, for example, 1000 to 1200 nm (10000 to 12000 mm) on the active region of the semiconductor substrate 2.

  When forming the interlayer insulating film 32, first, a thermal oxide film 33 is formed on the semiconductor substrate 2 by a thermal oxidation method. Next, an HDP film 34 is formed on the thermal oxide film 33 by HDP-CVD. Further, the PSG film 35 and the NSG film 36 are sequentially formed on the HDP film 34 by the CVD method. Thereafter, the surface of the NSG film 36 is planarized by CMP. Thereby, the interlayer insulating film 32 is obtained.

Also in the structure shown in FIG. 3, the same effects as the structure shown in FIG. 1 can be obtained.
Instead of the PSG film 35, a BPSG film may be interposed between the HDP film 34 and the NSG film 36.
Further, in the semiconductor device 1 shown in FIG. 1 and the semiconductor device 31 shown in FIG. 3, the semiconductor substrate 2 may be composed of a single layer of silicon, or a silicon layer is laminated on the silicon substrate (for example, epitaxial growth). ). The semiconductor substrate 2 may be an SOI (Silicon On Insulator) substrate having a structure in which a BOX (Buried Oxide) layer made of silicon oxide and a silicon layer are stacked in this order on a silicon substrate. Furthermore, the semiconductor substrate 2 may be made of a semiconductor material other than silicon, such as silicon carbide (SiC).

  In addition, various design changes can be made within the scope of matters described in the claims.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 8 Interlayer insulating film 9 Thermal oxide film (silicon oxide film)
10 HDP film (silicon oxide film)
11 NSG film 12 Gettering layer 13 Wiring (metal wiring)
31 Semiconductor device 32 Interlayer insulating film 33 Thermal oxide film (silicon oxide film)
34 HDP film (silicon oxide film)
35 PSG film (gettering layer)
36 NSG film

Claims (7)

A semiconductor substrate;
An interlayer insulating film formed on the semiconductor substrate,
The interlayer insulating film has a structure in which a silicon oxide film, a gettering layer having a property of capturing metal ions, and an NSG (None-doped Silicate Glass) film are stacked in this order from the semiconductor substrate side. Semiconductor device.   The semiconductor device according to claim 1, wherein the gettering layer is formed integrally with the silicon oxide film by doping phosphorus in a surface layer portion of the silicon oxide film.   The semiconductor device according to claim 2, wherein the gettering layer has a thickness of 50 to 100 nm.   The semiconductor device according to claim 1, wherein the gettering layer is a PSG (Phospho Silicate Glass) film or a BPSG (Boron Phospho Silicate Glass) film interposed between the silicon oxide film and the NSG film.   The semiconductor device according to claim 4, wherein the gettering layer has a thickness of 20 to 150 nm. The interlayer insulating film is in contact with the surface of the semiconductor substrate,
The semiconductor device according to claim 1, further comprising a metal wiring formed on the interlayer insulating film. Forming a silicon oxide film on a semiconductor substrate by high-density plasma chemical vapor deposition;
Forming a gettering layer by doping phosphorus in a surface layer of the silicon oxide film;
Forming a NSG (None-doped Silicate Glass) film on the gettering layer by a chemical vapor deposition method.

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