JP2010263293A - Current-voltage conversion circuit - Google Patents

Current-voltage conversion circuit Download PDF

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JP2010263293A
JP2010263293A JP2009110735A JP2009110735A JP2010263293A JP 2010263293 A JP2010263293 A JP 2010263293A JP 2009110735 A JP2009110735 A JP 2009110735A JP 2009110735 A JP2009110735 A JP 2009110735A JP 2010263293 A JP2010263293 A JP 2010263293A
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diffusion layer
voltage
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JP5199942B2 (en
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Toshihide Miyake
敏英 三宅
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SHIRINKUSU KK
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a logarithmic compression type current-voltage conversion circuit which has linearity even for a very low current value. <P>SOLUTION: The current-voltage conversion circuit includes a current input terminal 1, a reference voltage input terminal 2, a voltage output terminal 3, and an operational amplifier 4 and an NPN-type transistor 5 which are formed on a P-type semiconductor substrate. The operational amplifier 4 has an inverting input terminal connected to the current input terminal 1 and has a non-inverting input terminal connected to the reference voltage input terminal 2 and has an output terminal connected to the voltage output terminal 3. The NPN-type transistor 5 has a collector connected to the current input terminal 1 and has a base connected to the reference voltage input terminal 2 and has an emitter connected to the voltage output terminal 3. The NPN-type transistor 5 comprises an N-type epitaxial layer corresponding to the emitter, a P-type diffusion layer selectively formed on the N-type epitaxial layer and corresponding to the base, and an N-ype diffusion layer selectively formed on the P-type diffusion layer and corresponding to the collector. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は電流電圧変換回路に関し、特に入力電流を対数圧縮した電圧を発生する電流電圧変換回路に関する。   The present invention relates to a current-voltage conversion circuit, and more particularly to a current-voltage conversion circuit that generates a logarithmically compressed input current.

従来より、シリコンのフォトダイオードの光電流を対数的に圧縮する対数圧縮式の電流電圧変換回路が、カメラなどの測光回路に広く使われている。その代表的な構成を図４に示す。   Conventionally, a logarithmic compression current-voltage conversion circuit that logarithmically compresses the photocurrent of a silicon photodiode has been widely used in photometric circuits such as cameras. A typical configuration is shown in FIG.

図４において、フォトダイオード６のアノードは電流入力端子１に接続され、そのカソードは基準電圧源７の基準電圧Ｖrefが印加される基準電圧入力端子２に接続されている。演算増幅器４の反転入力端子は電流入力端子１に接続され、その非反転入力端子は基準電圧入力端子２に接続され、その出力端子は電圧出力端子３に接続されている。また、ＮＰＮ型トランジスタ８のコレクタが電源入力端子１に接続され、そのエミッタが電圧出力端子３に接続され、そのベースが基準電圧入力端子２に接続されている。 In FIG. 4, the anode of the photodiode 6 is connected to the current input terminal 1, and the cathode is connected to the reference voltage input terminal 2 to which the reference voltage V ref of the reference voltage source 7 is applied. The operational amplifier 4 has an inverting input terminal connected to the current input terminal 1, a non-inverting input terminal connected to the reference voltage input terminal 2, and an output terminal connected to the voltage output terminal 3. The collector of the NPN transistor 8 is connected to the power input terminal 1, the emitter thereof is connected to the voltage output terminal 3, and the base thereof is connected to the reference voltage input terminal 2.

フォトダイオード６で光電変換電流Ｉが発生すると、その光電変換電流ＩはＮＰＮ型トランジスタ８のコレクタに流れ込み、そのベースとエミッタとの間には光電変換電流Ｉを対数圧縮した電圧ＶBEが生じる。
ＶBE＝ＶT log(I/Is) …（1）
但し、ＶT＝kT/q（k：ボルツマン定数、T:絶対温度、q:単位電荷）、IsはＮＰＮ型トランジスタの飽和電流である。 When the photoelectric conversion current I is generated in the photodiode 6, the photoelectric conversion current I flows into the collector of the NPN transistor 8, and a voltage V BE obtained by logarithmically compressing the photoelectric conversion current I is generated between the base and the emitter.
V BE = V T log (I / I s ) (1)
However, V T = kT / q ( k: Boltzmann constant, T: absolute temperature, q: unit charge), I s is the saturation current of the NPN transistor.

そのため、電圧出力端子３には次式（2）に示されるように、基準電圧ＶrefからＶBEを差し引いた電圧Ｖoutが出力される。
Ｖout＝Ｖref−ＶBE＝Ｖref−ＶT log(I/Is) …（2） Therefore, the voltage V out obtained by subtracting V BE from the reference voltage V ref is output to the voltage output terminal 3 as shown in the following equation (2).
V out = V ref −V BE = V ref −V T log (I / I s ) (2)

ところで、電流電圧変換回路はその他の種類の回路と一緒に同一の半導体基板上に形成されることが多い。このとき、同じ半導体基板上に安定化電源回路などの比較的大電流が流れる回路が形成されていると、その影響を受けて誤差が生じるという課題がある。この課題について、以下詳細に説明する。   By the way, the current-voltage conversion circuit is often formed on the same semiconductor substrate together with other types of circuits. At this time, if a circuit through which a relatively large current flows, such as a stabilized power supply circuit, is formed on the same semiconductor substrate, there is a problem that an error occurs due to the influence. This problem will be described in detail below.

図５および図６はＮＰＮ型トランジスタ８の断面図および平面図である。Ｐ型サブストレート１１の上にコレクタとなるＮ型エピタキシャル層１２が形成されている。また、Ｎ型エピタキシャル層１２の上に選択的にＰ型拡散層１３が形成され、このＰ型拡散層１３がベースとなる。さらに、Ｐ型拡散層１３の上に選択的に不純物濃度の高いＮ型拡散層１４が形成され、エミッタとして使われる。なお、１５はＮ＋埋め込み層、１６は素子分離用のＰ＋埋め込み層、１７はコンタクト用のＮ＋層、１８はＳiＯ2層、１９はＡｌ配線層である。 5 and 6 are a cross-sectional view and a plan view of the NPN transistor 8. An N-type epitaxial layer 12 serving as a collector is formed on the P-type substrate 11. A P-type diffusion layer 13 is selectively formed on the N-type epitaxial layer 12, and this P-type diffusion layer 13 serves as a base. Further, an N-type diffusion layer 14 having a high impurity concentration is selectively formed on the P-type diffusion layer 13 and used as an emitter. Incidentally, 15 is N + buried layer, 16 is the P + buried layer for element isolation, N + layer of contact 17, 18 is S i O 2 layer, 19 is the Al wiring layer.

集積回路において比較的大きな電流が流れると、微小な光（主に赤外線）が発生することは良く知られた現象である。この発生した微小な光が、対数圧縮を行っているＮＰＮ型トランジスタ８のＮ型エピタキシャル層１２とＰ型サブストレート１１との間のＰＮ接合、Ｎ型エピタキシャル層１２とＰ型拡散層１３との間のＰＮ接合、Ｐ型拡散層１３とＮ＋拡散層１４との間のＰＮ接合に到達すると、そこに図示の矢印ａ、ｂ、ｃに示す向きの電流が発生する。この発生した電流を以下、誤差電流と呼ぶ。   It is a well-known phenomenon that minute light (mainly infrared rays) is generated when a relatively large current flows in an integrated circuit. The generated minute light is a PN junction between the N-type epitaxial layer 12 and the P-type substrate 11 of the NPN transistor 8 performing logarithmic compression, and between the N-type epitaxial layer 12 and the P-type diffusion layer 13. When the PN junction between them and the PN junction between the P-type diffusion layer 13 and the N + diffusion layer 14 are reached, currents in the directions indicated by the arrows a, b, and c shown in FIG. This generated current is hereinafter referred to as an error current.

これらの誤差電流ａ，ｂ，ｃのうち、誤差電流ａ，ｂは、ＮＰＮトランジスタ８のコレクタに流入するフォトダイオード６からの光電変換電流Ｉ（その流れは矢印２０で示す）から引き算する方向で発生する。誤差電流ａ、ｂは、通常０．０１ｐＡ程度以下の非常に微小な電流ではある。しかし、近年例えば一眼レフカメラの測光では被写体情報を多分割して測光するために、１つ当たりのフォトダイオードのサイズが非常に微小なものとなっている。このため、０．０１ｐＡ程度の誤差電流であっても、コレクタ電流が微小な領域では与える影響が大きくなり、低照度における測光精度の低下を招くことになる。シリコンのフォトダイオードの光電変換特性は、本来非常に高いリニアリティー（直線性）を有している。従って、誤差電流による影響を軽減することができれば、非常に低い電流値に対してもリニアリティーを持つ対数圧縮式の電流電圧変換回路が実現可能と考えられる。   Among these error currents a, b, and c, the error currents a and b are subtracted from the photoelectric conversion current I (the flow of which is indicated by an arrow 20) from the photodiode 6 flowing into the collector of the NPN transistor 8. appear. The error currents a and b are usually very small currents of about 0.01 pA or less. However, in recent years, for example, in the photometry of a single-lens reflex camera, since the subject information is measured in multiple divisions, the size of each photodiode is very small. For this reason, even if the error current is about 0.01 pA, the influence of the collector current in a region where the collector current is very small becomes large, and the photometric accuracy is lowered at low illuminance. The photoelectric conversion characteristic of a silicon photodiode inherently has very high linearity. Therefore, if the influence of the error current can be reduced, it is considered that a logarithmic compression type current-voltage conversion circuit having linearity even for a very low current value can be realized.

本発明はこのような事情に鑑みて提案されたものであり、その目的は、非常に低い電流値に対してもリニアリティーを持つ対数圧縮式の電流電圧変換回路を提供することにある。   The present invention has been proposed in view of such circumstances, and an object thereof is to provide a logarithmic compression type current-voltage conversion circuit having linearity even for a very low current value.

本発明の電流電圧変換回路は、入力電流が印加される電流入力端子と、基準電圧が印加される基準電圧入力端子と、電圧出力端子と、反転入力端子が前記電流入力端子に、非反転入力端子が前記基準電圧入力端子に、出力端子が前記電圧出力端子にそれぞれ接続され、Ｐ型半導体基板上に形成された演算増幅器と、コレクタが前記電流入力端子に、ベースが前記基準電圧入力端子に、エミッタが前記電圧出力端子にそれぞれ接続され、前記Ｐ型半導体基板上に形成されたＮＰＮ型トランジスタとを備え、前記ＮＰＮ型トランジスタは、前記Ｐ型半導体基板上に形成され、前記エミッタに相当するＮ型エピタキシャル層と、前記Ｎ型エピタキシャル層上に選択的に形成され、前記ベースに相当するＰ型拡散層と、前記Ｐ型拡散層上に選択的に形成され、前記コレクタに相当するＮ型拡散層とから構成されている。   The current-voltage conversion circuit of the present invention includes a current input terminal to which an input current is applied, a reference voltage input terminal to which a reference voltage is applied, a voltage output terminal, an inverting input terminal, and a non-inverting input. An operational amplifier formed on a P-type semiconductor substrate, a collector connected to the current input terminal, a base connected to the reference voltage input terminal, a terminal connected to the reference voltage input terminal, an output terminal connected to the voltage output terminal, respectively. And an NPN transistor connected to the voltage output terminal and formed on the P-type semiconductor substrate. The NPN transistor is formed on the P-type semiconductor substrate and corresponds to the emitter. An N-type epitaxial layer, a P-type diffusion layer selectively formed on the N-type epitaxial layer and corresponding to the base, and a shape selectively formed on the P-type diffusion layer It is, and a N-type diffusion layer corresponding to the collector.

本発明によれば、非常に低い電流値に対してもリニアリティーを持つ対数圧縮式の電流電圧変換回路が得られる。   According to the present invention, a logarithmic compression type current-voltage conversion circuit having linearity even for a very low current value can be obtained.

本発明の電流電圧変換回路の実施の形態の電気回路図である。It is an electric circuit diagram of an embodiment of a current-voltage conversion circuit of the present invention. 本発明の電流電圧変換回路で使用するＮＰＮ型トランジスタの構造例を示す断面図である。It is sectional drawing which shows the structural example of the NPN type transistor used with the current-voltage conversion circuit of this invention. 本発明の電流電圧変換回路で使用するＮＰＮ型トランジスタの構造例を示す平面図である。It is a top view which shows the structural example of the NPN type transistor used with the current-voltage conversion circuit of this invention. 従来の電流電圧変換回路の電気回路図である。It is an electric circuit diagram of a conventional current-voltage conversion circuit. 従来の電流電圧変換回路で使用するＮＰＮ型トランジスタの構造例を示す断面図である。It is sectional drawing which shows the structural example of the NPN type transistor used with the conventional current-voltage conversion circuit. 従来の電流電圧変換回路で使用するＮＰＮ型トランジスタの構造例を示す平面図である。It is a top view which shows the structural example of the NPN type transistor used with the conventional current-voltage converter circuit.

図１を参照すると、本発明の実施の形態に係る電流電圧変換回路は、図４に示した従来の電流電圧変換回路と比較して、対数圧縮に使用するＮＰＮ型トランジスタ８がＮＰＮ型トランジスタ５に置き換えられている点でのみ相違する。なお、ＮＰＮ型トランジスタ５の表記におけるエミッタは実際の動作上ではコレクタとして動作しているエミッタ拡散による端子を、Ｉ２Ｌ（インテグレーテッドインジェクションロジック）などの例に倣い、通常であればエミッタを意味する矢印で表している。   Referring to FIG. 1, in the current-voltage conversion circuit according to the embodiment of the present invention, the NPN transistor 8 used for logarithmic compression is an NPN transistor 5 as compared with the conventional current-voltage conversion circuit shown in FIG. The only difference is that it is replaced by. The emitter in the notation of the NPN transistor 5 is an arrow indicating an emitter in the case of an I2L (Integrated Injection Logic), which is a terminal by emitter diffusion that operates as a collector in actual operation. It is represented by

図２および図３はＮＰＮ型トランジスタ５の断面図および平面図である。Ｐ型サブストレート１１の上にエミッタとなるＮ型エピタキシャル層１２が形成されている。また、Ｎ型エピタキシャル層１２の上に選択的にＰ型拡散層１３が形成され、このＰ型拡散層１３がベースとなる。さらに、Ｐ型拡散層１３の上に選択的に不純物濃度の高いＮ型拡散層１４が形成され、このＮ型拡散層１４がコレクタとして使われる。すなわち、ＮＰＮ型トランジスタ５は、ＮＰＮ型トランジスタ８におけるコレクタ領域をエミッタ領域とし、エミッタ領域をコレクタ領域としている。換言すれば、ＮＰＮ型トランジスタ５は、ＮＰＮ型トランジスタ８を逆接続したものに相当する。   2 and 3 are a sectional view and a plan view of the NPN transistor 5. An N-type epitaxial layer 12 serving as an emitter is formed on the P-type substrate 11. A P-type diffusion layer 13 is selectively formed on the N-type epitaxial layer 12, and this P-type diffusion layer 13 serves as a base. Further, an N-type diffusion layer 14 having a high impurity concentration is selectively formed on the P-type diffusion layer 13, and this N-type diffusion layer 14 is used as a collector. That is, the NPN transistor 5 uses the collector region in the NPN transistor 8 as an emitter region and the emitter region as a collector region. In other words, the NPN transistor 5 corresponds to a reverse connection of the NPN transistor 8.

なお、図２および図３において、１５はＮ＋埋め込み層、１６は素子分離用のＰ＋埋め込み層、１７はコンタクト用のＮ＋層、１８はＳiＯ2層、１９はＡｌ配線層である。また、３１は、ベースに相当するＰ型拡散層１３の周囲を取り囲むように形成されたＮ＋拡散層から成るウォールである。 In FIG. 2 and FIG. 3, 15 N + buried layer, 16 is the P + buried layer for element isolation, N + layer of contact 17, 18 is S i O 2 layer, 19 is the Al wiring layer. Reference numeral 31 denotes a wall made of an N + diffusion layer formed so as to surround the periphery of the P-type diffusion layer 13 corresponding to the base.

フォトダイオード６で光電変換電流Ｉが発生すると、その光電変換電流ＩはＮＰＮ型トランジスタ５のコレクタに流れ込み、そのベースとエミッタとの間には、光電変換電流Ｉを対数圧縮した式１で示す電圧ＶBEが生じる。そのため、電圧出力端子３には式（2）に示したように、基準電圧ＶrefからＶBEを差し引いた電圧Ｖoutが出力される。 When the photoelectric conversion current I is generated in the photodiode 6, the photoelectric conversion current I flows into the collector of the NPN transistor 5, and between the base and the emitter, a voltage expressed by Equation 1 obtained by logarithmically compressing the photoelectric conversion current I. V BE occurs. Therefore, a voltage V out obtained by subtracting V BE from the reference voltage V ref is output to the voltage output terminal 3 as shown in Expression (2).

また、ＮＰＮ型トランジスタ５が形成されているＰ型サブストレート１１上には、図２および図３には図示していないが、フォトダイオード６に加えて、安定化電源回路などの比較的大電流が流れる回路が形成されている。このため、安定化電源回路などで発生した大電流によって生じた微小な光が、対数圧縮を行っているＮＰＮ型トランジスタ５のＮ型エピタキシャル層１２とＰ型サブストレート１１との間のＰＮ接合、Ｎ型エピタキシャル層１２とＰ型拡散層１３との間のＰＮ接合、Ｐ型拡散層１３とＮ＋拡散層１４との間のＰＮ接合に到達すると、そこに図示の矢印ａ、ｂ、ｃに示す向きの誤差電流が発生する。   Although not shown in FIGS. 2 and 3, on the P-type substrate 11 on which the NPN transistor 5 is formed, in addition to the photodiode 6, a relatively large current such as a stabilized power supply circuit is provided. Is formed. Therefore, a minute light generated by a large current generated in a stabilized power supply circuit or the like causes a PN junction between the N-type epitaxial layer 12 and the P-type substrate 11 of the NPN transistor 5 performing logarithmic compression, When the PN junction between the N-type epitaxial layer 12 and the P-type diffusion layer 13 and the PN junction between the P-type diffusion layer 13 and the N + diffusion layer 14 are reached, the arrows a, b, and c shown in FIG. A direction error current is generated.

しかし、ＮＰＮ型トランジスタ５のコレクタに流入するフォトダイオード６からの光電変換電流Ｉの向きは、図５のＮＰＮ型トランジスタ８とは逆方向であるため（その流れは矢印４０で示す）、これらの誤差電流ａ，ｂ，ｃのうち、誤差電流ａ，ｂは、ＮＰＮ型トランジスタ５のコレクタ電流に影響を及ぼさない。他方、図５のＮＰＮ型トランジスタ８ではコレクタ電流に影響を及ぼさなかった誤差電流ｃが、図２のＮＰＮ型トランジスタ５ではコレクタに流入するフォトダイオード６からの光電変換電流Ｉから引き算する方向で発生する。しかし、Ｎ型エピタキシャル層１２とＰ型サブストレート１１との間のＰＮ接合、Ｎ型エピタキシャル層１２とＰ型拡散層１３との間のＰＮ接合に比べて、Ｐ型拡散層１３とＮ＋拡散層１４との間のＰＮ接合の接合面積は格段に小さい。従って、誤差信号ｃは誤差信号ａ、ｂに比べて十分に小さいために、ＮＰＮ型トランジスタ５のコレクタ電流に及ぼす影響は軽微である。この結果、図４の従来の電流電圧変換回路に比べて、一桁以上低照度までリニアリティーを持って測光できる対数圧縮式の電流電圧変換回路が実現できる。   However, the direction of the photoelectric conversion current I from the photodiode 6 flowing into the collector of the NPN transistor 5 is opposite to that of the NPN transistor 8 in FIG. 5 (the flow is indicated by an arrow 40). Among the error currents a, b, and c, the error currents a and b do not affect the collector current of the NPN transistor 5. On the other hand, the error current c that did not affect the collector current in the NPN transistor 8 of FIG. 5 is generated in the direction of subtracting from the photoelectric conversion current I from the photodiode 6 flowing into the collector in the NPN transistor 5 of FIG. To do. However, compared with the PN junction between the N-type epitaxial layer 12 and the P-type substrate 11 and the PN junction between the N-type epitaxial layer 12 and the P-type diffusion layer 13, the P-type diffusion layer 13 and the N + diffusion layer. The junction area of the PN junction with 14 is remarkably small. Therefore, since the error signal c is sufficiently smaller than the error signals a and b, the influence on the collector current of the NPN transistor 5 is negligible. As a result, a logarithmic compression type current / voltage conversion circuit capable of performing photometry with linearity up to an order of magnitude lower than that of the conventional current / voltage conversion circuit of FIG. 4 can be realized.

また、ウォール３１を設けたことにより、エミッタの直列に入る寄生抵抗値が低減され、大電流側でのリニアリティーの悪化を防止することができる。   Further, the provision of the wall 31 reduces the parasitic resistance value entering the series of the emitters, and prevents the deterioration of linearity on the large current side.

１…電流入力端子
２…基準電圧入力端子
３…電圧出力端子
４…演算増幅器
５、８…ＮＰＮ型トランジスタ
６…フォトダイオード
７…基準電圧源 DESCRIPTION OF SYMBOLS 1 ... Current input terminal 2 ... Reference voltage input terminal 3 ... Voltage output terminal 4 ... Operational amplifier 5, 8 ... NPN transistor 6 ... Photodiode 7 ... Reference voltage source

Claims (4)

入力電流が印加される電流入力端子と、基準電圧が印加される基準電圧入力端子と、電圧出力端子と、反転入力端子が前記電流入力端子に、非反転入力端子が前記基準電圧入力端子に、出力端子が前記電圧出力端子にそれぞれ接続され、Ｐ型半導体基板上に形成された演算増幅器と、コレクタが前記電流入力端子に、ベースが前記基準電圧入力端子に、エミッタが前記電圧出力端子にそれぞれ接続され、前記Ｐ型半導体基板上に形成されたＮＰＮ型トランジスタとを備え、
前記ＮＰＮ型トランジスタは、前記Ｐ型半導体基板上に形成され、前記エミッタに相当するＮ型エピタキシャル層と、前記Ｎ型エピタキシャル層上に選択的に形成され、前記ベースに相当するＰ型拡散層と、前記Ｐ型拡散層上に選択的に形成され、前記コレクタに相当するＮ型拡散層とから構成される、
ことを特徴とする電流電圧変換回路。 A current input terminal to which an input current is applied, a reference voltage input terminal to which a reference voltage is applied, a voltage output terminal, an inverting input terminal to the current input terminal, a non-inverting input terminal to the reference voltage input terminal, An operational amplifier formed on a P-type semiconductor substrate, an output terminal is connected to the voltage output terminal, a collector is the current input terminal, a base is the reference voltage input terminal, and an emitter is the voltage output terminal And an NPN transistor formed on the P-type semiconductor substrate,
The NPN-type transistor is formed on the P-type semiconductor substrate, and an N-type epitaxial layer corresponding to the emitter, a P-type diffusion layer corresponding to the base selectively formed on the N-type epitaxial layer, , Selectively formed on the P-type diffusion layer, and composed of an N-type diffusion layer corresponding to the collector,
A current-voltage conversion circuit characterized by that. 前記ＮＰＮ型トランジスタは、前記ベースに相当するＰ型拡散層の周囲を取り囲むようにＮ型拡散層から成るウォールを備えることを特徴とする請求項１に記載の電流電圧変換回路。   2. The current-voltage conversion circuit according to claim 1, wherein the NPN transistor includes a wall made of an N-type diffusion layer so as to surround a P-type diffusion layer corresponding to the base. 前記Ｐ型半導体基板上に形成され、前記電流入力端子に光電変換電流を印加するシリコンフォトダイオードを備えることを特徴とする請求項１または２に記載の電流電圧変換回路。   The current-voltage conversion circuit according to claim 1, further comprising a silicon photodiode formed on the P-type semiconductor substrate and applying a photoelectric conversion current to the current input terminal. 前記Ｐ型半導体基板上に、安定化電源回路などの比較的大電流が流れる回路が形成されていることを特徴とする請求項１乃至３の何れか１項に記載の電流電圧変換回路。   4. The current-voltage conversion circuit according to claim 1, wherein a circuit through which a relatively large current flows, such as a stabilized power supply circuit, is formed on the P-type semiconductor substrate. 5.
JP2009110735A 2009-04-30 2009-04-30 Current-voltage conversion circuit Expired - Fee Related JP5199942B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018078415A (en) * 2016-11-08 2018-05-17 Ｎｔｔエレクトロニクス株式会社 Optical receiving circuit
JP2019054438A (en) * 2017-09-15 2019-04-04 アズビル株式会社 Photoelectric sensor

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56130954A (en) * 1980-03-17 1981-10-14 Sharp Corp Constant-temperature device for transistor
JPS6188552A (en) * 1984-10-05 1986-05-06 Mitsubishi Electric Corp Input circuit for semiconductor integrated circuit
JPS631056A (en) * 1986-06-20 1988-01-06 Sharp Corp Optoelectric transducer
JPH03165609A (en) * 1989-11-24 1991-07-17 Sharp Corp Optical current amplifier
JPH051951A (en) * 1991-06-24 1993-01-08 Nikon Corp Light measuring circuit
JP2004214924A (en) * 2002-12-27 2004-07-29 Sharp Corp Optical leak current compensating circuit and circuit for optical signal employing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56130954A (en) * 1980-03-17 1981-10-14 Sharp Corp Constant-temperature device for transistor
JPS6188552A (en) * 1984-10-05 1986-05-06 Mitsubishi Electric Corp Input circuit for semiconductor integrated circuit
JPS631056A (en) * 1986-06-20 1988-01-06 Sharp Corp Optoelectric transducer
JPH03165609A (en) * 1989-11-24 1991-07-17 Sharp Corp Optical current amplifier
JPH051951A (en) * 1991-06-24 1993-01-08 Nikon Corp Light measuring circuit
JP2004214924A (en) * 2002-12-27 2004-07-29 Sharp Corp Optical leak current compensating circuit and circuit for optical signal employing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018078415A (en) * 2016-11-08 2018-05-17 Ｎｔｔエレクトロニクス株式会社 Optical receiving circuit
JP2019054438A (en) * 2017-09-15 2019-04-04 アズビル株式会社 Photoelectric sensor

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