JP2010262600A - Processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processor capable of enhancing efficiency of time for operating an arithmetic unit to thereby improve performance of serial processing. <P>SOLUTION: The processor 1 has: a clock control circuit 21 which outputs a control clock signal ECLK generated on the basis of a supplied clock signal CLK according to a control signal S_CYCLE for controlling the clock signal CLK; and a plurality of serially connected ALUs 22-25. In an operation stage where a plurality of operations are executed by the plurality of ALUs 22-25, the plurality of operations to be serially executed are executed in one execution cycle by changing execution cycles on the basis of the control clock signal ECLK from the clock control circuit 21. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a processor, and more particularly to a processor that can change the number of execution cycles of an operation by a control clock signal.

  Conventionally, in an information device such as a personal computer or an embedded device, the processor is one of the important factors that influence the performance. In order to improve processor performance, high clocks and parallel processing have been widely implemented. In recent years, it has become difficult to increase clocks due to problems with power consumption or heat, so that emphasis is placed on parallel processing. It has become. However, there are many sequential operations that must be executed in order without being parallelized, and it is necessary to optimize these processing times.

  As described above, there is an inefficiency of calculation time as a problem when the sequential calculation processing is executed by the synchronous clock processor. Some operations include addition / subtraction with a large number of bits, and other logical operations have a small number of bits. The time required for these operations varies greatly, but when executed by a microprocessor, it often takes one clock time equally.

  Here, attention is paid only to the operation stage of the processor, and it is assumed that instruction fetches before and after, memory control, etc. do not affect the operation of the operation stage. For example, six cycles are required to execute six operations A to F, but there are operations that use almost all of one cycle time and other operations that can be executed in a very short time. As described above, in the case of an operation that can be executed in a very short time, there is a problem that there is a useless time in which the operation is not executed in the conventional configuration.

  In addition, there is a processor having a configuration in which only a specific composite operation such as a product-sum operation can be executed in one cycle. This configuration is applied, for example, for the purpose of improving the performance of multimedia processing, but also has the effect of reducing the above-described wasted time. However, in this configuration, since the composite operation is held in one cycle time, the clock cycle tends to be long. For this reason, there is a problem in that useless time increases depending on the type of calculation.

  In view of this, an information processing apparatus that prevents occurrence of a hazard based on a difference in instruction execution time has been proposed (see, for example, Patent Document 1). The proposed information processing apparatus changes the cycle of the clock signal based on the number of execution cycles of the instruction code, and executes the instruction code according to the clock signal whose cycle has been changed.

  However, in the proposed information processing apparatus, when one operation takes a plurality of cycles, the clock signal is masked and the instructions are efficiently executed. It does not execute in series at a time.

JP 2006-126893 A

  An object of the present invention is to provide a processor capable of improving the use time efficiency of an arithmetic unit and improving the performance of sequential processing.

  According to one aspect of the present invention, a processor that executes an instruction code read from a memory, the control generated based on a supplied clock signal according to clock signal control information for controlling the clock signal A control clock generation unit that outputs a clock signal; and a plurality of arithmetic units connected in series; information on contents of arithmetic processing executed by each of the plurality of arithmetic units and data necessary for the arithmetic processing In the operation stage in which a plurality of operations are executed by the plurality of arithmetic units according to the operation mode information including the information of the control clock signal from the control clock generator Based on the above, it is possible to provide a processor characterized in that the execution cycle is changed to be executed within one execution cycle. .

  According to the processor of the present invention, it is possible to increase the usage time efficiency of the arithmetic unit and improve the performance of sequential processing.

It is a block diagram which shows the structure of the processor system which concerns on the 1st Embodiment of this invention. It is explanatory drawing for demonstrating the example of an instruction code. It is a flowchart for demonstrating the example of the flow of a process which produces | generates an instruction code. 4 is an explanatory diagram for explaining an example of a configuration of an ALU 22. FIG. It is explanatory drawing for demonstrating the example of a response | compatibility with mode information and a calculation process. It is explanatory drawing for demonstrating the example of operation | movement of the calculation stage performed by the calculating part 15a. It is a block diagram which shows the structure of the processor system which concerns on the 2nd Embodiment of this invention. It is explanatory drawing for demonstrating the example of an instruction code. It is explanatory drawing for demonstrating the example of the connection of ALU31-38. It is explanatory drawing for demonstrating the example of the connection of ALU31-38. 4 is an explanatory diagram for explaining an example of a configuration of an ALU 31. FIG. It is explanatory drawing for demonstrating the example of mode information and a calculation process. It is explanatory drawing for demonstrating the example of a calculation process. It is a block diagram which shows the structure of the processor system which concerns on the 3rd Embodiment of this invention. It is explanatory drawing for demonstrating the example of the information which each of the entries 0-15 has. It is a flowchart for demonstrating the example of the flow of a process of the production | generation of an instruction code. It is a flowchart for demonstrating the example of the flow of a process of the production | generation of an instruction code. It is a block diagram which shows the structure of the processor system which concerns on the 4th Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
First, the configuration of the processor system according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a processor system according to the first embodiment of the present invention.

  As shown in FIG. 1, the processor system 100 includes a processor 1, a clock generator 101, a memory interface (hereinafter referred to as a memory I / F) 102, a bus 103, and a memory 104. ing.

  The clock generator 101 generates a clock signal CLK having a predetermined frequency and supplies the generated clock signal CLK to the processor 1. The processor 1 reads out an instruction code stored in the memory 104 via the bus 103 and the memory I / F 102, and executes predetermined arithmetic processing based on the read instruction code. Further, the processor 1 stores a calculation result obtained by executing predetermined calculation processing in the memory 104 via the memory I / F 102 and the bus 103.

  The processor 1 includes an instruction fetch unit 11, an instruction decode unit 12, three pipeline registers 13a, 13b and 13c, a data register 14, arithmetic units 15a and 15b, a selector 16, a memory access unit 17, And a write-back portion 18.

  The processor 1 of the present embodiment is a processor having a five-stage pipeline structure, and the pipeline processing is performed by a fetch stage executed by the instruction fetch unit 11, a decode stage executed by the instruction decode unit 12, an arithmetic unit 15a or The calculation unit is configured by a calculation stage executed by the calculation unit 15b, a memory access stage executed by the memory access unit 17, and a write back stage executed by the write back unit 18.

  The calculation unit 15a includes a clock control circuit 21 and a plurality of, in this case, four calculation units (hereinafter referred to as ALUs) 22, 23, 24, and 25 connected in series. The calculation unit 15b includes a general-purpose ALU 26. It is configured to include.

  The instruction fetch unit 11 reads an address stored in a program counter (not shown). Then, the instruction fetch unit 11 reads the instruction code stored at the address from the memory 104 and outputs the read instruction code to the instruction decoding unit 12.

  The instruction decode unit 12 decodes the instruction code read by the instruction fetch unit 11, and outputs the decoding result to the pipeline register 13a or 13b. The instruction decoding unit 12 outputs a decoding result to the pipeline register 13a when the instruction code is an instruction code indicating an instruction operation of the present embodiment as a result of decoding a bit indicating an instruction operation described later in the instruction code. Further, the instruction decode unit 12 outputs a selection signal for selecting the output of the arithmetic unit 15a to the selector 16 when the instruction code is an instruction code indicating the instruction operation of the present embodiment.

  On the other hand, when the instruction code is an instruction code indicating a normal instruction operation, the instruction decoding unit 12 outputs a decoding result to the pipeline register 13b. Furthermore, when the instruction code is an instruction code indicating a normal instruction operation, the instruction decoding unit 12 outputs a selection signal for selecting the output of the arithmetic unit 15b to the selector 16.

  The pipeline register 13a is controlled by a control clock signal ECLK from a clock control circuit 21, which will be described later. The pipeline register 13a takes in the decoding result from the instruction decoding unit 12 at the rising edge of the control clock signal ECLK, and the fetched decoding result is used as the arithmetic unit 15a. Output to.

  The arithmetic unit 15 a executes predetermined arithmetic processing based on the decoding result from the pipeline register 13 a and outputs the arithmetic result to the selector 16.

  On the other hand, although not shown, the pipeline register 13b is controlled by a control clock signal ECLK from a clock control circuit 21 to be described later, and the decoding result from the instruction decoding unit 12 is received by a rising edge of the control clock signal ECLK. The fetched and fetched decoding result is output to the arithmetic unit 15b.

  The arithmetic unit 15 b executes predetermined arithmetic processing based on the data from the pipeline register 13 b and outputs the arithmetic result to the selector 16.

  The selector 16 selects either the operation result output from the operation unit 15a or the operation result output from the operation unit 15b on the basis of the selection signal from the instruction decoding unit 12, and selects the selected operation result from the pipeline register. To 13c.

  The pipeline register 13c is controlled by a control clock signal ECLK from a clock control circuit 21 to be described later. The operation result from the selector 16 is fetched by the rising edge of the control clock signal ECLK, and the fetched computation result is sent to the memory access unit 17. Output.

  The memory access unit 17 performs memory access via the memory I / F 102 and the bus 103 and outputs a calculation result to the write back unit 18.

  The write-back unit 18 performs a process of writing the calculation result to the data register 14 or another data register (not shown).

  Here, the detailed structure of the calculating part 15a is demonstrated. The clock control circuit 21 is supplied with the clock signal CLK from the clock generator 101 and the control signal S_CYCLE from the pipeline register 13a. The clock control circuit 21 stalls the clock signal CLK by the value indicated by the control signal S_CYCLE that is the clock signal control information, and generates the control clock signal ECLK. This stall is to mask the clock signal CLK. That is, when the value indicated by the control signal S_CYCLE is 0, the clock control circuit 21 does not stall the clock signal and outputs the clock signal CLK as the control clock signal ECLK. When the value indicated by the control signal S_CYCLE is 1, the control clock signal ECLK in which the clock signal CLK is stalled by one clock is generated, and the generated control clock signal ECLK is output. As described above, the clock control circuit 21 configures a control clock generation unit that outputs the control clock signal ECLK generated based on the supplied clock signal CLK according to the control signal S_CYCLE for controlling the clock signal CLK. To do.

  The clock control circuit 21 supplies the generated control clock signal ECLK to the pipeline registers 13a, 13b, and 13c. The pipeline registers 13a and 13b may be supplied with the clock signal CLK from the clock generator 101 in place of the control clock signal ECLK from the clock control circuit 21.

  The ALUs 22 to 25 are supplied with mode information i0 to i3 and immediate values v0 to v3, respectively, from the pipeline register 13a. The mode information i0 to i3 is information on the contents of the arithmetic processing executed by each of the ALUs 22 to 25, and the immediate values v0 to v3 are immediate information necessary for the arithmetic processing. As described above, the mode information i0 to i3 and the immediate values v0 to v3 are operation mode information supplied to the ALUs 22 to 25, respectively. The ALU 22 is supplied with the data A0 stored in the data register 14.

  The ALU 22 performs predetermined arithmetic processing on the data A0 and the immediate value v0 stored in the data register 14 based on the mode information i0, and outputs an arithmetic result that is data to the ALU 23. Based on the mode information i1, the ALU 23 performs a predetermined calculation process on the calculation result from the ALU 22 and the immediate value v1, and outputs the calculation result to the ALU 24. Based on the mode information i2, the ALU 24 performs a predetermined calculation process on the calculation result from the ALU 23 and the immediate value v2, and outputs the calculation result to the ALU 25. Based on the mode information i3, the ALU 25 performs a predetermined calculation process on the calculation result from the ALU 24 and the immediate value v3, and outputs the calculation result to the selector 16. These ALUs 22 to 25 do not include a sequential circuit such as a flip-flop in the operation path, and are configured by combinational circuits.

  Here, an instruction code executed by the processor 1 will be described. FIG. 2 is an explanatory diagram for explaining an example of an instruction code.

  As shown in FIG. 2, the instruction code has a 32-bit bit field. Bits 31 to 26 are bits indicating instruction operation information, bits 25 and 24 are bits indicating stall information, and bits 23 to 0 are bits indicating mode information and immediate values.

  When bits 31 to 26 are all 1, this indicates an instruction operation of the present embodiment, and when bits 31 to 26 are not all 1, it indicates a normal instruction operation. Therefore, the instruction decode unit 12 outputs the decode result to the pipeline register 13a when the bits 31 to 26 are all 1, and outputs the decode result to the pipeline register 13b when the bits 31 to 26 are not all 1.

  Bits 25 and 24 indicate the number of stall cycles at the time of instruction execution. When the bit field is 0, it indicates that one cycle is required for execution. When the bit field is 1, it indicates that two cycles are required for execution. When the field is 2, it means that it takes 3 cycles to execute the operation, and when the bit field is 3, it means that it takes 4 cycles to execute the operation. The instruction decoding unit 12 generates the above-described control signal S_CYCLE based on the bits 25 and 24, and supplies the generated control signal S_CYCLE to the clock control circuit 21 via the pipeline register 13a.

  Bits 23 to 0 represent ALU mode information and an immediate value, which will be described later, and have 4 bit fields for ALUs 22 to 25 as a set of 3-bit mode information and a 3-bit immediate value.

  Bits 5 to 3 and bits 2 to 0 are mode information i0 and immediate value v0 for ALU 22, respectively. Bits 11 to 9 and bits 8 to 6 are mode information i1 and immediate value v1 for ALU 23, respectively. -15 and bits 14-12 are mode information i2 and immediate value v2 for ALU 24, respectively, and bits 23-21 and bits 20-18 are mode information i3 and immediate value v3 for ALU 25, respectively.

  Here, processing for generating such an instruction code will be described. FIG. 3 is a flowchart for explaining an example of a flow of processing for generating an instruction code.

  First, p = 0 and r = 3 are set as initial values (step S1). Here, r is a value obtained by subtracting 1 from the number of ALUs 22 to 25 of the arithmetic unit 15a. Next, q = p + r is calculated (step S2). It is determined whether the pth to qth lines of the input code can be converted into an instruction executable by the arithmetic unit 15a (step S3). In this determination, all the instructions on the p to q lines can be executed by the ALUs 22 to 25, the instruction pattern on the p to q lines can be configured by sequential processing, and the instructions on the p + 1 to q lines are If it is not the jump destination of the jump instruction, it is determined that conversion is possible.

  If it is determined in step S3 that conversion is not possible, NO is determined, and it is determined whether the values of p and q are the same (step S4). When it is determined that the values of p and q are not the same, NO is obtained, q = q−1 is calculated (step S5), and the process returns to step S3. If it is determined that the values of p and q are the same, the command in the p-th row is output as it is (step S6), and the process proceeds to step S9.

  On the other hand, if it is determined in step S3 that conversion is possible, the result is YES, the pth to qth rows are converted, the number of stalls is calculated (step S7), and the converted instruction is output (step S8). Next, p = q + 1 is calculated (step S9), and it is determined whether p is past the last row (step S10). If it is determined that p is not past the last line, the process returns to step S2 and the above-described processing is repeated. If it is determined that p is past the last line, YES is determined and the process is terminated. Through the above processing, the instruction code shown in FIG. 2 is generated.

  Here, the configuration of the ALUs 22 to 25 will be described. Since each of the ALUs 22 to 25 has the same configuration, the ALU 22 will be described as an example. FIG. 4 is an explanatory diagram for explaining an example of the configuration of the ALU 22.

  As shown in FIG. 4, the ALU 22 has terminals m, n, i, and x. Data A0 stored in the data register 14 is supplied to the terminal m. Note that the outputs of the preceding ALUs 22, 23, and 24 are supplied to the terminals m of the ALUs 23, 24, and 25, respectively. An immediate value v0 for the ALU 22 is supplied to the terminal n from the pipeline register 13a. The terminal i is supplied with mode information i0 for the ALU 22 from the pipeline register 13a. In the ALU 22, based on the mode information i0, the operation shown in FIG. 4 to be described later is performed on the data supplied to the terminal m and the terminal n. The calculation result obtained by this calculation is output from the terminal x to the terminal m of the ALU 23 at the next stage.

  FIG. 5 is an explanatory diagram for explaining an example of correspondence between mode information and arithmetic processing. In the ALU 22, a calculation process corresponding to the mode information i0 shown in FIG. 4 is executed. For example, when “000” is input as the 3-bit mode information i0, the ALU 22 adds m + n arithmetic processing, that is, adds data supplied to the terminals m and n. Similarly, when “001” is input as the 3-bit mode information i0, the ALU 22 subtracts the mn calculation process, that is, the data supplied to the terminals m and n.

  Further, the ALU 22 performs a left shift operation when the mode information i0 is “010”, a right shift operation when the mode information i0 is “011”, an AND operation and the mode information i0 when the mode information i0 is “100”. In the case of “101”, the OR operation, the mode information i0 is “110”, the EXOR operation, and the mode information i0 is “111”, the absolute value operation is executed.

Here, the operation of the processor 1 will be described by taking the calculation Z = ((A0 + 2) >> 1) & 7 as an example.
When this calculation is executed by a normal processor, three cycles of addition, shift operation, and AND operation are required. In order to realize by the processor 1 of the present embodiment, for example,
(I0, v0) = (2'b000, 2'b010)
(I1, v1) = (2'b011, 2'b001)
(I2, v2) = (2'b100, 2'b111)
(I3, v3) = (2'b101, 2'b000)
Should be set.

  The ALU 22 adds the data A0 from the data register 14 and the immediate value v0 based on the mode information i0, and outputs the addition result to the ALU 23. Based on the mode information i1, the ALU 23 performs a right shift operation on the addition result by the value of the immediate value v1, and outputs the operation result to the ALU 24. The ALU 24 performs an AND operation on the operation result and the immediate value v2 based on the mode information i2. The ALU 25 executes an OR operation and outputs the operation result from the ALU 24 as it is, and can be omitted when the above-described operation is executed by a normal microprocessor.

  By the way, normally, the cycle of the clock signal CLK must be set to be equal to or longer than the worst delay time of the ALU 22, 23, 24 or 25. This worst delay time is the longest calculation time determined according to the command, that is, mode information and input data. However, the time required for the operation of the ALU 22, 23, 24, or 25 may be shorter than one clock cycle when an operation that ends in a short time is used, or when the upper bits of the input data are fixed to 0. . If the total time required for the operations by the ALUs 22, 23, 24, and 25 is two clock cycles in the above-described operation, the conventional microprocessor is wasting time for one cycle.

  However, the processor 1 of the present embodiment sets the value of the stall information in the instruction code to 1 when the total time required for the calculation is 2 clock cycles. Then, based on the control signal S_CYCLE generated from the stall information, the clock control circuit 21 generates a control clock signal ECLK that stalls the clock signal CLK by one clock. Furthermore, the processor 1 can execute the above-described operation in two cycles by controlling the pipeline register 13c with the control clock signal ECLK.

  FIG. 6 is an explanatory diagram for explaining an example of the operation of the operation stage executed by the operation unit 15a.

  As shown in FIG. 6A, the operation stage executed by the operation unit 15a conventionally includes three operations A, B and C executed in series within three execution cycles based on the clock signal CLK. I was trying to run it.

  However, as shown in FIG. 6B, the operation stage executed by the operation unit 15a of the present embodiment controls three operations A, B, and C executed in series from the clock control circuit 21. Based on the clock signal ECLK, the execution cycle is changed to be executed within one execution cycle. As a result, when the total time required for the operations A, B, and C is 2 clock cycles, the operation stage can execute the operations A, B, and C in 2 cycles based on the control clock signal ECLK.

  As described above, the processor 1 designates a cycle related to a plurality of calculations by the stall information, and generates the control clock signal ECLK based on the stall information. The pipeline register 13c takes in the operation result by the control clock signal ECLK. As a result, it is possible to reduce the time during which calculations that have been wasted in the past are not executed, and the processing of the microprocessor can be speeded up.

  Therefore, according to the processor of the present embodiment, it is possible to improve the usage time efficiency of the arithmetic unit and improve the performance of sequential processing.

(Second Embodiment)
Next, a second embodiment will be described. FIG. 7 is a block diagram showing a configuration of a processor system according to the second embodiment of the present invention. In FIG. 7, the same components as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

  The processor system 100a of the present embodiment is configured using a processor 1a instead of the processor 1 of FIG. Although not shown for the sake of simplicity, the memory I / F 102 is connected to the memory 104 via the bus 103 as in FIG.

  The processor 1a of the present embodiment is configured by using a calculation unit 15c instead of the calculation unit 15a of FIG. Although illustration is omitted for the sake of simplicity, as in FIG. 1, in the case of normal instruction operation, the operation result obtained by the pipeline register 13b and the operation unit 15b is input to one of the selectors 16. It is supplied to the terminal.

  The arithmetic unit 15 includes a clock control circuit 21, a crossbar switch 30, and a plurality of (here, eight) ALUs 31 to 38.

  The pipeline register 13a outputs a connection information signal XB_CONF generated from a bit indicating connection information of the crossbar switch 30 described later to the crossbar switch 30.

  The crossbar switch 30 is supplied with data A0 from the data register 14 and data A1 and data A2 from a data register (not shown). The crossbar switch 30 is supplied with immediate values v0 to v7 from the pipeline register 13a. Based on the connection information signal XB_CONF, the crossbar switch 30 changes the connection of the ALUs 31 to 38 as shown in FIGS. 9A and 9B described later. Thus, the crossbar switch 30 constitutes a switching unit that can connect the connections between the plurality of ALUs 31 to 38 with a plurality of connection patterns.

  FIG. 8 is an explanatory diagram for explaining an example of an instruction code. As shown in FIG. 8, the instruction code has a 64-bit bit field.

  In the instruction code of the present embodiment, a bit indicating connection information of the crossbar switch 30 is added to the instruction code of FIG. The connection of the crossbar switch 30 is changed by the bits 57 and 56 indicating the connection information of the crossbar switch 30, and the connections of the ALUs 31 to ALU 38 are changed.

  Bits 63 to 61 are bits indicating instruction operation information. When bits 63 to 61 are all 1, this indicates an instruction operation according to the present embodiment. When bits 63 to 61 are not all 1, normal Indicates that the command operation. For this reason, the instruction decode unit 12 outputs the decoding result to the pipeline register 13a when the bits 63 to 61 are all 1, and when the bits 63 to 61 are not all 1, the decoding result is omitted in the pipeline. Output to the register 13b.

  Bits 60 to 58 represent the number of stall cycles at the time of instruction execution. When this bit field is 0, it indicates that 1 cycle is required for execution of the operation. When this bit field is 7, it indicates that 8 cycles are required for execution of the operation. .

  Bits 55 to 0 represent ALU mode information and an immediate value, which will be described later, and have 8 sets of bit fields for ALUs 31 to 38, each of which includes a 4-bit mode information and a 3-bit immediate value.

  Bits 6 to 3 and bits 2 to 0 are mode information i0 and immediate value v0 for ALU 31, respectively. Similarly, bits 55 to 52 and bits 51 to 29 are mode information i7 and immediate value v7 for ALU 38, respectively.

  Such an instruction code can be generated by the same flowchart as in FIG. However, in the determination of step S3 in FIG. 3, all the instructions in the p to q lines can be executed by the ALU, the instruction pattern in the p to q lines can be configured by the crossbar switch 30, and p + 1 to 1 If the q-th line instruction is not the jump destination of the jump instruction, it is determined that conversion is possible.

  9A and 9B are explanatory diagrams for explaining an example of connection of the ALUs 31 to 38. FIG. When the connection information signal XB_CONF is 00, the crossbar switch 30 changes the connection of the ALUs 31 to 38 as shown in FIG. 9A. When the connection information signal XB_CONF is 01, the crossbar switch 30 changes the connection of the ALUs 31 to 38 as shown in FIG. Change the connection. Note that the crossbar switch 30 also changes the connections of the ALUs 31 to 38 so as to become predetermined connections even when the connection information signal XB_CONF is 10 and 11.

  Here, the configuration of the ALUs 31 to 38 will be described. Since each of the ALUs 31 to 38 has the same configuration, the ALU 31 will be described as an example. FIG. 10 is an explanatory diagram for explaining an example of the configuration of the ALU 31.

  As shown in FIG. 10, the ALU 31 is configured by adding a terminal c to the ALU 22 of FIG. Information on condition setting is supplied to the terminal c. Therefore, the ALU 31 can execute a conditional operation based on the condition setting information.

  The terminal i is supplied with mode information i0 for the ALU 31 from the pipeline register 13a. Each of the terminals m, n, and c is supplied with data from any one of data A0 to A2, immediate values v0 to v7, and outputs of other ALUs 32 to 38, depending on the connection status of the crossbar switch 30. The In the ALU 31, based on the mode information i0 and the condition setting information, the operation shown in FIG. 11 described later is executed on the data supplied to the terminal m and the terminal n. The calculation result obtained by this calculation is output from the terminal x to the connection destination determined by the connection status of the crossbar switch 30.

  FIG. 11 is an explanatory diagram for describing an example of mode information and calculation processing. In the ALU 31, an arithmetic process corresponding to the mode information i0 shown in FIG. 11 is executed. For example, when “1000” is input as the 4-bit mode information i0, the ALU 31 c? (M + n): m arithmetic processing is executed. This “c? (M + n): m” is a conditional operation. If the value input to the terminal c is 1, the data supplied to the terminal m and the terminal n are added, and the addition result is Output from terminal x. On the other hand, if the value input to the terminal c is not 1, the data input to the terminal m is output from the terminal x.

Here, the operation of the processor 1a will be described by taking the following calculation as an example.
if ((A0 & 1) == 1)
Z = ((~ A1) >> 1) & 7
else
Z = ((A2 & 2) >> 1) & 7
When this operation is executed by a normal processor, the worst 8 cycles are required, and even a processor capable of ideally performing parallel processing requires 4 cycles.

  When this calculation is executed by parallel processing, the circuit shown in FIG. 9B may be used. That is, when the crossbar switch 30 is supplied with 01 as the connection information signal XB_CONF, the circuit shown in FIG. 9B is configured.

Processing of the above-described calculation by the circuit configured as described above will be described. FIG. 12 is an explanatory diagram for explaining an example of the arithmetic processing.
The ALU 31 performs an AND operation on the data A0 and the immediate value v0, and outputs the operation result to the terminal c of the ALU 38 as condition setting information.

  The ALU 32 performs an EXOR operation on the data A1 and the immediate value v1, and outputs the operation result to the ALU 33. The ALU 33 shifts the calculation result to the right by the bit indicated by the immediate value v2, and outputs the calculation result to the ALU 34. The ALU 34 performs an AND operation on the operation result and the immediate value v3, and outputs the operation result to the terminal m of the ALU 38. That is, in the ALUs 32 to 34, the above-described calculation ((˜A1) >> 1) & 7 is executed, and the calculation result is output to the ALU 38.

  The ALU 35 performs the addition operation of the data A2 and the immediate value v4, and outputs the operation result to the ALU 36. The ALU 36 shifts the calculation result to the right by the bit indicated by the immediate value v5 and outputs the calculation result to the ALU 37. The ALU 37 performs an AND operation on the operation result and the immediate value v6, and outputs the operation result to the terminal n of the ALU 38. That is, in the ALUs 35 to 37, the above-described calculation ((A2 & 2) >> 1) & 7 is executed, and the calculation result is output to the ALU 38.

  The ALU 38 outputs the calculation result input to the terminal m when the condition setting input from the ALU 31, that is, the calculation result of the AND calculation of the data A 0 and the immediate value v 0 is 1, and the AND of the data A 0 and the immediate value v 0. When the calculation result of the calculation is not 1, the calculation result input to the terminal n is output.

  If the total calculation time by the ALUs 35, 36, 37, and 38 is 3 clock cycles and is the longest path of the entire calculation, the conventional processor is wasting time for one cycle.

  However, the processor 1a according to the present embodiment sets the value of the stall information in the instruction code to 2 when the total time required for the calculation is 3 clock cycles. Then, based on the control signal S_CYCLE generated from the stall information, the clock control circuit 21 generates a control clock signal ECLK that stalls the clock signal CLK by two clocks. Furthermore, the processor 1a can execute the above-described calculation in three cycles by controlling the pipeline register 13c with the control clock signal ECLK.

  As described above, the processor 1a supplies the connection information signal XB_CONF to the crossbar switch 30 so that the connections of the ALUs 31 to 38 can be connected in series or in parallel. As a result, the processor 1a can increase the degree of freedom of connection of the ALUs 31 to 38, and can speed up the arithmetic processing.

(Third embodiment)
Next, a third embodiment will be described. FIG. 13 is a block diagram showing a configuration of a processor system according to the third embodiment of the present invention. In FIG. 13, the same components as those in FIG. 7 are denoted by the same reference numerals and description thereof is omitted.

  The processor system 100b of this embodiment is configured using a processor 1b instead of the processor 1 of FIG.

The processor 1b of the present embodiment has information corresponding to the instruction code shown in FIG. 8 in the processor 1b as table information.
As shown in FIG. 13, the processor 1b is configured by adding a configuration table 41 to the processor 1a of FIG.

  The configuration table 41 has 16 entries 0 to 15. Each of the entries 0 to 15 holds the number of stall cycles, the connection information of the crossbar switch 30, the mode information of each of the ALUs 31 to 38, and the immediate value.

  When the instruction code specifying any one of the entries 0 to 15 in the configuration table 41 is supplied, the instruction decoding unit 12 outputs information on the specified entry to the configuration table 41. Based on this information, the config table 41 outputs the number of stall cycles in the specified entry, the connection information of the crossbar switch 30, the mode information i0 to i7 and the immediate values v0 to v7 of the ALUs 31 to 38 to the pipeline register 13a. To do. As a result, the number of stall cycles, the connection information of the crossbar switch 30, the mode information i0 to i7 and the immediate values v0 to v7 of the ALUs 31 to 38 are supplied from the pipeline register 13a to the arithmetic unit 15c, as in the second embodiment. In addition, a predetermined calculation process is performed by the calculation unit 15c.

  Thus, the configuration having the configuration table 41 in the processor 1b eliminates the need for the instruction code to have the number of stall cycles, the connection information of the crossbar switch 30, the mode information i0 to i7 of the ALUs 31 to 38, and the immediate values v0 to v7. Therefore, the instruction code only needs to have a bit field that can specify 16 types of information of entries 0 to 15, and the bit field of the instruction code can be shortened.

  The configuration table 41 has 16 types of information, but may have 16 types or more of information. Alternatively, the processor 1b may have an instruction to rewrite the information of the entries 0 to 15 in the configuration table 41, or the information of the entries 0 to 15 may be rewritten from outside the processor 1b. As a result, the processor 1b can have more connection patterns of the ALUs 31 to 38 than the processor 1a, and can efficiently execute operations.

  FIG. 14 is an explanatory diagram for explaining an example of information included in each of the entries 0 to 15.

  Each of the entries 0 to 15 has the number of stall cycles, the connection information of the crossbar switch 30, the mode information and the immediate value of each of the ALUs 31 to 38, as in the instruction code of FIG.

  The connection information of the crossbar switch 30 shows a configuration in which all connection patterns can be realized because it is less necessary to shorten the bit length compared to the case where it is realized as an instruction code. For example, XB_0m of bits 3 to 0 represents signal information connected to the terminal m of the ALU 31. Any one of the data A0 to A2, the immediate value v0, and the outputs of the ALUs 32 to 38 may be connected to the terminal m of the ALU 31, and all connection patterns can be realized with 4 bits. With regard to the terminals n and c of the ALU 31, all the connection patterns can be realized with 4 bits each. For this reason, the connection information of the ALU 31 is 12 bits, and 96 bits from the eight ALUs 31 to 38.

  15 and 16 are flowcharts for explaining an example of the flow of processing for generating an instruction code. In FIG. 15, the same processes as those in FIG.

  First, p = 0, r = 3, and s = 0 are set as initial values (step S11). When the stall number is calculated by converting the pth to qth lines in step S7, it is determined whether or not there is a matching instruction in the instruction entries s to s-1 (step S12). If there is a matching instruction, YES is output, the instruction with the matching instruction entry number is output (step S13), and the process proceeds to step S9. On the other hand, if there is no matching instruction, the result is NO, using s as the instruction entry number, and outputting the converted instruction (step S14). Next, s = s + 1 is calculated (step S15), and the process proceeds to step S9. With the above processing, an assembler code including instruction entry data is generated.

  Next, moving to FIG. 16, the assembler code including the instruction entry data generated by the processing of FIG. 15 is read (step S21), and t = 2 is set (step S22). Next, it is determined whether or not the number of instructions in the instruction entry data fits in the configuration table 41 of the processor 1b (step S23). If the number of instructions in the instruction entry data fits in the configuration table 41, the determination is YES and the process ends. If the number of instructions in the instruction entry data does not fit in the configuration table 41, NO is determined, and it is determined whether or not an instruction having the number of used ALUs t is present in the instruction entry data (step S24). If there is an instruction with the number of used ALUs t, the answer is YES, one instruction with the number of used ALUs t in the instruction entry data is selected, the instruction is deleted from the instruction entry data, and the output code is changed to the original instruction. Is written back (step S25), and the process returns to step S23. On the other hand, if there is no instruction with the number of used ALUs t, NO is obtained, t = t + 1 is calculated (step S26), the process proceeds to step S25, and the above-described processing is repeated.

  In addition, although the processor 1a of 2nd Embodiment has the table, you may have the processor 1 of 1st Embodiment. In this case, the connection information of the crossbar switch 30 possessed by each of the entries 0 to 15 may be deleted.

  As described above, the processor 1b has the number of stall cycles, the crossbar switch 30 connection information, the mode information of each of the ALUs 31 to 38, and the immediate value in the configuration table 41. As a result, the processor 1b can shorten the bit field of the instruction code also by the processor 1a of the second embodiment. Furthermore, the processor 1b can increase the degree of freedom of connection of the ALUs 31 to 38 as compared with the processor 1a of the second embodiment, and can efficiently execute more patterns of operations.

(Fourth embodiment)
Next, a fourth embodiment will be described. FIG. 17 is a block diagram showing a configuration of a processor system according to the fourth embodiment of the present invention. In FIG. 17, the same components as those in FIG.

  In recent years, for example, in systems for portable devices, demands for low power consumption and low heat generation are further increased, and finer power control is required. Therefore, the processor system 100a of the present embodiment changes the frequency or operating voltage of the processor 1 to the processor system 100 of the first embodiment, enables finer power control, and optimizes arithmetic processing. Making it possible.

  As shown in FIG. 17, the processor system 100 c is configured by adding a clock control unit 105 and a power supply control unit 106 to the processor system 100 of FIG. 1, and a mode signal is supplied to the processor 1. The processor system 100c may use the processor 1a of the second embodiment or the processor 1b of the third embodiment instead of the processor 1.

  The memory 104 stores a program for a low power consumption mode, a program for a high-speed operation mode, and a program for a normal operation.

  The mode signal supplied to the processor 1 is a mode signal such as a low power consumption mode signal, a high-speed operation mode signal, and a normal operation mode signal. When this mode signal is supplied to the processor 1, the processor 1 changes to a mode corresponding to the mode signal.

  When the low power consumption mode signal is supplied to the processor 1, the clock control unit 105 performs control to reduce the frequency of the processor 1. After that, the processor 1 reads out the low power consumption mode program from the memory 104 and executes the read program.

  For example, the clock frequency of the processor 1 must be kept low in order to reduce power consumption, but there are cases where it is desired to execute a specific operation at high speed. In this case, for a specific operation sequence, the number of stall cycles in the instruction code is increased, the instruction code is changed so as to increase the number of ALUs to be operated at one time, and the instruction code is executed by the processor 1 to The arithmetic processing can be optimized while the frequency is lowered.

  On the other hand, when the high-speed operation mode signal is supplied to the processor 1, the power supply control unit 106 performs control to increase the voltage of the processor 1. Thereafter, the processor 1 reads the program for the high-speed operation mode from the memory 104 and executes the read program.

  For example, there is a case where it is desired to increase the voltage of the processor 1 and execute a specific operation at high speed, but to keep the clock frequency low according to the system. In this case, for a specific operation sequence, the number of stall cycles in the instruction code is reduced, and the instruction code is executed by the processor 1, so that the operation processing can be optimized while the clock frequency is lowered.

  As described above, in the processor system 100 c according to the present embodiment, the clock control unit 105 controls the frequency of the processor 1. Alternatively, the processor system 100 c controls the voltage of the processor 1 by the power supply control unit 106. As a result, the processor system 100c can change the frequency or operating voltage of the processor 1, perform finer power control, and optimize the arithmetic processing.

  Note that the steps in the flowcharts in this specification may be executed in a different order for each execution by changing the execution order and executing a plurality of steps at the same time, as long as the steps are not contrary to the nature.

  The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the scope of the present invention.

  DESCRIPTION OF SYMBOLS 1, 1a, 1b ... Processor, 11 ... Instruction fetch part, 12 ... Instruction decode part, 13a, 13b, 13c ... Pipeline register, 14 ... Data register, 15a, 15b, 15c ... Operation part, 16 ... Selector, 17 ... Memory access unit, 18 ... Write-back unit, 21 ... Clock control circuit, 22-26 ... ALU, 30 ... Crossbar switch, 31-38 ... ALU, 41 ... Configuration table, 100, 100a, 100b, 100c ... Processor system, 101 DESCRIPTION OF SYMBOLS ... Clock generator, 102 ... Memory I / F, 103 ... Bus, 104 ... Memory, 105 ... Clock control part, 106 ... Power supply control part.

Claims (5)

A processor for executing an instruction code read from a memory;
A control clock generator that outputs a control clock signal generated based on the supplied clock signal in accordance with clock signal control information for controlling the clock signal;
A plurality of arithmetic units connected in series;
Have
An arithmetic stage in which a plurality of operations are executed by the plurality of arithmetic units according to operation mode information including information on the contents of arithmetic processing executed by each of the plurality of arithmetic units and data information necessary for the arithmetic processing. The plurality of operations executed in series are executed in one execution cycle by changing an execution cycle based on the control clock signal from the control clock generation unit. Processor. The plurality of arithmetic units connected in series are configured to be able to change the connection between the plurality of arithmetic units,
A switching unit capable of connecting the plurality of arithmetic units with a plurality of connection patterns;
2. The processor according to claim 1, wherein the switching unit switches connection between the plurality of arithmetic units according to a connection pattern according to connection information among the plurality of connection patterns.   The processor according to claim 1, wherein the instruction code includes information on the clock signal control information to the control clock generation unit and the operation mode information of the plurality of arithmetic units. A storage unit that stores one or more sets of information of the clock signal control information to the control clock generation unit and the operation mode information of the plurality of computing units;
The processor according to claim 1, wherein the instruction code includes a code that specifies the information included in the storage unit. The operating frequency or operating voltage of the processor can be changed,
The processor according to claim 1, wherein the clock signal control information to the control clock generation unit is different according to the changed operating frequency or operating voltage.

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